Through-electrode substrate

Abstract

To provide a penetration electrode substrate with a structure in which the capacitance of a capacitor is easily controllable.SOLUTION: A penetration electrode substrate includes a substrate having a first surface and a second surface on the opposite side of the first surface, a penetration electrode electrically connecting the first surface and the second surface, a first conductive layer disposed on a first surface of the substrate and electrically connected to the penetration electrode, a first insulating layer disposed on the first conductive layer, and an intermediate layer disposed between the first conductive layer and the first insulating layer. The first insulating layer includes a first insulating part disposed on the intermediate layer, a second insulating part extending from the first insulating part and covering a side surface of the intermediate layer and a side surface of the first conductive layer, and a third insulating part extending from the second insulating part and covering at least a part of the first surface of the substrate.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present disclosure relates to a through electrode substrate.

Background Art

[0002] In recent years, in electronic devices, a form in which a semiconductor chip is attached to a wiring substrate via a through electrode substrate has been widely used. Patent Document 1 discloses a through electrode substrate using glass as a substrate material.

[0003]

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The above-described through electrode substrate has a MIM (Metal-Insulator-Metal) structure in which an insulating layer is sandwiched between metals. The MIM structure can be used, for example, as a MIM capacitor. When designing the capacitance of a capacitor, it is conceivable to adjust the size of the electrode pattern and the dielectric constant of the dielectric. However, when forming a high-density MIM structure on a through electrode substrate, there are restrictions on the size of the electrode pattern. Conventionally, a silicon nitride (SiN) layer has been used as a dielectric, but since silicon nitride has a high dielectric constant, there is little freedom in controlling the dielectric constant.

[0005] The present disclosure provides a through electrode substrate having a structure in which the capacitance of a capacitor can be easily controlled.

[0006]

Means for Solving the Problems

[0006] ​ This application includes several means to solve the above problem, but one example is the first page. A substrate having a first surface and a second surface on the opposite side to the first surface, and a through-hole connecting the first surface and the second surface. An electrode, a first conductive layer disposed on the first surface of the substrate and electrically connected to the through electrode, and a first conductive layer A first insulating layer placed on top of the electrode layer, and an intermediate layer placed between the first conductive layer and the first insulating layer. The first insulating layer comprises a first insulating portion placed on the intermediate layer and a portion from the first insulating portion. A second insulating portion that extends and covers the sides of the intermediate layer and the sides of the first conductive layer, and extending from the second insulating portion The present invention provides a through-electrode substrate having a third insulating portion that covers at least a part of the first surface of the substrate. do. [Effects of the Invention]

[0007] The technology of this disclosure provides a through-electrode substrate having a structure that facilitates control of the capacitance of a capacitor. Further features relating to this disclosure may be made clear from the description herein and the accompanying drawings. It will become smoother. Furthermore, the issues, structure, and effects other than those mentioned above will be discussed in the following implementation form. This will be clarified by the explanation of the state. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic cross-sectional view showing an interposer according to one embodiment of the present disclosure. [Figure 2] This is a cross-sectional view along line AA in Figure 1. [Figure 3] This is a schematic cross-sectional view of a MIM structure according to one embodiment of the present disclosure. [Figure 4] This is a schematic cross-sectional view of a MIM structure according to one embodiment of the present disclosure. [Figure 5] This is a schematic cross-sectional view of a MIM structure according to one embodiment of the present disclosure. [Figure 6] This is the XPS measurement result of the sample.

Mode for Carrying Out the Invention

[0009] Hereinafter, an embodiment of the present disclosure will be described with reference to the drawings. In the drawings attached to this specification, for the convenience of illustration and easy understanding, the scale, the aspect ratio of the vertical and horizontal dimensions, etc. are appropriately changed and exaggerated from those of the actual ones.

[0010] In this specification and the like, a numerical range represented by using "~" means a range including the numerical values described before and after "~" as the lower limit value and the upper limit value, respectively. [[ID=​​​​​​​​​​​​​​​​​​​​​​​​​​​​ The interposer 10 has a first surface 11a and a second surface 11 on the opposite side of the first surface 11a. A substrate 11 having b, a first conductive layer 12 disposed on the first surface 11a of the substrate 11, and The first insulating layer 14 is placed on the conductive layer 12, and the space between the first conductive layer 12 and the first insulating layer 14. It comprises an intermediate layer 13 placed on top of the first insulating layer 14 and a second conductive layer 15 placed on top of the first insulating layer 14. The first conductive layer 12 may be directly placed on the first surface 11a of the substrate 11, or At least one electrically conductive or insulating layer is arranged on the first surface 11a of the substrate 11. Alternatively, the first surface 11a of the substrate 11 may be made of epoxy resin or polyimide resin. By arranging an insulating resin, the difference in thermal expansion coefficients between the first conductive layer 12 and the substrate 11 causes It can alleviate the resulting stress.

[0014] The substrate 11 has through holes 16 that connect the first surface 11a and the second surface 11b. Layer 12 is a fourth layer positioned on the second surface 11b via a through electrode 17 formed in the through hole 16. It is electrically connected to the conductive layer 22. The shape of the through hole 16 is not limited to the illustration. This extends from the first surface 11a and the second surface 11b of the substrate 11 toward the center of the substrate 11 in the thickness direction. The shape may be such that the width decreases as it progresses, and the side wall of the through hole 16 is the first surface of the substrate 11. It may spread along the direction normal to 11a, or along the direction normal to the first surface 11a of the substrate 11 It may narrow along the curve, or a part of the side wall may have a curved shape. Substrate 1 1. Etching, laser processing, and processing using a combination of laser processing and etching. Through holes 16 are formed by sandblasting, electrical discharge machining, drilling, etc. The through electrode 17 is not limited to the form shown in Figure 1, but can also be a form in which a conductive material is filled inside the through hole 16. That's fine.

[0015] A resin layer 21 is formed on the first surface 11a and the second surface 11b of the substrate 11. On the first surface 11a of 1, the resin layer 21 is formed to cover the MIM structure. A connection hole 18 is provided in the lipid layer 21 at a position corresponding to the second conductive layer 15. The inside of 8 is filled with a conductive member 19. In addition, the surface 21a of the resin layer 21 is a third conductive A conductive layer 20 is formed. On the first surface 11a side of the substrate 11, the second conductive layer 15 is conductive The electrical component 19, the third conductive layer 20, and the solder ball 24 are connected to the semiconductor chip 50. It is being done.

[0016] On the second surface 11b of the substrate 11, at the position corresponding to the fourth conductive layer 22 of the resin layer 21, A connection hole 18 is provided. A conductive member 19 is filled inside the connection hole 18. A fifth conductive layer 23 is formed on the surface 21b of the resin layer 21. On side 1b, the fourth conductive layer 22 is connected to the conductive member 19, the fifth conductive layer 23, and the solder ball. It is connected to the wiring board 40 via 24.

[0017] According to this configuration, the interposer 10 is located on the first surface 11a side of the substrate 11. A semiconductor chip 50 electrically connected to the through electrode 17 and arranged on the second surface 11b side of the substrate 11 A semiconductor device is provided, having a wiring board 40 that is placed and electrically connected to a through electrode 17. According to the interposer 10 of this embodiment, a semiconductor chip 50 with a narrow terminal pitch This simplifies the mounting of the components onto large circuit boards (such as motherboards) 40.

[0018] The substrate 11 can be a glass substrate, a glass ceramic substrate, a quartz substrate, a sapphire substrate, Resin substrates, glass epoxy substrates, silicon substrates, SOI (Silicon on Ins ulator) substrate, SOS (Silicon on Sapphire) substrate, carbonized SiC (silicon) substrate, gallium arsenide (GaAs) substrate, indium phosphide (InP) group Plate, alumina (Al2O3) substrate, aluminum nitride (AlN) substrate, zirconium oxide A (ZrO2) substrate or a substrate in which these are laminated can be used.

[0019] Preferably, the substrate 11 is a glass substrate. Generally, the interposer is close to its edge. The greater the region, the greater the displacement due to thermal deformation. (Example: Interposer using a glass substrate) , the difference in thermal expansion coefficient between this region and the wiring boards etc. located above and below the interposer. This has the advantage of allowing us to address the issue by reducing its size.

[0020] More preferably, alkali-free glass is used as the substrate 11. Unlike soda glass, it does not contain alkaline components such as Na and K, so the glass surface is No lucari component precipitates. Therefore, in this embodiment, the interposer is connected. This has the advantage that, in principle, reliability degradation factors that corrode the terminals of semiconductor chips do not occur. Furthermore, alkali-free glass has a coefficient of thermal expansion that is about the same as that of silicon, and contact In terms of thermal expansion coefficient, it is compatible with the semiconductor chips that will be used next.

[0021] The materials used for each of the conductive layers mentioned above are gold (Au), silver (Ag), copper (Cu), iron (Fe), and nickel. Ni (Ni), Platinum (Pt), Palladium (Pd), Ruthenium (Ru), Tungsten Conductive materials such as (W) are used. Among them, materials with high conductivity and low material cost are used. It is preferable to use copper (Cu) with a low fluorine content. Also, the thickness of the first conductive layer 12 is 0.5 μm~ A thickness of 20 μm is preferred, and the thickness of the second conductive layer 15 is preferably 0.5 μm to 5 μm. Wiring pattern Regarding the lines, subtractive formation is achieved by etching metal foil (e.g., Cu). In addition, methods include applying conductive paste (e.g., metal nanopaste) and forming by plating. It is also possible to adopt an additive formation method.

[0022] The intermediate layer 13 is made of at least one of titanium (Ti), nickel (Ni), and gold (Au). It is a layer containing [a certain material]. In the example in Figure 2, the intermediate layer 13 is titanium (Ti). Thickness of the titanium layer The wavelength is 20 nm to 200 nm, preferably 50 nm to 100 nm.

[0023] The first insulating layer 14 in this embodiment is silicon nitride (SiN) containing carbon (C). When the amount of carbon (C) in the first insulating layer 14, which is a dielectric, increases, the relative permittivity decreases, and the capacitor It becomes easier to control the capacitance. Also, when the amount of carbon (C) in the first insulating layer 14, which is a dielectric, The adhesion with the titanium (Ti) intermediate layer 13 is improved. In this embodiment, the first insulating layer 1 The thickness of 4 is 50 nm to 800 nm, preferably 200 nm to 400 nm. .

[0024] As shown in Figure 2, the first insulating layer 14 is located between the upper surface 13d of the intermediate layer 13 and the second conductive layer 15. A first insulating portion 14a is positioned between them, and an intermediate layer 1 extends continuously from the first insulating portion 14a. A second insulating portion 14b that covers the side surface 13e of 3 and the side surface 12b of the first conductive layer 12, and the second insulating A third insulating layer extending continuously from portion 14b and covering at least a portion of the first surface 11a of the substrate 11. It has a portion 14c. The silicon nitride (SiN) of the first insulating layer 14 contains carbon (C). This also improves the adhesion between the third insulating portion 14c of the first insulating layer 14 and the substrate 11. ru.

[0025] In embodiments of this disclosure, the above-mentioned process for forming the conductive layer and insulating layer is chemical vapor deposition (C VD) (e.g., plasma CVD, atomic layer deposition (ALD)), physical vapor deposition (PVD) (for example) For example, sputtering or vapor deposition, or electroplating can be used. Photolithography can be used to form patterns for conductive and insulating layers. It is possible. In addition, as a planarization process for the conductive and insulating layers, etch-back, chemical-mechanical lacing, etc. Polishing (CMP), etc., can be used.

[0026] Figure 3 shows another example of the configuration of the intermediate layer 13. The intermediate layer 13 is made of nickel on the first conductive layer 12. The first layer 13-1 of nickel (Ni) and the second layer 13 of gold (Au) placed on the first layer 13-1 -2 may be composed of the first layer 13-1 of nickel (Ni). The thickness is 1 μm to 5.0 μm, and the thickness of the second layer 13-2 of gold (Au) is 0.05 The thickness is preferably μm to 0.5 μm. The intermediate layer 13 in this example also adheres closely to the first insulating layer 14. It has the characteristic of being highly efficient. Furthermore, comparing the example in Figure 2 and the example in Figure 3, the intermediate layer 13 is Using titanium (Ti) is preferable because it provides better adhesion.

[0027] Figure 4 shows another example of the configuration of the intermediate layer 13. The intermediate layer 13 is located on the upper surface 12 of the first conductive layer 12. The first part 13a is disposed between a and the first insulating portion 14a of the first insulating layer 14, and the first part A second portion 13b that extends continuously from portion 13a and covers the side surface 12b of the first conductive layer 12, and A third portion that extends continuously from portion 13b and covers at least a portion of the first surface 11a of the substrate 11. It has 13c. In this example, the second insulating portion 14b of the first insulating layer 14 is the intermediate layer 13 It is positioned to cover at least a portion of the second portion 13b and the third insulating portion of the first insulating layer 14 The portion 14c is positioned to cover at least a part of the third portion 13c of the intermediate layer 13. In this configuration, the intermediate layer 13 extends to the first surface 11a of the substrate 11, so the first insulation The adhesion between the edge layer 14 and the first surface 11a of the substrate 11 is improved.

[0028] Figure 5 shows another example of the configuration of the intermediate layer 13 and the first insulating layer 14. The insulating portion 14c covers the end of the third portion 13c of the intermediate layer 13 and the first surface of the substrate 11. It may be positioned to cover at least a portion of 11a.

[0029] Next, samples 1-5 of multiple silicon nitride (SiN) layers were prepared, and the relative permittivity and adhesion were examined. The evaluation was performed. Each of the samples 1-5 was formed on a Si wafer, and its layer thickness was 50 It is 0 nm. Samples 1-3 are samples that do not contain carbon (C), and sample 4- Sample 5 contains carbon (C).

[0030] Figure 6 shows the results of using ESCA-3400 (Shimadzu Corporation) on samples 1-5. S (X-ray Photoelectron Spectroscopy) measurements were performed. These are the quantitative values ​​for each sample 1-5 obtained. The measurement conditions are as follows: [XPS measurement] Incident X-ray: Mg K α (non-monochromatic X-ray) Measurement area: 6mmφ X-ray output: 120W [Depth analysis] Ion gun: Ar Acceleration voltage: 0.3kV Emissions: 30mA Etching time: 30 s / Cycle (1 to 20 Cycles), 100 s / Cycle le (from 21 to 45 cycles)

[0031] For samples 1-5 in Figure 6, the relative permittivity and adhesion to the intermediate layer 13 were investigated. Samples 4 and 5, which contained carbon (C), had lower dielectric constants compared to samples 1-3. Furthermore, samples 4 and 5 showed higher adhesion to the intermediate layer 13 compared to samples 1-3. Thus, when samples 4 and 5 are used as the first insulating layer 14, the relative permittivity becomes low. Therefore, it becomes easier to control the capacitance of the capacitor. Also, carbon (C) is used in the first insulating layer 14, which is the dielectric. It was found that increasing the amount of ) improves the adhesion between the intermediate layer 13 and the titanium.

[0032] Furthermore, samples 4 and 5, which are silicon nitride (SiN) containing carbon (C), are as follows: It can be manufactured by law. For example, when manufacturing sample 4, the raw material gas Tetrameter is placed in a vacuum chamber beforehand. Introducing 30 sccm of tilsilane and 100 sccm of nitrogen gas, the film deposition pressure was set to 1 Pa. Keep it in place. A heater is installed on the support, and the substrate temperature is controlled to 200°C. Vacuum processing A 3kW high-frequency radio wave is applied from the top of the room through a matching box to generate plasma. This plasma generation causes a chemical reaction in the gas phase, which is more effective than supporting the vacuum processing chamber. A silicon nitride (SiN) film containing carbon (C) is formed on the substrate on which the substrate is placed. . For example, for sample 5, the amount of tetramethylsilane introduced was determined using the same film formation method. The film deposition was carried out under the same conditions as Sample 4, with a setting of 60 sccm.

[0033] The above-mentioned interposer and through-electrode substrate are used in mobile phones and smartphones, wireless Local Area Network (LAN) devices, set-top boxes, music players Video players, entertainment units, navigation devices, communication devices Select from a group of devices including personal digital assistants (PDAs), fixed-position data units, and computers. It can be applied to the selected device.

[0034] This disclosure is not limited to the embodiments described above, and includes various other modifications. For example, the embodiments described above have been explained in detail in order to make the present disclosure easier to understand. This refers to a system that does not necessarily have all the configurations described. Furthermore, some parts of the configuration of one embodiment may be replaced with the configuration of another embodiment, and also, It is also possible to add the configuration of other embodiments to the configuration of each embodiment. It is possible to add, delete, or replace other components within a given set of components. [Explanation of Symbols]

[0035] 10... Interposer 11 ... Circuit board 11a...Side 1 11b…Second side 12 ...First conductive layer 13…Middle class 14 ...First insulating layer 15 ...Second conductive layer 16 ... through hole 17...Through electrode 18…connection holes 19 ... Conductive material 20 ...Third conductive layer 21 ... Resin layer 22 ...Fourth conductive layer 23 ... Fifth conductive layer 24...solder ball 40 ... Wiring board 50... Semiconductor chips

Claims

1. A substrate having a first surface and a second surface on the opposite side to the first surface, A through electrode that conducts electrical current between the first surface and the second surface, A first conductive layer electrically connected to the through electrode, A first insulating layer disposed on the first conductive layer, An intermediate layer disposed between the first conductive layer and the first insulating layer, Equipped with, The first insulating layer covers at least a portion of the first surface of the substrate, The intermediate layer has a portion that extends from the first insulating layer and covers at least a part of the first surface of the substrate. Through-electrode substrate.

2. The through-electrode substrate according to claim 1, wherein the first insulating layer covers at least a portion of the side surface of the first conductive layer.

3. The through-electrode substrate according to claim 1, wherein the substrate is a glass substrate.

4. The through-electrode substrate according to claim 1, wherein the first insulating layer is silicon nitride containing carbon.

5. The through-electrode substrate according to claim 4, wherein the atomic composition percentage (at.%) of carbon in the first insulating layer is 40 to 60.

6. The end of the intermediate layer and the end of the first insulating layer are spaced apart. The through-electrode substrate according to claim 1.

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