Manufacturing equipment for display devices

Abstract

To suppress reduction in reliability and yield.SOLUTION: An apparatus for manufacturing a display device includes: a vacuum chamber; a conveyance path provided in the inside of the vacuum chamber for conveying a display device processing substrate; and an ionizer for generating ions in the inside of the vacuum chamber. The ionizer stored in the inside of the vacuum chamber includes: a sub-chamber having an aperture; a gas supply part for supplying inert gas to the sub-chamber; and an emission source for emitting vacuum ultraviolet rays or X-rays for ionizing the inert gas supplied to the inside of the sub-chamber.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] Embodiments of the present invention relate to a manufacturing apparatus for a display device.

【Background

【Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. Such a display element includes a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. The organic layer includes functional layers such as a hole transport layer and an electron transport layer in addition to the light-emitting layer. In the process of manufacturing such a display element, technologies for suppressing a decrease in reliability and yield are required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Patent Document 8

Summary of the Invention

Problems to be Solved by the Invention

[0004] The object of the present invention is to provide a manufacturing apparatus for a display device that can suppress a decrease in reliability and yield. [Means for solving the problem]

[0005] According to one embodiment, the manufacturing apparatus for a display device is The apparatus comprises a vacuum chamber, a transport path provided inside the vacuum chamber for transporting a processing substrate for a display device, and an ionizer for generating ions inside the vacuum chamber, wherein the ionizer comprises a sub-chamber housed inside the vacuum chamber and having an opening, a gas supply unit for supplying an inert gas to the sub-chamber, and an irradiation source for irradiating the inert gas supplied to the sub-chamber with vacuum ultraviolet light or X-rays to ionize it.

[0006] According to one embodiment, the manufacturing apparatus for a display device is The device comprises a substrate stocker for housing a processing substrate for a display device having a lower electrode formed on it; a pre-processing unit for performing pre-treatment on the processing substrate; a deposition chamber configured to radiate one of the materials of an organic layer, an upper electrode, or a cap layer onto the processing substrate; a transport chamber for transporting the processing substrate; a rotation chamber configured to rotate while holding the processing substrate; a post-processing unit for performing post-treatment on the processing substrate; and an ionizer provided in at least one of the substrate stocker, the pre-processing unit, the deposition chamber, the transport chamber, and the post-processing unit for generating ions inside, wherein the ionizer comprises a sub-chamber housed inside a vacuum chamber and having an opening; a gas supply unit for supplying an inert gas to the sub-chamber; and an irradiation source for irradiating vacuum ultraviolet light or X-rays to ionize the inert gas supplied inside the sub-chamber. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 shows an example of the configuration of a display device DSP. [Figure 2]Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3. [Figure 3] Figure 3 is a schematic cross-sectional view of the DSP display device along line A and B in Figure 2. [Figure 4] Figure 4 shows an example configuration of the display element 20. [Figure 5] Figure 5 shows an example configuration of the manufacturing apparatus 100. [Figure 6] Figure 6 is a cross-sectional view showing a typical configuration example of an EV11 deposition chamber. [Figure 7] Figure 7 is a diagram illustrating an ionizer 200 applicable to the manufacturing apparatus 100 shown in Figure 5. [Figure 8] Figure 8 is a diagram illustrating an example of the installation of the ionizer 200 in the manufacturing apparatus 100 shown in Figure 5. [Modes for carrying out the invention]

[0008] One embodiment will be described with reference to the drawings. The disclosure is merely an example, and any modifications that a person skilled in the art could easily conceive of while maintaining the spirit of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may schematically represent the width, thickness, shape, etc., of each part in order to clarify the explanation, but these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each drawing, the same reference numerals are used for components that perform the same or similar functions as those described above with respect to previously shown drawings, and redundant detailed explanations may be omitted as appropriate.

[0009] Furthermore, the drawings will include mutually orthogonal X, Y, and Z axes as needed to facilitate understanding. The direction along the X axis will be referred to as the first direction X, the direction along the Y axis as the second direction Y, and the direction along the Z axis as the third direction Z. Viewing the various elements parallel to the third direction Z is called a plan view.

[0010] The display device according to this embodiment is an organic electroluminescence display device including an organic light-emitting diode (OLED) as a display element, and can be mounted on a television, a personal computer, in-vehicle equipment, a tablet terminal, a smartphone, a mobile phone terminal, or the like.

[0011] FIG. 1 is a diagram showing a configuration example of the display device DSP.

[0012] The display device DSP includes a display panel PNL having a display area DA for displaying an image and a peripheral area SA outside the display area DA on an insulating substrate 10. The substrate 10 may be glass or a resin film having flexibility.

[0013] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0014] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. The pixel PX includes a plurality of sub-pixels SP. In one example, the pixel PX includes a sub-pixel SP1 of the first color, a sub-pixel SP2 of the second color, and a sub-pixel SP3 of the third color. The first color, the second color, and the third color are different from each other. Note that the pixel PX may include sub-pixels SP of other colors such as white, together with or instead of the sub-pixels SP1, SP2, and SP3.

[0015] The sub-pixel SP includes a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements constituted by, for example, thin film transistors.

[0016] The gate electrode of the pixel switch 2 is connected to the scan line GL. One of the source and drain electrodes of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source and drain electrodes is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element 20.

[0017] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.

[0018] The display element 20 is an organic light-emitting diode (OLED) as a light-emitting element, and is sometimes referred to as an organic EL element.

[0019] The peripheral region SA, though not described in detail here, has multiple terminals for connecting IC chips and flexible printed circuit boards.

[0020] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3. In the example in Figure 2, sub-pixels SP2 and SP3 are aligned in the second direction Y. Sub-pixels SP1 and SP2 are aligned in the first direction X, and sub-pixels SP1 and SP3 are aligned in the first direction X.

[0021] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP2 and SP3 are alternately arranged in the second direction Y, and columns in which multiple sub-pixels SP1 are arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0022] Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2. Another example is that the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged sequentially in the first direction X.

[0023] The display area DA has ribs 5 and partition walls 6. Ribs 5 have apertures AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively.

[0024] In a plan view, partition wall 6 overlaps with rib 5. Partition wall 6 is formed in a grid pattern surrounding openings AP1, AP2, and AP3. Partition wall 6 can also be said to have openings in sub-pixels SP1, SP2, and SP3, similar to rib 5.

[0025] The sub-pixels SP1, SP2, and SP3 each comprise display elements 201, 202, and 203, respectively, as display elements 20.

[0026] The sub-pixel SP1 display element 201 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with the aperture AP1, respectively. The periphery of the lower electrode LE1 is covered by a rib 5. The display element 201, comprising the lower electrode LE1, the organic layer OR1, and the upper electrode UE1, is surrounded by a partition wall 6 in a plan view. The periphery of the organic layer OR1 and the upper electrode UE1 overlap with the rib 5 in a plan view. The organic layer OR1 includes, for example, a light-emitting layer that emits light in the blue wavelength range.

[0027] The display element 202 of the sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with the aperture AP2, respectively. The periphery of the lower electrode LE2 is covered by a rib 5. The display element 202, comprising the lower electrode LE2, the organic layer OR2, and the upper electrode UE2, is surrounded by a partition wall 6 in a plan view. The periphery of the organic layer OR2 and the upper electrode UE2 overlap with the rib 5 in a plan view. The organic layer OR2 includes, for example, a light-emitting layer that emits light in the green wavelength range.

[0028] The sub-pixel SP3 display element 203 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with the aperture AP3, respectively. The periphery of the lower electrode LE3 is covered by a rib 5. The display element 203, comprising the lower electrode LE3, the organic layer OR3, and the upper electrode UE3, is surrounded by a partition wall 6 in a plan view. The periphery of the organic layer OR3 and the upper electrode UE3 overlap with the rib 5 in a plan view. The organic layer OR3 includes, for example, a light-emitting layer that emits light in the red wavelength range.

[0029] In the example in Figure 2, the outlines of the lower electrodes LE1, LE2, and LE3 are shown by dotted lines, and the outlines of the organic layers OR1, OR2, OR3 and the upper electrodes UE1, UE2, and UE3 are shown by dashed lines. Note that the outlines of the lower electrodes, organic layers, and upper electrodes shown in the figure do not necessarily reflect their exact shapes.

[0030] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anode of a display element. The upper electrodes UE1, UE2, and UE3 correspond to the cathode of a display element, or to a common electrode.

[0031] The lower electrode LE1 is connected to the pixel circuit 1 of the sub-pixel SP1 (see Figure 1) through the contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the sub-pixel SP2 through the contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the sub-pixel SP3 through the contact hole CH3.

[0032] In the example shown in Figure 2, the areas of aperture AP1, aperture AP2, and aperture AP3 are different from each other. The area of ​​aperture AP1 is larger than the area of ​​aperture AP2, and the area of ​​aperture AP2 is larger than the area of ​​aperture AP3. In other words, the area of ​​the lower electrode LE1 exposed from aperture AP1 is larger than the area of ​​the lower electrode LE2 exposed from aperture AP2, and the area of ​​the lower electrode LE2 exposed from aperture AP2 is larger than the area of ​​the lower electrode LE3 exposed from aperture AP3.

[0033] Figure 3 is a schematic cross-sectional view of the DSP display device along line A and B in Figure 2.

[0034] The circuit layer 11 is placed on the substrate 10. The circuit layer 11 includes various circuits such as the pixel circuit 1 shown in Figure 1, and various wirings such as scan lines GL, signal lines SL, and power lines PL. The circuit layer 11 is covered by an insulating layer 12. The insulating layer 12 is an organic insulating layer that flattens the irregularities caused by the circuit layer 11.

[0035] The lower electrodes LE1, LE2, and LE3 are positioned on the insulating layer 12 and spaced apart from each other. The rib 5 is positioned on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The opening AP1 of the rib 5 overlaps with the lower electrode LE1, the opening AP2 overlaps with the lower electrode LE2, and the opening AP3 overlaps with the lower electrode LE3. The periphery of the lower electrodes LE1, LE2, and LE3 is covered by the rib 5. Between the lower electrodes LE1, LE2, and LE3 that are adjacent to each other, the insulating layer 12 is covered by the rib 5. The lower electrodes LE1, LE2, and LE3 are connected to the respective pixel circuits 1 of the sub-pixels SP1, SP2, and SP3 through contact holes provided in the insulating layer 12. Note that the contact holes in the insulating layer 12 are omitted in Figure 3, but correspond to CH1, CH2, and CH3 in Figure 2.

[0036] The partition wall 6 includes a conductive lower part (stem) 61 positioned on the rib 5 and an upper part (cap) 62 positioned on top of the lower part 61. The lower part 61 of the partition wall 6 shown on the right side of the figure is located between opening AP1 and opening AP2. The lower part 61 of the partition wall 6 shown on the left side of the figure is located between opening AP2 and opening AP3. The upper part 62 has a greater width than the lower part 61. Both ends of the upper part 62 protrude beyond the sides of the lower part 61. This shape of partition wall 6 is called an overhang.

[0037] The organic layer OR1 contacts the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed through the opening AP1, and its peripheral edge is located on the rib 5. The upper electrode UE1 covers the organic layer OR1 and is in contact with the lower part 61.

[0038] The organic layer OR2 contacts the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed through the opening AP2, and its peripheral edge is located on the rib 5. The upper electrode UE2 covers the organic layer OR2 and is in contact with the lower part 61.

[0039] The organic layer OR3 contacts the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed through the opening AP3, and its peripheral edge is located on the rib 5. The upper electrode UE3 covers the organic layer OR3 and is in contact with the lower part 61.

[0040] In the example shown in Figure 3, sub-pixel SP1 has a cap layer CP1 and a sealing layer SE1, sub-pixel SP2 has a cap layer CP2 and a sealing layer SE2, and sub-pixel SP3 has a cap layer CP3 and a sealing layer SE3. The cap layers CP1, CP2, and CP3 each serve as optical adjustment layers that improve the efficiency of light extraction from the organic layers OR1, OR2, and OR3, respectively.

[0041] The cap layer CP1 is placed on top of the upper electrode UE1. The cap layer CP2 is positioned on top of the upper electrode UE2. The cap layer CP3 is placed on top of the upper electrode UE3.

[0042] The sealing layer SE1 is positioned on top of the cap layer CP1, in contact with the partition wall 6, and continuously covers each component of the sub-pixel SP1. The sealing layer SE2 is positioned on top of the cap layer CP2, in contact with the partition wall 6, and continuously covers each component of the sub-pixel SP2. The sealing layer SE3 is positioned on top of the cap layer CP3, in contact with the partition wall 6, and continuously covers each component of the sub-pixel SP3.

[0043] In the example shown in Figure 3, portions of the organic layer OR1, the upper electrode UE1, and the cap layer CP1 are located above the partition wall 6 surrounding the sub-pixel SP1. These portions are separated from the organic layer OR1, the upper electrode UE1, and the portion of the cap layer CP1 located at the aperture AP1 (the portion that constitutes the display element 201). Similarly, portions of the organic layer OR2, the upper electrode UE2, and the cap layer CP2 are located above the partition wall 6 surrounding the sub-pixel SP2, and these portions are spaced apart from the portions of the organic layer OR2, the upper electrode UE2, and the cap layer CP2 located at the aperture AP2 (the portions that constitute the display element 202). Similarly, portions of the organic layer OR3, the upper electrode UE3, and the cap layer CP3 are located above the partition wall 6 surrounding the sub-pixel SP3, and these portions are separated from the portions of the organic layer OR3, the upper electrode UE3, and the cap layer CP3 located at the aperture AP3 (the portions that constitute the display element 203).

[0044] The ends of the sealing layers SE1, SE2, and SE3 are located on the partition wall 6. In the example in Figure 3, the ends of sealing layers SE1 and SE2 located on the partition wall 6 between sub-pixels SP1 and SP2 are spaced apart, and the ends of sealing layers SE2 and SE3 located on the partition wall 6 between sub-pixels SP2 and SP3 are spaced apart.

[0045] The sealing layers SE1, SE2, and SE3 are covered by a resin layer 13. The resin layer 13 is covered by a sealing layer 14. The sealing layer 14 is covered by a resin layer 15.

[0046] The ribs 5, sealing layers SE1, SE2, SE3, and sealing layer 14 are formed of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0047] The lower part 61 of the partition wall 6 is made of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The upper part 62 of the partition wall 6 is made of a conductive material, for example, but may also be made of an insulating material. The lower part 61 is made of a different material from the upper part 62.

[0048] The lower electrodes LE1, LE2, and LE3 are multilayer structures that include, for example, transparent electrodes made of an oxide conductive material such as indium tin oxide (ITO) and metallic electrodes made of a metallic material such as silver.

[0049] Organic layer OR1 includes light-emitting layer EM1. Organic layer OR2 includes light-emitting layer EM2. Organic layer OR3 includes light-emitting layer EM3. Light-emitting layers EM1, EM2, and EM3 are formed from different materials. In one example, light-emitting layer EM1 is formed from a material that emits light in the blue wavelength range, light-emitting layer EM2 is formed from a material that emits light in the green wavelength range, and light-emitting layer EM3 is formed from a material that emits light in the red wavelength range. Furthermore, each of the organic layers OR1, OR2, and OR3 includes multiple functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, another hole blocking layer, an electron transport layer, and an electron injection layer.

[0050] The upper electrodes UE1, UE2, and UE3 are formed from a metallic material such as a magnesium-silver alloy (MgAg).

[0051] The cap layers CP1, CP2, and CP3 are multilayer structures of multiple thin films. Each of the multiple thin films is transparent and has a different refractive index from one another.

[0052] Next, we will describe an example configuration of the display element 20.

[0053] Figure 4 shows an example configuration of the display element 20. The display element 20 shown in Figure 4 can correspond to any of the display elements 201, 202, and 203 described above. Here, we will explain using the example where the lower electrode LE corresponds to the anode and the upper electrode UE corresponds to the cathode.

[0054] The display element 20 includes an organic layer OR (OR1, OR2, OR3) between the lower electrode LE (LE1, LE2, LE3) and the upper electrode UE (UE1, UE2, UE3).

[0055] In the organic layer OR, the hole injection layer HIL, hole transport layer HTL, electron blocking layer EBL, light emission layer EML, hole blocking layer HBL, electron transport layer ETL, and electron injection layer EIL are stacked in this order. Furthermore, the organic layer OR may include other functional layers, such as a carrier generation layer, as needed, in addition to the functional layers described above, or at least one of the functional layers described above may be omitted.

[0056] The light-emitting layer EML corresponds to one of the light-emitting layers EM1, EM2, or EM3 shown in Figure 3.

[0057] The cap layer CP (CP1, CP2, CP3) includes a first transparent layer TL1 and a second transparent layer TL2. The first transparent layer TL1 is located on top of the upper electrode UE. The first transparent layer TL1 is a high refractive index layer having a higher refractive index than the upper electrode UE. The second transparent layer TL2 is located on top of the first transparent layer TL1. The second transparent layer TL2 is a low refractive index layer having a lower refractive index than the first transparent layer TL1. The sealing layer SE (SE1, SE2, SE3) is located on top of the second transparent layer TL2.

[0058] Furthermore, the configuration of the organic layer OR is not limited to a configuration in which the organic layer OR comprises one light-emitting layer EML as shown in the figure, but may also be a configuration in which the organic layer OR comprises multiple light-emitting layers.

[0059] Next, we will describe the manufacturing apparatus 100 for forming the organic layer OR, the upper electrode UE, and the cap layer CP shown in Figure 4.

[0060] Figure 5 shows an example configuration of the manufacturing apparatus 100.

[0061] The manufacturing apparatus 100 is used, for example, in a process of continuously forming an organic layer OR, an upper electrode UE, and a cap layer CP. The processing substrate SUB that is fed into the manufacturing apparatus 100 has a circuit layer 11, an insulating layer 12, lower electrodes LE1, LE2, LE3, ribs 5, and partition walls 6 on a substrate 10.

[0062] The manufacturing apparatus 100 includes a pre-processing section 101, a vapor deposition section 102, a post-processing section 103, and a substrate stocker 104.

[0063] The pre-processing unit 101 is equipped with a mechanism for performing various pre-processing treatments on the incoming processing substrate SUB, such as cleaning, drying, and plasma treatment. The pre-processing unit 101 also includes a mechanism for setting the processing substrate SUB in a predetermined transport position and a mechanism for fixing the processing substrate SUB to a dedicated carrier using an electrostatic chuck. Each transport path in the deposition unit 102 is configured to transport the carrier.

[0064] The post-processing unit 103 includes a mechanism for releasing the fixation by the electrostatic chuck and removing the processing board SUB from the carrier, and a mechanism for setting the processing board SUB in a predetermined position.

[0065] The substrate stocker 104 houses multiple processing substrates SUB. The pre-processing unit 101 and the post-processing unit 103 are connected to the substrate stocker 104. In the substrate stocker 104, processing substrates SUB with lower electrodes and partitions formed on them are brought in from other processing units, processing substrates SUB are brought out to the pre-processing unit 101, and processing substrates SUB are brought in from the post-processing unit 103. In one example, the processing substrates SUB housed in the substrate stocker 104 are in a horizontal position, while the processing substrates SUB being transported by the deposition unit 102 are in a vertical position.

[0066] The deposition unit 102 comprises a plurality of deposition chambers EV11 to EV20, a rotation chamber R11, and a plurality of transport chambers TR. The pre-processing unit 101, post-processing unit 103, substrate stocker 104, the plurality of deposition chambers EV11 to EV20, the rotation chamber R11, and the plurality of transport chambers TR are connected to each other and maintained under high vacuum. In one example, each part is 10 -3 Maintained at a pressure less than Pa, and furthermore, 10 -5 It is possible that the pressure may be maintained at around Pa.

[0067] The deposition chambers EV11 to EV15 are arranged in a row. Deposition chamber EV11 is connected to the pre-processing unit 101. Deposition chamber EV15 is connected to the rotation chamber R11. Transfer chambers TR are provided and connected to each other between deposition chambers EV11 and EV12, between deposition chambers EV12 and EV13, between deposition chambers EV13 and EV14, and between deposition chambers EV14 and EV15. The transfer path T11 is provided across deposition chambers EV11 to EV15 and the multiple transfer chambers TR.

[0068] The deposition chambers EV16 to EV20 are arranged in a row. Deposition chamber EV20 is connected to the post-processing unit 103. Deposition chamber EV16 is connected to the rotation chamber R11. Transfer chambers TR are provided and connected to each other between deposition chambers EV16 and EV17, between deposition chambers EV17 and EV18, between deposition chambers EV18 and EV19, and between deposition chambers EV19 and EV20. The transfer path T12 is provided across deposition chambers EV16 to EV20 and the multiple transfer chambers TR.

[0069] The deposition chamber EV11 is equipped with a deposition source S11. The deposition source S11 is configured to emit material toward the transport path T11 for forming a hole injection layer (HIL). The deposition chamber EV12 is equipped with a deposition source S12. The deposition source S12 is configured to emit material toward the transport path T11 for forming a hole transport layer HTL. The deposition chamber EV13 is equipped with a deposition source S13. The deposition source S13 is configured to radiate material toward the transport path T11 for forming the electron block layer EBL. The deposition chamber EV14 is equipped with a deposition source S14. The deposition source S14 is configured to emit material toward the transport path T11 for forming the light-emitting layer EML. The deposition chamber EV15 is equipped with a deposition source S15. The deposition source S15 is configured to emit material toward the transport path T11 for forming a hole block layer (HBL).

[0070] The deposition chamber EV16 is equipped with a deposition source S16. The deposition source S16 is configured to emit material toward the transport path T12 for forming the electron transport layer (ETL). The deposition chamber EV17 is equipped with a deposition source S17. The deposition source S17 is configured to emit material toward the transport path T12 for forming the electron injection layer EIL. The deposition chamber EV18 is equipped with a deposition source S18. The deposition source S18 is configured to radiate material toward the transport path T12 to form the upper electrode UE. The deposition chamber EV19 is equipped with a deposition source S19. The deposition source S19 is configured to emit material toward the transport path T12 for forming the first transparent layer TL1. The deposition chamber EV20 is equipped with a deposition source S20. The deposition source S20 is configured to discharge material toward the transport path T12 to form the second transparent layer TL2.

[0071] The transport paths T11 and T12 are located inside the deposition section 102. The deposition sources S11 to S20 are located outside the transport paths T11 and T12 in the deposition section 102. For example, focusing on deposition chambers EV11 and EV20, the transport paths T11 and T12 are located between deposition source S11 and deposition source S20. Also, focusing on deposition chambers EV15 and EV16, the transport paths T11 and T12 are located between deposition source S15 and deposition source S16.

[0072] The rotation chamber R11 is configured to transport the processed substrate SUB, which has been transported from the transport path T11, to the transport path T12. The rotation chamber R11 is equipped with a rotation mechanism RM11. The rotation mechanism RM11 holds the processed substrate SUB that has been transported in via the transport path T11 and is configured to be rotatable about a rotation axis A11.

[0073] The manufacturing process in the manufacturing apparatus 100 will be described below.

[0074] The processed substrate SUB, which has the lower electrode LE formed on it, is first unloaded from the substrate stocker 104 and brought into the pre-processing unit 101. In the pre-processing unit 101, predetermined pre-processing is performed on the processed substrate SUB. Subsequently, the processing substrate SUB is transported into the deposition chamber EV11. In the deposition chamber EV11, material emitted from the deposition source S11 is deposited onto the processing substrate SUB as it is transported along the transport path T11. This forms a hole injection layer HIL on the lower electrode LE. Subsequently, the processed substrate SUB is transported to the deposition chamber EV12 via the transport chamber TR. In the deposition chamber EV12, material emitted from the deposition source S12 is deposited onto the processed substrate SUB as it is transported along the transport path T11. This forms a hole transport layer HTL on top of the hole injection layer HIL.

[0075] Subsequently, the processed substrate SUB is transported to the deposition chamber EV13 via the transport chamber TR. In the deposition chamber EV13, material emitted from the deposition source S13 is deposited onto the processed substrate SUB as it is transported along the transport path T11. This forms an electron blocking layer EBL on top of the hole transport layer HTL. Subsequently, the processing substrate SUB is transported to the deposition chamber EV14 via the transport chamber TR. In the deposition chamber EV14, material emitted from the deposition source S14 is deposited onto the processing substrate SUB as it is transported along the transport path T11. This forms an emissive layer EML on top of the electron blocking layer EBL. Subsequently, the processed substrate SUB is transported to the deposition chamber EV15 via the transport chamber TR. In the deposition chamber EV15, material emitted from the deposition source S15 is deposited onto the processed substrate SUB as it is transported along the transport path T11. This forms a hole block layer HBL on top of the light-emitting layer EML.

[0076] Subsequently, the processing substrate SUB is moved into the rotation chamber R11. In the rotation chamber R11, the rotating mechanism RM11 holds the loaded processing substrate SUB. Then, the rotating mechanism RM11 rotates 180° while holding the processing substrate SUB. Subsequently, the processing substrate SUB is transported to the deposition chamber EV16. In the deposition chamber EV16, material emitted from the deposition source S16 is deposited onto the processing substrate SUB as it is transported along the transport path T12. This forms an electron transport layer ETL on top of the hole blocking layer HBL. Subsequently, the processing substrate SUB is transported to the deposition chamber EV17 via the transport chamber TR. In the deposition chamber EV17, material emitted from the deposition source S17 is deposited onto the processing substrate SUB as it is transported along the transport path T12. This forms an electron injection layer EIL on top of the electron transport layer ETL.

[0077] Subsequently, the processing substrate SUB is transported to the deposition chamber EV18 via the transport chamber TR. In the deposition chamber EV18, material emitted from the deposition source S18 is deposited onto the processing substrate SUB as it is transported along the transport path T12. This forms the upper electrode UE on top of the electron injection layer EIL.

[0078] Subsequently, the processing substrate SUB is transported to the deposition chamber EV19 via the transport chamber TR. In the deposition chamber EV19, material emitted from the deposition source S19 is deposited onto the processing substrate SUB as it is transported along the transport path T12. This forms the first transparent layer TL1 on the upper electrode UE. Subsequently, the processing substrate SUB is transported to the deposition chamber EV20 via the transport chamber TR. In the deposition chamber EV20, material emitted from the deposition source S20 is deposited onto the processing substrate SUB as it is transported along the transport path T12. This forms a second transparent layer TL2 on top of the first transparent layer TL1. Subsequently, the processing board SUB is transported to the post-processing unit 103. In the post-processing unit 103, predetermined post-processing is performed on the processing board SUB. Afterward, the processing board SUB is loaded into the board stocker 104.

[0079] Figure 6 is a cross-sectional view showing a typical configuration example of an EV11 deposition chamber.

[0080] In the deposition chamber EV11, the deposition source S11 faces the transport path T11 across the opening OP11 of the partition plate P11. The rail RL11 is provided on the transport path T11. The carrier CR, which holds the processing substrate SUB, is configured to move along the rail RL11.

[0081] The deposition source S11 is configured to heat and vaporize the material and continuously discharge the material while the manufacturing apparatus 100 is in operation. In the mode in which the discharged material is deposited onto the processing substrate SUB, the discharge port SA11 of the deposition source S11 is set to face the transport path T11 (or the processing substrate SUB). In the mode in which the discharge source S11 is not deposited onto the processing substrate SUB, it is rotated by approximately 90° from the illustrated state so that the discharge port SA11 faces inward, surrounded by the partition plate P11. Alternatively, although not shown in the diagram, a shutter that can be opened and closed may be provided in the opening OP11.

[0082] The other deposition chambers EV12 to EV20 shown in Figure 5 are configured in the same way as deposition chamber EV11 shown in Figure 6.

[0083] Figure 7 is a diagram illustrating an ionizer 200 applicable to the manufacturing apparatus 100 shown in Figure 5.

[0084] The vacuum chamber VC is 10 -3 It is maintained at a pressure less than Pa. The vacuum chamber VC is, for example, made of metal and is grounded. The vacuum chamber VC also has an inlet VCA for loading the processing substrate SUB (shown by the dotted line) and an outlet VCB for unloading the processing substrate SUB. A transport path T10 for transporting the processing substrate SUB is provided inside the vacuum chamber VC, extending from the inlet VCA to the outlet VCB.

[0085] The ionizer 200 is configured to generate ions inside the vacuum chamber VC. The ionizer 200 is installed, for example, on the top plate of the vacuum chamber VC, but it may also be installed on the side plate or the bottom plate. Such an ionizer 200 includes a sub-chamber 210, a gas supply unit 220, and an irradiation source 230.

[0086] The sub-chamber 210 is housed inside the vacuum chamber VC. The sub-chamber 210 also has a small opening 211. The sub-chamber 210 communicates with the vacuum chamber VC through the opening 211. There may be one opening 211 or multiple openings. The diameter of the opening 211 is, for example, about 2 to 10 mm.

[0087] The subchamber 210 is electrically insulated from the vacuum chamber VC. For example, the subchamber 210 is made of an insulating material such as ceramic, glass, or synthetic resin. In other examples, the subchamber 210 is made of metal and is connected to the vacuum chamber VC via an insulating material.

[0088] The gas supply unit 220 is configured to supply an inert gas to the inside of the sub-chamber 210. The flow rate of the inert gas supplied from the gas supply unit 220 is set to such an extent that the vacuum level of the vacuum chamber VC does not decrease, for example, to about 2 ml / min. Examples of inert gases include krypton, xenon, argon, and nitrogen. From the viewpoint of being efficiently ionized even at high vacuum and being inexpensive, it is desirable to use argon or nitrogen as the inert gas.

[0089] The irradiation source 230 is an energy source for ionizing the inert gas supplied to the sub-chamber 210. The irradiation source 230 is driven by the driver 231. For example, the irradiation source 230 is a light source configured to emit vacuum ultraviolet (VUV) light. In other examples, the irradiation source 230 is an X-ray source configured to emit X-rays or soft X-rays. The inert gas is supplied to the sub-chamber 210, and when vacuum ultraviolet or X-rays are emitted from the irradiation source 230, the inert gas is ionized. Furthermore, both positive and negative ions can be generated in the sub-chamber 210. These ions are used to neutralize the static electricity of the processing substrate SUB as it is transported inside the vacuum chamber VC.

[0090] In a vacuum chamber (VC) maintained at a high vacuum, there is inherently little gas present inside. Therefore, even if vacuum ultraviolet or X-rays are irradiated inside the vacuum chamber (VC), sufficient ions will not be generated.

[0091] According to this embodiment, an inert gas is supplied to the sub-chamber 210, and vacuum ultraviolet light or X-rays are irradiated onto the inert gas in the sub-chamber 210, thereby generating a high density of ions inside the sub-chamber 210. The generated ions are radiated from the opening 211 to the vacuum chamber VC.

[0092] If the processing substrate SUB being transported inside the vacuum chamber VC is undesirably charged, ions emitted from the sub-chamber 210 are attracted to the processing substrate SUB, neutralizing (discharging) the charge. This suppresses problems such as electrostatic discharge caused by the undesirable charging of the processing substrate SUB during the manufacturing process. Therefore, a decrease in reliability and yield can be suppressed.

[0093] From the standpoint of obtaining sufficient static discharge time, it is desirable to install the ionizer 200 described above in a vacuum chamber where the transport time or stay time of the processing substrate SUB is relatively long.

[0094] Furthermore, from the standpoint of increasing ion density, it is desirable that the ionizer 200 be driven continuously while the manufacturing apparatus 100 is in operation, regardless of whether or not there are processing substrates SUB being transported.

[0095] Figure 8 is a diagram illustrating an example of the installation of the ionizer 200 in the manufacturing apparatus 100 shown in Figure 5.

[0096] The ionizer 200 can be installed in any of the pre-processing section 101, the deposition section 102, the post-processing section 103, and the substrate stocker 104. In the deposition section 102, the ionizer 200 can be installed in any of the multiple deposition chambers EV11 to EV20, the multiple transport chambers TR, and the rotation chamber R11.

[0097] For example, if the ionizer 200 is installed in the deposition chamber EV11, the vacuum chamber VC shown in Figure 7 corresponds to the deposition chamber EV11, and the transport path T10 corresponds to the transport path T11. In this case, the vacuum chamber VC shown in Figure 7 is further equipped with a deposition source S11 in addition to the ionizer 200. When the ionizer 200 is installed in the deposition chambers EV11 to EV20, the type and flow rate of the inert gas are set so that the generated ions do not adversely affect the deposition process.

[0098] For example, if the ionizer 200 is installed in the rotation chamber R11, the vacuum chamber VC shown in Figure 7 corresponds to the rotation chamber R11, and the rotation mechanism RM11 is installed in the transport path T10. Since no material deposition takes place in the rotation chamber R11, there are many options for the type of inert gas. Also, because the processing substrate SUB rotates while being held, the dwell time of the processing substrate SUB in the rotation chamber R11 is relatively long, allowing for sufficient static elimination time.

[0099] When the ionizer 200 is provided in the substrate stocker 104, the processing substrate SUB stays in the stocker for a longer period, allowing for sufficient static elimination time.

[0100] As described above, according to this embodiment, it is possible to provide a manufacturing apparatus for a display device that can suppress a decrease in reliability and yield.

[0101] All manufacturing apparatuses that can be implemented by those skilled in the art by appropriately modifying the design based on the manufacturing apparatus described above as an embodiment of the present invention also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0102] Within the scope of the spirit of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, modifications made by a person skilled in the art to the above-described embodiments, such as adding, deleting, or changing the design of components, or adding, omitting, or changing the conditions of processes, are also included within the scope of the present invention, as long as they retain the gist of the present invention.

[0103] Furthermore, any other effects and advantages brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0104] DSP…display device 10…board 5... Ribs AP1, AP2, AP3... Openings 6...Bulkhead 61...Lower 62...Upper SP1, SP2, SP3... subpixels 20, 201, 202, 203... Display elements (organic EL elements) LE, LE1, LE2, LE3...lower electrode UE, UE1, UE2, UE3...upper electrode OR, OR1, OR2, OR3…Organic layer 100...Manufacturing equipment 101...Pre-processing section 102...Evaporation section 103...Post-processing section 104... PCB stocker T10~T12... Conveyor path EV11~EV20... Evaporation chamber S11~S20... Evaporation source TR... Conveyor Chamber R11...Rotation Chamber RM11...Rotation Mechanism 200...Ionizer 210...Sub-chamber 220...Gas supply unit 230...Irradiation source VC... Vacuum Chamber

Claims

1. A vacuum chamber and A transport path is provided inside the vacuum chamber for transporting a processing substrate for a display device, The vacuum chamber comprises an ionizer that generates ions inside the vacuum chamber, The ionizer mentioned above is A sub-chamber having an opening is housed inside the vacuum chamber, A gas supply unit that supplies inert gas to the sub-chamber, A device for manufacturing a display device, comprising: an irradiation source for irradiating vacuum ultraviolet light or X-rays to ionize an inert gas supplied inside the sub-chamber.

2. The vacuum chamber is 10 －３ A manufacturing apparatus for the display device according to claim 1, which is maintained at a pressure less than Pa.

3. The vacuum chamber is grounded, The apparatus for manufacturing a display device according to claim 1, wherein the sub-chamber is electrically insulated from the vacuum chamber.

4. The apparatus for manufacturing a display device according to claim 1, wherein the sub-chamber is formed of an insulating material.

5. The apparatus for manufacturing a display device according to claim 1, wherein the gas supply unit is configured to supply nitrogen or argon as an inert gas.

6. Furthermore, the vacuum chamber is equipped with an evaporation source housed inside the vacuum chamber. The apparatus for manufacturing a display device according to claim 1, wherein the deposition source is configured to discharge material toward a transport path for transporting the processing substrate on which the lower electrode is formed.

7. The apparatus for manufacturing a display device according to claim 6, wherein the material emitted from the deposition source is a material for forming an organic layer, an upper electrode, or a cap layer.

8. Furthermore, it is equipped with a rotating mechanism housed inside the vacuum chamber, The manufacturing apparatus for a display device according to claim 1, wherein the rotating mechanism is configured to rotate while holding the processing substrate.

9. A substrate stocker for housing a processing substrate for a display device, on which a lower electrode is formed, A pre-processing unit that performs pre-processing on the processing substrate, A deposition chamber configured to emit one of the materials of the organic layer, upper electrode, and cap layer onto the processing substrate, A transport chamber into which the processing substrate is transported, A rotation chamber configured to rotate while holding the processing substrate, A post-processing unit that performs post-processing on the aforementioned processing substrate, The substrate stocker, the pre-processing unit, the deposition chamber, the transport chamber, and at least one of the post-processing unit are provided with an ionizer that generates ions inside, The ionizer mentioned above is A sub-chamber housed inside a vacuum chamber and having an opening, A gas supply unit that supplies inert gas to the sub-chamber, A device for manufacturing a display device, comprising: an irradiation source for irradiating vacuum ultraviolet light or X-rays to ionize an inert gas supplied inside the sub-chamber.

10. The substrate stocker, the pre-processing unit, the deposition chamber, the transport chamber, and the post-processing unit are connected to each other, 10 －３ A manufacturing apparatus for the display device according to claim 9, which is maintained at a pressure less than Pa.

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