Power supply unit and image forming apparatus

Abstract

To reduce a peak value of a current flowing in a switching element at the start-up of a power supply device, thereby reducing a cost resulting from the switching element.SOLUTION: A power supply device comprises a power control unit that controls a switching operation by alternately bringing an FET 1 and an FET2 into conduction, thereby generating output voltage on a secondary side of a transformer. The power control unit performs the switching operation of the FET 2 (S307) while it brings the FET 1 into non-conduction (S306) in a period from when it stops the generation of the output voltage (S305: NO) until it resumes the generation of the output voltage (S301).SELECTED DRAWING: Figure 3

Description

Technical Field

[0005]

[0001] The present invention relates to a power supply device and an image forming apparatus, and more particularly, to a switching control method at the time of stop or start of an active clamp type switching power supply.

Background Art

[0002] In a switching power supply that converts an AC power supply such as a commercial power supply into a DC voltage, an active clamp method is used (see, for example, Patent Document 1). The switching power supply is mounted on, for example, an image forming apparatus.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] While FET1 and FET2, which are switching elements of a conventional switching power supply, alternately repeat on and off, a voltage proportional to the voltage across the secondary-side smoothing capacitor is applied to the capacitor connected in series with FET2. When the switching of FET1 and FET2 is stopped to stop the output, FET2 turns off, so the charge of the capacitor connected in series with FET2 remains. When the power supply restarts in this state and the switching of FET1 and FET2 resumes, the charge of the capacitor connected in series flows through FET2 at the timing when FET2 is turned on, causing an excessive current to flow through FET2. Therefore, it is necessary to increase the current rating of FET2, which increases the cost.

[0005] This invention was made under these circumstances, and aims to suppress the peak value of the current flowing through the switching element when the power supply is started up, thereby reducing costs associated with the switching element. [Means for solving the problem]

[0006] To solve the above-mentioned problems, the present invention has the following configuration. (1) A transformer having a primary winding and a secondary winding; a first switching element connected in series with the primary winding; a second switching element connected in parallel with the primary winding; a first capacitor connected in series with the second switching element and connected in parallel with the primary winding together with the second switching element; and a device that makes the first switching element and the second switching element conductive or non-conductive. Yo A power supply device comprising a control means for controlling the first switching element and the second switching element, wherein the control means alternately conducts the first switching element and the second switching element to generate an output voltage on the secondary side of the transformer, If the operation by the control means to cause the second switching element to be conductive and then to be deconductive is defined as a switching operation, and the operation of performing the switching operation periodically multiple times is defined as a multiple switching operation, The control means keeps the first switching element in a non-conductive state from the time the output voltage generation is stopped until the output voltage generation is restarted. Before Note multiple Perform switching operations i. The period of the multiple switching operations between stopping the generation of the output voltage and restarting the generation of the output voltage is shorter than the period of the multiple switching operations during the period in which the output voltage is being generated. A power supply device characterized by the following features. (2) A transformer having a primary winding and a secondary winding; a first switching element connected in series with the primary winding; a second switching element connected in parallel with the primary winding; a first capacitor connected in series with the second switching element and connected in parallel with the primary winding together with the second switching element; and a device that makes the first switching element and the second switching element conductive or non-conductive. Yo A power supply device comprising a control means for controlling the first switching element and the second switching element, wherein the control means alternately conducts the first switching element and the second switching element to generate an output voltage on the secondary side of the transformer, If the operation by the control means to cause the second switching element to be conductive and then to be deconductive is defined as a switching operation, and the operation of performing the switching operation periodically multiple times is defined as a multiple switching operation, The control means, when starting the generation of the output voltage, After performing the multiple switching operations in the first period, the multiple switching operations are performed again in the second period, and the cycle of the multiple switching operations performed in the first period is shorter than the cycle of the multiple switching operations performed in the second period. A power supply device characterized by the following features. (3) The power supply device is provided as described in (1) or (2) above. Image forming apparatus characterized by 。 [Effects of the Invention]

[0007] According to the present invention, the peak value of the current flowing through the switching element when the power supply unit is started can be suppressed, thereby reducing costs associated with the switching element. [Brief explanation of the drawing]

[0008] [Figure 1] Circuit diagrams of power supply units for Examples 1-3 [Figure 2] Circuit diagrams of the active clamp flyback power supply in Examples 1-3 [Figure 3] Flowchart of switching control in Example 1 [Figure 4] Schematic diagram of each waveform in the switching control of Example 1 [Figure 5] Flowchart of switching control in Example 2 [Figure 6] Schematic diagram of each waveform in the switching control of Example 2 [Figure 7] Schematic diagrams of the laser beam printers in Examples 1-3 [Modes for carrying out the invention]

[0009] Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings using examples. [Examples]

[0010] (Power supply unit configuration) Figure 1 is a diagram showing the schematic configuration of the power supply unit of Embodiment 1. As shown in Figure 1, the power supply unit has a rectifier and smoothing unit that rectifies and smooths the AC voltage input from the AC power supply 100, and a switching power supply 200. The rectifier and smoothing unit consists of a diode bridge 101 and a smoothing capacitor 102. The AC voltage input from the AC power supply 100 is full-wave rectified via a current fuse 103 for circuit protection and the diode bridge 101, smoothed by the smoothing capacitor 102 which is a second capacitor, and a DC voltage Vin is generated. The lower potential of the smoothing capacitor 102 is denoted as potential DCL, and the higher potential is denoted as potential DCH. The DC voltage Vin is input to the switching power supply 200, where the input DC voltage Vin is stepped down and the output voltage Vout, which is a DC voltage, is output.

[0011] (Configuration of switching power supplies) Figure 2 is a circuit diagram showing the circuit configuration of the switching power supply 200. In Figure 2, the switching power supply 200 is equipped with an isolated transformer T1 having a primary winding P1 and an auxiliary winding P2 on the primary side, and a secondary winding S1 on the secondary side. Energy is supplied from the primary winding P1 of the transformer T1 to the secondary winding S1 by switching control, which will be described later. A voltage equal to NP2 / NP1 × Vin (hereinafter referred to as the forward voltage) is induced in the auxiliary winding P2 of the transformer T1 during the ON period of the switching operation. The voltage induced in the auxiliary winding P2 is rectified and smoothed by a diode D4 and a capacitor C4, which are rectifier and smoothing means, to generate the power supply voltage V1. NP1 indicates the number of turns of the primary winding P1, and NP2 indicates the number of turns of the auxiliary winding P2.

[0012] The primary side of the switching power supply 200 has a field effect transistor (hereinafter referred to as FET1) connected in series to the primary winding P1, and a series circuit connected in parallel to the primary winding P1. Here, the series circuit is a circuit in which a capacitor C2 for voltage clamping, which is a first capacitor, and FET2 are connected in series. The capacitor C2 is connected in series to FET2 and, together with FET2, is connected in parallel to the primary winding P1. The capacitor C1 for voltage resonance connected in parallel to FET1 is provided to reduce the loss during the OFF state of the switching operations of FET1, which is the first switching element, and FET2, which is the second switching element. Instead of providing the capacitor C1 for voltage resonance, the capacitance between the drain terminal and the source terminal of FET1 may be used. Note that the diodes D1 and D2 are the body diodes of FET1 and FET2, respectively. On the other hand, on the secondary side of the switching power supply 200, a diode D11 and a capacitor Cll are provided as rectifying and smoothing means on the secondary side for the flyback voltage generated in the secondary winding S1.

[0013] (Feedback section) Also, the switching power supply 200 has a feedback section 205, which is feedback means for feeding back voltage information of the output voltage Vout output to a load connected to the secondary side to the primary side of the transformer T1. The feedback section 205 generates a voltage signal (hereinafter referred to as the FB terminal voltage) input to the FB terminal of the power supply control section 201 based on the target voltage and the output voltage Vout. The feedback section 205 includes a shunt regulator ICs, a photocoupler PC5, and resistors R51, R52, and R53. The target voltage of the output voltage Vout is set by the reference voltage of the reference terminal REF of the shunt regulator IC5, the resistor R52, and the resistor R53.

[0014] The FB terminal voltage is generated by charging the capacitor C6 with the power supply voltage V2 and the resistor R2 and discharging it by the feedback unit 205. Note that the capacitor C6 discharges when the photocoupler PC5 of the feedback unit 205 is in the conductive state and charges when the photocoupler PC5 is in the non-conductive state. When the output voltage Vout is the same voltage value as the target voltage, the FB terminal voltage becomes a predetermined voltage value. Also, when the output voltage Vout is higher than the target voltage, the FB terminal voltage becomes smaller, and when it is lower than the target voltage, the FB terminal voltage becomes larger.

[0015] (Configuration of the power supply control unit) In the first embodiment, the power supply control unit 201 uses arithmetic control means (such as a CPU, ASIC, etc.) that operates with a clock signal from an oscillator or the like. The power supply control unit 201 has a timer (not shown) for measuring time and a storage unit (not shown) such as a memory for storing data and the like.

[0016] The power supply control unit 201, which is the control means, controls the conduction and non-conduction of FET1 and FET2. Specifically, it controls FET1 and FET2 via the FET drive unit 202, which is the drive means for driving FET1 and FET2. The power supply control unit 201 generates the output voltage Vout on the secondary side of the transformer T by alternately conducting FET1 and FET, and controlling the switching operation of FET1 and FET2. The power supply voltage V2 generated by the DC / DC converter 204 is supplied to the VC terminal of the power supply control unit 201. The G terminal of the power supply control unit 201 is connected to the potential DCL. The power supply control unit 201 outputs a control signal DS1 for driving FET1 and a control signal DS2 for driving FET2 based on the FB terminal voltage and the VS terminal voltage described later. The control signal DS1 and the control signal DS2 are PWM signals output at a predetermined frequency and a predetermined on-duty ratio described later. The control signal DS1 and the control signal DS2 will be described later.

[0017] The VS terminal voltage is the voltage obtained by dividing the power supply voltage V1 by the first resistor R3 and the second resistor R4. When the power supply control unit 201 detects the VS terminal voltage, it can predict the DC voltage Vin and the AC power supply voltage 100 based on the voltage division ratio of resistors R3 and R4, and the winding ratio information of the number of turns NP1 of the primary winding P1 of the transformer T1 and the number of turns NP2 of the auxiliary winding P2.

[0018] (FET drive unit, DC / DC converter, startup circuit) The FET drive unit 202 is a circuit that generates the gate drive signal DL for FET1 according to the control signal DS1, and the gate drive signal DH for FET2 according to the control signal DS2. A power supply voltage V1 is supplied between the VC terminal and the G terminal of the FET drive unit 202. In addition, to drive FET2, a charge pump circuit consisting of a capacitor C5 and a diode D5 supplies the power supply voltage V1 between the VH terminal and the GH terminal. When the control signal DS1 is at a high level, the FET drive unit 202 sets the gate drive signal DL for FET1 to a high level, and FET1 turns on. Similarly, when the control signal DS2 is at a high level, the FET drive unit 202 sets the gate drive signal DH for FET2 to a high level, and FET2 turns on.

[0019] The DC / DC converter 204 is a three-terminal regulator or a step-down switching power supply. It generates a power supply voltage V2 from the power supply voltage V1 input to the VC terminal and outputs the generated power supply voltage V2 from the OUT terminal. The G terminal of the DC / DC converter 204 is connected to the potential DCL.

[0020] The startup circuit 203 is a three-terminal regulator or a step-down switching power supply. It generates a power supply voltage V1 from the DC voltage Vin input to the VC terminal and outputs the generated power supply voltage V1 from the OUT terminal. The G terminal of the startup circuit 203 is connected to the potential DCL. The startup circuit 203 operates only when the power supply voltage V1 generated from the voltage induced in the auxiliary winding P2 is below a predetermined voltage value, and is used to supply the power supply voltage V1 when the switching power supply 200 is started up.

[0021] (Control of the power supply unit) Figure 3 is a flowchart showing the control of the power supply control unit 201 in Embodiment 1. When a DC voltage Vin is supplied to the switching power supply 200, the power supply control unit 201 starts control from step (hereinafter referred to as S) 301 onwards. In S301, the power supply control unit 201 sets the control signal DS1 to an initial value under predetermined initial conditions and outputs it as a PWM signal. The initial value of the control signal DS1 may be stored in, for example, the memory unit (not shown) described above. Here, the control signal DS2 is output to be turned on during the off time of the control signal DS1, with a dead time, and off otherwise. The dead time is the period during which both the control signal DS1 and the control signal DS2 are off (low level). As a result, during the dead time, both FET1 and FET2 are in an off state (non-conductive state).

[0022] In S302, the power control unit 201 increases the on-duty cycle of the control signal DS1 (gate drive signal DL) from its initial value to prevent overshoot of the output voltage Vout and outputs a PWM signal. On-duty cycle is the proportion of the PWM signal that is high level in one cycle. Alternatively, the control signal DS1 may be controlled by the off-duty cycle, which is the proportion of the PWM signal that is low level in one cycle. In S303, the power control unit 201 determines whether the FB terminal voltage is within a predetermined range. If the power control unit 201 determines in S303 that the FB terminal voltage is not within the predetermined range, it returns to S302; if it determines that the voltage is within the predetermined range, it proceeds to S304. In this way, the power control unit 201 can safely raise the output voltage Vout to the target voltage by gradually increasing the on-duty cycle from the initial condition (initial value). The control signal DS2 (gate drive signal DH) is output to be on during the off-time of the control signal DS1, with a dead time, and off otherwise. In other words, the control signal DS2 should be controlled according to the control signal DS1. When the FB terminal voltage falls within a predetermined range in S303, the power supply control unit 201 determines that the output voltage Vout has reached the target voltage and proceeds to S304.

[0023] In S304, the power control unit 201 determines the on-duty cycle of the control signal DS1 based on the VS terminal voltage and the FB terminal voltage, and outputs a PWM signal. The power control unit 201 outputs a control signal DS2, which is turned on during the off-time of the control signal DS1 with a dead time, and turned off otherwise. In other words, the control signal DS2 should be controlled according to the control signal DS1. As a result, the power control unit 201 can maintain the output voltage Vout at a constant voltage even if the load of the DC voltage Vin and output voltage Vout changes. Details of the operation will be described later.

[0024] In S305, the power control unit 201 determines whether to continue outputting the PWM signals of control signals DS1 and DS2 determined in S304. If the power control unit 201 determines in S305 not to continue outputting the PWM signals, it proceeds to S306. If the power control unit 201 determines in S305 to continue outputting the PWM signals, it returns to S304. In Embodiment 1, to prevent control signals DS1 and DS2 from being output as PWM signals while the DC voltage Vin is below a predetermined voltage, the power control unit 201 proceeds to S306 when it detects that the VS terminal voltage is below a predetermined voltage. Factors that cause the DC voltage Vin to be below a predetermined voltage, in other words, the VS terminal voltage to be below a predetermined voltage, include, for example, the power of the device being turned off, or a power outage.

[0025] In S306, the power control unit 201 sets the control signal DS1 to a low level, stopping the switching operation of FET1. In S307, the power control unit 201 determines the on-time and frequency of the control signal DS2 and outputs a PWM signal. Details will be described later. In S308, the power control unit 201 determines whether the voltage of the voltage clamping capacitor C2 is less than (sufficiently less than) a predetermined voltage. In Embodiment 1, the power control unit 201 determines whether the voltage of capacitor C2 is below a predetermined voltage based on the relationship between the number of PWM signal outputs and the voltage of capacitor C2, which has been determined in advance through experiments, etc., by determining whether the PWM signal of control signal DS2 has been output a predetermined number of times. Note that information (e.g., a table) showing the relationship between the number of PWM signal outputs and the voltage of capacitor C2 may be stored in the storage unit mentioned above. The power control unit 201 may determine that the voltage of capacitor C2 has fallen below a predetermined voltage based on the information read from the storage unit and the number of PWM signal outputs. The number of PWM signal outputs may be counted by the power control unit 201 using a counter (not shown). In S308, if the power supply control unit 201 determines that the capacitor C2 is not below a predetermined voltage, it returns to processing S307; otherwise, it proceeds to processing S309.

[0026] In S309, the power control unit 201 lowers the control signal DS2 to a low level, turning off the switching operation of FET2 and shutting down the power supply. After the power supply is shut off, for example, when the power outage is restored and the DC voltage Vin is input, the power control unit 201 restarts operation from S300.

[0027] (Timing chart of control by the power control unit) Figure 4 shows the voltage waveforms of (i) the gate drive signal DL, (ii) the gate drive signal DH, and (iii) the output voltage Vout from S304 to S310, which are processes performed by the power control unit 201 in Figure 3. Also, Figure 4 shows the voltage waveform of (iv) capacitor C2 and the current waveform of FET2. In Figure 4, time is shown on the horizontal axis. Note that "S304" etc. in Figure 4 correspond to the step numbers in Figure 3. Furthermore, the voltage waveform of capacitor C2 (iv) is the waveform when the potential DCH is used as the reference, and the current waveform of FET2 is shown with the current flowing from capacitor C2 to FET2 as positive, i.e., the direction in which the current flows out of capacitor C2 as positive.

[0028] In S304, gate drive signals DH and DL are output as PWM signals according to control signals DS1 and DS2. Therefore, gate drive signal DL is output with the same on-duty cycle and frequency as control signal DS1. In addition, gate drive signal DH is output to be turned on during the off-time of gate drive signal DL, with a dead time (Td in Figure 4), and off at all other times.

[0029] When the gate drive signal DL reaches a high level, energy is stored in transformer T1. When the gate drive signal DL reaches a low level, the energy stored in transformer T1 flows through diode D2 to capacitor C2. Consequently, the voltage across capacitor C2 rises.

[0030] After the dead time, when the gate drive signal DH reaches a high level, the current that was flowing through diode D2 now flows through FET2. While the gate drive signal DH is at a high level, charging and discharging occur due to resonance between capacitor C2 and transformer T1, causing the voltage across capacitor C2 to rise and then fall. The current through FET2 also gradually decreases, and current flows from capacitor C2 to discharge. During this time, energy is stored in the output voltage Vout, and the output voltage Vout is maintained at a constant voltage.

[0031] When the gate drive signal DH goes low, the voltage across capacitor C2 becomes constant, and the current across FET2 becomes zero. After a dead time, when the gate drive signal DL goes high again, energy is stored in transformer T1. The above control is repeated until the condition in S305 of Figure 3 is met (S304⇔S305).

[0032] When the conditions in S305 are met, in S306, the gate drive signal DL is fixed at a low level. As a result, energy is no longer stored in the transformer T1, and energy is no longer supplied to the secondary side. Therefore, the output voltage Vout is consumed by the connected load and gradually decreases. Also, energy is no longer supplied to the capacitor C2, and the charge on the capacitor C2 decreases.

[0033] In S307, while the gate drive signal DL remains at a low level, the gate drive signal DH is output at a predetermined on-time and a predetermined frequency. In Example 1, the gate drive signal DH is PWM-output at a higher frequency than the PWM signal output in S304. At this time, since no energy is supplied to the capacitor C2, when the gate drive signal DH is at a high level, the charge flows out from the capacitor C2. Therefore, when the gate drive signal DH is at a high level, the current of FET2 flows to reduce the voltage of the capacitor C2, and the voltage of the capacitor C2 decreases. Also, by reducing the high-level time of the PWM signal of the gate drive signal DH and shortening the on-time of FET2, the charge of the capacitor C2 can be discharged while reducing the current peak of FET2.

[0034] In FIG. 4, the current peak value was Ip1 for the gate drive signal DH output in S304, but the current peak value becomes Ip2 smaller than Ip1 (Ip2 < Ip1) after S306. In Example 1, in order to shorten the high-level time of the gate drive signal DH, the frequency of the PWM signal is increased. Note that in order to shorten the high-level time of the gate drive signal DH, the on-duty may be decreased. Also, in FIG. 4(ii), the power supply control unit 201 turns on / off FET2 a plurality of times, but the on / off switching operation may be performed at least two or more times.

[0035] In S308, the gate drive signal DH is output a predetermined number of times, and in S309, when the gate drive signal DH is fixed at a low level, the power supply stops. Note that the output voltage Vout decreases due to the connected load. After the power supply stops, for example, when the power is restored from a power outage and the DC voltage Vin is input, the operation starts again from S300. By such control, the voltage of the capacitor C2 can be sufficiently reduced when the power supply stops.

[0036] If the voltage across capacitor C2 remains high when the power supply is shut off and then restarted, a large current will flow from capacitor C2 through FET2 to transformer T1 when the gate drive signal DH becomes high level in S301. Therefore, it was necessary to select FET2 with a high current rating. On the other hand, by lowering the voltage across capacitor C2 in advance when the system is shut off using the control method in Example 1, the current flowing through FET2 is reduced, allowing the use of an FET with a lower current rating, thus reducing the cost of FET2.

[0037] The power supply control unit 201 should control the switching operation of FET2 while FET1 is non-conducting between the time output voltage Vout generation is stopped and the time output voltage Vout generation is restarted. The power supply control unit 201 should conduct FET2 at least twice between the time output voltage Vout generation is stopped and the time output voltage Vout generation is restarted. The power supply control unit 201 should make the time FET2 conducts after output voltage Vout generation is stopped shorter than the time FET2 conducted before output voltage Vout generation is stopped. The power supply control unit 201 may also make the switching frequency of FET2 after output voltage Vout generation is stopped higher than the switching frequency of FET2 before output voltage Vout generation is stopped.

[0038] In Example 1, in S308, the power supply control unit 201 determined that the voltage across capacitor C2 was less than a predetermined voltage by determining whether it had output the control signal DS2 a predetermined number of times. However, the determination that the voltage across capacitor C2 is less than a predetermined voltage is not limited to this. For example, a voltage detection circuit may be provided to detect the voltage across capacitor C2, and the power supply control unit 201 may determine that the voltage across capacitor C2 is less than a predetermined voltage based on the detection result of the voltage detection circuit. Alternatively, a current detection circuit may be provided to detect the current flowing through capacitor C2, taking advantage of the correlation between the voltage across capacitor C2 and the discharge current. By monitoring the change in the discharge current, the power supply control unit 201 may determine that the voltage across capacitor C2 is less than a predetermined voltage based on the detection result of the current detection circuit. This allows for the detection of residual charge in capacitor C2, which can reduce the residual charge to near zero, thereby reducing the current flowing through FET2 and preventing failure.

[0039] In Example 1, the control signal DS2 in S307 is output at a frequency earlier (higher) than the frequency of the PWM signal in S304, but this is not limited to this. For example, the high-level time of the control signal DS2 can be shortened to shorten the on-time of FET2. For example, the high-level time of the control signal DS2 can be shortened at the same frequency to shorten the on-time of FET2.

[0040] In Example 1, the control signal DS2 was output as a fixed PWM signal in S307, but this is not the only option. For example, a voltage detection circuit that detects the voltage of capacitor C2 may be provided, and the power supply control unit 201 may change the high-level time and frequency of the PWM signal based on the detected voltage. Since the current of FET2 changes with the voltage of capacitor C2, the control signal DS2 can be optimized within a range that does not exceed the current rating of FET2 for each voltage of capacitor C2. This allows the voltage of capacitor C2 to be lowered quickly and safely.

[0041] Furthermore, the power control unit 201 may change the high-level time and frequency of the PWM signal of the control signal DS2 based on the VS terminal voltage. The charge stored in capacitor C2 is returned to the smoothing capacitor 102 via transformer T2 in S307. Since different DC voltages Vin result in different discharge times for capacitor C2, the voltage of capacitor C2 can be rapidly reduced within a range that does not exceed the current rating of FET2 by detecting the VS terminal voltage and changing the control signal DS2.

[0042] The determination that the voltage across capacitor C2 has become sufficiently low, in other words, below a predetermined voltage, can be made as follows: The power supply control unit 201 may have a memory unit that stores information showing the relationship between the number of switching operations of FET2 and the voltage across capacitor C2, and it may determine the voltage across capacitor C2 based on the information stored in the memory unit and the number of switching operations of FET2. The power supply control unit 201 can then control the switching operation of FET2 until the determined voltage across capacitor C2 falls below a predetermined voltage. Furthermore, for example, the switching power supply 200 includes a voltage detection circuit which is a first voltage detection means for detecting the voltage of capacitor C2, and the power supply control unit 201 only needs to control the switching operation of FET2 until the detected voltage of capacitor C2 falls below a predetermined voltage. Alternatively, for example, the switching power supply 200 may include a current detection circuit, which is a current detection means for detecting the current that flows when the capacitor C2 discharges, and the power supply control unit 201 may determine the voltage of the capacitor C2 based on the detected current. The power supply control unit 201 should control the switching operation of the FET2 until the determined voltage of the capacitor C2 falls below a predetermined voltage. Furthermore, the switching power supply 200 includes a voltage detection circuit, which is a second voltage detection means for detecting the voltage of the smoothing capacitor 102, and the power supply control unit 201 may determine the voltage of capacitor C2 based on the detected voltage. The power supply control unit 201 can then control the switching operation of FET2 until the determined voltage of capacitor C2 falls below a predetermined voltage.

[0043] In Example 1, the operation of switching FET2 while FET1 is off was performed after determining whether or not to continue outputting the PWM signal in S305 (S305), but this is not limited to this. For example, the timing of the operations from S306 to S308 can be performed before the power supply is started up again. In other words, it is sufficient that the voltage across capacitor C2 drops before the switching power supply 200 is started up again.

[0044] Thus, according to Example 1, when stopping the switching operation, the charge in capacitor C2 can be discharged by controlling the switching of FET2 while keeping FET1 turned off. Because the charge remaining in capacitor C2 is small, the current flowing from capacitor C2 to FET2 can be reduced when restarting the power supply. This allows the use of a switching FET with a lower current rating, thereby reducing the cost of FET2.

[0045] As described above, according to Example 1, the peak value of the current flowing through the switching element when the power supply is started can be suppressed, and costs related to the switching element can be reduced. [Examples]

[0046] In Example 2, the configuration of the power supply unit, the configuration of the switching power supply, the feedback unit, the configuration of the power control unit, and the FET drive unit are the same as in Example 1, and their explanation will be omitted.

[0047] (Control of the power supply unit) Figure 5 is a flowchart showing the control of the power supply control unit 201 in Embodiment 2. When a DC voltage Vin is supplied to the switching power supply 200, the power supply control unit 201 starts control from S501 onwards. In S501, the power supply control unit 201 outputs control signals DS1 and DS2 at predetermined on-times and frequencies. Details will be described later. In S502, the power supply control unit 201 determines whether the voltage of the voltage clamp capacitor C2 is lower than a predetermined voltage. In Embodiment 2, based on the relationship between the number of PWM signal outputs and the voltage of capacitor C2, which has been determined in advance through experiments, the power supply control unit 201 determines whether the voltage of capacitor C2 is low based on whether the control signals DS1 and DS2 have been output a predetermined number of times.

[0048] In S502, the power control unit 201 determines that the voltage of capacitor C2 is not less than a predetermined voltage, and returns to S501. If it determines that the voltage is less than a predetermined voltage, it proceeds to S503. The processes from S503 to S508 are the same as those from S301 to S306 as explained in Figure 3, and are therefore omitted from the explanation. In S508, the power control unit 201 stops the switching operation and shuts off the power supply by setting the control signals DS1 and DS2 to low levels. After the power supply is shut off, for example, when a power outage is restored and the DC voltage Vin, which is the input voltage, is input again, the operation starts again from S501.

[0049] (Timing chart of control by the power control unit) Figure 6 shows the (i) control signal DS1, (ii) control signal DS2, (iii) gate drive signal DL, and (iv) gate drive signal DH from the time the power supply is shut off in the process of S508 in Figure 5 until the power supply is started up and proceeds from S501 to S505. Figure 6 also shows (v) the voltage waveform of capacitor C2 and (vi) the current waveform of FET2. The horizontal axis in Figure 6 represents time. The voltage of capacitor C2 is taken with the potential DCH as the reference, and the current waveform of FET2 is taken with the current flowing from capacitor C2 to FET2 as positive. "S508" etc. in Figure 6 correspond to the step numbers in Figure 5.

[0050] At S508, control signals DS1 and DS2 are at a low level. Therefore, gate drive signals DL and DH are also at a low level. Since gate drive signal DH is off, no current flows through FET2, and the voltage across capacitor C2 remains the same as it was at S507.

[0051] At S508, the switching power supply 200 stops, and until the switching power supply 200 starts up again (DC voltage Vin is supplied), control signals DS1 and DS2 remain at a low level, and therefore gate drive signals DL and DH also remain at a low level. During this time, capacitor C2 does not discharge and maintains its voltage. Since gate drive signal DH is at a low level and FET2 does not turn on, no current flows through FET2.

[0052] When S501 occurs, control signals DS1 and DS2 begin outputting as PWM signals, and the output of PWM signals continues until the condition of S502 is met. The on-time Ton2 of control signal DS2 at this time is shorter than the on-time Ton1 of control signal DS2 in S503, which will be described later (Ton2 <Ton1)。

[0053] The gate drive signal DL alternates between high and low levels, similar to the control signal DS1. On the other hand, the gate drive signal DH remains low because the voltage at the VH terminal of the FET drive unit 202 is not charged. While the gate drive signal DH is low, the voltage across capacitor C2 is maintained, and no current flows through FET2. During this time, each time the gate drive signal DL goes low, power is supplied to the VH terminal from the power supply voltage V1. When sufficient power is supplied to the VH terminal at timing t1, the gate drive signal DH is output as a PWM signal according to the control signal DS2. When the gate drive signal DH goes high, FET2 flows current towards transformer T1, and the voltage across capacitor C2 decreases. At this time, since the control signal DS2 is a PWM signal with a short on-time, the current flowing through FET2 during one cycle of the PWM signal can be reduced, and the current peak can be suppressed. This allows the use of a FET with a smaller rating for FET2, thus reducing costs. Subsequently, as the voltage across capacitor C2 decreases, the current peak of FET2 decreases (arrow α).

[0054] In S503, the initial control signal DS1 is output as a PWM signal. Control signal DS2 is output so that it becomes high during the low-level state of control signal DS1, with a dead time in between, and remains low otherwise. Gate drive signals DL and DH are output as PWM signals according to control signals DS1 and DS2.

[0055] To prevent output voltage Vout from overshooting while bringing it closer to the target voltage, S503 reduces the on-duty cycle of the PWM signal of control signal DS1, and S504 gradually increases the on-duty cycle of the PWM signal. In other words, S503 increases the high-level time of the control signal DS2, thereby increasing the on-time of FET2.

[0056] If steps S501 and S502 are omitted and the transition to S503 is made while the voltage of capacitor C2 remains high, the on-time of FET2 will be long, resulting in a large current flowing through FET2 when it is turned on. Therefore, it was necessary to select FET2 with a high current rating. On the other hand, in Embodiment 2, at S503, the voltage of capacitor C2 is sufficiently low, so the current flowing through FET2 is small, and an FET with a lower current rating can be used, thus reducing the cost of FET2. Subsequently, in S504, the on-duty cycle of the control signal DS1 is gradually increased, supplying energy to the secondary side and raising the output voltage Vout to the target voltage. In summary, when the power supply control unit 201 starts generating the output voltage Vout, it turns on FET2 for a shorter time than the time required to turn on FET2 in order to generate the output voltage Vout. The power supply control unit 201 controls FET1 and FET2 via the FET drive unit 202, and FET2 remains non-conductive until the charge pump circuit is charged to a predetermined voltage, regardless of the control of the power supply control unit 201.

[0057] In Example 2, in S502, it was determined whether the voltage of capacitor C2 was less than a predetermined voltage based on whether the control signal DS2 was output a predetermined number of times, but this is not limited to this. For example, a voltage detection circuit may be provided on capacitor C2 for detection. Alternatively, taking advantage of the correlation between the voltage of capacitor C2 and the discharge current, a current detection circuit may be provided to detect the current flowing through capacitor C2, and the change in the discharge current may be monitored to make a determination.

[0058] In Example 2, the control signal DS2 in S501 was set to a fixed PWM signal output, but this is not the only option. For example, a voltage detection circuit that detects the voltage of capacitor C2 may be provided, and the high-level time (on time) and frequency of the PWM signal may be changed based on the detected voltage. Since the current of FET2 changes with the voltage of capacitor C2, the control signal DS2 can be optimized within a range that does not exceed the current rating of FET2 for each voltage of capacitor C2. This allows the voltage of capacitor C2 to be lowered quickly and safely.

[0059] Furthermore, the high-level time (on-time) and frequency of the PWM output of the control signal DS2 may be changed based on the VS terminal voltage. The charge stored in capacitor C2 is returned to the smoothing capacitor 102 via transformer T2 in S501. Since different DC voltages Vin result in different discharge times for capacitor C2, the voltage across capacitor C2 can be rapidly reduced within a range that does not exceed the current rating of FET2 by detecting the VS terminal voltage and changing the control signal DS2.

[0060] In Example 2, S501 and S502 were performed immediately before the switching operation started, but this is not limited to that. For example, they may be performed between the moment S507 determines that the output of the PWM signal will not be continued and the start of the next switching operation.

[0061] As explained above, according to Embodiment 2, by controlling FET2 to be briefly turned on at the start of the switching operation, the current flowing from capacitor C2 to FET2 can be suppressed while reducing the voltage across capacitor C2. Furthermore, even if the VH terminal voltage required for switching FET2 is insufficient, the VH terminal voltage can be charged by turning on FET1 when FET2 is off, thereby enabling FET2 to be switched. This allows the use of a switching FET with a lower current rating, thereby reducing the cost of FET2.

[0062] As described above, according to Example 2, the peak value of the current flowing through the switching element when the power supply is started can be suppressed, and costs related to the switching element can be reduced. [Examples]

[0063] [Explanation of laser beam printers] Figure 7 shows a schematic configuration of a laser beam printer as an example of an image forming apparatus. The laser beam printer 1000 (hereinafter referred to as printer 1000) comprises a photosensitive drum 1010, a charging unit 1020, and a developing unit 1030. The photosensitive drum 1010 is an image carrier on which an electrostatic latent image is formed. The charging unit 1020 uniformly charges the photosensitive drum 1010. The optical scanning device 1025, which is an exposure means, forms an electrostatic latent image by scanning laser light corresponding to the image data onto the photosensitive drum 1010. The developing unit 1030 forms a toner image by developing the electrostatic latent image formed on the photosensitive drum 1010 with toner. The toner image formed on the photosensitive drum 1010 (on the image carrier) is transferred by the transfer unit 1050 to a sheet P as a recording material supplied from the cassette 1040, and the unfixed toner image transferred to the sheet P is fixed by the fuser 1060 and discharged to the tray 1070. The photosensitive drum 1010, charging unit 1020, developing unit 1030, and transfer unit 1050 constitute the image forming unit. The printer 1000 also includes a power supply unit 1080, which supplies power to the drive unit such as the motor and the control unit 5000. The power supply unit 1080 includes, for example, the switching power supply 200 of Embodiments 1 and 2.

[0064] The control unit 5000 has a CPU (not shown) and controls the image forming operation by the image forming unit and the transport operation of the sheet P. After the printer 1000 finishes printing, it transitions to a standby state where it can immediately perform printing operations after a predetermined time has elapsed. After another predetermined time has elapsed, the printer 1000 transitions from the standby state to a sleep state, which is a low power consumption mode, in order to reduce power consumption while in standby mode. The printer 1000 has three states: a second mode, the sleep state and the standby state, and a first mode, the printing state, and the control unit 5000 transitions to each of these states. Note that the image forming apparatus to which the switching power supply 200 of Examples 1 and 2 included in the power supply unit 1080 can be applied is not limited to the configuration illustrated in Figure 7.

[0065] As described above, according to Example 3, the peak value of the current flowing through the switching element when the power supply is started can be suppressed, and costs related to the switching element can be reduced. [Explanation of symbols]

[0066] 201 Power Control Unit C2 Capacitor FET1, FET2 Field-effect transistors T Transformer

Claims

1. A transformer having a primary winding and a secondary winding, A first switching element connected in series with the primary winding, A second switching element connected in parallel to the primary winding, A first capacitor is connected in series with the second switching element and in parallel with the primary winding together with the second switching element, Control means for controlling the first switching element and the second switching element to conduct or not conduct, A power supply device comprising, wherein the control means alternately conducts the first switching element and the second switching element to generate an output voltage on the secondary side of the transformer, If the control means defines the operation of causing the second switching element to be conductive and then deconductive as a switching operation, and the operation of performing the switching operation periodically multiple times is defined as a multiple switching operation, The control means performs the multiple switching operations with the first switching element de-conducting between the time the output voltage generation is stopped and the time the output voltage generation is restarted. The period of the multiple switching operations between stopping the generation of the output voltage and restarting the generation of the output voltage is shorter than the period of the multiple switching operations during the period in which the output voltage is being generated. A power supply device characterized by the following features.

2. The power supply device according to claim 1, characterized in that the control means makes the time during which the second switching element is conducted in the switching operation after the generation of the output voltage is stopped shorter than the time during which the second switching element is conducted in the switching operation during the period in which the output voltage is generated.

3. The system includes a storage unit that stores information indicating the relationship between the number of switching operations of the second switching element and the voltage of the first capacitor, The power supply device according to claim 2, characterized in that the control means determines the voltage of the first capacitor based on the information stored in the storage unit and the number of switching operations of the second switching element, and performs the switching operation of the second switching element until the determined voltage of the first capacitor falls below a predetermined voltage.

4. The system includes a first voltage detection means for detecting the voltage of the first capacitor, The power supply device according to claim 2, characterized in that the control means performs the switching operation of the second switching element until the voltage of the first capacitor detected by the first voltage detection means falls below a predetermined voltage.

5. The system includes a current detection means for detecting the current that flows when the first capacitor discharges, The power supply device according to claim 2, characterized in that the control means determines the voltage of the first capacitor based on the current detected by the current detection means, and performs the switching operation of the second switching element until the determined voltage of the first capacitor falls below a predetermined voltage.

6. A transformer having a primary winding and a secondary winding, A first switching element connected in series with the primary winding, A second switching element connected in parallel to the primary winding, A first capacitor is connected in series with the second switching element and in parallel with the primary winding together with the second switching element, Control means for controlling the first switching element and the second switching element to conduct or not conduct, A power supply device comprising, wherein the control means alternately conducts the first switching element and the second switching element to generate an output voltage on the secondary side of the transformer, If the control means defines the operation of causing the second switching element to be conductive and then deconductive as a switching operation, and the operation of performing the switching operation periodically multiple times is defined as a multiple switching operation, The control means, when starting the generation of the output voltage, performs the multiple switching operations in the first period, and then performs the multiple switching operations in the second period. The period of the multiple switching operations performed during the first period is shorter than the period of the multiple switching operations performed during the second period. A power supply device characterized by the following features.

7. The system includes a storage unit that stores information indicating the relationship between the number of switching operations of the second switching element and the voltage of the first capacitor, The power supply device according to claim 6, characterized in that the control means determines the voltage of the first capacitor based on the information stored in the storage unit and the number of switching operations of the second switching element, and performs the switching operation of the second switching element until the determined voltage of the first capacitor falls below a predetermined voltage.

8. The system includes a first voltage detection means for detecting the voltage of the first capacitor, The power supply device according to claim 6, characterized in that the control means performs the switching operation of the second switching element until the voltage of the first capacitor detected by the first voltage detection means falls below a predetermined voltage.

9. The system includes a current detection means for detecting the current that flows when the first capacitor discharges, The power supply device according to claim 6, characterized in that the control means determines the voltage of the first capacitor based on the current detected by the current detection means, and performs the switching operation of the second switching element until the determined voltage of the first capacitor falls below a predetermined voltage.

10. The system includes a first voltage detection means for detecting the voltage of the first capacitor, The power supply device according to any one of claims 1, 2, or 6, characterized in that the control means changes the on-time or frequency of the PWM signal for controlling the second switching element based on the voltage detected by the first voltage detection means.

11. An image forming apparatus characterized by comprising a power supply device according to any one of claims 1 to 9.

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