Memory device and its operating method

Abstract

To provide a memory device with improved operation speed and an operation method thereof.SOLUTION: In a storage device, a memory device includes a control logic for grouping a current sensing circuit and a plurality of page buffers into a plurality of page buffer groups and controlling to perform a current sensing operation. The control logic determines a logical group number and a physical group number corresponding to a column address of each of the plurality page buffers, performs a first operation, which is the current sensing operation for each of the page buffer groups having the same logical group number, and controls to perform a second operation, which is the current sensing operation for each of the page groups having the same physical group number. The current sensing circuit outputs a verification pass signal in response to the results of the first operation and the second operation all meeting pass criteria.SELECTED DRAWING: Figure 11

Description

Technical Field

[0001] The present invention relates to an electronic device, and more specifically, to a memory device and an operation method thereof.

Background Art

[0002] A storage device is a device that stores data under the control of a host device such as a computer or a smartphone. The storage device can include a memory device that stores data and a memory controller that controls the memory device. The memory device can be classified into a volatile memory device and a non-volatile memory device.

[0003] A volatile memory device can be a memory device that stores data only while power is supplied and the stored data disappears when the power supply is cut off. The volatile memory device may include a static random access memory (SRAM), a dynamic random access memory (DRAM), and the like.

[0004] A non-volatile memory device is a memory device in which data does not disappear even when the power supply is cut off, and includes a ROM (Read Only Memory), a PROM (Programmable ROM), an EPROM (Electrically Programmable ROM), an EEPROM (Electrically Erasable and Programmable ROM), and a flash memory.

Summary of the Invention

Problems to be Solved by the Invention

[0005] Embodiments of the present invention provide a memory device having an improved operation speed and an operation method thereof.

Means for Solving the Problems

[0006] A memory device according to an embodiment of the present invention includes a memory block including a memory cell, a read and write circuit including a plurality of page buffers each connected to the memory cell through a plurality of bit lines, a current sensing circuit that performs a verification operation comparing sensing voltages received from the plurality of page buffers with a reference voltage corresponding to a number of error-correctable bits, and control logic that groups the plurality of page buffers into a plurality of page buffer groups and controls the current sensing circuit to perform the verification operation for each of the plurality of page buffer groups, wherein the control logic determines a logical group number and a physical group number corresponding to the column address of each of the plurality of page buffers, controls the current sensing circuit to perform a first verification operation for each of the page buffer groups with the same logical group number, and controls the current sensing circuit to perform a second verification operation for each of the page buffer groups with the same physical group number, and the current sensing circuit can output a verification pass signal corresponding to the fact that all results of the first and second verification operations satisfy the pass criteria.

[0007] A method for operating a memory device, which includes a read and write circuit including a plurality of page buffers each connected to a memory cell in a memory block through a plurality of bit lines, a current sensing circuit that performs a verification operation comparing sensing voltages received from the plurality of page buffers with a reference voltage corresponding to a number of error-correctable bits, and a control logic that groups the plurality of page buffers into a plurality of page buffer groups and controls the current sensing circuit to perform the verification operation for each of the plurality of page buffer groups, can include the steps of: determining page buffers whose column addresses are consecutive and corresponding to a predetermined number of page buffers from the plurality of page buffers with the same logical group number; determining a predetermined number of adjacent page buffers from the plurality of page buffers with the same physical group number; performing a first verification operation for each of the page buffer groups with the same logical group number; performing a second verification operation for each of the page buffer groups with the same physical group number; and outputting a verification pass signal in response to the results of the first and second verification operations all satisfying the pass criteria. [Effects of the Invention]

[0008] This technology may provide a memory device with improved accuracy in verification operations. [Brief explanation of the drawing]

[0009] [Figure 1] These are drawings illustrating a storage device including a memory device according to an embodiment of the present invention. [Figure 2] This is a diagram illustrating the memory device shown in Figure 1. [Figure 3] This diagram illustrates the structure of one of the memory blocks shown in Figure 2. [Figure 4] This is a block diagram illustrating the verification operation according to an embodiment of the present invention. [Figure 5] These drawings illustrate the verification path and verification failure according to an embodiment of the present invention. [Figure 6] These drawings illustrate a method for determining logical group numbers and physical group numbers according to embodiments of the present invention. [Figure 7] This is a block diagram illustrating a current sensing circuit according to an embodiment of the present invention. [Figure 8] Figure 7 is a diagram illustrating the sensing voltage receiving unit and the comparison voltage generation unit. [Figure 9] This diagram illustrates the comparison circuit and reference voltage generation unit shown in Figure 7. [Figure 10] This is a diagram illustrating a method for grouping multiple page buffers into a physical group according to an embodiment of the present invention. [Figure 11] This is a flowchart illustrating how to perform a verification operation in an embodiment of the present invention. [Figure 12] This drawing illustrates a data processing system including a solid-state drive according to an embodiment of the present invention. [Figure 13] Figure 12 is a diagram illustrating the configuration of the controller. [Figure 14] This drawing illustrates a data processing system including a data storage device according to an embodiment of the present invention. [Figure 15] This drawing illustrates a data processing system including a data storage device according to an embodiment of the present invention. [Figure 16] This drawing illustrates a network system including a data storage device according to an embodiment of the present invention. [Modes for carrying out the invention]

[0010] The specific structural or functional descriptions of embodiments of the concept of the present invention disclosed herein or in the application are merely illustrative for the purpose of illustrating embodiments of the concept of the present invention, and embodiments of the concept of the present invention may be carried out in a variety of forms and should not be construed as being limited to the embodiments described herein or in the application.

[0011] Figure 1 is a diagram illustrating a storage device including a memory device according to an embodiment of the present invention.

[0012] Referring to Figure 1, the storage device 50 may include a memory device 100 and a memory controller 200 that controls the operation of the memory device. The storage device 50 may be a device that stores data under the control of a host 300 such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0013] The storage device 50 can be manufactured as any one of various types of storage devices by a host interface which is a communication method with the host 300. For example, the storage device 50 can be configured as any one of various types of storage devices such as SSD, MMC, eMMC, RS-MMC, multimedia card in the form of micro-MMC, secure digital card in the form of SD, mini-SD, micro-SD, USB (universal serial bus) storage device, UFS (universal flash storage) device, storage device in the form of PCMCIA (personal computer memory card international association) card, storage device in the form of PCI (peripheral component interconnection) card, storage device in the form of PCI-E (PCI express) card, CF (compact flash) card, smart media card, memory stick, etc.

[0014] The storage device 50 can be manufactured as any one of various types of package forms. For example, the storage device 50 can be manufactured as any one of various types of package forms such as POP (package on package), SIP (system in package), SOC (system on chip), MCP (multi-chip package), COB (chip on board), WFP (wafer-level fabricated package), WSP (wafer-level stack package), etc.

[0015] The memory device 100 can store data. The memory device 100 operates in response to the control of the memory controller 200. The memory device 100 can include a memory cell array (not shown) including a plurality of memory cells for storing data.

[0016] Memory cells can each be composed of a Single Level Cell (SLC) that stores one data bit, a Multi Level Cell (MLC) that stores two data bits, a Triple Level Cell (TLC) that stores three data bits, or a Quad Level Cell (QLC) that can store four data bits.

[0017] A memory cell array (not shown) can include a plurality of memory blocks. Each memory block can include a plurality of memory cells. One memory block can include a plurality of pages. In an embodiment, a page can be a unit for storing data in the memory device 100 or reading data stored in the memory device 100. A memory block can be a unit for erasing data.

[0018] In the embodiments, the memory device 100 may be DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR4 (Low Power Double Data Rate 4) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), RDRAM (Rambus Dynamic Random Access Memory), NAND flash memory, Vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM®), spin transfer torque random access memory (STT-RAM), etc. For the sake of explanation, this specification will assume that the memory device 100 is a NAND flash memory.

[0019] The memory device 100 may be configured to receive a command CMD and address ADDR from the memory controller 200 and access a region of the memory cell array selected by the address. The memory device 100 can perform the operations instructed by the command CMD on the region selected by address ADDR. For example, the memory device 100 can perform program operations, read operations, and erase operations. During a program operation, the memory device 100 can save data to the region selected by address ADDR. During a read operation, the memory device 100 can read data from the region selected by address ADDR. During an erase operation, the memory device 100 can erase the data saved in the region selected by address ADDR.

[0020] In this embodiment, the memory device 100 may include multiple planes. Each plane can be an independent unit capable of performing operations. For example, the memory device 100 may include two, four, or eight planes. Each of these planes can independently perform program operations, read operations, or erase operations simultaneously.

[0021] The memory controller 200 can control the overall operation of the storage device 50.

[0022] When power is applied to the storage device 50, the memory controller 200 can execute firmware (FW). If the memory device 100 is a flash memory device, the firmware (FW) may include a Host Interface Layer (HIL) that controls communication with the host 300, and the memory controller 200 may include a Flash Translation Layer (FTL) that controls communication between the host 300 and the memory device 100, and a Flash Interface Layer (FIL) that controls communication with the memory device 100.

[0023] The memory controller 200 receives write data and a logical block address (LBA) from the host 300 and can convert the logical block address into a physical block address (PBA) representing the address of the memory cell where the data contained in the memory device 100 is stored. In this specification, "logical block address (LBA)" and "logical address" or "logical address" may be used interchangeably. In this specification, "physical block address (PBA)" and "physical address" or "physical address" may be used interchangeably.

[0024] The memory controller 200 can control the memory device 100 to perform program operations, read operations, or erase operations in response to requests from the host 300. During program operations, the memory controller 200 can provide program commands, physical block addresses (PBAs), and data to the memory device 100. During read operations, the memory controller 200 can provide read commands and physical block addresses (PBAs) to the memory device 100. During erase operations, the memory controller 200 can provide erase commands and physical block addresses (PBAs) to the memory device 100.

[0025] In this embodiment, the memory controller 200 can autonomously generate commands, addresses, and data and transmit them to the memory device 100, independently of any requests from the host 300. For example, the memory controller 200 can provide the memory device 100 with commands, addresses, and data for performing read operations and program operations associated with wear leveling, read reclaim, garbage collection, etc.

[0026] In this embodiment, the memory controller 200 can control at least two or more memory devices 100. In this case, the memory controller 200 can control the memory devices 100 in an interliving manner to improve operational performance. The interliving manner may be a method of controlling at least two or more memory devices 100 so that their operations overlap. Alternatively, the interliving manner may be a method in which at least two or more memory devices 100 operate in parallel.

[0027] A buffer memory (not shown) can temporarily store data provided by the host 300, i.e., data to be stored in the memory device 100, or data read from the memory device 100. In this embodiment, the buffer memory (not shown) may be a volatile memory device. For example, the buffer memory (not shown) may be a dynamic random access memory (DRAM) or a static random access memory (SRAM).

[0028] The host 300 can communicate with the storage device 50 using at least one of a variety of communication methods, such as USB (Universal Serial Bus), SATA (Serial AT Attachment), SAS (Serial Attached SCSI), HSIC (High Speed ​​Interchip), SCSI (Small Computer System Interface), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe (NonVolatile Memory express), UFS (Universal Flash Storage), SD (Secure Digital), MMC (MultiMedia Card), eMMC (embedded MMC), DIMM (Dual In-line Memory Module), RDIMM (Registered DIMM), and LRDIMM (Load Reduced DIMM).

[0029] Figure 2 is a diagram illustrating the memory device shown in Figure 1.

[0030] Referring to Figure 2, the memory device 100 can include a memory cell array 110, an address decoder 120, a read and write circuit 130, a control logic 140, a voltage generation unit 150, and a current sensing circuit 160. The address decoder 120, the read and write circuit 130, the voltage generation unit 150, and the current sensing circuit 160 can be considered peripheral circuits controlled by the control logic 140.

[0031] The memory cell array 110 can include a number of memory blocks BLK1 to BLKz. The number of memory blocks BLK1 to BLKz can be connected to the address decoder 120 via word lines WL. The number of memory blocks BLK1 to BLKz can be connected to the read and write circuit 130 via bit lines BL1 to BLm. Each of the number of memory blocks BLK1 to BLKz can include a number of memory cells. In one embodiment, the number of memory cells are non-volatile memory cells and may consist of non-volatile memory cells having a vertical channel structure. The memory cell array 110 may consist of a two-dimensional memory cell array. In another embodiment, the memory cell array 110 may consist of a three-dimensional memory cell array. On the other hand, each of the multiple memory cells included in the memory cell array can store at least one bit of data. In one embodiment, each of the multiple memory cells included in the memory cell array 110 may be a single-level cell (SLC) that stores one bit of data. In another embodiment, each of the multiple memory cells included in the memory cell array 110 may be a multi-level cell (MLC) that stores two bits of data. In yet another embodiment, each of the multiple memory cells included in the memory cell array 110 may be a triple-level cell (TLC) that stores 3 bits of data. In yet another embodiment, each of the multiple memory cells included in the memory cell array 110 may be a quad-level cell (QLC) that stores 4 bits of data. Depending on the embodiment, the memory cell array 110 may include multiple memory cells, each storing 5 bits or more of data.

[0032] The address decoder 120 can be connected to the memory cell array 110 via a word line WL. The address decoder 120 can be configured to operate in response to control logic 140. The address decoder 120 can receive addresses through an input / output buffer (not shown) inside the memory device 100.

[0033] The address decoder 120 can be configured to decode a block address from the received address. The address decoder 120 can select at least one memory block based on the decoded block address. During a read operation, the address decoder 120 can apply the read voltage Vread generated by the voltage generation unit 150 to the selected word line of the memory block selected during the read voltage application operation, and apply the pass voltage Vpass to the remaining unselected word lines. During a program verification operation, the verification voltage generated by the voltage generation unit 150 can apply the verification voltage to the selected word line of the memory block, and apply the pass voltage Vpass to the remaining unselected word lines.

[0034] The address decoder 120 may be configured to decode the column address from the received address. The address decoder 120 can transmit the decoded column address to the read and write circuit 130.

[0035] Read and program operations of the memory device 100 can be performed in page units. The address received when a read or program operation is requested may include a block address, a row address, and a column address. The address decoder 120 can select a memory block and a word line based on the block address and row address. The column address may be decoded by the address decoder 120 and provided to the read and write circuit 130. In this specification, memory cells linked to a word line may be referred to as a "physical page".

[0036] The read and write circuit 130 may include a number of page buffers PB1 to PBm. The read and write circuit 130 can operate as a "read circuit" during read operations on the memory cell array 110 and as a "write circuit" during write operations. The number of page buffers PB1 to PBm may be connected to the memory cell array 110 via bit lines BL1 to BLm. During read and program verification operations, the number of page buffers PB1 to PBm can sense the threshold voltage of the memory cells by continuously supplying sensing current to the bit lines connected to the memory cells, and can sense through sensing nodes that the amount of current flowing changes depending on the program state of the corresponding memory cell, and latch this as sensing data. The read and write circuit 130 can operate in response to page buffer control signals output by the control logic 140. In this specification, the write operation of the write circuit may be used synonymously with the program operation for a selected memory cell.

[0037] The read and write circuit 130 senses data from the memory cell during a read operation, temporarily stores the read data, and then outputs the data (DATA) to the input / output buffer (not shown) of the memory device 100. In exemplary embodiments, the read and write circuit 130 may include a column selection circuit or the like in addition to a page buffer (or page register). In embodiments of the present invention, the read and write circuit 130 may be a page buffer.

[0038] The control logic 140 can be connected to the address decoder 120, the read and write circuit 130, the voltage generation unit 150, and the current sensing circuit 160. The control logic 140 can receive command CMD and control signal CTRL through the input / output buffer (not shown) of the memory device 100. The control logic 140 can be configured to control various operations of the memory device 100 in response to the control signal CTRL. The control logic 140 also outputs control signals to adjust the sensing node precharge potential levels of several page buffers PB1 to PBm. The control logic 140 can control the read and write circuit 130 to perform read operations on the memory cell array 110.

[0039] On the other hand, the control logic 140 can determine whether the verification operation for a specific target program state has passed or failed in response to the verification pass signal PASS or fail signal FAIL received from the current sensing circuit 160.

[0040] The voltage generation unit 150 generates a read voltage Vread and a pass voltage Vpass during a read operation in response to a control signal output by the control logic 140. The voltage generation unit 150 may include multiple pumping capacitors that receive an internal power supply voltage in order to generate multiple voltages with various voltage levels. The voltage generation unit 150 can selectively activate multiple pumping capacitors in response to control by the control logic 140 to generate multiple voltages.

[0041] The current sensing circuit 160 can generate a reference current and reference voltage in response to the allowable bit (VRY_BTI<#>) received from the control logic 140 during verification operation. By comparing the generated reference voltage with the sensing voltage VPB received from the page buffers PB1 to PBm included in the read and write circuit 130, or by comparing the generated reference current with the sensing current received from the page buffers PB1 to PBm included in the read and write circuit 130, the circuit can output a verification pass signal PASS or a fail signal FAIL.

[0042] The address decoder 120, read and write circuit 130, voltage generation unit 150, and current sensing circuit 160 can function as "peripheral circuits" that perform read, write, and erase operations on the memory cell array 110. Based on the control of the control logic 140, the peripheral circuits can perform read, write, and erase operations on the memory cell array 110.

[0043] Figure 3 is a diagram illustrating the structure of one of the memory blocks shown in Figure 2.

[0044] The memory block BLKz shown in Figure 2 is a diagram representing one of the memory blocks BLK1 to BLKz.

[0045] Referring to Figure 3, multiple word lines arranged parallel to each other can be concatenated between the first and second select lines. Here, the first select line may be the source select line SSL, and the second select line may be the drain select line DSL. More specifically, a memory block BLKz can contain multiple strings (ST) concatenated between bit lines BL1 to BLm and source line SL. Bit lines BL1 to BLm may each be concatenated to a string ST, and source line SL may be commonly concatenated to a string ST. Since the strings ST can be identical to each other, we will specifically explain using the string ST concatenated to the first bit line BL1 as an example.

[0046] A string ST may include a source select transistor SST connected in series between the source line SL and the first bit line BL1, multiple memory cells MC1 to MC16, and a drain select transistor DST. A single string ST may contain at least one source select transistor SST and one drain select transistor DST, and may also contain more memory cells MC1 to MC16 than the number shown in the diagram.

[0047] The source of a source select transistor (SST) may be connected to the source line SL, and the drain of a drain select transistor (DST) may be connected to the first bit line BL1. Memory cells MC1 to MC16 may be connected in series between the source select transistor (SST) and the drain select transistor (DST). The gates of source select transistors (SST) contained in different strings (ST) may be connected to the source select line SSL, the gate of a drain select transistor (DST) may be connected to the drain select line DSL, and the gates of memory cells MC1 to MC16 may be connected to multiple word lines WL1 to WL16. A group of memory cells contained in different strings (ST) that are connected to the same word line can be called a physical page (PG). Therefore, a memory block BLKz may contain as many physical pages (PG) as there are word lines WL1 to WL16.

[0048] A single memory cell can store 1 bit of data. This is commonly called a single-level cell (SLC). In this case, a single physical page (PG) can store one logical page (LPG) of data. A single logical page (LPG) can contain as many data bits as there are cells in that single physical page (PG).

[0049] A single memory cell can store more than two bits of data. In this case, one physical page (PG) can store more than two logical pages (LPG) of data.

[0050] Figure 4 is a block diagram illustrating the verification operation according to an embodiment of the present invention.

[0051] Referring to Figure 4, the control logic can control peripheral circuits, including a page buffer and a current sensing circuit. The peripheral circuits can perform write, read, and erase operations on memory blocks contained in the memory cell array. The peripheral circuits can apply voltage to the bit lines and word lines of the memory cells contained in the memory blocks. For example, the peripheral circuits can perform programmed operations that include multiple programmed loops. Each of the programmed loops may include a programmed pulse application operation that applies programmed pulses to increase the threshold voltage of the memory cell, and a verification operation that verifies whether the threshold voltage of the memory cell has reached a target threshold voltage.

[0052] In an embodiment of the present invention, the control logic 140 can transmit control signals to the read and write circuit 130 and the current sensing circuit 160. The memory cell array 110 can include a number of memory blocks. The number of memory blocks can be connected to the read and write circuit 130 through bit lines BLs. Each of the number of memory blocks can include a number of memory cells.

[0053] The read and write circuit 130 may include a number of page buffers. The number of page buffers may be connected to the memory cell array 110 via bit lines. The number of page buffers can sense changes in the amount of current flowing depending on the program state of the corresponding memory cell and transmit sensing data to the current sensing circuit 160.

[0054] The current sensing circuit 160 can receive sensing data from the read and write circuit 130 and perform current sensing operations. Current sensing operations determine whether memory cells are programmed to a target state and can include individual current sensing operations and overall current sensing operations.

[0055] The current sensing circuit 160 can generate a reference current and reference voltage corresponding to the number of error-correctable bits, and can generate a verification current and verification voltage from the sensing data. The current sensing circuit 160 can compare the reference voltage and verification voltage with each other and transmit a verification pass signal or a verification fail signal to the control logic 140. The current sensing circuit 160 can perform a current sensing operation that compares the sensing voltages received from multiple page buffers with a reference voltage corresponding to the number of error-correctable bits.

[0056] The control logic 140 can group multiple page buffers into multiple page buffer groups. The control logic 140 can control the current sensing circuit 160 to perform verification operations for each of the multiple page buffer groups.

[0057] The control logic 140 can determine the logical group number and physical group number corresponding to the column address of each of the multiple page buffers. The control logic 140 can be controlled to perform a first verification operation, which is a verification operation for each page buffer group with the same logical group number. The control logic 140 can be controlled to perform a second verification operation, which is a verification operation for each page buffer group with the same physical group number.

[0058] The current sensing circuit 160 can output a verification pass signal when the results of both the first and second verification operations satisfy the pass criteria. The current sensing circuit 160 can perform the first and second verification operations in a different order. The current sensing circuit 160 can output a fail signal when the results of the first verification operation do not satisfy the pass criteria. The current sensing circuit 160 can output a fail signal even if the results of the first verification operation satisfy the pass criteria, if the results of the second verification operation do not satisfy the pass criteria.

[0059] The control logic 140 can determine that page buffers with consecutive column addresses from among multiple page buffers are assigned the same logical group number. In this case, the number of page buffers with the same logical group number can be predetermined. For example, it can be assumed that the column addresses of the multiple page buffers range from 0 to 1024. The number of page buffers with the same logical group number can be determined to be 128. The control logic 140 can determine that the logical group number for the page buffers corresponding to column addresses 0 to 127 is 0. Similarly, the control logic 140 can determine that the logical group number for the page buffers corresponding to column addresses 128 to 255 is 1.

[0060] The control logic 140 can determine that adjacent page buffers from among multiple page buffers are assigned the same physical group number by the read and write circuit 130. In this case, the number of page buffers with the same physical group number can be predetermined. The number of page buffers with the same physical group number can be determined to be 128. For example, the control logic 140 can determine that 128 adjacent page buffers by the read and write circuit 130 are physical group number 0. The column addresses of the page buffers included in the physical group number can differ by 8. That is, the column addresses can be 0, 8, 16, ..., 1016.

[0061] In an embodiment of the present invention, the control logic 140 can determine logical group numbers and physical group numbers based on the layout of multiple page buffers. The layout of multiple page buffers may vary depending on the design of the memory device.

[0062] The control logic 140 can transmit a first signal to the current sensing circuit that indicates the page buffer corresponding to a logical group number. For example, the first signal can indicate that the logical group number for the page buffers corresponding to column addresses 0 to 127 is 0, and the logical group number for the page buffers corresponding to column addresses 128 to 255 is 1.

[0063] The control logic 140 can transmit a second signal to the current sensing circuit that indicates the page buffer corresponding to the physical group number. For example, the second signal can indicate that the physical group number of the page buffer corresponding to the low byte in bank 0 is 0, and the physical group number of the page buffer corresponding to the high byte in bank 0 is 1. In another embodiment of the present invention, the second signal can indicate that the physical group number of the page buffers whose column addresses differ by 8, such as column addresses 0, 8, 16, ..., 1016, is 0.

[0064] Figure 5 is a diagram illustrating the verification path and verification failure according to an embodiment of the present invention.

[0065] Referring to Figure 5, the current sensing circuit cannot output a verification pass signal unless both the logical verification operation and the physical verification operation satisfy the pass conditions.

[0066] The current sensing circuit can perform both logical and physical verification operations. The current sensing circuit can perform verification operations on a page buffer group basis. Logical verification operations can be performed through verification operations corresponding to each page buffer group with the same logical group number. Physical verification operations can be performed through verification operations corresponding to each page buffer group with the same physical group number.

[0067] The control logic can control the current sensing circuit to perform a logical verification operation. The control logic can transmit a first signal to the current sensing circuit that indicates the page buffer corresponding to each logical group number. Based on the first signal, the current sensing circuit can perform a logical verification operation for the page buffers with the same logical group number.

[0068] The control logic can transmit a second signal to the current sensing circuit, instructing it to use the page buffer corresponding to each physical group number. Based on the second signal, the current sensing circuit can perform a physical verification operation for the page buffers with the same physical group number.

[0069] A current sensing circuit cannot output a verification pass signal unless the results of both the logical and physical verification operations satisfy the verification pass conditions. A current sensing circuit can perform the logical verification operation first and the physical verification operation afterward. Conversely, a current sensing circuit can perform the physical verification operation first and the logical verification operation afterward.

[0070] The current sensing circuit can output a verification fail signal if either the result of the logical verification operation or the result of the physical verification operation does not satisfy the pass condition. In embodiments of the present invention, the pass conditions for the logical verification operation and the physical verification operation may be different from each other.

[0071] The current sensing circuit can compare the verification voltage corresponding to the page buffer group with the reference voltage corresponding to the number of error-correctable bits. If the fail bits included in the page buffer group are distributed, fail bits may exist even if a verification pass is output. Logical verification and physical verification operations can be complementary because the column addresses of the page buffers included in the page buffer group are different from each other.

[0072] Figure 6 is a diagram illustrating a method for determining logical group numbers and physical group numbers according to an embodiment of the present invention.

[0073] Referring to Figure 6, a physical page can be divided into four banks. Each bank can be divided into low bytes and high bytes. In Figure 6, it is assumed that page buffers corresponding to column addresses 0 to 1023 are grouped together. In Figure 6, as an example, logical group number 0 (INVER_LOG <0> ) corresponds to the page buffer and physical group number 0 (INVER_PHY <0> A corresponding page buffer may be illustrated.

[0074] Logical group number 0 (INVER_LOG <0> The column addresses of the page buffer corresponding to ) can be contiguous. In an embodiment of the present invention, the page buffers corresponding to column addresses 0 to 127 are logical group number 0 (INVER_LOG <0> ) can correspond to (610). Although not shown in Figure 6, page buffers corresponding to column addresses 128 to 255 can correspond to logical group number 1. In a similar manner, page buffers can be grouped for logical group numbers 2 to 6. The column addresses of the page buffer corresponding to logical group number 7 can be from 896 to 1023.

[0075] Physical group number 0 (INVER_PHY <0> The page buffer corresponding to physical group number 0 (INVER_PHY) may be the page buffer corresponding to the low byte of bank 0 (620). <0> The column address of the page buffer corresponding to physical group number 0 (INVER_PHY) can differ by as much as 8. <0> The column addresses of the 128 page buffers corresponding to ) could be 0, 8, 16, ..., 1016.

[0076] Similarly, the page buffer corresponding to physical group number 1 could be the page buffer corresponding to the high byte of bank 0. The page buffer corresponding to physical group number 2 could be the page buffer corresponding to the high byte of bank 1. The page buffer corresponding to physical group number 3 could be the page buffer corresponding to the low byte of bank 1. The page buffer corresponding to physical group number 4 could be the page buffer corresponding to the low byte of bank 2. The page buffer corresponding to physical group number 5 could be the page buffer corresponding to the high byte of bank 2. The page buffer corresponding to physical group number 6 could be the page buffer corresponding to the high byte of bank 3. The page buffer corresponding to physical group number 7 could be the page buffer corresponding to the low byte of bank 3. The column addresses of the page buffers corresponding to physical group numbers 1 through 7 can also differ by 8.

[0077] Figure 7 is a block diagram illustrating a current sensing circuit according to an embodiment of the present invention.

[0078] Referring to Figure 7, the current sensing circuit may include at least one comparator. The number of comparators may be the same as the number of page buffer groups. For example, if there are 8 page buffer groups, the number of comparators included in the current sensing circuit may also be 8. Figure 7 can illustrate the comparator corresponding to group number 0 among the at least one comparator.

[0079] In an embodiment of the present invention, the current sensing circuit can sum the outputs of the comparators and output the summed output. If all of the comparator outputs are verification passes, the current sensing circuit can output a verification pass signal for the entire page buffer.

[0080] The comparator may include a sensing voltage receiving unit, a comparison voltage generating unit, a reference voltage generating unit, a comparison circuit, and a power supply unit. The sensing voltage receiving unit 710 can receive sensing data from multiple page buffers. In embodiments of the present invention, the sensing voltage receiving unit 710 can receive a sensing voltage. The sensing voltage may be a voltage stored in the latch circuit of the page buffer.

[0081] In an embodiment of the present invention, the sensing voltage receiving unit 710 can receive sensing data from m page buffers. The sensing voltage receiving unit 710 can receive sensing voltages SO1, ..., SOm from page buffer 1 to page buffer m. The sensing voltage receiving unit 710 can provide the received sensing data to the comparison voltage generation unit 720.

[0082] The comparison voltage generation unit 720 can generate a comparison voltage, which is the sum of the sensing voltages that are compared with a reference voltage, based on the first signal and the second signal received from the control logic. The comparison voltage generation unit 720 can provide the generated comparison voltage to the comparison circuit 740 through the positive terminal VP of the comparison circuit 740.

[0083] In embodiments of the present invention, the first signal may be a signal indicating the page buffer corresponding to the logical group number. The second signal may be a signal indicating the page buffer corresponding to the physical group number. The first signal is a signal that selects the page buffer corresponding to logical group number 0 from among the page buffers (SEL_LOG <0> ) can include. The second signal is a signal to select the page buffer corresponding to physical group number 0 among the page buffers (SEL_PHY <0> ) may include. In embodiments of the present invention, SEL_LOG <0> and SEL_PHY <0> They cannot be turned ON at the same time.

[0084] The reference voltage generation unit 730 can generate a reference voltage corresponding to the number of bits for which error correction is possible. The reference voltage generation unit 730 can provide the generated reference voltage to the comparator circuit 740 through the negative terminal VN of the comparator circuit 740.

[0085] The comparison circuit 740 can output a comparison result (Vout0) by comparing the comparison voltage with the reference voltage. The comparison circuit 740 can output a verification fail signal in response to the comparison voltage exceeding the reference voltage. The comparison circuit 740 can output a verification pass signal in response to the comparison voltage being less than or equal to the reference voltage.

[0086] In an embodiment of the present invention, the comparison voltage generation unit 720 can generate a logical comparison voltage, which is the sum of sensing voltages corresponding to the first signal. The comparison circuit 740 can perform a first verification operation that compares the logical comparison voltage with a reference voltage. The comparison circuit 740 can output the comparison result of the first verification operation. At this time, the comparison voltage generation unit 720 can generate the logical comparison voltage using at least two or more transistors connected in series.

[0087] In an embodiment of the present invention, the comparison voltage generation unit 720 can generate a physical comparison voltage, which is the sum of sensing voltages corresponding to the second signal. The comparison circuit 740 can perform a second verification operation that compares the physical comparison voltage with a reference voltage. The comparison circuit 740 can output the comparison result of the second verification operation. At this time, the comparison voltage generation unit 720 can generate the physical comparison voltage using at least two or more transistors connected in series.

[0088] The reference voltage generation unit 730 can generate a first reference voltage corresponding to the comparison voltage generated based on the first signal. The reference voltage generation unit 730 can generate a second reference voltage corresponding to the comparison voltage generated based on the second signal.

[0089] In embodiments of the present invention, the first reference voltage and the second reference voltage may be different from each other. The first reference voltage and the second reference voltage may vary depending on the number of activated transistors among the multiple transistors included in the reference voltage generation unit 730.

[0090] Figure 8 is a diagram illustrating the sensing voltage receiving unit and the comparison voltage generation unit shown in Figure 7.

[0091] Referring to Figure 8, the sensing voltage receiver 710 can be implemented with 2m transistors, and the comparison voltage generator can be implemented with 2m+2 transistors. In Figure 8, it can be assumed that the number of page buffers is m.

[0092] The sensing voltages SO1, ..., SOm received by the sensing voltage receiver 710 can be input to m transistors TR21, ..., TR2m, respectively. The series-connected transistors included in the sensing voltage receiver 710 can represent sensing data received from the page buffer. The sensing voltage receiver 710 can provide sensing voltages to the comparison voltage generator 720.

[0093] The comparison voltage generation unit 720 can generate a comparison voltage to be provided to the comparison circuit 740 based on the first and second signals from the sensing voltages provided by the sensing voltage receiving unit 710. The comparison voltage generation unit 720 can generate a logical comparison voltage and a physical comparison voltage using 2m transistors TR31, ..., TR3m, TR41, ..., TR4m. The comparison voltage generation unit 720 can provide one of the logical comparison voltages and the physical comparison voltage to the comparison circuit 740 using two transistors TR5 and TR6.

[0094] In Figure 8, the number of page buffers is 1024, and it can be assumed that the column address of the sensing voltages connected through TR31 and TR41 is 0. It can be assumed that the column address of the sensing voltages connected through TR3n and TR4n is 513. It can be assumed that the column address of the sensing voltages connected through TR3m and TR4m is 1023.

[0095] Logical group number 0 (INVER_LOG <0> The column address of the page buffer corresponding to ) can range from 0 to 127. Physical group number 0 (INVER_PHY <0> The column addresses of the 128 page buffers corresponding to ) can be 0, 8, 16, ..., 1016. Physical group number 0 (INVER_PHY <0> The column addresses of the corresponding page buffers can differ by as much as 8.

[0096] Transistors TR31 and TR41, corresponding to column address 0, have logical group number 0 (INVER_LOG <0> ) and physical group number 0 (INVER_PHY <0> ) Therefore, TR31 contains SEL_LOG <0> The following is applied, and TR41 is set to SEL_PHY <0> This can be applied. Transistors TR3n and TR4n, corresponding to column address 513, have logical group number 0 (INVER_LOG <0> ) and physical group number 0 (INVER_PHY <0> Since it does not fall under this category, TR3n will contain UNSEL_LOG <0> The following is applied, and TR4n is set to UNSEL_PHY <0> This can be applied. Transistors TR3m and TR4m, corresponding to column address 1023, have logical group number 0 (INVER_LOG <0> ) does not apply, physical group number 0 (INVER_PHY <0> ) Therefore, TR3m contains UNSEL_LOG <0> The following is applied, and TR4m is set to SEL_PHY <0> It may be applied.

[0097] In the embodiment of the present invention, SEL_LOG is applied to TR5. <0> This may lead to the selection of a logical verification operation. SEL_PHY is applied to TR6. <0> Therefore, a physical verification operation may be selected.

[0098] Figure 9 is a diagram illustrating the comparison circuit and reference voltage generation unit shown in Figure 7.

[0099] Referring to Figure 9, the reference voltage generation unit 730 may be composed of multiple transistors TR71, TR72, TR81, TR82, TR91, and TR92. The comparator circuit 740 may be composed of a differential amplifier.

[0100] The reference voltage generation unit 730 can generate a reference voltage corresponding to the number of bits for which error correction is possible. TR81 and TR82 included in the reference voltage generation unit 730 can represent the number of bits for which error correction is possible. In the embodiment of the present invention, unlike in Figure 9, TR83 and TR84 may also be included in the reference voltage generation unit 730.

[0101] The reference voltage generated by the reference voltage generation unit 730 may vary depending on the number of transistors included.

[0102] In embodiments of the present invention, TR71 and TR72 may be added for current path matching. Corresponding to the fact that the comparison voltage input to the positive terminal VP of the comparator circuit 740 passes through four transistors, the reference voltage input to the negative terminal VN of the comparator circuit 740 may also pass through four transistors. A certain amount of voltage drop may occur as the reference voltage passes through the transistors.

[0103] The comparison circuit 740 can compare the provided comparison voltage with the reference voltage. The comparison result can be fed back through the gate voltages of transistors TR81 and TR82, which represent the number of error-correctable bits in the reference voltage generation unit 730.

[0104] If the comparison voltage provided through the positive terminal VP of the comparison circuit 740 is a logical comparison voltage, output Vout1 can be a logical verification result. In this case, output Vout1 can be a verification result for logical group number 0. Similarly, if the comparison voltage provided through the positive terminal VP of the comparison circuit 740 is a physical comparison voltage, output Vout1 can be a physical verification result. In this case, output Vout1 can be a verification result for physical group number 0.

[0105] Figure 10 is a diagram illustrating a method for grouping multiple page buffers into a physical group according to an embodiment of the present invention.

[0106] Referring to Figure 10, physical pages can be grouped into 16 physical groups. Physical pages can be distinguished by the bank number of the cell matrix. Within the same bank number, they can be distinguished into low bytes and high bytes. Low bytes can also be distinguished by whether the bit line number is odd or even (1010).

[0107] In Figure 10, the logical group number can be determined by the column address. The physical group number can be determined by the page buffer adjacent to the physical page. In embodiments of the present invention, the physical group number can be determined by the bitline number. A page buffer with an odd bitline number may have a different physical group number than a page buffer with an even bitline number.

[0108] In another embodiment of the present invention, physical group numbers may be determined such that the bitline numbers are consecutive (1020). According to an embodiment of the present invention, adjacent page buffers may be grouped together on a physical page. The number of page buffer groups may be 16. The number of page buffers corresponding to a physical group number may be the same.

[0109] Figure 11 is a flowchart illustrating how to perform a verification operation in an embodiment of the present invention.

[0110] Referring to Figure 11, a verification operation may be performed in the memory device. The verification operation may be performed for each page buffer group with the same logical group number. The verification operation may also be performed for each page buffer group with the same physical group number. The current sensing circuit can output a verification pass signal when the results of both the logical and physical verification operations satisfy the verification pass criteria.

[0111] At stage S1110, the control logic can determine, from among multiple page buffers, that page buffers whose column addresses are consecutive, corresponding to a predetermined number of page buffers, and assign them the same logical group number. At stage S1120, the control logic can determine, from among multiple page buffers, that number of adjacent page buffers, predetermined by the read and write circuits, and assign them the same physical group number.

[0112] The control logic can group multiple page buffers into multiple page buffer groups. The control logic can control the current sensing circuit to perform verification operations for each of the multiple page buffer groups. The control logic can determine the logical group number and physical group number corresponding to the column address of each of the multiple page buffers.

[0113] The control logic can determine that page buffers with consecutive column addresses should be assigned the same logical group number. In this case, the number of page buffers with the same logical group number can be predetermined. For example, it can be assumed that the column addresses of the multiple page buffers range from 0 to 1024. The number of page buffers with the same logical group number can be determined to be 128. The control logic can determine that the logical group number of the page buffers corresponding to column addresses 0 to 127 is 0. Similarly, the control logic can determine that the logical group number of the page buffers corresponding to column addresses 128 to 255 is 1.

[0114] The control logic can determine that adjacent page buffers in the read and write circuits share the same physical group number. The number of page buffers with the same physical group number can be predetermined. For example, the number of page buffers with the same physical group number can be determined to be 128. For instance, the control logic can determine that 128 adjacent page buffers in the read and write circuits belong to physical group number 0. The column addresses of the page buffers included in the physical group number can differ by 8. That is, the column addresses could be 0, 8, 16, ..., 1016.

[0115] In embodiments of the present invention, the control logic can determine logical group numbers and physical group numbers based on the layout of multiple page buffers. The layout of multiple page buffers may vary depending on the design of the memory device.

[0116] At step S1130, the control logic can be controlled to perform a first verification operation, which is a verification operation for each page buffer group with the same logical group number. The control logic can transmit a first signal to the current sensing circuit that indicates the page buffer corresponding to each logical group number.

[0117] The control logic can transmit a first signal to the current sensing circuit that indicates the page buffer corresponding to a logical group number. For example, the first signal can indicate that the logical group number for the page buffers corresponding to column addresses 0 through 127 is 0, and the logical group number for the page buffers corresponding to column addresses 128 through 255 is 1.

[0118] At step S1140, the control logic can be controlled to perform a second verification operation, which is a verification operation for each page buffer group with the same physical group number. The control logic can transmit a second signal to the current sensing circuit that indicates the page buffer corresponding to each physical group number.

[0119] The control logic can transmit a second signal to the current sensing circuit that indicates the page buffer corresponding to the physical group number. For example, the second signal can indicate that the physical group number of the page buffer corresponding to the low byte in bank 0 is 0, and the physical group number of the page buffer corresponding to the high byte in bank 0 is 1. In another embodiment of the present invention, the second signal can indicate that the physical group number of the page buffers whose column addresses differ by 8, such as 0, 8, 16, ..., 1016, is 0.

[0120] At step S1150, the current sensing circuit can output a verification pass signal if the results of both the first and second verification operations satisfy the pass criteria. The current sensing circuit can perform the first and second verification operations in a different order. The current sensing circuit can output a fail signal if the result of the first verification operation does not satisfy the pass criteria. The current sensing circuit can output a fail signal if the result of the first verification operation satisfies the pass criteria, but the result of the second verification operation does not satisfy the pass criteria.

[0121] A current sensing circuit cannot output a verification pass signal unless both the logical and physical verification operations satisfy the pass conditions. The current sensing circuit can compare the verification voltage corresponding to the page buffer group with the reference voltage corresponding to the number of error-correctable bits. If the fail bits included in the page buffer group are distributed, fail bits may exist even if a verification pass signal is output. The logical and physical verification operations can be complementary because the column addresses of the page buffers included in the page buffer group are different.

[0122] The current sensing circuit can output a verification fail signal if either the result of the logical verification operation or the result of the physical verification operation does not satisfy the pass condition. In embodiments of the present invention, the pass conditions for the logical verification operation and the physical verification operation may be different from each other.

[0123] The verification operation in Figure 11 can correspond to the verification operation of the present invention described with reference to Figures 4 to 9.

[0124] Figure 12 is an illustrative drawing showing a data processing system including a solid-state drive (SSD) according to an embodiment of the present invention. Referring to Figure 12, the data processing system 2000 may include a host device 2100 and an SSD 2200.

[0125] The SSD2200 may include a controller 2210, a buffer memory device 2220, non-volatile memories 2231-223n, a power supply 2240, a signal connector 2250, and a power connector 2260. The controller 2210 can control the various operations of the SSD2200.

[0126] The buffer memory device 2220 can temporarily store data stored in the non-volatile memories 2231-223n. The buffer memory device 2220 can also temporarily store data read from the non-volatile memories 2231-223n. Data temporarily stored in the buffer memory device 2220 can be transmitted to the host device 2100 or the non-volatile memories 2231-223n under the control of the controller 2210.

[0127] Non-volatile memories 2231-223n can be used as storage media for the SSD 2200. Each of the non-volatile memories 2231-223n can be connected to the controller 2210 through multiple channels CH1-CHn. One or more non-volatile memories can be connected to a single channel. Non-volatile memories connected to a single channel can be connected to the same signal bus and data bus.

[0128] The power supply unit 2240 can supply power PWR, which is input through the power connector 2260, to the SSD 2200. The power supply unit 2240 may include an auxiliary power supply unit 2241. The auxiliary power supply unit 2241 can supply power to the SSD 2200 so that it can shut down properly in the event of a sudden power off. The auxiliary power supply unit 2241 may include large-capacity capacitors that can charge power PWR.

[0129] The controller 2210 can exchange signals SGL with the host device 2100 through the signal connector 2250. Here, signals SGL can include commands, addresses, data, etc. The signal connector 2250 can be composed of various types of connectors depending on the interface method between the host device 2100 and the SSD 2200.

[0130] Figure 13 is an illustrative diagram showing the configuration of the controller in Figure 12. Referring to Figure 13, the controller 2210 may include a host interface unit 2211, a control unit 2212, a random access memory 2213, an error correction code (ECC) unit 2214, and a memory interface unit 2215.

[0131] The host interface unit 2211 can interface the host device 2100 and the SSD 2200 according to the host device 2100's protocol. For example, the host interface unit 2211 can communicate with the host device 2100 through any one of the following protocols: Secure Digital, USB (Universal Serial Bus), MMC (Multi-Media Card), eMMC (Embedded MMC), PCMCIA (Personal Computer Memory Card International Association), PATA (Parallel Advanced Technology Attachment), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), PCI (Peripheral Component Interconnection), PCI-E (PCI Express), and UFS (Universal Flash Storage). The host interface unit 2211 can also perform disk emulation, which helps the host device 2100 recognize the SSD 2200 as a general-purpose data storage device, such as a hard disk drive (HDD).

[0132] The control unit 2212 can analyze and process the signal SGL input from the host device 2100. The control unit 2212 can control the operation of internal functional blocks by firmware or software for driving the SSD 2200. The random access memory 2213 can be used as operating memory for driving such firmware or software.

[0133] The error correction code ECC unit 2214 can generate parity data for data transmitted to non-volatile memories 2231-223n. The generated parity data can be stored in non-volatile memories 2231-223n along with the data. Based on the parity data, the error correction code ECC unit 2214 can detect errors in the data read from non-volatile memories 2231-223n. If the detected error is within the correction range, the error correction code ECC unit 2214 can correct the detected error.

[0134] The memory interface unit 2215 can provide control signals, such as commands and addresses, to the non-volatile memories 2231-223n under the control of the control unit 2212. Furthermore, the memory interface unit 2215 can exchange data with the non-volatile memories 2231-223n under the control of the control unit 2212. For example, the memory interface unit 2215 can provide data stored in the buffer memory device 2220 to the non-volatile memories 2231-223n, or provide data read from the non-volatile memories 2231-223n to the buffer memory device 2220.

[0135] Figure 14 is an illustrative drawing showing a data processing system including a data storage device according to an embodiment of the present invention. Referring to Figure 14, the data processing system 3000 may include a host device 3100 and a data storage device 3200.

[0136] The host device 3100 may be configured in the form of a board, such as a printed circuit board. Although not shown, the host device 3100 may include internal functional blocks for performing the functions of a host device.

[0137] The host device 3100 may include a connection terminal 3110 such as a socket, slot, or connector. The data storage device 3200 may be mounted on the connection terminal 3110.

[0138] The data storage device 3200 may be configured in the form of a circuit board, such as a printed circuit board. The data storage device 3200 may be called a memory module or memory card. The data storage device 3200 may include a controller 3210, a buffer memory device 3220, non-volatile memories 3231-3232, a PMIC (power management integrated circuit; 3240), and a connection terminal 3250.

[0139] The controller 3210 can control various operations of the data storage device 3200. The controller 3210 can be configured identically to the controller 2210 shown in Figure 12.

[0140] The buffer memory device 3220 can temporarily store data stored in the non-volatile memories 3231-3232. The buffer memory device 3220 can also temporarily store data read from the non-volatile memories 3231-3232. Data temporarily stored in the buffer memory device 3220 can be transmitted to the host device 3100 or the non-volatile memories 3231-3232 under the control of the controller 3210.

[0141] Non-volatile memories 3231-3232 can be used as storage media for the data storage device 3200.

[0142] The PMIC3240 can supply power to the data storage device 3200 via the connection terminal 3250. The PMIC3240 can manage the power supply of the data storage device 3200 under the control of the controller 3210.

[0143] The connection terminal 3250 can be connected to the connection terminal 3110 of the host device. Through the connection terminal 3250, signals such as commands, addresses, and data, as well as power, can be transmitted between the host device 3100 and the data storage device 3200. The connection terminal 3250 can be configured in various ways depending on the interface method between the host device 3100 and the data storage device 3200. The connection terminal 3250 can be located on either side of the data storage device 3200.

[0144] Figure 15 is an illustrative drawing of a data processing system including a data storage device according to an embodiment of the present invention. Referring to Figure 15, the data processing system 4000 may include a host device 4100 and a data storage device 4200.

[0145] The host device 4100 may be configured in the form of a board, such as a printed circuit board. Although not shown, the host device 4100 may include internal functional blocks for performing the functions of a host device.

[0146] The data storage device 4200 may be configured in the form of a surface-mount package. The data storage device 4200 may be mounted to the host device 4100 via a solder ball 4250. The data storage device 4200 may include a controller 4210, a buffer memory device 4220, and a non-volatile memory 4230.

[0147] The controller 4210 can control the various operations of the data storage device 4200. The controller 4210 can be configured identically to the controller 2210 shown in Figure 12.

[0148] The buffer memory device 4220 can temporarily store data stored in the non-volatile memory 4230. The buffer memory device 4220 can also temporarily store data read from the non-volatile memory 4230. Data temporarily stored in the buffer memory device 4220 can be transmitted to the host device 4100 or the non-volatile memory 4230 under the control of the controller 4210.

[0149] The non-volatile memory 4230 can be used as a storage medium for the data storage device 4200.

[0150] Figure 16 is an illustrative diagram showing a network system including a data storage device according to an embodiment of the present invention. Referring to Figure 16, the network system 5000 may include a server system 5300 and a number of client systems 5410-5430 connected via a network 5500.

[0151] The server system 5300 can service data in response to requests from multiple client systems 5410-5430. For example, the server system 5300 can store data provided by multiple client systems 5410-5430. Another example is that the server system 5300 can provide data to multiple client systems 5410-5430.

[0152] The server system 5300 may include a host device 5100 and a data storage device 5200. The data storage device 5200 may consist of the memory device 100 in Figure 1, the SSD 2200 in Figure 12, the data storage device 3200 in Figure 14, and the data storage device 4200 in Figure 15.

[0153] A person ordinary in the art to which the present invention pertains should understand that the embodiments described above are illustrative and not limiting in all respects, as the present invention can be carried out in other specific forms without altering its technical idea or essential features. The scope of the present invention is indicated by the claims, which are set forth below rather than by the detailed description above, and all modifications or altered forms derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included within the scope of the present invention. [Explanation of symbols]

[0154] 50: Storage device 100: Memory device 200: Memory Controller 300: Host

Claims

1. A memory block containing memory cells; A read and write circuit including a plurality of page buffers, each connected to the memory cell through a plurality of bit lines; A current sensing circuit that performs a verification operation comparing the sensing voltage received from the plurality of page buffers with a reference voltage corresponding to the number of bits for which error correction is possible; and The control logic includes grouping the plurality of page buffers into a plurality of page buffer groups, and controlling the current sensing circuit to perform the verification operation for each of the plurality of page buffer groups. The control logic described above is Determine the logical group number and physical group number corresponding to the column address of each of the plurality of page buffers, perform a first verification operation for each page buffer group with the same logical group number, and control the system to perform a second verification operation for each page buffer group with the same physical group number. The current sensing circuit is, A memory device that outputs a verification pass signal in response to the fact that the results of the first verification operation and the second verification operation all satisfy the pass criteria.

2. The aforementioned control logic is Among the plurality of page buffers, page buffers with consecutive column addresses are determined to be assigned the same logical group number. The memory device according to claim 1, wherein the number of page buffers with the same logical group number is predetermined.

3. The control logic described above is Among the plurality of page buffers, the read and write circuits determine adjacent page buffers to be assigned the same physical group number. The memory device according to claim 2, wherein the number of page buffers with the same physical group number is predetermined.

4. The aforementioned control logic is The memory device according to claim 3, wherein the logical group number and the physical group number are determined based on the layout of the plurality of page buffers.

5. The aforementioned control logic is The memory device according to claim 3, which transmits a first signal indicating a page buffer corresponding to the logical group number to the current sensing circuit.

6. The aforementioned control logic is The memory device according to claim 5, which transmits a second signal indicating a page buffer corresponding to the physical group number to the current sensing circuit.

7. The current sensing circuit is, A sensing voltage receiving unit that receives sensing voltages from the aforementioned multiple page buffers; A comparison voltage generation unit that generates a comparison voltage, which is the sum of the sensing voltages that are compared with the reference voltage, from among the sensing voltages, based on the first signal and the second signal; A reference voltage generation unit that generates the aforementioned reference voltage; and The memory device according to claim 6, comprising at least one comparator including a comparison circuit that outputs a comparison result obtained by comparing the comparison voltage with the reference voltage.

8. The comparison voltage generation unit is, The memory device according to claim 7, which generates a logical comparison voltage that is the sum of the sensing voltages corresponding to the first signal.

9. The aforementioned comparison circuit is The memory device according to claim 8, which performs the first verification operation of comparing the logical comparison voltage with the reference voltage and outputs the comparison result of the first verification operation.

10. The comparison voltage generation unit is, The memory device according to claim 8, which generates the logical comparison voltage using at least two or more transistors connected in series.

11. The comparison voltage generation unit is, The memory device according to claim 7, which generates a physical comparison voltage that is the sum of the sensing voltages corresponding to the second signal.

12. The aforementioned comparison circuit is The memory device according to claim 11, which performs the second verification operation of comparing the physical comparison voltage with the reference voltage and outputs the comparison result of the second verification operation.

13. The comparison voltage generation unit is, The memory device according to claim 11, which generates the physical comparison voltage using at least two or more transistors connected in series.

14. The aforementioned reference voltage generation unit is The memory device according to claim 7, which generates a first reference voltage corresponding to a comparison voltage generated based on the first signal, and generates a second reference voltage corresponding to a comparison voltage generated based on the second signal.

15. The memory device according to claim 14, wherein the first reference voltage and the second reference voltage are different from each other.

16. The aforementioned reference voltage generation unit is The memory device according to claim 14, further comprising at least one transistor corresponding to the number of transistors constituting the comparison voltage generation unit.

17. The aforementioned comparator is The memory device according to claim 7, wherein the number of comparators is the same as the number of the plurality of page buffer groups.

18. A method for operating a memory device, comprising: a read and write circuit including a memory cell contained in a memory block and a plurality of page buffers each connected through a plurality of bit lines; a current sensing circuit that performs a current sensing operation comparing sensing voltages received from the plurality of page buffers with a reference voltage corresponding to a number of error-correctable bits; and a control logic that groups the plurality of page buffers into a plurality of page buffer groups and controls the current sensing circuit to perform the current sensing operation for each of the plurality of page buffer groups, The step of determining, among the aforementioned plurality of page buffers, page buffers whose column addresses are consecutive and which correspond to a predetermined number of page buffers are assigned the same logical group number; A step in which a predetermined number of adjacent page buffers from the plurality of page buffers are assigned the same physical group number by the read and write circuit; The first step is to perform the current sensing operation for each page buffer group having the same logical group number; A step of performing a second operation, which is the current sensing operation for each page buffer group having the same physical group number; and An operating method comprising the step of outputting a verification pass signal in response to the fact that all results of the first and second operations satisfy the pass criteria.

19. A step of transmitting a first signal to the current sensing circuit that indicates the page buffer corresponding to each of the logical group numbers; and The operating method according to claim 18, further comprising the step of transmitting a second signal to the current sensing circuit that indicates a page buffer corresponding to each of the physical group numbers.

20. The step of outputting the verification pass signal is: The step of receiving sensing voltages from the aforementioned multiple page buffers; A step of generating a comparison voltage, which is the sum of the sensing voltages that are compared with the reference voltage, based on the first signal and the second signal; The step of generating the aforementioned reference voltage; and The operating method according to claim 19, further comprising the step of outputting a comparison result obtained by comparing the comparison voltage with the reference voltage.

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