Circuit board

Abstract

A circuit board according to an embodiment includes an insulating layer including first to third regions, an outer layer circuit pattern arranged on the upper surface of the first to third regions of the insulating layer, and a solder resist including a first part arranged in the first region of the insulating layer, a second part arranged in the second region, and a third part arranged in the third region, wherein the outer layer circuit pattern includes a first trace arranged on the upper surface of the first region of the insulating layer and a second trace arranged on the upper surface of the third region of the insulating layer, wherein the height of the first trace is different from the height of the second trace, and the upper surface of the first part of the solder resist is located lower than the upper surface of the first trace.

Description

Technical Field

[0005] , , ,

[0006]

[0001] The embodiments relate to a circuit board, and more particularly to a circuit board that can support an outermost circuit pattern using a solder resist.

Background Art

[0002] With the acceleration of miniaturization, weight reduction, and integration of electronic components, the circuit line width is being miniaturized. In particular, as the design rules of semiconductor chips are integrated on the nanometer scale, the circuit line width of package substrates or circuit boards on which semiconductor chips are mounted is being miniaturized to less than several micrometers.

[0003] In order to increase the circuit integration density of circuit boards, that is, to miniaturize the circuit line width, various manufacturing methods have been proposed. For the purpose of preventing the loss of circuit line width in the etching step for forming a pattern after copper plating, SAP (semi-additive process) method, MSAP (modified semi-additive process), etc. have been proposed.

[0004] After that, in order to embody a finer circuit pattern, the ETS (Embedded Trace Substrate, hereinafter referred to as "ETS") method of embedding a copper foil in an insulating layer has been used in the industry. The ETS method manufactures in a form of embedding a copper foil circuit in an insulating layer instead of forming a copper foil circuit on the surface of the insulating layer, so there is no circuit loss due to etching, which is advantageous for miniaturizing the circuit pitch.

[0005] On the other hand, recently, efforts have been made to develop an improved 5G (5th generation) communication system or a pre-5G communication system to meet the demand for wireless data traffic. Here, the 5G communication system uses an ultra-high frequency (mmWave) band (sub6 giga (6 GHz), 28 giga (28 GHz), 38 giga (38 GHz) or higher frequencies) to achieve a high data transmission rate.

[0006] Furthermore, in order to mitigate path loss in the ultra-high frequency band and increase the transmission distance of radio waves, beamforming, massive MIMO (Multi-Input / Output Multiplexing), and array antennas are being developed for 5G communication systems. Considering that such frequency bands can be composed of hundreds of active antennas with wavelengths, the antenna system becomes relatively large.

[0007] Since such antennas and AP modules are patterned or mounted on a circuit board, low loss on the circuit board is extremely important. This means that the multiple boards that make up the active antenna system—namely the antenna board, antenna feed board, transceiver board, and baseband board—must be integrated into a single compact unit.

[0008] Furthermore, the circuit boards used in the 5G communication systems described above are manufactured in line with the trend towards lighter, thinner, and smaller designs, resulting in increasingly miniaturized circuit patterns.

[0009] However, conventional circuit boards containing fine circuit patterns have a structure in which the outermost circuit pattern protrudes above the insulating layer, which has the problem that the outermost circuit pattern can easily collapse. [Overview of the Initiative] [Problems that the invention aims to solve]

[0010] The embodiment aims to provide a circuit board with a new structure and a method for manufacturing the same.

[0011] Furthermore, the embodiment aims to provide a circuit board and a method for manufacturing the same that can provide a structure including a solder resist that supports the outermost circuit pattern.

[0012] Furthermore, the embodiment aims to provide a circuit board and a method for manufacturing the same that can improve the reliability of a circuit pattern by removing residual resin from the surface of a circuit pattern placed in an open area of ​​the solder resist.

[0013] The technical problems to be solved in the proposed embodiments are not limited to those mentioned above, and other technical problems not mentioned will be clearly understood by those with ordinary skill in the art to which the proposed embodiments belong, based on the following description. [Means for solving the problem]

[0014] The circuit board according to the embodiment includes an insulating layer including first to third regions, an outer layer circuit pattern disposed on the upper surfaces of the first to third regions of the insulating layer, and a solder resist including a first part disposed in the first region of the insulating layer, a second part disposed in the second region, and a third part disposed in the third region, wherein the outer layer circuit pattern includes a first trace disposed on the upper surface of the first region of the insulating layer and a second trace disposed on the upper surface of the third region of the insulating layer, the height of the first trace being different from the height of the second trace, and the upper surface of the first part of the solder resist being lower than the upper surface of the first trace.

[0015] Furthermore, the first trace has a first height, the second trace has a second height greater than the first height, and the upper surface of the third part of the solder resist is positioned higher than the upper surface of the second trace.

[0016] Furthermore, the first height of the first trace is within the range of 90% to 95% of the second height of the second trace.

[0017] Furthermore, the first part of the solder resist has a third height that is smaller than the first height, and the third height of the first part of the solder resist is in the range of 70% to 85% of the first height of the first trace.

[0018] Furthermore, the outer layer circuit pattern includes a first pad positioned on the upper surface of the first region of the insulating layer, the first pad having a height corresponding to the first trace.

[0019] Furthermore, the third height of the first part of the solder resist is within the range of 70% to 85% of the height of the first pad.

[0020] Furthermore, the outer layer circuit pattern includes a second pad positioned on the upper surface of the second region of the insulating layer, and the second part of the solder resist has an opening region that exposes a portion of the upper surface of the second pad.

[0021] Furthermore, the upper surface of the second pad includes a first portion covered by the second part of the solder resist and a second portion exposed through an opening in the second part of the solder resist, wherein the first portion of the second pad is positioned higher than the second portion of the second pad.

[0022] Furthermore, the height of the second portion of the second pad is within the range of 90% to 95% of the height of the first portion of the second pad.

[0023] Furthermore, the height of the first portion of the second pad corresponds to the height of the second trace, and the height of the second portion of the second pad corresponds to the height of the first trace.

[0024] Furthermore, the surface roughness of the second and third parts of the solder resist is smaller than the surface roughness of the first part of the solder resist.

[0025] Furthermore, the insulating layer includes a plurality of insulating layers, and the outer layer circuit pattern is positioned protruding from the upper surface of the uppermost insulating layer among the plurality of insulating layers, and includes a primer layer positioned between the uppermost insulating layer, the outer layer circuit pattern and the solder resist.

[0026] On the one hand, the method for manufacturing a circuit board according to the embodiment includes manufacturing an inner layer substrate, forming an uppermost insulating layer having a primer layer disposed on the upper surface of the inner layer substrate, forming an outer layer circuit pattern on the primer layer of the uppermost insulating layer, forming a solder resist layer that is divided into a first region, a second region, and a third region covering the outer layer circuit pattern on the primer layer, partially exposing and developing the solder resist layer to form a solder resist including a first part formed in the first region, a second part formed in the second region, and a third part formed in the third region, and etching the outer layer circuit pattern exposed through the first part and the second part of the solder resist. The outer layer circuit pattern includes a first trace disposed in the first region and a second trace disposed in the third region. The first trace before etching has the same second height as the second trace, and has a first height smaller than the second height of the first trace after etching. The first height of the first trace after etching satisfies the range of 90% to 95% of the second height of the second trace.

[0027] Also, the upper surface of the first part of the solder resist is positioned lower than the upper surface of the first trace, and the upper surface of the third part of the solder resist is positioned higher than the upper surface of the second trace.

[0028] Also, the first part of the solder resist has a third height smaller than the first height, and the third height of the first part of the solder resist satisfies the range of 70% to 85% of the first height of the first trace.

[0029] Also, the outer layer circuit pattern includes a first pad disposed in the first region, and during the etching, the first pad is etched together with the first trace.

[0030] Furthermore, the outer layer circuit pattern includes a second pad located in the second region, the second part of the solder resist having an opening region that exposes a portion of the upper surface of the second pad, the upper surface of the second pad including a first portion covered by the second part of the solder resist and a second portion exposed through the opening region of the second part of the solder resist, and etching of the second portion of the second pad is performed during etching.

[0031] Furthermore, the height of the second part of the second pad is within the range of 90% to 95% of the height of the first part of the second pad.

[0032] Furthermore, the surface roughness of the second and third parts of the solder resist is smaller than the surface roughness of the first part of the solder resist. [Effects of the Invention]

[0033] The circuit board in this embodiment may have eight or more insulating layers. The circuit board is placed on the outermost insulating layer among the insulating layers and includes an outer layer circuit pattern that protrudes above the surface of the outer insulating layer. In this case, the outer layer circuit pattern includes a first outer layer circuit pattern placed in first and second open regions where the solder resist is not placed, and a second outer layer circuit pattern located in a third region where the solder resist is placed. In this case, the second outer layer circuit pattern can be supported and protected by the solder resist, but the first outer layer circuit pattern has the problem of easily collapsing due to various factors because there is no support layer that can support it.

[0034] In this embodiment, the solder resist in the first and second regions is left intact without being completely removed, so that the solder resist supports and protects the first outer layer circuit pattern. As a result, in this embodiment, problems such as collapse and abrasion of the first outer layer circuit pattern in the first and second regions can be solved by miniaturizing the outer layer circuit pattern. In this way, the reliability of the product can be improved in this embodiment. In particular, in this embodiment, problems such as collapse and abrasion of the traces constituting the first outer layer circuit pattern can be solved in the first region. Therefore, the product reliability of the circuit board can be improved in this embodiment.

[0035] Furthermore, in the embodiment, an etching process is performed on the surface of the second outer layer circuit pattern arranged in the first and second regions. The etching process may be a process for removing residual resin from the surface of the second outer layer circuit pattern arranged in the first and second regions. As a result, in the embodiment, the residual resin from the surface of the second outer layer circuit pattern can be completely removed through the etching process. As a result, in the embodiment, the electrical reliability of the second outer layer circuit pattern can be improved, thereby improving the product reliability of the circuit board.

[0036] Furthermore, the embodiment has a structure in which the entire surface of the insulating layer or the entire surface of the primer layer is covered with solder resist. This makes it possible to solve the reliability problem that arises when a part of the surface of the insulating layer or a part of the surface of the primer layer is exposed in the embodiment. Specifically, the exposure of a part of the surface of the insulating layer or a part of the surface of the primer layer means that a certain space exists between the outer layer circuit pattern and the solder resist. When such a certain space exists, residual solution such as adhesive material remains in the space, causing voids and resulting in reliability problems. In contrast, in the embodiment, the space can be filled with solder resist, thereby solving the reliability problem.

[0037] Furthermore, in the embodiment, the solder resist is removed using an exposure and development method rather than a sandblasting or plasma method. When removing the solder resist using a sandblasting or plasma method, deformation of the outer layer circuit pattern may occur. For example, the cross-section of the outer layer circuit pattern may be deformed into a triangular shape. When the cross-section of the outer layer circuit pattern is triangular, it may not be possible to stably place the adhesive member on the outer layer circuit pattern, which may lead to reliability problems. In contrast, in the embodiment, the solder resist can be removed without deformation of the outer layer circuit pattern, thereby improving reliability.

[0038] Furthermore, the circuit board in the embodiment is applicable to 5G communication systems, thereby minimizing high-frequency transmission loss and further improving reliability. Specifically, the circuit board in the embodiment can be used at high frequencies and can reduce propagation loss. [Brief explanation of the drawing]

[0039] [Figure 1a] This figure shows a circuit board manufactured using the SAP method in a comparative example. [Figure 1b] This figure shows a circuit board manufactured using the SAP method in a comparative example. [Figure 2] This figure shows a circuit board manufactured using the ETS method in a comparative example. [Figure 3] This is a diagram showing a circuit board according to an embodiment. [Figure 4] This is a plan view of a circuit board including a protective layer according to an embodiment. [Figure 5] This is an enlarged view of the trace in area B of Figure 3. [Figure 6] This figure shows R1 and R2 in region B of Figure 3. [Figure 7] This figure shows the degree of residual resin depending on the degree of etching. [Figure 8] This figure shows the degree of residual resin depending on the degree of etching. [Figure 9] This figure shows the shape of the second outer layer circuit pattern according to the embodiment, depending on the etching state. [Figure 10] Figure 2 shows the manufacturing process of the circuit board in order of steps. [Figure 11] Figure 2 shows the manufacturing process of the circuit board in order of steps. [Figure 12] Figure 2 shows the manufacturing process of the circuit board in order of steps. [Figure 13] Figure 2 shows the manufacturing process of the circuit board in order of steps. [Figure 14] Figure 2 shows the manufacturing process of the circuit board in order of steps. [Figure 15] Figure 2 shows the manufacturing process of the circuit board in order of steps. [Figure 16] Figure 2 shows the manufacturing process of the circuit board in order of steps. [Figure 17] Figure 2 shows the manufacturing process of the circuit board in order of steps. [Modes for carrying out the invention]

[0040] The embodiments disclosed herein will be described in detail below with reference to the attached drawings, but identical or similar components will be given the same reference numeral regardless of the drawing reference numerals, and redundant descriptions will be omitted. The suffixes “module” and “part” used for components in the following description are added or used interchangeably to facilitate the preparation of the specification and do not have any mutually distinguishing meaning or role in themselves. Furthermore, in the description of the embodiments disclosed herein, if it is determined that a specific description of such prior art would interfere with the understanding of the embodiments disclosed herein, such detailed description will be omitted. In addition, the attached drawings are provided to facilitate the understanding of the embodiments disclosed herein and should be understood as including all modifications, equivalents or substitutes that fall within the concept and scope of the present invention, and not limiting the technical ideas disclosed herein.

[0041] Terms including ordinal numbers such as "first," "second," etc., can be used to describe a variety of components, but the components are not limited by such terms. These terms are used solely for the purpose of distinguishing one component from another.

[0042] When it is stated that one component is “linked” or “connected” to another component, it should be understood that it may be directly “linked” or “connected” to the other component, and that other components may exist in between. Conversely, when it is stated that one component is “directly linked” or “directly connected” to another component, it should be understood that there are no other components in between.

[0043] A singular expression includes plural expressions unless the context clearly indicates otherwise.

[0044] In this application, terms such as “includes” or “having” are intended to specify the presence of features, figures, steps, actions, components, parts, or combinations thereof as described in the specification, and should be understood not to preemptively exclude the presence or possibility of adding one or more other features, figures, steps, actions, components, parts, or combinations thereof.

[0045] The embodiments of the present invention will be described in detail below with reference to the attached drawings.

[0046] Before describing this example, we will explain comparative examples that are comparable to this embodiment.

[0047] Figure 1 shows a circuit board relating to a comparative example.

[0048] Referring to Figure 1, as shown in (a), the circuit board relating to the comparative example includes a circuit pattern manufactured using a general SAP method.

[0049] Specifically, the circuit board includes an insulating layer 10, a circuit pattern 20, and a protective layer 30.

[0050] The circuit pattern 20 is placed on the upper and lower surfaces of the insulating layer 10, respectively.

[0051] At this time, at least one of the circuit patterns 20 arranged on the surface of the insulating layer 10 includes a fine circuit pattern.

[0052] In Figure 1, the circuit pattern 20 located on the upper surface of the insulating layer 10 includes a fine circuit pattern. The fine circuit pattern includes traces 21, which are signal transmission wiring lines, and pads 22, which are for chip mounting and the like.

[0053] In this embodiment, a support layer using solder resist is formed for the purpose of protecting the fine circuit pattern, so the structure in the region where the fine circuit pattern was formed in the comparative example will be described.

[0054] Furthermore, a protective layer 30 is placed on the surface of the insulating layer 10 to protect the circuit pattern 20.

[0055] In this case, the upper region of the insulating layer 10 includes a first region where the protective layer 30 is placed, and a second region which is an open region where the protective layer 30 is not placed.

[0056] As a result, a portion of the circuit pattern 20 arranged on the upper surface of the insulating layer 10 is covered by the protective layer 30, while the remaining portion is exposed to the outside without being covered by the protective layer 30.

[0057] At this time, the second region, which is the open region of the protective layer 30, is arranged with traces 21 and pads 22 corresponding to the fine circuit patterns, as described above.

[0058] For example, at least one of the trace 21 and pad 22 is formed with a width / spacing of 15 μm / 15 μm or less.

[0059] In this case, if the circuit pattern formed in the open region of the protective layer 30 is not a fine circuit pattern but a pattern with a width of more than 15 μm, it may be resistant to external impacts.

[0060] However, as shown in Figure 1(b), as the circuit pattern is gradually miniaturized, the width and spacing of the trace 21, which is the outermost layer of fine circuit patterns, become smaller and smaller. This creates a problem where, if a fine circuit pattern protruding from the upper surface of the insulating layer 10 is placed in the second region, which is the open region of the protective layer, the fine circuit pattern can easily collapse due to external impact.

[0061] In other words, as shown in Figure 1(b)B, the trace 21 corresponding to the outermost layer's fine circuit pattern has an extremely fine pattern shape, which causes the problem that it can easily crumble or get rubbed off even by small external impacts.

[0062] On the other hand, recently, the ETS method has been used to form fine circuit patterns that are embedded within the insulating layer while being positioned in the open regions of the protective layer.

[0063] Figure 2 shows a circuit board manufactured using the ETS method in a comparative example.

[0064] Referring to Figure 2, specifically, the circuit board includes an insulating layer 10A, a circuit pattern 20A, and a protective layer 30A.

[0065] The circuit pattern 20A is placed on the upper and lower surfaces of the insulating layer 10A, respectively.

[0066] In this case, at least one of the circuit patterns 20A arranged on the surface of the insulating layer 10A includes a fine circuit pattern.

[0067] In this case, when forming a circuit pattern using the ETS method, the initially formed circuit pattern has a structure embedded within the insulating layer 10A. Therefore, when the initially formed circuit pattern is a fine circuit pattern, the comparative example can also have a structure embedded within the insulating layer 10A.

[0068] In other words, the circuit board manufactured by the ETS method includes a fine circuit pattern having a structure embedded within the surface of the insulating layer 10A. Specifically, the fine circuit pattern includes traces 21A, which are signal transmission wiring lines, and pads 22A for chip mounting and the like.

[0069] Furthermore, in the case of circuit boards manufactured using the ETS method as described above, the fine circuit patterns are embedded within an insulating layer, thus protecting the fine circuit patterns from external impacts.

[0070] In this case, for substrates with a two-layer structure (based on the number of layers of the circuit pattern) as shown in Figure 2, there are no major problems in manufacturing circuit boards using the ETS method. However, when manufacturing circuit boards with eight or more layers, especially ten or more layers, using the ETS method, the lead time required for manufacturing is at least two months, which results in low productivity.

[0071] Furthermore, in order to manufacture the fine circuit patterns of structures embedded using the ETS method, the fine circuit patterns must be formed first during the manufacturing process of the multilayer circuit board. Recently, to apply to AP modules and the like, which have high integration and high specifications, 8 to 10 layers of circuit boards are required. In this case, during the ETS process, the fine circuit patterns are formed first, and then during the subsequent multilayer lamination process, damage to the fine circuit patterns occurs due to thermal stress and other reasons, making it difficult to properly realize the fine circuit patterns.

[0072] Furthermore, when manufacturing a circuit board using the ETS method, a separate ETS core layer is required. In this case, when manufacturing a circuit board using the ETS method, an additional step is required to remove the ETS core layer at the end.

[0073] Furthermore, when manufacturing circuit boards using the ETS method, there is a problem in that the yield decreases due to cumulative tolerances after a certain number of laminations, which increases product costs. Additionally, because the lamination process is performed on both sides, centered around the ETS core layer, there is a problem in that pattern damage due to stress increases.

[0074] Furthermore, with the recent development of 5G technology, there is growing interest in circuit boards that can accommodate it. For 5G technology to be applied, the circuit board needs to have a highly multilayered structure, requiring miniaturization of the circuit patterns. However, in the comparative example, while it is possible to form fine patterns, there is a problem in that these patterns cannot be stably protected.

[0075] Thus, the embodiment aims to provide a new circuit board structure and a control method thereof that can solve the reliability problem of the fine patterns placed on the outermost surface.

[0076] Figure 3 shows a circuit board according to an embodiment, Figure 4 is a plan view of the circuit board including the protective layer according to an embodiment, Figure 5 is an enlarged view of the trace in area B of Figure 3, and Figure 6 shows R1 and R2 in area B of Figure 3.

[0077] Prior to describing Figures 3 to 6, the circuit board according to the embodiment may have a multilayer structure. Preferably, the circuit board according to the embodiment may have a structure of 10 or more layers based on the number of layers of the circuit pattern. However, this is only one embodiment and is not limited thereto. That is, the circuit board in the embodiment may have fewer than 10 layers, or conversely, it may have more than 10 layers.

[0078] However, the circuit board in the embodiment is intended to solve the problems of the ETS method in the comparative example. In this case, the ETS method in the comparative example has many problems in producing circuit boards with 8 or more layers, and therefore, the embodiment will be described as having a 10-layer structure for comparison with the comparative example.

[0079] Referring to Figures 3 to 6, the circuit board 100 includes an insulating layer 110.

[0080] Preferably, the circuit board 100 may include first to ninth insulating layers 111, 112, 113, 114, 115, 116, 117, 118, and 119 to embody a 10-layer structure.

[0081] In this case, among the insulating layers 110, the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, the fourth insulating layer 114, the fifth insulating layer 115, the sixth insulating layer 116, and the seventh insulating layer 117 may be internal insulating layers arranged on the inside in the laminated structure of the insulating layers, the eighth insulating layer 118 may be the uppermost insulating layer (first outermost insulating layer) arranged on top of the inner insulating layers, and the ninth insulating layer 119 may be the bottommost insulating layer (second outermost insulating layer) arranged below the inner insulating layers.

[0082] The first insulating layer 111 may be a core insulating layer located in the center of the laminated structure of the insulating layers 110. The second insulating layer 112, the fourth insulating layer 114, the sixth insulating layer 116, and the eighth insulating layer 118 may be upper insulating layers arranged sequentially above the first insulating layer 111. The third insulating layer 113, the fifth insulating layer 115, the seventh insulating layer 117, and the ninth insulating layer 119 may be lower insulating layers arranged sequentially below the first insulating layer 111.

[0083] The insulating layer 110 can include all printed circuit boards, wiring boards, and insulating substrates made of insulating material on which an electrical circuit can be arranged and on which a circuit pattern can be formed on the surface, and on which an electrical circuit can be arranged.

[0084] For example, at least one of the insulating layers 110 may be rigid or flexible. For example, at least one of the insulating layers 110 may include glass or plastic. More specifically, at least one of the insulating layers 110 may include chemically strengthened / semi-strengthened glass such as soda-lime glass or aluminosilicate glass, or reinforced or ductile plastics such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC), or may include sapphire.

[0085] Furthermore, at least one of the insulating layers 110 may include an isotropic film. For example, at least one of the insulating layers 110 may include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), isotropic polycarbonate PC (polycarbonate), or isotropic polymethyl methacrylate (PMMA).

[0086] Furthermore, at least one of the insulating layers 110 may have a partially curved surface and bend. That is, at least one of the insulating layers 110 may have a partially flat surface and a partially curved surface and bend. More specifically, at least one of the insulating layers 110 may have a curved end and bend, or have a surface with random curvature and bend or fold.

[0087] Furthermore, at least one of the insulating layers 110 may be a flexible substrate having flexible properties. Also, at least one of the insulating layers 110 may be a curved or bent substrate. In this case, at least one of the insulating layers 110 can represent electrical wiring connecting circuit components based on the circuit design using wiring diagrams, and can reproduce electrical conductors on the insulator. Furthermore, at least one of the insulating layers 110 can mount electrical components and form wiring that connects them circuit-wise, and can mechanically fix components other than those that provide electrical connection functions.

[0088] A circuit pattern may be arranged on the surface of the insulating layer 110.

[0089] That is, a circuit pattern 110 can be arranged on the surface of each of the first to ninth insulating layers 111, 112, 113, 114, 115, 116, 117, 118, and 119 that constitute the insulating layer 110.

[0090] Here, the circuit pattern may include an inner layer circuit pattern 120 and outer layer circuit patterns 130 and 140. The inner layer circuit pattern 120 is a circuit pattern located inside the insulating layer 110 in the laminated structure of the circuit board, and the outer layer circuit patterns 130 and 140 may be circuit patterns located on the outermost surface of the insulating layer 110 in the laminated structure of the circuit board.

[0091] The inner layer circuit pattern 120 may include a first circuit pattern 121, a second circuit pattern 122, a third circuit pattern 123, a fourth circuit pattern 124, a fifth circuit pattern 125, a sixth circuit pattern 126, and a seventh circuit pattern 127.

[0092] The first circuit pattern 121 may be placed on the upper surface of the first insulating layer 111 and thereby covered by the second insulating layer 112. The second circuit pattern 122 may be placed on the lower surface of the first insulating layer 111 and thereby covered by the third insulating layer 113. The third circuit pattern 123 may be placed on the upper surface of the second insulating layer 112 and thereby covered by the fourth insulating layer 114. The fourth circuit pattern 124 may be placed on the lower surface of the third insulating layer 113 and thereby covered by the fifth insulating layer 115. The fifth circuit pattern 125 may be placed on the upper surface of the fourth insulating layer 114 and thereby covered by the sixth insulating layer 116. The sixth circuit pattern 126 may be placed on the lower surface of the fifth insulating layer 115 and thereby covered by the seventh insulating layer 117. The seventh circuit pattern 127 may be placed on the upper surface of the sixth insulating layer 116 and thereby covered by the eighth insulating layer 118. The eighth circuit pattern 128 may be located on the underside of the seventh insulating layer 117, thereby being covered by the ninth insulating layer.

[0093] The outer layer circuit pattern may be located on the surface of the outermost insulating layer, which is the outermost of the insulating layers 110. Preferably, the outer layer circuit pattern may include a first outer layer circuit pattern 130 located on the underside of a ninth insulating layer 119, which is the lowest of the insulating layers 110.

[0094] Furthermore, the outer layer circuit pattern may include a second outer layer circuit pattern 140 located on the upper surface of an eighth insulating layer 118, which is located at the top of the insulating layer 110.

[0095] In this case, at least one of the first outer layer circuit pattern 130 and the second outer layer circuit pattern 140 may be formed protruding from the surface of the insulating layer. Preferably, the first outer layer circuit pattern 130 may be formed protruding below the lower surface of the ninth insulating layer 119. The second outer layer circuit pattern 140 may be formed protruding above the upper surface of the eighth insulating layer 118.

[0096] In other words, the upper surface of the first outer layer circuit pattern 130 can be located on the same plane as the lower surface of the ninth insulating layer 119. The lower surface of the second outer layer circuit pattern 140 can be located on the same plane as the upper surface of the primer layer 150 which is located on the upper surface of the eighth insulating layer 180.

[0097] In other words, a primer layer 150 may be placed on the upper surface of the eighth insulating layer 180 and on the second outer layer circuit pattern 140.

[0098] That is, the second outer layer circuit pattern 140 may include a fine circuit pattern. Preferably, the second outer layer circuit pattern 140 may be a fine circuit pattern with a line width of 10 μm or less and spacing between patterns of 10 μm or less. As a result, when the second outer layer circuit pattern 140 is directly placed on the eighth insulating layer 118, the contact area between the eighth insulating layer 118 and the second outer layer circuit pattern 140 is small, which may cause the second outer layer circuit pattern 150 to detach from the eighth insulating layer 118.

[0099] Therefore, in the embodiment, a primer layer 150 is placed between the second outer layer circuit pattern 140 and the eighth insulating layer 118. The primer layer 150 can improve the adhesion between the second outer layer circuit pattern 140 and the eighth insulating layer 118. The primer layer 150 may be placed so as to completely cover the upper surface of the eighth insulating layer 118. The second outer layer circuit pattern 140 may be placed partially on the primer layer 150. Therefore, the upper surface of the primer layer 150 in the embodiment may include a first portion that contacts the second outer layer circuit pattern 140 and a second portion that contacts the lower surface of the solder resist 160, which will be described later. That is, the primer layer 150 can play a role in strengthening the bonding force between the eighth insulating layer 118 and the second outer layer circuit pattern 140 when the second outer layer circuit pattern 140 is formed by the SAP process. Such a primer layer 150 may include, but is not limited to, polyurethane resins, acrylic resins, and silicone resins.

[0100] On the other hand, Figure 3 shows that no primer layer is placed between the ninth insulating layer 119 and the first outer layer circuit pattern 130, but the primer layer may also be placed between the ninth insulating layer 119 and the first outer layer circuit pattern 130. However, the first outer layer circuit pattern 130 may not be a fine circuit pattern, and as a result, the primer layer between the ninth insulating layer 119 and the first outer layer circuit pattern 130 may be selectively omitted.

[0101] In conclusion, when a microcircuit pattern is arranged in the inner layer, it is covered by at least one of the insulating layers 110, so the primer layer can be omitted. On the other hand, in the embodiment, when a microcircuit pattern is arranged in the outermost layer, there is no insulating layer covering the microcircuit pattern, so the primer layer 150 is provided to improve the bonding strength between the microcircuit pattern and the insulating layer.

[0102] In the following description, the second outer layer circuit pattern 140 is formed on a fine circuit pattern. However, the embodiments are not limited to this, and the first outer layer circuit pattern 130 may also be formed on a fine circuit pattern. Thus, it is clear that the structures for improving reliability, such as strengthening the bonding force and preventing collapse of the second outer layer circuit pattern 140, as described below, can also be applied to the first outer layer circuit pattern 130.

[0103] The inner layer circuit pattern 120, the first outer layer circuit pattern 130, and the second outer layer circuit pattern 140 are wirings that transmit electrical signals and can be formed from a highly electrically conductive metallic material. For this reason, the inner layer circuit pattern 120, the first outer layer circuit pattern 130, and the second outer layer circuit pattern 140 can consist of at least one metallic material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Furthermore, the inner layer circuit pattern 120, the first outer layer circuit pattern 130, and the second outer layer circuit pattern 140 can consist of a paste or solder paste containing at least one metallic material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which have excellent bonding strength. Preferably, the inner layer circuit pattern 120, the first outer layer circuit pattern 130, and the second outer layer circuit pattern 140 can be made of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0104] At least one of the inner layer circuit pattern 120, the first outer layer circuit pattern 130, and the second outer layer circuit pattern 140 can be manufactured using conventional circuit board manufacturing processes such as the additive process, subtractive process, MSAP (Modified Semi Additive Process), and SAP (Semi Additive Process), and a detailed explanation is omitted here.

[0105] Preferably, the first outer layer circuit pattern 130 and the second outer layer circuit pattern 140 are outermost layer circuit patterns located on the outermost part of the circuit board, and thus they can be formed by the SAP (Semi Additive Process) method.

[0106] On the other hand, vias V can be placed within the insulating layer 110. These vias V are placed within each insulating layer and thereby serve to electrically connect circuit patterns located in different layers.

[0107] A first via V1 may be placed within the first insulating layer 111. The first via V1 can electrically connect a first circuit pattern 121 located on the upper surface of the first insulating layer 111 and a second circuit pattern 122 located on the lower surface of the first insulating layer 111.

[0108] A second via V2 may be placed within the second insulating layer 112. The second via V2 can electrically connect the first circuit pattern 121 located on the upper surface of the first insulating layer 111 and the third circuit pattern 123 located on the upper surface of the second insulating layer 112.

[0109] A third via V3 may be placed within the third insulating layer 113. The third via V3 can electrically connect the second circuit pattern 122 located on the lower surface of the first insulating layer 111 and the fourth circuit pattern 124 located on the lower surface of the third insulating layer 113.

[0110] A fourth via V4 may be placed within the fourth insulating layer 114. The fourth via V4 can electrically connect the third circuit pattern 123, which is located on the upper surface of the second insulating layer 112, and the fifth circuit pattern 125, which is located on the upper surface of the fourth insulating layer 114.

[0111] A fifth via V5 may be placed within the fifth insulating layer 115. The fifth via V5 can electrically connect the fourth circuit pattern 124 located on the lower surface of the third insulating layer 113 and the sixth circuit pattern 126 located on the lower surface of the fifth insulating layer 115.

[0112] A sixth via V6 may be placed within the sixth insulating layer 116. The sixth via V6 can electrically connect the fifth circuit pattern 125, which is located on the upper surface of the fourth insulating layer 114, and the seventh circuit pattern 127, which is located on the upper surface of the sixth insulating layer 116.

[0113] A seventh via V7 may be placed within the seventh insulating layer 117. The seventh via V7 can electrically connect the sixth circuit pattern 126 located on the lower surface of the fifth insulating layer 115 and the eighth circuit pattern 128 located on the lower surface of the seventh insulating layer 117.

[0114] An eighth via V8 may be placed within the eighth insulating layer 118. The eighth via V8 can electrically connect the seventh circuit pattern 127, which is located on the upper surface of the sixth insulating layer 116, and the second outer layer circuit pattern 140, which is located on the upper surface of the primer layer 150.

[0115] A ninth via V9 may be placed within the ninth insulating layer 119. The ninth via V9 can electrically connect the eighth circuit pattern 128, which is located on the lower surface of the seventh insulating layer 117, and the first outer layer circuit pattern 130, which is located on the lower surface of the ninth insulating layer 119.

[0116] The via V described above can be formed by filling the inside of via holes formed within each insulating layer with a metallic material.

[0117] The via holes can be formed by any one of the following processing methods: mechanical, laser, or chemical. When the via holes are formed by mechanical processing, methods such as milling, drilling, and routing can be used; when they are formed by laser processing, UV or CO2 laser methods can be used; and when they are formed by chemical processing, chemicals including aminosilanes and ketones can be used to open the insulating layer 110.

[0118] On the other hand, the laser processing method is a cutting method that concentrates optical energy on the surface to melt and evaporate a portion of the material, thereby taking on a desired shape. It can easily process complex shapes created by computer programs and can also process composite materials that are difficult to cut by other methods.

[0119] Furthermore, the aforementioned laser processing has the advantage of being able to cut materials down to a minimum diameter of 0.005 mm and having a wide range of thicknesses that can be processed.

[0120] It is preferable to use a YAG (Yttrium Aluminum Garnet) laser, a CO2 laser, or an ultraviolet (UV) laser as the laser processing drill. A YAG laser can process both the copper foil layer and the insulating layer, while a CO2 laser can process only the insulating layer.

[0121] Once the via holes are formed, the inside of the via holes can be filled with a conductive material to form the first to ninth vias V1, V2, V3, V4, V5, V6, V7, V8, and V9. The metallic material used to form the first to ninth vias V1, V2, V3, V4, V5, V6, V7, V8, and V9 may be any one of the following: copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). The filling of the conductive material can be carried out by any one of the following methods, or a combination thereof: electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjet printing, and defencing.

[0122] On the other hand, a protective layer may be placed on the outermost surface of the circuit board 100. Preferably, a first protective layer 160 may be placed on top of the eighth insulating layer 118 (preferably on top of the primer layer 150). Also, a second protective layer 175 may be placed below the ninth insulating layer 119.

[0123] The first protective layer 160 and the second protective layer 175 can be formed in at least one layer using one or more of SR (Solder Resist), oxide, and Au. Preferably, the first protective layer 160 and the second protective layer 175 can be solder resist.

[0124] On the other hand, a first protective layer 160 is placed on the primer layer 150. The first protective layer 160 can support the second outer layer circuit pattern 140 placed on the primer layer 150 and protect the surface of the second outer layer circuit pattern 140.

[0125] That is, the first protective layer 160 may partially overlap with the second outer layer circuit pattern 140 disposed on the primer layer 150. The area of ​​the first protective layer 160 may be smaller than the area of ​​the eighth insulating layer 118. The area of ​​the first protective layer 160 may be smaller than the area of ​​the primer layer 150. The first protective layer 160 may be disposed partially or entirely on the primer layer 150 and the second outer layer circuit pattern 140, thereby including open areas that expose the surface of the second outer layer circuit pattern 140.

[0126] The first protective layer 160 may include open regions in the shape of grooves. Preferably, the first protective layer 160 includes open regions that expose the surfaces of the second outer layer circuit pattern 140 located in the first region R1 and the second region R2. In this case, the first region R1 and the second region R2 may be open regions on which the surfaces of the second outer layer circuit pattern 140 are exposed. That is, the first region R1 and the second region R2 include element mounting pads on which chip elements are mounted, core pads or BGA pads that serve as dies for connecting to an external board, and traces which are signal transmission lines. The first protective layer 160 has open regions in the first region R1 and the second region R2 that expose the surfaces of the element mounting pads, the core pads, and the BGA pads.

[0127] In conclusion, the first region R1 and the second region R2 can be defined as the upper regions of the primer layer 150 and the second outer circuit pattern 140, where the surface of the second outer circuit pattern 140 is exposed via the first protective layer 160.

[0128] That is, the circuit board includes a first region R1, a second region R2, and a third region R3. The first region R1 and the second region R2 are open regions in which the surface of the second outer layer circuit pattern 140 should be exposed via the first protective layer 160, and the third region R3 may be a recessed region in which the surface of the second outer layer circuit pattern 140 is covered by the first protective layer 160.

[0129] Specifically, the first region R1 is the region of the second outer layer circuit pattern 140 in which the first pad 142 and trace 141a for electrically connecting to components such as chips are arranged. Therefore, the first protective layer 160 can have an open region that exposes the surface of the first pad 142 included in the first region R1. The second region R2 is the region of the second outer layer circuit pattern 140 in which the second pad 143 corresponding to a core pad or BGA pad that performs die function for bonding to an external board or the like is arranged.

[0130] Furthermore, the second outer layer circuit pattern 140, which is placed within the first region R1 as described above, may experience reliability problems such as collapse or abrasion due to various factors. Moreover, the traces 141a constituting the second outer layer circuit pattern 140 are fine circuit patterns, and thus have a line width W1 of 10 μm or less and a spacing of 10 μm or less, and are placed on the primer layer 150. As a result, the traces 141 placed on the first region R1 may easily experience problems such as collapse or abrasion due to various small external impacts.

[0131] In this embodiment, in order to improve the reliability of the second outer layer circuit pattern 140 placed on the first region R1, the first protective layer 160 is also placed on the primer layer 150 corresponding to the first region R1.

[0132] That is, the first protective layer 160 may be placed on the upper surface of the primer layer 150 in an area where the second outer layer circuit pattern 140 is not located. For example, the first protective layer 160 may be placed on the upper surface of the primer layer 150 and thereby positioned between the second outer layer circuit patterns 140 on the first region R1.

[0133] In this case, the second outer layer circuit pattern 140 includes a second-first outer layer circuit pattern arranged in the first region R1 and the second region R2, and a second-second outer layer circuit pattern formed in the third region R3.

[0134] Furthermore, the upper surface of the primer layer 150 may include a first upper surface corresponding to the first region R1, a second upper surface corresponding to the second region R2, and a third upper surface corresponding to the third region R3.

[0135] In this case, the first protective layer 160 is distributed evenly on the primer layer 150 without distinguishing between the first region R1, the second region R2, and the third region R3. That is, the first protective layer 160 can be distributed in the region between the second-1 outer layer circuit patterns and the region between the second-2 outer layer circuit patterns, respectively.

[0136] As a result, the first protective layer 160 includes a first part located in the first region R1, a second part located in the second region R2, and a third part located in the third region R3.

[0137] In this case, the first protective layer 160 may have steps.

[0138] That is, in the first region R1 and the second region R2, the surface of the second outer layer circuit pattern 140 should be exposed to the outside, and in the third region R3, the surface of the second outer layer circuit pattern 140 should be covered by a protective layer.

[0139] Here, the second outer layer circuit patterns 140 arranged in the first region R1 and the second region R2 may have different widths depending on their function. For example, the second outer layer circuit patterns 140 arranged in the first region R1 and the second region R2 may include a first pad 142, a second pad 143, and a trace 141, as described above.

[0140] In this case, trace 141 can have a width of 10 μm or less. The first pad can have a width of approximately 45 μm. The second pad 143 can have a width W3 between 100 μm and 300 μm.

[0141] As a result, in the embodiment, a first protective layer 160 having different heights or structures is formed in the open region of the solder resist as described above, with respect to the region where the trace 141 is located, the region where the first pad 142 is located, and the region where the second pad 143 is located.

[0142] That is, the first protective layer 160 may include a first part located in the first region R1, a second part located in the second region R2, and a third part located in the third region R3. At least one of the first part, the second part, and the third part may have a different height from at least one of the others.

[0143] For example, the upper surface of the first part located in the first region R1 can be positioned lower than the upper surfaces of the second part located in the second region R2 and the third part located in the third region R3.

[0144] Furthermore, the upper surface of the second part may be positioned higher than the upper surface of the first part. Also, the upper surface of the second part may be at the same height as the upper surface of the third part. That is, the upper surface of the second part may be located on the same plane as the upper surface of the third part.

[0145] The first protective layer 160 will be described in detail below.

[0146] The first protective layer 160 may be placed on the primer layer 150. The first protective layer 160 is a solder resist.

[0147] The first protective layer 160 may be placed on the primer layer 150 between the second outer layer circuit patterns 140. That is, the second outer layer circuit patterns 140 are placed on the primer layer 150 at regular intervals apart. The first protective layer 160 may be placed on the upper surface of the primer layer 150 in an area where the second outer layer circuit patterns 140 are not placed. The first protective layer 160 may also be selectively placed on the second outer layer circuit patterns 140.

[0148] In the following description, the first protective layer 160 will be referred to as solder resist 160.

[0149] The solder resist 160 may be placed on the upper surface of the primer layer 150 in an area where the second outer layer circuit pattern 140 is not located.

[0150] As a result, the lower surface of the solder resist 160 may be in direct contact with the upper surface of the primer layer 150. Furthermore, the solder resist 160 may have a structure that allows it to be in direct contact with the second outer layer circuit pattern 140.

[0151] For example, the first part of the solder resist 160 located in the first region R1 may be in direct contact with the side surface of the second outer layer circuit pattern 140. Alternatively, the first part of the solder resist 160 located in the first region R1 may not be in contact with the top surface of the second outer layer circuit pattern 140. That is, the first part of the solder resist 160 located in the first region R1 may expose the top surface of the second outer layer circuit pattern 140. As a result, the height of the first part of the solder resist 160 may be lower than the height of the second outer layer circuit pattern 140. As a result, the first part of the solder resist 160 located in the first region R1 may expose the entire top surface and part of the side surface of the second outer layer circuit pattern 140.

[0152] Furthermore, the second part of the solder resist 160 located in the second region R2 may be in direct contact with the side surface of the second outer layer circuit pattern 140. Also, the second part of the solder resist 160 located in the second region R2 may be in direct contact with a portion of the upper surface of the second outer layer circuit pattern 140. Furthermore, the second part of the solder resist 160 located in the second region R2 may expose the upper surface of the second outer layer circuit pattern 140.

[0153] Furthermore, the third part of the solder resist 160 located in the third region R3 may be in direct contact with the side surface of the second outer layer circuit pattern 140. Also, the third part of the solder resist 160 located in the third region R3 may be in direct contact with the top surface of the second outer layer circuit pattern 140. That is, the third part of the solder resist 160 located in the third region R3 may protrude above the top surface of the second outer layer circuit pattern 140 to a certain height, covering the second outer layer circuit pattern 140. More specifically, the third part of the solder resist 160 located in the third region R3 may be arranged to enclose the side and top surfaces of the second outer layer circuit pattern 140.

[0154] On the other hand, the second outer layer circuit pattern 140 according to the embodiment may have different heights in each region. On the other hand, the second outer layer circuit pattern 140 may include trace 141, first pad 142, and second pad 142 as described above.

[0155] In this case, the first pad 142 may be located in the first region R1, and the second pad 142 may be located in the second region R2. Furthermore, the trace 141 may include a first trace 141a located in the first region R1 and a second trace 141b located in the third region R3.

[0156] Furthermore, the height of the first trace 141a may be different from the height of the second trace 141b.

[0157] The first trace 141a may have a first height H1. The first height H1 of the first trace 141a may be between 14.5 μm and 16.25 μm.

[0158] The second trace 141b may have a second height H2 that is greater than the first height H1. The second height H2 may be 16 μm to 17 μm. Here, the height difference between the first trace 141a and the second trace 141b may be 0.75 μm to 1.5 μm.

[0159] For example, the first height H1 of the first trace 141a can be in the range of 90% to 95% of the second height H2 of the second trace 141b.

[0160] That is, the first height H1 of the first trace 141a in the embodiment is smaller than the second height H2 of the second trace H2. This is because etching was performed on the first trace 141a formed in the first region R1 in order to remove the resin remaining on the upper surface of the first trace 141a. In other words, the first part of the solder resist 160 is removed by the thinning process while it is placed on the first region R1 covering the first trace 141a, and comes to have a height lower than the first trace 141a. At this time, the thinning process does not completely remove the resin remaining on the surface of the first trace 141a, which can cause reliability problems. Therefore, in the embodiment, an etching process is performed on the surface of the first trace 141a to completely remove the remaining resin.

[0161] If the first height H1 of the first trace 141a is less than 90% of the second height H2 of the second trace 141b, this means that the first trace 141a has been excessively etched, which may cause reliability problems due to deformation of the shape of the first trace 141a. Also, if the first height H1 of the first trace 141a is greater than 95% of the second height H2 of the second trace 141b, this means that the first trace 141a has not been etched sufficiently, which may cause reliability problems due to residual resin on the surface of the first trace 141a. Therefore, in this embodiment, the first height H1 of the first trace 141a is set to be within the range of 90% to 95% of the second height H2 of the second trace 141b, thereby resolving the above-mentioned reliability problems.

[0162] The first part of the solder resist 160 may have a third height H3. The third height H3 may be smaller than the first height H1. For example, the third height H3 of the first part of the solder resist 160 may be 70% to 85% of the first height H1 of the first trace 141a. For example, if the third height H3 of the first part of the solder resist 160 is smaller than 70% of the first height H1 of the first trace 141a, the first part of the solder resist 160 may not be able to provide stable support for the first trace 141a. For example, if the third height H3 of the first part of the solder resist 160 is smaller than 70% of the first height H1 of the first trace 141a, the area of ​​the portion of the first trace 141a that protrudes above the surface of the solder resist 160 becomes larger, which may make it difficult to control the etching process of the first trace 141a. In other words, if the area of ​​the portion of the first trace 141a that protrudes above the surface of the solder resist 160 becomes large, it becomes difficult to accurately etch only the desired height in the etching process. For example, if the area of ​​the portion of the first trace 141a that protrudes above the surface of the solder resist 160 becomes large, more etching than the desired height may occur in the etching process, resulting in severe deformation (e.g., crushing) of the first trace 141a, which can cause reliability problems.

[0163] On the other hand, the third part of the solder resist 160 may have a fourth height H4. The fourth height H4 of the third part of the solder resist 160 is greater than the first height H1, the second height H2, and the third height H3.

[0164] In this case, the third part of the solder resist 160 is positioned to cover the second outer layer circuit pattern 140 in order to stably protect the second outer layer circuit pattern 140. In this case, the fourth height H4 may be 20 μm to 40 μm. If the fourth height H4 is less than 20 μm, the second outer layer circuit pattern 140 embedded in the third part of the solder resist 160 cannot be stably protected from various factors. Also, if the fourth height H4 is greater than 40 μm, the overall thickness of the circuit board may increase. Also, if the fourth height H4 is greater than 40 μm, the manufacturing cost of the circuit board may increase.

[0165] On the other hand, the second part of the solder resist 160 located in the second region R2 may include an opening. The second part of the solder resist 160 may be located in the second region R2 and have an opening that exposes a portion of the upper surface of the second pad 143. Alternatively, the second part of the solder resist 160 may be positioned to cover a portion of the upper surface of the second pad 143. In this case, the height of the second part of the solder resist 160 may correspond to the height of the third part of the solder resist 160.

[0166] That is, the second outer layer circuit pattern 140 included in the second region R2 is the second pad 143. The second pad 143 may be a BGA pad or a core pad, as described above. Therefore, the second pad 143 can have a relatively larger width compared to other pads. For example, the second pad 143 may have a width W3 of 100 μm to 300 μm. And because the second pad 143 has a relatively large width, it is not greatly affected by the exposure resolution. That is, because the second pad 143 has a relatively large width, there is no reliability problem even if only a part of the upper surface of the second pad 143 is exposed, rather than the whole. In other words, even if only a part of the upper surface of the second pad 143 is exposed, it does not greatly affect the die function for bonding with other external boards. Therefore, the second part of the solder resist 160 may be arranged to cover a part of the upper surface of the second pad 143 as described above. More specifically, the second part of the solder resist 160 is positioned to protrude above the upper surface of the second pad 143, having the same fourth height H4 as the first part, and has an opening region that exposes a portion of the upper surface of the second pad 143.

[0167] On the other hand, the second pad 143 may also undergo an etching process to remove residual resin along with the first trace 141a. As a result, the upper surface of the second pad 143 may have a step. That is, the second pad 143 may include a first portion covered by the second part of the solder resist 160 and a second portion that exposes the opening region of the second part of the solder resist 160. The first and second portions of the second pad 143 may have different heights from each other.

[0168] Furthermore, the first portion of the second pad 143 may have a fifth height H5. Also, the second portion of the second pad 143 may have a sixth height H6 that is smaller than the fifth height H5. The sixth height H6 of the second portion of the second pad 143 may be between 14.5 μm and 16.25 μm.

[0169] Furthermore, the first portion of the second pad 143 may have a fifth height H5 that is greater than the sixth height H6. The fifth height H5 may be 16 μm to 17 μm. Here, the height difference between the first portion and the second portion of the second pad 143 may be 0.75 μm to 1.5 μm.

[0170] For example, the sixth height H6 of the second part of the second pad can be in the range of 90% to 95% of the fifth height H5 of the first part of the second pad 143.

[0171] That is, the sixth height H6 of the second portion of the second pad 143 in the embodiment is smaller than the fifth height H5 of the first portion of the second pad 143. This is because etching was performed on the second portion of the second pad 143 exposed through the opening region of the second part of the solder resist 160 in order to remove the resin remaining on the upper surface of the second pad 143. In other words, the second part of the solder resist 160 is removed through a thinning process while covering the second pad 143 on the second region R2, thereby forming the opening region. At this time, the thinning process does not completely remove the resin remaining on the surface of the second pad 143, which can cause reliability problems. Therefore, in the embodiment, an etching process is performed on the surface of the second portion of the second pad 143 to completely remove the remaining resin.

[0172] In this case, etching of the second pad 143 may be performed together with the first trace 141a. Therefore, the etching conditions for the second pad 143 may correspond to the etching conditions for the first trace 141a.

[0173] Consequently, if the sixth height H6 of the second portion of the second pad 143 is less than 90% of the fifth height H5 of the first portion of the second pad 143, this means that the second pad 143 has been excessively etched, which may cause reliability problems due to deformation of the shape of the second pad 143. Also, if the sixth height H6 of the second portion of the second pad 143 is greater than 95% of the fifth height H5 of the first portion of the second pad 143, this means that the second portion of the second pad 143 has not been sufficiently etched, which may cause reliability problems due to residual resin on the surface of the second portion of the second pad 143. Therefore, in this embodiment, the sixth height H6 of the second portion of the second pad 143 is set to be within the range of 90% to 95% of the fifth height H5 of the first portion of the second pad 143, thereby resolving the above-mentioned reliability problems.

[0174] On the other hand, the first pad 142 may have the same height as the second portion of the second pad 143. That is, the first pad 142 may have a lower height than the first portion of the second pad 143. That is, the first pad 142 may be etched together with the second portion of the second pad 143, thereby allowing the first pad 142 to have a seventh height H7 corresponding to the sixth height H6 of the second portion of the second pad 143.

[0175] The solder resist 160 can be a photosolder resist film. The solder resist 160 may have a structure in which resin and filler are mixed.

[0176] For example, the solder resist 160 may contain fillers such as BaSO4, SiO2, and Talc, and the content of these fillers may be 20% to 35% by weight.

[0177] In this case, if the filler content in the solder resist 160 is less than 20% by weight, the second outer layer circuit pattern 140 may not be stably protected by the solder resist 160. Also, if the filler content in the solder resist 160 is greater than 35% by weight, some filler may remain on the second outer layer circuit pattern 140 when the solder resist 160 is developed.

[0178] That is, a protective layer including a solder resist 160 according to an embodiment will be described. Here, the solder resist 160 may be a protective layer that protects the surface of the second outer layer circuit pattern 140 in the third region R3, and may be a support layer that supports the second outer layer circuit pattern 140 in the first region R1.

[0179] In this comparative example, the circuit pattern is arranged with a structure that protrudes from the insulating layer. Furthermore, the circuit pattern is not supported by any other support layer and can be arranged independently on the insulating layer. As a result, in the region corresponding to the fine pattern in the comparative example, distortion and friction phenomena of the circuit pattern occur.

[0180] This can occur in the outermost layer of circuit patterns in circuit boards containing circuit patterns manufactured using the SAP method.

[0181] In contrast, in this embodiment, a primer layer 150 is placed on the eighth insulating layer 118, and a second outer layer circuit pattern 140 is placed on the primer layer 150.

[0182] Then, the first to third parts of the solder resist 160, which functions as a support layer and a protective layer, are placed on the primer layer 150, surrounding the second outer layer circuit pattern 140.

[0183] In this case, the solder resist 160 may be placed in the first region R1, the second region R2, and the third region R3. The solder resist 160 can support the second outer layer circuit pattern 140 which is placed on the outermost layer of the circuit board 100, and in particular can support the traces 141a and the first pads 142 of the second outer layer circuit pattern 140 which is placed in the first region R1, thereby protecting the second outer layer circuit pattern 140 from external impacts.

[0184] On the other hand, as described above, in the embodiment, an etching process is performed on the second outer layer circuit pattern 140 exposed through the first region R1 and the second region R2, and a residual resin removal process is performed. Therefore, even for the same trace, the heights of the second trace 141b located in the third region R3 and the first trace 141a located in the first region R1 are shown to be different from each other.

[0185] In this case, the etching must completely remove the residual resin without causing deformation of the second outer layer circuit pattern 140. That is, if the degree of etching is too small, residual resin may still be present on the surface of the second outer layer circuit pattern 140 despite the etching being performed. Also, if the degree of etching is too severe, the etching may cause deformation of the second outer layer circuit pattern 140 (for example, surface crushing), which may lead to reliability problems.

[0186] Figures 7 and 8 show the degree of residual resin depending on the degree of etching.

[0187] Referring to Figure 7, Figure 7(a) shows the surface of the second outer layer circuit pattern 140 after etching under the first condition. Figure 7(b) is an enlarged view of Figure 7(a). Specifically, Figures 7(a) and (b) show the surface of the second outer layer circuit pattern 140 when etched to a height of approximately 0.5 μm.

[0188] At this time, it was confirmed that residual resin remained on the surface of the second outer layer circuit pattern 140 even after etching the surface of the second outer layer circuit pattern 140 to a thickness of approximately 0.5 μm.

[0189] That is, the surface properties of the second outer layer circuit pattern 140 after etching the second outer layer circuit pattern 140 under the first condition are as shown in Table 1 below.

[0190] [Table 1]

[0191] As shown in Table 1, the surface properties of the second outer layer circuit pattern 140 after 0.5 μm etching confirmed that Cu was present in an amount of 80 Wt% or less. Furthermore, as shown in Table 1, the surface properties of the second outer layer circuit pattern 140 after 0.5 μm etching confirmed that C, corresponding to the solder resist, was present in an amount of 20 Wt% or more.

[0192] Referring to Figure 8, Figure 8(a) shows the surface of the second outer layer circuit pattern 140 after etching under the second condition. Figure 8(b) is an enlarged view of Figure 8(a). Specifically, Figures 8(a) and (b) show the surface of the second outer layer circuit pattern 140 when etched to a height of approximately 0.75 μm to 0.95 μm.

[0193] At this time, after etching the surface of the second outer layer circuit pattern 140 to a thickness of approximately 0.75 μm to 0.95 μm, it was confirmed that no residual resin remained on the surface of the second outer layer circuit pattern 140.

[0194] That is, the surface properties of the second outer layer circuit pattern 140 after etching the second outer layer circuit pattern 140 under the second condition are as shown in Table 2 below.

[0195] [Table 2]

[0196] As shown in Table 2, the surface properties of the second outer layer circuit pattern 140 after etching to 0.75 μm~0.95 μm confirmed that the Cu content was 80 Wt% or more. Furthermore, as shown in Table 2, the surface properties of the second outer layer circuit pattern 140 after etching to 0.75 μm~0.95 μm confirmed that the C corresponding to the solder resist was present at 20 Wt% or less. This means that when etching the second outer layer circuit pattern 140 to 0.75 μm, the resin remaining on the surface of the second outer layer circuit pattern 140 was completely removed.

[0197] Here, while Table 2 explains that the second outer layer circuit pattern 140 is etched to a depth of approximately 0.75 μm to 0.95 μm, this can be substantially determined by the height of the initially formed second outer layer circuit pattern 140. That is, the etching degree may be performed to a height of 5% to 10% of the initially formed second outer layer circuit pattern 140.

[0198] Figure 9 shows the shape of the second outer layer circuit pattern according to the embodiment, depending on the etching state.

[0199] Referring to Figure 9, (a) shows the change in shape of trace 141 after etching to approximately 0.5 μm, and (b) shows the change in shape of trace 141 after etching to approximately 0.75 μm to 0.95 μm.

[0200] As shown in Figure 8, even after etching trace 141 to approximately 0.75 μm to 0.95 μm, changes in surface shape still occurred, but it was confirmed that there were no reliability issues, and that any residual resin on the surface was completely removed.

[0201] Figures 10 to 17 show the manufacturing process of the circuit board shown in Figure 2, in chronological order.

[0202] Referring to Figure 10, the embodiment can prioritize the process of manufacturing the inner layer substrate 100-1, which is the inner portion of the circuit board 100.

[0203] A brief explanation will be given regarding the process for manufacturing the inner layer substrate 100-1.

[0204] The inner layer substrate 100-1 may include one insulating layer, or it may include multiple insulating layers.

[0205] Figure 10 shows the inner layer substrate 100-1 having a 7-layer insulating layer structure, but it is not limited to this. For example, the inner layer substrate 100-1 may contain fewer than 7 insulating layers, or conversely, it may contain more than 7 insulating layers.

[0206] The inner layer substrate 100-1 may include the remaining insulating layers in the circuit board 100, excluding the insulating layer located at the outermost layer. For example, the inner layer substrate 100-1 may include the remaining insulating layers in the circuit board 100, excluding the insulating layer located at the top and the insulating layer located at the bottom.

[0207] To briefly explain the process for manufacturing the inner layer substrate 100-1, the first insulating layer 111 is prepared as a priority.

[0208] Then, once the first insulating layer 111 is prepared, a first via V1 is formed within the first insulating layer 111, and together with the via V1, a first circuit pattern 121 and a second circuit pattern 122 are formed on the upper and lower surfaces of the first insulating layer 111, respectively.

[0209] Subsequently, a second insulating layer 112 is formed on the first insulating layer 111, and a third insulating layer 113 is formed below the first insulating layer 111.

[0210] Next, a second via V2 is formed within the second insulating layer 112, and a third circuit pattern 123 is formed on the upper surface of the second insulating layer 112. Furthermore, a third via V3 is formed within the third insulating layer 113, and a fourth circuit pattern 124 is formed below the lower surface of the third insulating layer 113.

[0211] Subsequently, a fourth insulating layer 114 is formed on the second insulating layer 112, and a fifth insulating layer 115 is formed below the third insulating layer 113.

[0212] Next, a fourth via V4 is formed within the fourth insulating layer 114, and a fifth circuit pattern 125 is formed on the upper surface of the fourth insulating layer 114. Furthermore, a fifth via V5 is formed within the fifth insulating layer 115, and a sixth circuit pattern 126 is formed below the lower surface of the fifth insulating layer 115.

[0213] Subsequently, a sixth insulating layer 116 is formed on the fourth insulating layer 114, and a seventh insulating layer 117 is formed below the fifth insulating layer 115.

[0214] Next, a sixth via V6 is formed within the sixth insulating layer 116, and a seventh circuit pattern 127 is formed on the upper surface of the sixth insulating layer 116. Furthermore, a seventh via V7 is formed within the seventh insulating layer 117, and an eighth circuit pattern 128 is formed below the lower surface of the seventh insulating layer 117.

[0215] Since the process for manufacturing the inner layer substrate 100-1 is a known technique in the art to which the present invention belongs, a detailed explanation thereof will be omitted.

[0216] Referring to Figure 11, when the inner layer substrate 100-1 is manufactured, an eighth insulating layer 118 corresponding to the first outermost insulating layer is formed on the upper surface of the inner layer substrate 100-1. Also, a ninth insulating layer 119 corresponding to the second outermost insulating layer is formed below the lower surface of the inner layer substrate 100-1.

[0217] In this case, when the eighth insulating layer 118 and the ninth insulating layer 119 are laminated, a primer layer 150 may be placed on the upper surface of the eighth insulating layer 118 and the lower surface of the ninth insulating layer 119, and a metal layer 155 may be placed on the primer layer 150. The metal layer 155 can serve to flatten the eighth insulating layer 118 and the ninth insulating layer 119 so that they have a uniform height. For example, the metal layer 155 may be placed to improve the lamination reliability of the eighth insulating layer 118 and the ninth insulating layer 119.

[0218] The primer layer 150 can enhance the bonding force between the eighth insulating layer 118 and the ninth insulating layer 119 and the first outer layer circuit pattern 130 and the second outer layer circuit pattern 140, which are positioned above and below them, respectively. That is, if the first outer layer circuit pattern 130 and the second outer layer circuit pattern 140 are positioned without the primer layer 150, the bonding force between the eighth insulating layer 118 and the second outer layer circuit pattern 140 is low, and they may separate from each other.

[0219] On the other hand, while Figure 11 shows that the primer layer 150 is placed on the upper surface of the eighth insulating layer 118 and the lower surface of the ninth insulating layer 119, the invention is not limited to this. For example, the primer layer 150 can be selectively placed on the surface of the insulating layer on which the fine circuit pattern is placed. That is, if only the first outer layer circuit pattern 130 is a fine circuit pattern, the primer layer 150 can be placed only on the lower surface of the ninth insulating layer 119. Also, if only the second outer layer circuit pattern 140 is a fine circuit pattern, the primer layer 150 can be placed only on the upper surface of the eighth insulating layer 118. Furthermore, if both the first outer layer circuit pattern 130 and the second outer layer circuit pattern 140 are fine circuit patterns, the primer layer 150 can be placed on both the upper surface of the eighth insulating layer 118 and the lower surface of the ninth insulating layer 119.

[0220] Referring to Figure 12, when the eighth insulating layer 118 and the ninth insulating layer 119 are arranged, via holes VH are formed within the eighth insulating layer 118 and the ninth insulating layer 119, respectively. At this time, the via holes VH may be formed not only within the eighth insulating layer 118 and the ninth insulating layer 119, but also in the primer layer 150 and the metal layer 155, respectively.

[0221] Next, referring to Figure 13, once the via hole VH is formed, an etching process can be performed to remove the metal layer 155 placed on the primer layer 150. For example, after the via hole VH is formed, a flash etching process can be performed to remove the metal layer 155, thereby exposing the surface of the primer layer 150.

[0222] Next, referring to Figure 14, a via V formation step can be performed to fill the via hole VH, thereby forming a second outer layer circuit pattern 140 on the upper surface of the eighth insulating layer 118 and a first outer layer circuit pattern 130 on the lower surface of the ninth insulating layer 119. In this embodiment, the first outer layer circuit pattern 130 is shown to be a general circuit pattern and not a fine circuit pattern. However, it is not limited to this, and the first outer layer circuit pattern 130, along with the second outer layer circuit pattern, may also be a fine circuit pattern. In this case, if the first outer layer circuit pattern 130 is a general circuit pattern, the primer layer 150 between the ninth insulating layer 119 and the first outer layer circuit pattern 130 may be omitted.

[0223] An upper outer layer circuit pattern 140 is arranged on the upper surface of the eighth insulating layer 118. In this case, the upper outer layer circuit pattern 140 arranged on the upper surface of the eighth insulating layer 118 may include portions arranged in the open regions R1 and R2 of the first protective layer 170 and portions arranged in the arrangement region R3 of the first protective layer 170. Traces and pads, which are wiring lines for signal transmission, may be arranged in each of the regions R1, R2, and R3.

[0224] Specifically, a trace 141 and a first pad 142 may be arranged in the first region R1. The first pad 142 may be a mounting pad on which an element is mounted.

[0225] Furthermore, a second pad 143 may be placed in the second region R2. The second pad 143 may be a BGA pad or a core pad. In particular, the second pad 143 may have a larger width than the first pad 142. Therefore, the second pad 143 is not significantly affected by the development resolution, and a solder resist 170 with a different shape from the solder resist 170 placed in the first region R1 may be placed there.

[0226] On the other hand, trace 141 may include a first trace 141a located in the first region R1 and a second trace 141b located in the second region R2.

[0227] Next, referring to Figure 15, a solder resist layer is placed on the primer layer 150 so as to cover the upper outer layer circuit pattern 140. The solder resist layer formed at this time may be placed in all of the first region R1, the second region R2, and the third region R3, and may be formed to have a height greater than the upper outer layer circuit pattern 140.

[0228] Referring to Figure 16, once the solder resist layer is formed, the solder resist layer can be exposed and developed to form a solder resist 160 having different heights in each region. Preferably, in the embodiment, a part of the second region R2 and the entire third region R3 of the solder resist layer can be exposed, thereby developing the entire first region R1 and a part of the second region R2 of the solder resist layer.

[0229] To achieve this, a process is performed to mask only a desired area on the solder resist layer and perform UV exposure, and then, in the unexposed areas, the height of the solder resist layer is adjusted by dipping it in an organic alkaline compound containing tetramethylammonium hydroxide (TMAH) or trimethyl-2-hydroxyethylammonium hydroxide (choline), thereby forming the solder resist 160. At this time, the height adjustment of the solder resist layer in the second region R2 can be determined based on the height of the second outer layer circuit pattern 140. For example, the height of the solder resist layer in the second region R2 can be set to 70% to 85% of the height of the second outer layer circuit pattern 140.

[0230] Next, referring to Figure 17, an etching step can be performed on the first trace 141a and first pad 142 located in the first region R1, and the second pad 143 located in the second region R2. The etching step may be a step of removing the resin remaining on the surfaces of the first trace 141a, first pad 142, and second pad 143.

[0231] The features, structures, and effects described in the above embodiments are included in at least one embodiment, but are not necessarily limited to a single embodiment. Furthermore, the features, structures, and effects exemplified in each embodiment can be combined or modified for implementation in other embodiments by a person with ordinary skill in the art to which the embodiment belongs. Therefore, such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0232] While the above description has focused on examples, these are merely illustrative and not limiting. Anyone with ordinary knowledge in the field to which the examples belong will understand that a variety of modifications and applications not illustrated above are possible, as long as they do not deviate from the essential characteristics of these examples. For example, each component specifically shown in the examples can be modified and implemented. Such differences in modifications and applications should be interpreted as being included within the scope of the examples set forth in the attached claims.

Claims

1. Insulating layer and, An outer layer circuit pattern arranged on the insulating layer, The insulating layer includes a solder resist layer disposed on the insulating layer and comprising a first region having a first thickness and a second region having a second thickness greater than the first thickness, The solder resist layer includes through holes that penetrate the second region along the thickness direction of the solder resist layer. The outer layer circuit pattern is A first circuit pattern that penetrates the first region of the solder resist layer along the thickness direction, A second circuit pattern embedded within the second region of the solder resist layer, which does not overlap with the through-hole along the thickness direction, It includes a third circuit pattern that overlaps the through-hole along the thickness direction, The thickness of the first circuit pattern is less than the thickness of the second circuit pattern. The upper surface of the third circuit pattern includes a first portion that overlaps with the through-hole along the thickness direction, and a second portion connected to the first portion that does not overlap with the through-hole along the thickness direction. The first part is positioned lower than the second part, The upper surface of the first circuit pattern is positioned lower than the second portion of the third circuit pattern and at the same height as the first portion. The upper surface of the second circuit pattern and the second portion of the third circuit pattern are located on the same plane. The upper surface of the first circuit pattern and the first portion of the third circuit pattern each have a copper content of 80 wt% or more and a carbon content of 20 wt% or less. The upper surface of the first circuit pattern and the first portion of the third circuit pattern have a first thickness, The second portion of the second circuit pattern and the third circuit pattern has a second thickness, A circuit board in which the difference between the first thickness and the second thickness is 0.75 μm to 0.95 μm, and is 5% to 10% of the first thickness.

2. The circuit board according to claim 1, wherein the upper surface of the second circuit pattern is positioned higher than the upper surface of the first circuit pattern with reference to the upper surface of the insulating layer.

3. The circuit board according to claim 1, wherein the upper surface of the second circuit pattern is positioned higher than the first portion of the third circuit pattern with reference to the upper surface of the insulating layer.

4. The thickness of the first region of the solder resist layer is The circuit board according to claim 1, wherein the thickness of the first circuit pattern is in the range of 70% to 85%.

5. The circuit board according to claim 1, wherein the surface roughness of the upper surface of the first region of the solder resist layer is greater than the surface roughness of the upper surface of the second region of the solder resist layer.

6. The circuit board according to claim 1, further comprising a primer layer disposed between the outer layer circuit pattern and the insulating layer.

7. The invention further includes vias that penetrate the insulating layer from the upper surface of the insulating layer toward the lower surface of the insulating layer, The circuit board according to claim 6, wherein the via is further arranged to penetrate the primer layer.

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