Semiconductor equipment

Abstract

To provide a technology that can suppress characteristic fluctuations of semiconductor devices.SOLUTION: A semiconductor device has a semiconductor substrate, a plurality of first trenches, and two second trenches located between the plurality of first trenches and adjacent to each other. The semiconductor substrate has an n-type region in contact with a gate insulating film on the side of each first trench, a p-type body region in contact with the gate insulating film on the side of each first trench below the n-type region, a p-type first bottom region in contact with the gate insulating film at the bottom of each first trench, a p-type voltage holding region located between the two second trenches and extending from the gate insulating film in one second trench to the gate insulating film in the other second trench, and a p-type second bottom region at the bottom of each second trench that is in contact with the gate insulating film, is connected to the voltage holding region, and extends below the first bottom region.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The technology disclosed in this specification relates to a semiconductor device.

Background Art

[0002] In a semiconductor device having a trench, various structures have been proposed to mitigate the electric field concentration near the bottom of the trench. Patent Document 1 discloses a semiconductor device including a semiconductor substrate provided with a trench on its upper surface, a gate insulating film and a gate electrode disposed in the trench, and an upper electrode contacting the upper surface of the semiconductor substrate. In this semiconductor device, the semiconductor substrate has an n-type source region, a p-type contact region, a p-type base region, an n-type drift region, and a p-type bottom region (i.e., a deep region). The source region contacts the gate insulating film and the upper electrode. The contact region contacts the upper electrode. The base region is disposed below the source region and the contact region and contacts the gate insulating film below the source region. The drift region contacts the gate insulating film below the base region. Cited Document 1 discloses an aspect in which the bottom region contacts the gate insulating film on the bottom surface of the trench and an aspect in which the bottom region extends downward from the base region at a position spaced apart from the trench.

[0003] When this semiconductor device is turned off, a depletion layer spreads from the bottom region into the drift region. The depletion layer extending from the bottom region into the drift region suppresses the concentration of the electric field near the lower end of the trench.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] When this type of semiconductor device is turned off, a high voltage with a reverse bias is applied to the pn junction inside the semiconductor substrate, which may cause avalanche breakdown. In the semiconductor device described in Patent Document 1, when the above-mentioned high voltage is applied, the electric field concentrates at the lower end of the bottom region, causing avalanche breakdown at the lower end of the bottom region. In the semiconductor device described in Patent Document 1, holes generated by the avalanche breakdown flow through the base region to the upper electrode. At this time, some of the holes are injected into the gate insulating film, adversely affecting the gate insulating film. As a result, there is a problem that the characteristics of the semiconductor device fluctuate. This specification provides a technology that can control the region that causes avalanche breakdown and suppress fluctuations in the characteristics of the semiconductor device. [Means for solving the problem]

[0006] The semiconductor device (10) disclosed herein comprises a semiconductor substrate (12), a plurality of trenches (22) provided on the upper surface (12a) of the semiconductor substrate, a gate insulating film (24) covering the inner surface of the trenches, a gate electrode (26) disposed within the trenches and insulated from the semiconductor substrate by the gate insulating film, and an upper electrode (70) in contact with the upper surface of the semiconductor substrate. The plurality of trenches comprises a plurality of first trenches (22a) and two second trenches (22b) disposed between the plurality of first trenches and adjacent to each other. The semiconductor substrate comprises an n-type region (30) in contact with the gate insulating film on the side surface of each first trench and in contact with the upper electrode, a p-type body region (32) in contact with the gate insulating film on the side surface of each first trench below the n-type region, a p-type first bottom region (36a) in contact with the gate insulating film on the bottom surface of each first trench, and a region positioned between the two second trenches, in contact with the upper electrode, and extending from the gate insulating film in one second trench to the gate insulating film in the other second trench. The structure includes a p-type pressure-resistant holding region (40), a p-type second bottom region (36b) that is in contact with the gate insulating film at the bottom surface of each second trench, connected to the pressure-resistant holding region, and extending below the first bottom region, and an n-type drift region (34) that is distributed across the lower part of the body region and the lower part of the pressure-resistant holding region, is in contact with the gate insulating film at the side surface of each first trench below the body region, is separated from the n-type region by the body region, and is in contact with the first bottom region and the second bottom region.

[0007] In the semiconductor device described above, the second bottom region extends lower than the first bottom region. Therefore, when the semiconductor device is turned off, equipotential lines are distributed lower in the lower part of the second trench compared to the lower part of the first trench. As a result, the spacing between equipotential lines becomes narrower in the lower part of the second bottom region, and the electric field becomes concentrated. In other words, in this semiconductor device, avalanche breakdown is likely to occur at the lower end of the second bottom region. When avalanche breakdown occurs at the lower end of the second bottom region, the generated holes flow through the breakdown-resistant holding region connected to the second bottom region toward the upper electrode. Here, the breakdown-resistant holding region located between the second trenches is in contact with the upper electrode and extends from the gate insulating film in one second trench to the gate insulating film in the other second trench. In other words, even when the semiconductor device is turned on, the semiconductor region sandwiched between the two second trenches does not function as a current path. Therefore, even if some of the holes flowing to the upper electrode through the breakdown-resistant holding region are injected into the gate insulating film facing the semiconductor region, the characteristics of the semiconductor device are unlikely to change. As described above, the semiconductor device can suppress variations in its characteristics by selectively inducing avalanche breakdown in the second bottom region. [Brief explanation of the drawing]

[0008] [Figure 1] Cross-sectional view of the semiconductor device of the example. [Figure 2] Cross-sectional view of a semiconductor substrate before processing. [Figure 3] A diagram illustrating the recess formation process of the semiconductor device in the embodiment. [Figure 4] A diagram illustrating the process of forming the pressure-resistant holding region of the semiconductor device in the embodiment. [Figure 5] A diagram illustrating the trench formation process of the semiconductor device in the example. [Figure 6] A diagram illustrating the process of forming the bottom region of the semiconductor device in the embodiment. [Modes for carrying out the invention]

[0009] In one example semiconductor device disclosed herein, each of the second trenches may extend below the first trench.

[0010] In this configuration, a second bottom region extending below the first bottom region can be formed more easily.

[0011] In one example semiconductor device disclosed herein, the two second trenches may have a first side facing each other through the withstand voltage holding region and a second side located opposite the first side. The depth of the first side may be greater than the depth of the second side.

[0012] In this configuration, when forming the second bottom region, it becomes easier to make the depth of the first side surface greater than that of the second side surface. Within the second bottom region, avalanche yielding can be caused in the area closer to the pressure-bearing region.

[0013] In one example semiconductor device disclosed herein, the bottom surface of each second bottom region may be inclined such that it is displaced downward as it approaches the pressure-bearing holding region.

[0014] In this configuration, when forming the second bottom region, it becomes easy to gradually increase the depth of the second bottom region from the second side towards the first side (i.e., as it approaches the pressure-resistant region).

[0015] In one example semiconductor device disclosed herein, the angle between the bottom surface and the first side surface of each second trench may be obtuse.

[0016] In this configuration, the concentration of the electric field near the corner between the bottom surface of the second trench and the first side surface is suppressed, thereby preventing dielectric breakdown of the gate insulating film.

[0017] In a semiconductor device of an example disclosed in this specification, the n-type region may be in contact with the gate insulating film on each of the second side surfaces, the body region may be in contact with the gate insulating film on each of the second side surfaces below the n-type region, and the drift region may be in contact with the gate insulating film on each of the second side surfaces below the body region.

[0018] With such a configuration, a channel can be formed in the semiconductor region on the second side surface side of the second trench, and the semiconductor region can be used as a current path.

[0019] In a semiconductor device of an example disclosed in this specification, a first trench set composed of the plurality of first trenches and a second trench set composed of the two second trenches may be alternately arranged along a specific direction, and the ratio of the number of the first trenches included in the first trench set to the number of the second trenches included in the second trench set may be within the range of 4:1 to 2:1.

[0020] With such a configuration, the avalanche current can be suitably dispersed by arranging the second trench set at the above ratio.

[0021] (Example) FIG. 1 shows a semiconductor device 10 of an example. The semiconductor device 10 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), and has a semiconductor substrate 12, electrodes, insulating films, etc. The semiconductor substrate 12 is made of SiC (silicon carbide). However, the material constituting the semiconductor substrate 12 is not particularly limited, and for example, other semiconductor materials such as Si (silicon), GaN (gallium nitride), diamond, etc. may be used. Hereinafter, a direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x direction, a direction parallel to the upper surface 12a of the semiconductor substrate 12 and orthogonal to the x direction is referred to as the y direction, and the thickness direction of the semiconductor substrate 12 is referred to as the z direction.

[0022] As shown in Figure 1, a plurality of trenches 22 are provided on the upper surface 12a of the semiconductor substrate 12. Each trench 22 extends linearly in the y direction. Each trench 22 is arranged with spacing in the x direction. The inner surface of each trench 22 is covered with a gate insulating film 24. A gate electrode 26 is placed inside each trench 22. Each gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating film 24. The upper surface of each gate electrode 26 is covered with an interlayer insulating film 28. An upper electrode 70 is placed on the upper surface 12a of the semiconductor substrate 12. The upper electrode 70 is in contact with the upper surface 12a of the semiconductor substrate 12 and the upper surface of the interlayer insulating film 28. The upper electrode 70 is insulated from the gate electrode 26 by the interlayer insulating film 28. A lower electrode 72 is placed on the lower surface 12b of the semiconductor substrate 12. The lower electrode 72 is in contact with almost the entire area of ​​the lower surface 12b of the semiconductor substrate 12.

[0023] The multiple trenches 22 have multiple first trenches 22a and multiple second trenches 22b. As shown in Figure 1, two second trenches 22b are arranged between the multiple first trenches 22a. The two second trenches 22b are adjacent to each other between the multiple first trenches 22a. Although not shown, multiple first trenches 22a and multiple second trenches 22b are provided on the left and right sides of Figure 1. Specifically, in this embodiment, eight first trenches 22a and two second trenches 22b are arranged alternately along the x-direction. That is, the first trenches 22a and second trenches 22b are arranged alternately along the x-direction in a ratio of 4:1. In the following, of the sides of the second trench 22b, the side where two second trenches 22b face each other will be referred to as the first side 23a, and the side located on the opposite side of the first side 23a (the side facing the first trench 22a) will be referred to as the second side 23b.

[0024] In the second trench 22b, the depth of the first side surface 23a is greater than the depth of the second side surface 23b. The lower end of the first side surface 23a and the lower end of the second side surface 23b are connected by a bottom surface 25. The bottom surface 25 is inclined to displace downward from the second side surface 23b toward the first side surface 23a.

[0025] The second trench 22b extends lower than the first trench 22a. More specifically, the lower end of the first side surface 23a of the second trench 22b is located lower than the lower end of the first trench 22a. The lower end of the second side surface 23b of the second trench 22b is located at approximately the same depth as the lower end of the first trench 22a. The bottom surface of the first trench 22a is approximately parallel to the top surface 12a of the semiconductor substrate 12.

[0026] As shown in Figure 1, the semiconductor substrate 12 is provided with a plurality of source regions 30, a body region 32, a plurality of first bottom regions 36a, a breakdown voltage holding region 40, a plurality of second bottom regions 36b, a drift region 34, and a drain region 35.

[0027] Each source region 30 is n-type. Each source region 30 is located in the region between the two first trenches 22a and in the region between the first trench 22a and the second trench 22b. Each source region 30 is positioned to be exposed on the upper surface 12a of the semiconductor substrate 12. Each source region 30 is in ohmic contact with the upper electrode 70. Each source region 30 is in contact with the gate insulating film 24 on the side surface of the first trench 22a and on the second side surface 23b of the second trench 22b.

[0028] The body region 32 is p-type. The body region 32 is located in each region between the two first trenches 22a and in each region between the first trench 22a and the second trench 22b. The body region 32 is located below each source region 30. The body region 32 is in contact with each source region 30 from below. The body region 32 is in contact with the gate insulating film 24 below the source region 30 on the side surface of the first trench 22a and the second side surface 23b of the second trench 22b. The body region 32 is in ohmic contact with the upper electrode 70 at a position not shown.

[0029] Each first bottom region 36a is p-shaped. Each first bottom region 36a is positioned to be exposed to the bottom surface of the corresponding first trench 22a. Each first bottom region 36a is in contact with the gate insulating film 24 at the bottom surface of the corresponding first trench 22a. Each first bottom region 36a extends elongated in the y-direction along the bottom surface of the first trench 22a. Each first bottom region 36a is connected to the upper electrode 70 via a body region 32 at a position not shown.

[0030] The breakdown dielectric strength holding region 40 is p-type. The breakdown dielectric strength holding region 40 is located between two adjacent second trenches 22b. The breakdown dielectric strength holding region 40 is exposed on the upper surface 12a of the semiconductor substrate 12. The breakdown dielectric strength holding region 40 is in ohmic contact with the upper electrode 70. The breakdown dielectric strength holding region 40 extends from the gate insulating film 24 in one second trench 22b to the gate insulating film 24 in the other second trench 22b. The breakdown dielectric strength holding region 40 extends to the underside of the second trenches 22b. The breakdown dielectric strength holding region 40 is in contact with the gate insulating film 24 over the entire area of ​​the first side surface 23a of each second trench 22b. That is, the source region 30 and the body region 32 are not located in the region sandwiched between the two second trenches 22b.

[0031] Each second bottom region 36b is p-shaped. Each second bottom region 36b is positioned to be exposed to the bottom surface of the corresponding second trench 22b. Each second bottom region 36b is in contact with the gate insulating film 24 at the bottom surface of the corresponding second trench 22b. Each second bottom region 36b extends long in the y-direction along the bottom surface of the second trench 22b. Each second bottom region 36b is connected to the withstand voltage holding region 40 on the side of the second trench 22b facing the first side surface 23a. Each second bottom region 36b is connected to the upper electrode 70 via the withstand voltage holding region 40.

[0032] In the second bottom region 36b, the depth on the first side surface 23a side is greater than the depth on the second side surface 23b side. The shape of the lower surface of the second bottom region 36b is inclined to match the shape of the bottom surface 25 of the second trench 22b. That is, the lower surface of the second bottom region 36b is inclined to displace downward from the second side surface 23b side towards the first side surface 23a side.

[0033] The second bottom region 36b extends below the first bottom region 36a. More specifically, the lower end of the second bottom region 36b on the first side surface 23a is located below the lower end of the first bottom region 36a. The lower end of the second bottom region 36b on the second side surface 23b is located at approximately the same depth as the lower end of the first bottom region 36a.

[0034] The drift region 34 is n-type. The drift region 34 is distributed across the lower part of the body region 32 and the lower part of the withstand voltage region 40. The drift region 34 is in contact with the body region 32 and the withstand voltage region 40 from below. Below the body region 32, the drift region 34 is in contact with the gate insulating film 24 on the side surface of the first trench 22a and the second side surface 23b of the second trench 22b. The drift region 34 is not in contact with the first side surface 23a of the second trench 22b. The drift region 34 is separated from the source region 30 by the body region 32. The drift region 34 is in contact with the first bottom region 36a and the second bottom region 36b.

[0035] The drain region 35 is n-type. The drain region 35 is located below the drift region 34. The n-type impurity concentration in the drain region 35 is higher than that in the drift region 34. The drain region 35 is exposed on the lower surface 12b of the semiconductor substrate 12. The drain region 35 is in ohmic contact with the lower electrode 72.

[0036] When the semiconductor device 10 is in use, a higher potential is applied to the lower electrode 72 than to the upper electrode 70. When a voltage above the gate threshold is applied to the gate electrode 26, a channel is formed in the body region 32 in contact with the gate insulating film 24, and the semiconductor device 10 turns on. Note that since there is no source region 30 in the region between the second trenches 22b (i.e., the withstand voltage holding region 40), the region between the second trenches 22b does not function as a current path. When the voltage applied to the gate electrode 26 is reduced to below the gate threshold, the channel disappears, and the semiconductor device 10 turns off.

[0037] When the semiconductor device 10 is turned off, the potential of the lower electrode 72 is much higher than the potential of the upper electrode 70. In this state, the drift region 34 has a potential close to that of the lower electrode 72. Also, as described above, the first bottom region 36a and the second bottom region 36b have a potential approximately equal to that of the upper electrode 70. Therefore, a high reverse voltage is applied to the pn junction at the interface between the drift region 34 and each bottom region 36a, 36b. Consequently, a depletion layer spreads widely from each bottom region 36a, 36b into the drift region 34. This suppresses electric field concentration near the lower end of the trench 22, ensuring the breakdown voltage of the semiconductor device 10.

[0038] When the semiconductor device 10 is turned off, the depletion layer extending from the body region 32, bottom regions 36a and 36b, and the withstand voltage holding region 40 depletes almost the entire area of ​​the drift region 34. When a high voltage is applied to the lower electrode 72 while the semiconductor device 10 is turned off, avalanche breakdown occurs within the semiconductor substrate 12, and an avalanche current flows.

[0039] In the semiconductor device 10 of this embodiment, the second bottom region 36b extends lower than the first bottom region 36a. Therefore, when the semiconductor device 10 is off, equipotential lines are distributed lower in the region where the second bottom region 36b is located compared to the region where the first bottom region 36a is located. As a result, the spacing between equipotential lines becomes narrower below the second bottom region 36b, and a high electric field is concentrated there. In other words, in the semiconductor device 10 of this embodiment, avalanche breakdown preferentially occurs at the lower end of the second bottom region 36b (more specifically, the lower end on the first side surface 23a side of the second trench 22b). When avalanche breakdown occurs at the lower end of the second bottom region 36b, the resulting holes flow through the withstand voltage holding region 40 connected to the second bottom region 36b towards the upper electrode 70. As described above, the withstand voltage holding region 40 does not function as a current path when the semiconductor device 10 is turned on. Therefore, even if some of the holes flowing from the withstand voltage holding region 40 to the upper electrode 70 are injected into the gate insulating film 24 facing the semiconductor region (i.e., on the first side surface 23a side), the characteristics of the semiconductor device 10 are unlikely to change.

[0040] As described above, in the semiconductor device 10 of this embodiment, avalanche breakdown can be selectively induced in the second bottom region 36b. Furthermore, by connecting the withstand voltage holding region 40 to the second bottom region 36b, holes generated by avalanche breakdown can be allowed to flow into the withstand voltage holding region 40. This suppresses the flow of holes generated by avalanche breakdown into the body region 32. Therefore, the injection of holes into the gate insulating film 24 near the body region 32 can be suppressed, and fluctuations in the characteristics of the semiconductor device can be suppressed.

[0041] In this embodiment, the lower surface of the second bottom region 36b is inclined to displace downward as it approaches the pressure-resistant holding region 40. Therefore, the lower end of the second bottom region 36b is located near the pressure-resistant holding region 40. Consequently, holes generated by avalanche yielding can easily flow into the pressure-resistant holding region 40. This makes it difficult for holes generated by avalanche yielding to flow towards the body region 32, and more effectively suppresses the injection of holes into the gate insulating film 24 near the body region 32.

[0042] Furthermore, in this embodiment, the source region 30, body region 32, and drift region 34 are arranged so as to be in contact with the second side surface 23b of each second trench 22b. Therefore, when the semiconductor device 10 is turned on, a current path is formed along the second side surface 23b. As described above, since avalanche breakdown occurs near the breakdown holding region 40 of the second bottom region 36b, holes generated by avalanche breakdown are unlikely to flow into the vicinity of the second side surface 23b. For this reason, holes are unlikely to be injected into the gate insulating film 24 covering the second side surface 23b. Therefore, even in the current path along the second side surface 23b, characteristic fluctuations are unlikely to occur. In addition, by providing a current path along the second side surface 23b, the on-resistance of the semiconductor device 10 can be reduced.

[0043] Furthermore, in this embodiment, the first trench 22a and the second trench 22b are arranged alternately along the x-direction in a ratio of 4:1. By arranging the second trench 22b in this ratio, the avalanche current can be suitably distributed.

[0044] Next, the semiconductor device 10 will be described with reference to Figures 2 to 6. First, a semiconductor substrate 12 made of SiC, as shown in Figure 2, is prepared. As shown in Figure 2, the semiconductor substrate 12 has an n-type drain region 35, an n-type drift region 34 provided on the upper surface of the drain region 35, a p-type body region 32 provided on the upper surface of the drift region 34, and an n-type source region 30 provided on the upper surface of the body region 32. The semiconductor substrate 12 can be manufactured as appropriate using known methods such as ion implantation or epitaxial growth.

[0045] Next, as shown in Figure 3, a mask 50 having an opening 52 is formed on the upper surface 12a of the semiconductor substrate 12. Then, a recess 54 is formed on the upper surface 12a of the semiconductor substrate 12 through the opening 52 of the mask 50. The dashed lines 100a and 100b in Figure 3 indicate the areas where the first trench 22a and the second trench 22b are to be formed, respectively. As shown in Figure 3, in this step, the recess 54 is formed such that the stepped portion 56 is located in the area connecting the centers of the two adjacent second trenches 22b to be formed in the width direction (x direction).

[0046] Next, as shown in Figure 4, a p-type withstand voltage holding region 40 is formed. Here, p-type impurities 90 are injected from the upper surface 12a of the semiconductor substrate 12 through the opening 52 of the mask 50 used to form the recess 54. The p-type impurities 90 are injected from the upper surface 12a of the semiconductor substrate 12, across the source region 30 and the body region 32, to reach the drift region 34. This forms a withstand voltage holding region 40 that penetrates from the upper surface 12a of the semiconductor substrate 12 through the source region 30 and the body region 32 to reach the drift region 34.

[0047] Next, as shown in Figure 5, a mask 60 having an opening 62 is formed on the upper surface 12a of the semiconductor substrate 12, and then multiple trenches 22 are formed on the upper surface 12a of the semiconductor substrate 12 through the opening 62 of the mask 60 by etching. In this process, multiple first trenches 22a are formed on the upper surface 12a of the semiconductor substrate 12, and a second trench 22b is formed that spans from the upper surface 12a of the semiconductor substrate 12 to the bottom surface of the recess 54, as shown by the dashed line. That is, the second trench 22b is formed such that the stepped portion 56 is located at the center in the width direction. As a result, the first side surface 23a reaches a position deeper than the second side surface 23b by the depth of the recess 54. Also, during the process of forming the second trench 22b, the stepped portion 56 is leveled as etching progresses. As a result, the bottom surface 25 of the formed second trench 22b has a shape that is inclined so as to be displaced downward from the second side surface 23b toward the first side surface 23a. In this process, a trench 22 is formed from the upper surface 12a of the semiconductor substrate 12, penetrating the source region 30 and the body region 32 to reach the drift region 34. However, the bottom surface 25 of the second trench 22b is positioned above the lower end of the withstand voltage holding region 40 when the second trench 22b is formed.

[0048] Next, using the mask 60 used to form the trench 22, p-type impurities 92 are injected from the upper surface 12a side of the semiconductor substrate 12 to form p-type bottom regions 36a and 36b in the areas exposed to the bottom surfaces of each trench 22a and 22b. Since the bottom surface 25 of the second trench 22b is displaced downward from the second side surface 23b toward the first side surface 23a, the second bottom region 36b formed in the area exposed to the bottom surface 25 of the second trench 22b is formed so that the shape of its lower surface conforms to the shape of the bottom surface 25. In other words, the second bottom region 36b formed in this process is deepest on the first side surface 23a side.

[0049] Subsequently, the semiconductor device 10 is completed by forming the gate insulating film 24, gate electrode 26, interlayer insulating film 28, upper electrode 70, and lower electrode 72 using known methods.

[0050] In the manufacturing method described above, the second trench 22b is formed to extend below the first trench 22a. Therefore, the second bottom region 36b, which extends below the first bottom region 36a, can be formed without changing the injection conditions for p-type impurities 92.

[0051] Furthermore, in the above manufacturing method, the second trench 22b is formed such that the depth of the first side surface 23a of the second trench 22b is greater than the depth of the second side surface 23b. Therefore, when forming the second bottom region 36b, it becomes easier to make the depth of the second bottom region 36b greater on the first side surface 23a side than on the second side surface 23b side.

[0052] In the above-described embodiment, the second trench 22b extended below the first trench 22a. However, for example, the bottom surface 25 of the second trench 22b does not have to be inclined, and the depth of the first side surface 23a does not have to be greater than the depth of the second side surface 23b. For example, the second trench 22b may have the same shape as the first trench 22a. If the second bottom region 36b extends below the first bottom region 36a, avalanche yielding can be selectively caused in the lower part of the second bottom region 36b.

[0053] Furthermore, in the above-described embodiment, the angle between the first side surface 23a and the bottom surface 25 of the second trench 22b may be obtuse. For example, by configuring the second trench 22b so that its side surfaces 23a, 23b are more inclined with respect to the top surface 12a of the semiconductor substrate 12, the angle can be made obtuse. With this configuration, the concentration of an electric field near the corner between the bottom surface 25 and the first side surface 23a of the second trench 22b is suppressed, and dielectric breakdown of the gate insulating film 24 can be suppressed.

[0054] Furthermore, in the embodiments described above, a MOSFET (metal-oxide-semiconductor field-effect transistor) was used as an example of the semiconductor device 10. However, the technology disclosed herein may also be applied to an IGBT (insulated-gate bipolar transistor), for example. By changing the drain region 35 to a p-type region, an IGBT structure can be obtained.

[0055] The components disclosed herein are listed below. (Composition 1) Semiconductor substrate and Multiple trenches provided on the upper surface of the semiconductor substrate, A gate insulating film covering the inner surface of the trench, A gate electrode, disposed within the trench and insulated from the semiconductor substrate by the gate insulating film, The upper electrode in contact with the upper surface of the semiconductor substrate, Equipped with, The plurality of trenches comprises a plurality of first trenches and two second trenches that are located between the plurality of first trenches and are adjacent to each other. The aforementioned semiconductor substrate On the side surface of each of the first trenches, there is an n-type region that is in contact with the gate insulating film and in contact with the upper electrode, A p-type body region in contact with the gate insulating film on the side surface of each of the first trenches below the n-type region, A p-shaped first bottom region in contact with the gate insulating film at the bottom surface of each of the first trenches, A p-type breakdown-holding region is located between the two second trenches, is in contact with the upper electrode, and extends from the gate insulating film in one of the second trenches to the gate insulating film in the other second trench, A p-shaped second bottom region is in contact with the gate insulating film at the bottom surface of each of the second trenches, is connected to the pressure-resistant holding region, and extends below the first bottom region, The n-type drift region is distributed across the lower part of the body region and the lower part of the pressure-resistant holding region, is in contact with the gate insulating film on the side surface of each of the first trenches on the lower side of the body region, is separated from the n-type region by the body region, and is in contact with the first bottom region and the second bottom region. It has, Semiconductor equipment. (Configuration 2) The semiconductor device according to configuration 1, wherein each of the second trenches extends below the first trench. (Composition 3) The two second trenches have a first side facing each other across the pressure-resistant holding region, and a second side located on the opposite side of the first side. The semiconductor device according to configuration 1 or 2, wherein the depth of the first side surface is greater than the depth of the second side surface. (Composition 4) The semiconductor device according to configuration 3, wherein the bottom surface of each of the second bottom regions is inclined to displace downward as it approaches the pressure-resistant holding region. (Composition 5) The semiconductor device according to configuration 3 or 4, wherein in each of the second trenches, the angle between the bottom surface and the first side surface of the second trench is an obtuse angle. (Composition 6) The n-type region is in contact with the gate insulating film on each of the second sides, The body region is in contact with the gate insulating film at each of the second sides below the n-type region. The semiconductor device according to any one of configurations 3 to 5, wherein the drift region is in contact with the gate insulating film on each of the second sides below the body region. (Composition 7) The first trench set, composed of the plurality of first trenches, and the second trench set, composed of the two second trenches, are arranged alternately along a specific direction. A semiconductor device according to any one of configurations 1 to 6, wherein the ratio of the number of first trenches in the first trench set to the number of second trenches in the second trench set is within the range of 4:1 to 2:1.

[0056] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of symbols]

[0057] 10: Semiconductor Devices 12: Semiconductor substrates 12a:Top surface 12b: Bottom surface 22a: Trench 1 22b: Trench 2 23a: 1st side 23b:Second side 24: Gate Insulator 25: Bottom 26: Grid control point 28: Interlayer insulating film 30: Source area 32: Body area 34: Drift Region 35: Drain area 36a: 1st bottom area 36b: 2nd bottom area 40: Pressure-resistant holding area 70: Upper electrode 72: Lower electrode

Claims

1. A semiconductor substrate (12) and A plurality of trenches (22) are provided on the upper surface (12a) of the semiconductor substrate, A gate insulating film (24) covering the inner surface of the trench, A gate electrode (26) is located within the trench and is insulated from the semiconductor substrate by the gate insulating film, The upper electrode (70) in contact with the upper surface of the semiconductor substrate, Equipped with, The plurality of trenches comprises a plurality of first trenches (22a) and two second trenches (22b) that are located between the plurality of first trenches and are adjacent to each other. The aforementioned semiconductor substrate On the side surface of each of the first trenches, there is an n-type region (30) that is in contact with the gate insulating film and in contact with the upper electrode, A p-type body region (32) is in contact with the gate insulating film on the side surface of each of the first trenches below the n-type region, A p-shaped first bottom region (36a) in contact with the gate insulating film at the bottom surface of each of the first trenches, A p-type breakdown-holding region (40) is located between the two second trenches, is in contact with the upper electrode, and extends from the gate insulating film in one of the second trenches to the gate insulating film in the other second trench, The bottom surface (25) of each of the second trenches is in contact with the gate insulating film, connected to the withstand voltage holding region, and has a p-shaped second bottom region (36b) that extends below the first bottom region, An n-type drift region (34) is distributed across the lower part of the body region and the lower part of the pressure-resistant holding region, is in contact with the gate insulating film on the side surface of each of the first trenches on the lower side of the body region, is separated from the n-type region by the body region, and is in contact with the first bottom region and the second bottom region. It has, The two second trenches have a first side surface (23a) facing each other through the pressure-resistant holding region, and a second side surface (23b) located on the opposite side of the first side surface. The depth of the first side is greater than the depth of the second side. The bottom surface of each of the second bottom regions is inclined such that it is displaced downward as it approaches the pressure-resistant holding region. Semiconductor device (10).

2. A semiconductor substrate (12) and A plurality of trenches (22) are provided on the upper surface (12a) of the semiconductor substrate, A gate insulating film (24) covering the inner surface of the trench, A gate electrode (26) is located within the trench and is insulated from the semiconductor substrate by the gate insulating film, The upper electrode (70) in contact with the upper surface of the semiconductor substrate, Equipped with, The plurality of trenches comprises a plurality of first trenches (22a) and two second trenches (22b) that are located between the plurality of first trenches and are adjacent to each other. The aforementioned semiconductor substrate On the side surface of each of the first trenches, there is an n-type region (30) that is in contact with the gate insulating film and in contact with the upper electrode, A p-type body region (32) is in contact with the gate insulating film on the side surface of each of the first trenches below the n-type region, A p-shaped first bottom region (36a) in contact with the gate insulating film at the bottom surface of each of the first trenches, A p-type breakdown-holding region (40) is located between the two second trenches, is in contact with the upper electrode, and extends from the gate insulating film in one of the second trenches to the gate insulating film in the other second trench, The bottom surface (25) of each of the second trenches is in contact with the gate insulating film, connected to the withstand voltage holding region, and has a p-shaped second bottom region (36b) that extends below the first bottom region, An n-type drift region (34) is distributed across the lower part of the body region and the lower part of the pressure-resistant holding region, is in contact with the gate insulating film on the side surface of each of the first trenches on the lower side of the body region, is separated from the n-type region by the body region, and is in contact with the first bottom region and the second bottom region. It has, The two second trenches have a first side surface (23a) facing each other through the pressure-resistant holding region, and a second side surface (23b) located on the opposite side of the first side surface. The depth of the first side is greater than the depth of the second side. In each of the second trenches, the angle between the bottom surface and the first side surface of the second trench is obtuse. Semiconductor equipment.

3. The semiconductor device according to claim 1 or 2, wherein each of the second trenches extends below the first trench.

4. The n-type region is in contact with the gate insulating film on each of the second surfaces, The body region is in contact with the gate insulating film at each of the second sides below the n-type region. The semiconductor device according to claim 1 or 2, wherein the drift region is in contact with the gate insulating film on each of the second sides below the body region.

5. The first trench set, composed of the plurality of first trenches, and the second trench set, composed of the two second trenches, are arranged alternately along a specific direction. The semiconductor device according to claim 1 or 2, wherein the ratio of the number of first trenches in the first trench set to the number of second trenches in the second trench set is within the range of 4:1 to 2:1.

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