semiconductor device, memory device

Abstract

Provided is a semiconductor device that allows for microfabrication or high integration. This semiconductor device includes: a first electrical conductor; a metal oxide disposed on the first electrical conductor; a second electrical conductor disposed on the metal oxide; a first insulator; a second insulator disposed on the first insulator; and a third electrical conductor disposed on the second insulator. The first electrical conductor has a region which overlaps with the metal oxide. The metal oxide has a first opening. The second electrical conductor has a second opening. The first opening and the second opening overlap one another. The first insulator is disposed inside each of the first opening and the second opening. The second insulator is disposed in a recessed portion of the first insulator. The third electrical conductor is disposed in a recessed portion of the second insulator.

Description

[Technical Field]

[0001] One aspect of the present invention relates to a transistor, a semiconductor device, a memory device, and an electronic device. Alternatively, one aspect of the present invention relates to a method for manufacturing a transistor and a method for manufacturing a semiconductor device. Alternatively, one aspect of the present invention relates to a semiconductor wafer and a module.

[0002] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Semiconductor elements such as transistors, as well as semiconductor circuits, computing devices, and memory devices, are all forms of semiconductor devices. Display devices (such as liquid crystal displays and light-emitting displays), projection devices, lighting devices, electro-optical devices, energy storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices may also be considered to have semiconductor devices.

[0003] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the invention disclosed herein relates to a product, a method, or a method of manufacture. Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] DRAM (Dynamic Random Access Memory), which consists of one capacitor and one transistor (also called a cell transistor), is a widely used and representative type of memory device.

[0005] With the increasing integration of memory devices, there is a growing demand for reducing the memory's footprint. However, miniaturizing memory devices using Si transistors is becoming increasingly difficult from both a technical and cost perspective.

[0006] In recent years, oxide semiconductors have attracted attention as semiconductor materials that can form transistors during the BEOL (Back End of Line) process for forming wiring in semiconductor devices. The technique of directly forming OS transistors (transistors with metal oxide in the channel formation region) on top of conventional Si transistors (transistors with silicon in the channel formation region) (also known as BEOL-Tr technology) makes it possible to construct 3D functional circuits while maintaining design rules. Therefore, it is expected to be a technology that can realize high-performance memory devices with low power consumption and low cost.

[0007] Furthermore, if the OS transistor can be oriented vertically, the design rule can be changed to 6F. 2 (F is the minimum machining dimension) to 4F 2 This makes it possible to minimize the size. For example, Patent Document 1 discloses a vertical transistor in which the side surface of an oxide semiconductor is covered with a word line via a gate insulating layer. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Publication No. 2021-108331 [Overview of the project] [Problems that the invention aims to solve]

[0009] One aspect of the present invention aims to provide a transistor capable of miniaturization or high integration. Or, one aspect of the present invention aims to provide a transistor having good electrical characteristics. Or, one aspect of the present invention aims to provide a transistor with little variation in electrical characteristics. Or, one aspect of the present invention aims to provide a transistor having a large on-current. Or, one aspect of the present invention aims to provide a transistor with good reliability. Or, one aspect of the present invention aims to provide a novel transistor. Or, one aspect of the present invention aims to provide a semiconductor device having such a transistor. Or, one aspect of the present invention aims to provide a low-power consumption semiconductor device.

[0010] Note that the description of these problems does not preclude the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Other problems will become apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other problems from the descriptions in the specification, drawings, claims, etc.

Means for Solving the Problems

[0011] One aspect of the present invention is a transistor having a first conductor, a metal oxide on the first conductor, a second conductor on the metal oxide, a first insulator, a second insulator on the first insulator, and a third conductor on the second insulator. The first conductor has a region overlapping with the metal oxide. The metal oxide has a first opening. The second conductor has a second opening. The first opening and the second opening overlap. The first insulator is disposed inside each of the first opening and the second opening. The second insulator is disposed in a recess of the first insulator. The third conductor is disposed in a recess of the second insulator.

[0012] In the above transistor, it is preferable that the metal oxide and the second conductor have a hollow cylindrical shape.

[0013] Furthermore, in a top view of the transistor, it is preferable that the center of the first conductor does not coincide with the center of the hollow cylindrical shape of the metal oxide.

[0014] Furthermore, in a cross-sectional view of the transistor, it is preferable that the side surface on the first opening side and the side surface on the second opening side have a tapered shape.

[0015] Furthermore, in the above-mentioned transistor, it is preferable that the uppermost part of the second insulator is at the same or approximately the same height as the uppermost part of the first insulator.

[0016] Furthermore, in the above-mentioned transistor, it is preferable that the first insulator has a region in which its film thickness is thinner than that of the second insulator.

[0017] Another aspect of the present invention is a memory device having the above-mentioned transistor and a capacitive element. The transistor is provided above the capacitive element.

[0018] Another aspect of the present invention is a semiconductor device comprising: a first insulator; a first conductor arranged to be embedded in the first insulator; a metal oxide on the first conductor; a second conductor on the metal oxide; a third conductor on the second conductor; a second insulator; a third insulator on the second insulator; a fourth conductor on the third insulator; and a fifth conductor on the fourth conductor. The first conductor has a region that overlaps with the metal oxide. The metal oxide has a first opening. The second conductor has a second opening. The first opening and the second opening overlap. The second insulator is positioned inside the first opening and the second opening, respectively. The third insulator is positioned in a recess of the second insulator. The fourth conductor is positioned in a recess of the third insulator. The third conductor is positioned in contact with at least a portion of the upper surface of the second conductor. The fifth conductor is positioned in contact with the upper surface of the fourth conductor. In a top view of the semiconductor device, the third conductor and the fifth conductor do not overlap.

[0019] In the semiconductor device described above, it is preferable that a fourth insulator is provided between the second insulator, the third insulator and the fifth conductor, the fourth insulator has a region in contact with the lower surface of the fifth conductor, and the upper surface of the third conductor is located between the lower and upper surfaces of the fourth insulator.

[0020] In the semiconductor device described above, it is preferable that the metal oxide and the second conductor have a hollow cylindrical shape.

[0021] Furthermore, in a top view of the semiconductor device, it is preferable that the center of the first conductor does not coincide with the center of the hollow cylindrical shape of the metal oxide.

[0022] Furthermore, in a cross-sectional view of the semiconductor device, it is preferable that the side surface on the first opening side and the side surface on the second opening side have a tapered shape.

[0023] Furthermore, in the semiconductor device described above, it is preferable that the uppermost part of the third insulator is at the same height as or approximately the same height as the uppermost part of the second insulator.

[0024] Furthermore, in the semiconductor device described above, it is preferable that the second insulator has a region in which its film thickness is thinner than that of the third insulator.

[0025] Furthermore, in the semiconductor device described above, it is preferable that the direction in which the fifth conductor extends is perpendicular to the direction in which the third conductor extends.

[0026] Another aspect of the present invention is a memory device having the above-described semiconductor device and a capacitive element. The semiconductor device is provided above the capacitive element. [Effects of the Invention]

[0027] One aspect of the present invention can provide a transistor that can be miniaturized or highly integrated; or a transistor with good electrical characteristics; or a transistor with little variation in electrical characteristics; or a transistor with a large on-current; or a transistor with good reliability; or a novel transistor; or a semiconductor device having such a transistor; or a semiconductor device with low power consumption.

[0028] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one embodiment of the present invention does not need to possess all of these effects. Other effects will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other effects from the description in the specification, drawings, and claims. [Brief explanation of the drawing]

[0029] Figure 1A is a schematic top view showing an example of the configuration of a semiconductor device. Figures 1B and 1C are cross-sectional perspective views showing an example of the configuration of a transistor. Figures 2A and 2B are cross-sectional perspective views showing examples of transistor configurations. Figures 3A to 3E are schematic top views showing examples of semiconductor device configurations. Figures 4A to 4C are cross-sectional perspective views showing examples of transistor configurations. Figures 5A and 5D are top views showing examples of semiconductor device configurations. Figures 5B, 5C, and 5E are cross-sectional views showing examples of semiconductor device configurations. Figures 6A to 6C are cross-sectional views showing examples of semiconductor device configurations. Figures 7A and 7B are cross-sectional views showing examples of semiconductor device configurations. Figures 8A and 8C are top views showing examples of semiconductor device fabrication methods. Figures 8B and 8D are cross-sectional views showing examples of semiconductor device fabrication methods. Figures 9A and 9C are top views showing examples of semiconductor device fabrication methods. Figures 9B and 9D are cross-sectional views showing examples of semiconductor device fabrication methods. Figures 10A and 10C are top views showing examples of semiconductor device fabrication methods. Figures 10B and 10D are cross-sectional views showing examples of semiconductor device fabrication methods. Figures 11A and 11C are top views showing examples of semiconductor device fabrication methods. Figures 11B and 11D are cross-sectional views showing examples of semiconductor device fabrication methods. Figure 12A is a top view showing an example of a semiconductor device fabrication method. Figures 12B1 and 12B2 are cross-sectional views showing an example of a semiconductor device fabrication method. Figures 13A and 13C are top views showing examples of semiconductor device fabrication methods. Figures 13B and 13D are cross-sectional views showing examples of semiconductor device fabrication methods. Figures 14A and 14C are top views showing examples of semiconductor device fabrication methods. Figures 14B and 14D are cross-sectional views showing examples of semiconductor device fabrication methods. Figures 15A and 15C are top views showing examples of semiconductor device fabrication methods. Figures 15B and 15D are cross-sectional views showing examples of semiconductor device fabrication methods. Figure 16A is a top view showing an example of a semiconductor device fabrication method. Figure 16B is a cross-sectional view showing an example of a semiconductor device fabrication method. Figure 17A is a cross-sectional view showing an example of the configuration of a memory device. Figures 17B to 17D are cross-sectional views showing an example of the configuration of a capacitive element. Figures 18A to 18E are cross-sectional views showing examples of capacitive element configurations. Figure 19A is a block diagram showing an example of a storage device configuration. Figure 19B is a perspective view showing an example of a storage device configuration. Figure 20A is a circuit diagram showing an example of a memory cell configuration. Figures 20B and 20C are perspective views showing an example of a storage device configuration. Figure 21 is a cross-sectional view showing an example of a storage device configuration. Figure 22A is a circuit diagram showing an example of a semiconductor device configuration. Figure 22B is a perspective view showing an example of a semiconductor device configuration. Figures 23A to 23E illustrate an example of a storage device. Figures 24A to 24G are diagrams illustrating an example of an electronic device. Figure 25 is a cross-sectional view showing an example of a storage device configuration. [Modes for carrying out the invention]

[0030] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope. Therefore, the present invention is not to be construed as being limited to the following embodiments.

[0031] Furthermore, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. Also, the drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, in the actual manufacturing process, layers, resist masks, etc., may be unintentionally reduced due to processes such as etching, but this may not be reflected in the drawings for ease of understanding. In addition, in the drawings, the same reference numerals may be used in common across different drawings for the same part or parts with similar functions, and repeated explanations may be omitted. Also, when referring to similar functions, the hatching pattern may be the same, and no specific reference numeral may be assigned.

[0032] Furthermore, in particular, in top views (also called "plan views"), perspective views, etc., descriptions of some components may be omitted to facilitate understanding of the invention. In addition, descriptions of some hidden lines may be omitted.

[0033] Furthermore, the ordinal numbers used in this specification, such as "first," "second," etc., are for convenience only and do not indicate the order of processes or stacking. Therefore, for example, "first" can be replaced with "second" or "third," etc., as appropriate in the explanation. Also, the ordinal numbers described in this specification may not be the same as the ordinal numbers used to specify an aspect of the present invention.

[0034] Furthermore, in this specification, terms indicating placement, such as "above" and "below," are used for convenience to explain the positional relationships between components with reference to the drawings. The positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms used are not limited to those described in the specification and can be appropriately rephrased depending on the situation.

[0035] For example, if it is explicitly stated in this specification that X and Y are connected, then the disclosure in this specification includes cases where X and Y are electrically connected, where X and Y are functionally connected, and where X and Y are directly connected. Therefore, it is not limited to predetermined connection relationships, such as those shown in the figures or text, but also includes connection relationships other than those shown in the figures or text. Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0036] Furthermore, in this specification, a transistor is defined as an element having at least three terminals, including a gate, a drain, and a source. It also has a region where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) (hereinafter also referred to as the channel-forming region), and current can flow between the source and the drain through the channel-forming region. In this specification, the channel-forming region refers to the region through which current primarily flows.

[0037] Furthermore, the functions of the source or drain may be reversed when transistors of different polarities are used, or when the direction of current changes during circuit operation. For this reason, the terms source and drain may be used interchangeably in this specification.

[0038] Impurities in semiconductors refer to elements other than the main components that make up the semiconductor. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities. The presence of impurities can cause problems such as an increase in the defect level density of the semiconductor or a decrease in crystallinity. In the case of oxide semiconductors, impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of oxide semiconductors, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. Furthermore, for example, the inclusion of impurities can cause oxygen vacancies (V) in oxide semiconductors. O (Also known as an oxygen vacancy) may form.

[0039] In this specification, silicon oxide nitride refers to a material whose composition contains more oxygen than nitrogen. Similarly, silicon oxide nitride refers to a material whose composition contains more nitrogen than oxygen. Similarly, aluminum oxide nitride refers to a material whose composition contains more oxygen than nitrogen. Similarly, aluminum oxide nitride refers to a material whose composition contains more nitrogen than oxygen. Similarly, hafnium oxide nitride refers to a material whose composition contains more oxygen than nitrogen. Similarly, hafnium oxide nitride refers to a material whose composition contains more nitrogen than oxygen.

[0040] Furthermore, in this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." Similarly, the term "conductor" may be replaced with "conductive film" or "conductive layer." Finally, the term "semiconductor" may be replaced with "semiconductor film" or "semiconductor layer."

[0041] Furthermore, in this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Also, "approximately parallel" means a state in which two lines are positioned at an angle of -30 degrees or more and 30 degrees or less. Also, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Also, "approximately perpendicular" means a state in which two lines are positioned at an angle of 60 degrees or more and 120 degrees or less.

[0042] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), etc. For example, when a metal oxide is used in the semiconductor layer of a transistor, that metal oxide may be referred to as an oxide semiconductor. In other words, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or oxide semiconductor.

[0043] Furthermore, in this specification, normally off means that when no potential is applied to the gate, or when the gate is given a ground potential, the drain current flowing through the transistor per 1 μm of channel width is 1 × 10⁻¹⁶ at room temperature. -20 A or less, 1 × 10 at 85℃ -18 A or less, or 1 × 10 at 125°C -16 This means being less than or equal to A.

[0044] Furthermore, in this specification, "voltage" and "potential" may be used interchangeably as appropriate. "Voltage" is the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be replaced with "potential." Note that the ground potential does not necessarily mean 0V. Also, potential is relative, and as the reference potential changes, the potential applied to the wiring, the potential applied to the circuit, and the potential output from the circuit also change.

[0045] In this specification, when the same symbol is used for multiple elements, and especially when it is necessary to distinguish them, an identifying symbol such as "_1", "[n]", or "[m,n]" may be added to the symbol.

[0046] In this specification, "heights match or approximately match" refers to a configuration in which the heights from a reference surface (e.g., a flat surface such as the substrate surface) are equal in a cross-sectional view. For example, in the manufacturing process of semiconductor devices, planarization (typically CMP) may be performed to expose the surfaces of one or more layers. In this case, the surfaces to be planarized will have a configuration in which the heights from the reference surface are equal. However, the heights of the multiple layers may differ depending on the processing apparatus, processing method, or material of the surface to be processed during the planarization process. In this specification, this case will also be treated as "heights match or approximately match." For example, if there are two layers with different heights relative to the reference surface (here referred to as the first layer and the second layer), and the difference between the height of the top surface of the first layer and the height of the top surface of the second layer is 20 nm or less, this is also referred to as "heights match or approximately match."

[0047] In this specification, "edges coincide or roughly coincide" means that, when viewed from above, at least a portion of the contours of the stacked layers overlap. For example, this includes cases in the manufacturing process of semiconductor devices where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer; in this case, it is also referred to as "edges coincide or roughly coincide".

[0048] (Embodiment 1) In this embodiment, an example of the configuration of a semiconductor device according to one aspect of the present invention, and an example of the configuration of a transistor in a semiconductor device according to one aspect of the present invention will be described using Figures 1A to 4C.

[0049] <Example of semiconductor device configuration> The configuration of a semiconductor device having multiple transistors will be explained using Figure 1A. Figure 1A is a top view of a semiconductor device having multiple transistors 20. Note that some elements have been omitted from the top view of Figure 1A for clarity.

[0050] In drawings, arrows indicating the X, Y, and Z directions may be included. In this specification, the "X direction" refers to the direction along the X-axis, and the forward and reverse directions may not be distinguished. The same applies to the "Y direction" and "Z direction." Furthermore, the X, Y, and Z directions are directions that intersect each other. More specifically, the X, Y, and Z directions are directions that are orthogonal to each other. In this specification, one of the X, Y, or Z directions may be referred to as the "first direction" or "first direction." Another may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0051] One embodiment of the present invention is a semiconductor device having a plurality of transistors 20. Figure 1A shows an example in which the semiconductor device has a plurality of transistors 20 arranged in an m x n matrix (where m and n are each independent integers of 2 or more).

[0052] Rows and columns extend in mutually orthogonal directions. In this embodiment, the X direction is defined as "rows" and the Y direction as "columns". Alternatively, the X direction may be defined as "columns" and the Y direction as "rows".

[0053] In Figure 1A, the transistor 20 in the 1st row and 1st column is shown as transistor 20[1,1], the transistor 20 in the mth row and 1st column is shown as transistor 20[m,1], the transistor 20 in the 1st row and nth column is shown as transistor 20[1,n], and the transistor 20 in the mth row and nth column is shown as transistor 20[m,n].

[0054] Furthermore, in this embodiment, an arbitrary row may be referred to as row i, and an arbitrary column may be referred to as column j. Therefore, i is an integer between 1 and m, and j is an integer between 1 and n. Also, in this embodiment, the transistor 20 in the i-th row and j-th column is referred to as transistor 20[i,j]. Note that in this embodiment, when "i+α" (where α is a positive or negative integer) is used, "i+α" is not less than 1 and not greater than m. Similarly, when "j+α" is used, "j+α" is not less than 1 and not greater than n.

[0055] Furthermore, a semiconductor device according to one aspect of the present invention includes m conductors 62 extending in the row direction and n conductors 46 extending in the column direction. In this embodiment, the first conductor 62 (first row) is denoted as conductor 62[1], and the mth conductor 62 (mth row) is denoted as conductor 62[m]. Similarly, the first conductor 46 (first column) is denoted as conductor 46[1], and the nth conductor 46 (nth column) is denoted as conductor 46[n].

[0056] Transistor 20[i,j] is located below the region where the i-th row conductor 62 (conductor 62[i]) and the j-th column conductor 46 (conductor 46[j]) intersect. Transistor 20[i,j] is also electrically connected to conductor 62[i] and conductor 46[j]. Transistor 20[i,j] also has an oxide 30[i,j] in which a channel is formed.

[0057] Hereafter, the conductor 62 refers to one or more of the conductors 62[1] through conductor 62[m]. Similarly, the conductor 46 referred to hereafter refers to one or more of the conductors 46[1] through conductor 46[n]. Similarly, the transistor 20 referred to hereafter refers to one or more of the transistors 20[1,1] through transistor 20[m,n].

[0058] In Figure 1A, a conductor 46 is provided above the transistor 20, and a conductor 62 is provided above the conductor 46. Furthermore, since the conductor 62 extends in the row direction and the conductor 46 extends in the column direction, the conductors 62 and 46 are perpendicular to each other. The conductors 62 and 46 function as wiring.

[0059] <Transistor 20> Using Figure 1B, an example of the configuration of a transistor 20 in a semiconductor device according to one embodiment of the present invention will be explained. Figure 1B is a perspective view of the transistor 20, including a cross-section corresponding to the area shown by the dashed line L1-L2 in Figure 1A. In perspective views including a cross-section, such as Figure 1B, a hatching pattern is applied only to the cross-section for clarity. Also, a perspective view including a cross-section, as shown in Figure 1B, may be described as a cross-sectional perspective view.

[0060] Since transistors 20[1,1] through 20[m,n] have the same configuration, they are referred to as transistor 20 in Figure 1B and other diagrams, and no identifying code is added.

[0061] The transistor 20 shown in Figure 1B comprises a conductor 42a, an oxide 30 on the conductor 42a, a conductor 42b on the oxide 30, an insulator 50, and a conductor 60. The conductor 42a, oxide 30, and conductor 42b have a circular shape when viewed from above. Furthermore, the conductor 42a, oxide 30, and conductor 42b extend in the Z direction. Therefore, as shown in Figure 1B, the conductor 42a, oxide 30, and conductor 42b have a cylindrical shape (also called a cylindrical shape). The cylindrical shape of the conductor 42a, oxide 30, and conductor 42b extends in the Z direction. In addition, the conductor 42a has a recess. Furthermore, the oxide 30 and conductor 42b have openings in the region that overlaps with the recess of the conductor 42a when viewed from above. In other words, as shown in Figure 1A, the upper surfaces of the oxide 30 and conductor 42b have a hollow circular shape. In other words, the oxide 30 and the conductor 42b have a cylindrical shape with a hollow section. The openings in the oxide 30 and the conductor 42b may be referred to as openings, hollows, or hollow sections. Furthermore, the cylindrical shape with a hollow section may be referred to as a hollow cylindrical shape.

[0062] In Figure 1A, the upper surface of the oxide 30 is shown as a hollow circular shape, but the present invention is not limited to this. For example, the upper surface of the oxide 30 may be a hollow ellipse, a hollow polygon, or a hollow polygon with rounded corners. Here, a polygon refers to a triangle, quadrilateral, pentagon, hexagon, etc.

[0063] Furthermore, when the conductor 42a has a recess and the oxide 30 and conductor 42b have openings, it may be stated that the laminate of conductor 42a, oxide 30, and conductor 42b has a recess. Note that conductor 42a may also have an opening. In this case, it may be stated that the laminate of conductor 42a, oxide 30, and conductor 42b has an opening.

[0064] The insulator 50 and the conductor 60 are arranged inside the recess of the conductor 42a and inside the openings of the oxide 30 and the conductor 42b. The insulator 50 has a region in contact with the side surface of the conductor 60 and a region in contact with the bottom surface of the conductor 60.

[0065] The conductor 60 functions as a gate electrode. The insulator 50 functions as a gate insulator. The gate insulator may also be called a gate insulating layer or gate insulating film. The conductor 42a functions as one of the source electrode and drain electrode, and the conductor 42b functions as the other of the source electrode and drain electrode. At least a portion of the region of the oxide 30 that overlaps with the conductor 60 functions as a channel-forming region. The region of the oxide 30 that overlaps with the conductor 60 can be rephrased as the region of the oxide 30 that faces the conductor 60 via the insulator 50.

[0066] Transistor 20 is a so-called vertical transistor in which current flows vertically because one of the source and drain electrodes is located below the channel formation region and the other is located above the channel formation region. Vertical transistors can be formed at cross points where the minimum pitch wiring intersects. Specifically, transistor 20 is formed below the region where conductor 62 and conductor 46 intersect. Therefore, miniaturization or high integration of semiconductor devices can be achieved. Specifically, the design rule is 6F 2 From 4th floor 2 It becomes possible to minimize it to this extent.

[0067] The channel length of transistor 20 is defined as the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap in a cross-sectional view, or in the channel formation region. In other words, the channel length of transistor 20 corresponds to the film thickness of the oxide 30. Therefore, since the channel length of transistor 20 can be adjusted by the film thickness of the oxide 30, a transistor 20 with a shorter channel length can be fabricated by reducing the film thickness of the oxide 30. By forming the oxide 30 using a film formation method that allows for the formation of thin films, the channel length of transistor 20 can be set to, for example, 30 nm or less, 20 nm or less, 15 nm or less, 10 nm or less, 8 nm or less, or 5 nm or less. In other words, it is preferable to form the oxide 30 so that its film thickness is, for example, 3 nm or more and 30 nm or less. Because OS transistors have an extremely small off-current, the off-current of transistor 20 can be kept low even with the above channel lengths.

[0068] On the other hand, when operating a transistor in the saturation region, the channel length of the transistor may be increased to improve the electrical characteristics in the saturation region. Since transistor 20 is a vertical transistor, the area occupied by transistor 20 when viewed from above does not depend on the thickness of the oxide 30. Therefore, the thickness of the oxide 30 corresponding to the channel length may be thick. For example, the thickness of the oxide 30 may be greater than 30 nm and less than or equal to 100 nm.

[0069] Based on the above, the film thickness of the oxide 30 is 3 nm to 100 nm, preferably 3 nm to 30 nm, more preferably 5 nm to 30 nm, and even more preferably 5 nm to 15 nm.

[0070] Furthermore, the channel width of transistor 20 refers to the length of the channel formation region perpendicular to the channel length direction, in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate electrode overlap when viewed from above, or in the channel formation region. In other words, the channel width of transistor 20 corresponds to the circumference of the hollow circle of the oxide 30. Note that the channel width is not necessarily the same value in all regions of a single transistor. That is, the channel width of a single transistor may not be fixed to a single value. Therefore, in this specification, the channel width is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0071] The channel length and channel width can be determined, for example, by analyzing cross-sectional TEM images.

[0072] In the transistor 20, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor in the oxide 30 including the channel formation region.

[0073] Furthermore, the band gap of the metal oxide that functions as a semiconductor is preferably 2 eV or more, and more preferably 2.5 eV or more. By using a metal oxide with a large band gap, the off-current of the transistor can be reduced.

[0074] The oxide 30 preferably contains at least indium or zinc. In particular, it is preferable that it contains indium and zinc. In addition, it is preferable that it contains one or more selected from aluminum, gallium, yttrium, and tin. It may also contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt.

[0075] Here, we consider the case where In-M-Zn oxide, having indium, element M, and zinc, is used as oxide 30. Element M is aluminum, gallium, yttrium, or tin. Other elements that can be used for element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or cobalt. However, it is also possible to use a combination of multiple of the aforementioned elements as element M. In particular, it is preferable that element M is one or more selected from gallium, aluminum, yttrium, and tin. Furthermore, In-Ga oxide, In-Zn oxide, or indium oxide may also be used as oxide 30.

[0076] Specifically, as oxide 30, metal oxides with a composition of In:M:Zn=4:2:3 [atomic ratio] or nearby, In:M:Zn=1:1:1 [atomic ratio] or nearby, In:M:Zn=1:1:1.2 [atomic ratio] or nearby, or In:M:Zn=1:1:2 [atomic ratio] or nearby can be used. Note that nearby compositions include a range of ±30% of the desired atomic ratio.

[0077] In particular, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also written as IGZO) as the oxide 30. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also written as IAZO) may be used as the oxide 30. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also written as IAGZO, IGAZO, or AGIZO) may be used as the oxide 30.

[0078] In this specification, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may be called metal oxynitrides.

[0079] When silicon is used in the channel formation region of a vertical transistor, the substrate levitation effect occurs, leading to unstable electrical characteristics of the vertical transistor. On the other hand, metal oxides such as IGZO, IAZO, and IAGZO have a large effective hole mass. Therefore, by using these metal oxides in the channel formation region, the accumulation of holes in the channel formation region can be suppressed, and a vertical transistor with little or no effect from the substrate levitation effect can be fabricated. In other words, by using the above metal oxides for oxide 30, stable electrical characteristics can be imparted to the transistor 20. Therefore, a transistor with good electrical characteristics can be provided. Furthermore, a transistor with less variation in electrical characteristics can be provided.

[0080] Furthermore, it is preferable that the oxide 30 is crystalline. In particular, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) as the oxide 30.

[0081] CAAC-OS is a metal oxide with a highly crystalline, dense structure and few impurities and defects (e.g., oxygen vacancies). In particular, by heat-treating the metal oxide after its formation at a temperature that does not cause polycrystallization (e.g., between 400°C and 600°C), the CAAC-OS can be made to have an even more crystalline and dense structure. By increasing the density of CAAC-OS in this way, the diffusion of impurities or oxygen within the CAAC-OS can be further reduced.

[0082] Furthermore, because it is difficult to identify clear grain boundaries in CAAC-OS, a decrease in electron mobility due to grain boundary issues is less likely to occur. Therefore, metal oxides containing CAAC-OS have stable physical properties. Consequently, metal oxides containing CAAC-OS are highly heat-resistant and reliable.

[0083] Furthermore, by using a crystalline metal oxide such as CAAC-OS as the oxide 30, the extraction of oxygen from the oxide 30 by the source electrode or drain electrode can be suppressed. As a result, even when heat treatment is performed, the extraction of oxygen from the oxide 30 is reduced, making the transistor 20 stable against the high temperatures (so-called thermal budget) in the manufacturing process.

[0084] When CAAC-OS is used as oxide 30, the c-axis of the CAAC-OS crystal is oriented perpendicular or approximately perpendicular to the surface or upper surface of the metal oxide film that will become oxide 30. In other words, the crystal of CAAC-OS is c-axis oriented with respect to the surface or upper surface of the metal oxide film that will become oxide 30. That is, the crystal of oxide 30 is c-axis oriented with respect to the substrate surface.

[0085] Furthermore, when using In-M-Zn oxides such as IGZO and IAZO as the oxide 30, the crystal structure of the oxide 30 may include, for example, a YbFe2O4 type structure, a Yb2Fe3O7 type structure, and modified forms thereof.

[0086] The oxide 30 can be deposited using methods such as sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or atomic layer deposition (ALD). Sputtering is particularly preferred for depositing the oxide 30. Sputtering allows for the formation of crystalline metal oxides. Furthermore, because sputtering is a film deposition method capable of forming thin films, it is suitable for depositing the oxide 30.

[0087] In a so-called gate-all-around transistor, where the sides of a semiconductor-functioning metal oxide are covered by a word line via a gate insulating layer, the metal oxide is formed inside the openings formed in the word line or gate insulating layer. To miniaturize such a transistor, the inner walls of the openings must be as perpendicular as possible to the substrate surface. At this time, high step coverage is required during the deposition of the metal oxide, which limits the flexibility of the deposition method for the metal oxide.

[0088] On the other hand, the transistor 20 is manufactured by forming recesses or openings in a laminate of conductor 42a, oxide 30, and conductor 42b, and forming an insulator 50 and a conductor 60 inside the recesses or openings. In this case, the oxide 30 only needs to be formed on the conductor 42a, and high step coverage is not required when depositing the oxide 30. Therefore, the method of depositing the oxide 30 can be freely applied. For example, sputtering can be used to deposit the oxide 30, and a crystalline metal oxide can be formed.

[0089] Furthermore, to form the aforementioned recesses or openings, it is advisable to use double patterning techniques such as LELE (Litho-Etch-Litho-Etch) and SADP (Self-Aligned Double Patterning), quadruple patterning techniques such as SAQP (Self-Aligned Quadruple Patterning), and multi-patterning techniques such as octave patterning. By using multi-patterning techniques, it is possible to form fine recesses or fine openings.

[0090] Alternatively, the openings in the resist pattern may be reduced by using a shrinking agent on the resist pattern. For example, after applying the shrinking agent to the resist surface, a heat treatment is performed. This causes the resist to react with the shrinking agent, forming a reaction layer on the resist surface. At this time, the reaction layer is formed on the sides of the openings in the resist pattern, thus reducing the size of the openings. By using a resist pattern with reduced openings, fine recesses or fine openings can be formed. The shrinking agent described above is sometimes called a pattern shrinking agent or a hole shrinking agent.

[0091] Alternatively, fine patterns may be directly formed by exposure using EUV (Extreme Ultraviolet) light or the like.

[0092] Alternatively, you can combine the above methods to perform patterning.

[0093] Based on the above, an oxide semiconductor with little or no substrate levitation effect is deposited by sputtering, and then a cylindrical channel with a hollow portion is formed using multi-patterning technology such as SAQP. By providing a vertical transistor structure with a gate electrode in the hollow portion, a transistor that can be miniaturized can be provided. Using this transistor, a memory cell with a minimum processing dimension (F) of, for example, 15 nm or less can be realized. Here, the minimum processing dimension (F) is, for example, the width of the conductor 46 in the X direction, or the width of the conductor 62 in the Y direction.

[0094] Conductor 42a is provided in contact with the lower surface of oxide 30, and conductor 42b is provided in contact with the upper surface of oxide 30. In the following, conductors 42a and 42b may be collectively referred to as conductor 42.

[0095] As the conductor 42, it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferred. Alternatively, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0096] The conductive film that becomes conductor 42a and the conductive film that becomes conductor 42b are formed by different processes. Therefore, conductor 42a and conductor 42b may be formed from different materials or from the same material.

[0097] Furthermore, hydrogen contained in oxide 30, etc., may diffuse into the conductor 42a. In particular, by using a tantalum-containing nitride for the conductor 42a, hydrogen contained in oxide 30, etc., diffuses easily into the conductor 42a, and the diffused hydrogen may combine with the nitrogen present in the conductor 42a. In other words, hydrogen contained in oxide 30, etc., may be absorbed by the conductor 42a. Similarly, hydrogen contained in oxide 30, etc., may diffuse into the conductor 42b. In particular, by using a tantalum-containing nitride for the conductor 42b, hydrogen contained in oxide 30, etc., diffuses easily into the conductor 42b, and the diffused hydrogen may combine with the nitrogen present in the conductor 42b. In other words, hydrogen contained in oxide 30, etc., may be absorbed by the conductor 42b.

[0098] Furthermore, when heat treatment is performed with the conductor 42a and the oxide 30 in contact, the sheet resistance of the oxide 30 near the conductor 42a may decrease. Also, the carrier concentration may increase. Therefore, the oxide 30 near the conductor 42a can be made to have a self-aligned low resistance. Similarly, when heat treatment is performed with the conductor 42b and the oxide 30 in contact, the sheet resistance of the oxide 30 near the conductor 42b may decrease. Also, the carrier concentration may increase. Therefore, the oxide 30 near the conductor 42b can be made to have a self-aligned low resistance.

[0099] In the above case, for example, as shown in Figure 1C, regions 30n1 and 30n2 are formed in the oxide 30. Here, Figure 1C is a cross-sectional perspective view of the transistor 20.

[0100] Region 30n1 is a low-resistance region of oxide 30 near the conductor 42a, and region 30n2 is a low-resistance region of oxide 30 near the conductor 42b. Regions 30n1 and 30n2 function as source or drain regions. The region of oxide 30 that functions as a channel-forming region is denoted as region 30i. Note that it may be difficult to clearly detect the boundaries of each region in oxide 30.

[0101] In some cases, depending on the material used for the conductor 42a, region 30n1 may not be formed. In this case, the oxide 30 has region 30i and region 30n2. Similarly, depending on the material used for the conductor 42b, region 30n2 may not be formed. In this case, the oxide 30 has region 30n1 and region 30i.

[0102] It is preferable that the insulator 50 be formed using an insulator that has the function of suppressing the diffusion of oxygen. By adopting this configuration, the diffusion of oxygen contained in the oxide 30 into the conductor 60 can be suppressed. In other words, the formation of oxygen vacancies in the oxide 30 can be suppressed. Furthermore, oxidation of the conductor 60 by the oxygen contained in the oxide 30 can be suppressed. Therefore, the electrical characteristics of the transistor 20 can be improved and its reliability can be enhanced.

[0103] As the insulator 50, it is preferable to use an insulator containing an oxide of either or both aluminum and hafnium. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or an oxide containing hafnium and silicon (hafnium silicate) can be used.

[0104] Furthermore, the insulator 50 may be made of a high-dielectric constant (high-k) material. By using a high-dielectric constant material as the insulator 50, it becomes possible to reduce the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator. Therefore, the dielectric breakdown voltage of the insulator 50 can be increased.

[0105] Examples of high dielectric constant materials include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxide nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxide nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0106] Furthermore, the insulator 50 extends in the Z direction such that its upper surface is located above the conductor 42b. This prevents the conductor 42b and the conductor 62 from coming into contact, thereby preventing leakage current and short circuits between the conductor 42b and the conductor 62. Similarly, it prevents the conductor 46 and the conductor 62 from coming into contact, thereby preventing leakage current and short circuits between the conductor 46 and the conductor 62.

[0107] Figure 1B shows a configuration in which the insulator 50 is a single layer, but the present invention is not limited to this, and a laminated structure of two or more layers may be used. For example, when the insulator 50 is a two-layer laminated structure, the insulator provided on the oxide 30 side may be formed using an insulator that has the function of suppressing oxygen diffusion, and the insulator provided on the conductor 60 side may be formed using a high dielectric constant material.

[0108] It is preferable to use a conductive material for the conductor 60 that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0109] Furthermore, because the conductor 60 has the function of suppressing oxygen diffusion, it is possible to suppress the oxidation of the conductor 60 by the oxygen contained in the insulator 50, which would reduce its conductivity. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0110] Conductor 46 has a region in contact with conductor 42b, and conductor 62 has a region in contact with conductor 60. Conductors 46 and 62 function as wiring.

[0111] The conductor 46 has an opening. An insulator 50 and a conductor 60 are provided within this opening. When viewed from above, if the width of the conductor 46 in the X direction is greater than the outer diameter of the insulator 50, the conductor 46 extends in the Y direction as a continuous conductor. On the other hand, when viewed from above, if the width of the conductor 46 in the X direction is equal to or less than the outer diameter of the insulator 50, the conductor 46 is divided by the insulator 50. However, the divided conductors 46 are electrically connected via the conductor 42b. Therefore, since the conductor 46 extends in the Y direction via the conductor 42b, it can be considered to extend in the Y direction.

[0112] Furthermore, the conductor 46 may or may not have a region that overlaps with the conductor 62.

[0113] It is preferable that the conductor 46 and conductor 62 be made of conductive materials mainly composed of tungsten, copper, or aluminum. Furthermore, one or both of the conductor 46 and conductor 62 may be in a laminated structure, for example, a laminate of titanium or titanium nitride with the above conductive material.

[0114] <Modified version of transistor 20> Below, we will describe a configuration example different from the transistor 20 described above, using Figures 2A to 4C.

[0115] Figure 1B shows a configuration in which the oxide 30 is a single layer, but the present invention is not limited to this. For example, the oxide 30 may be in a laminated structure of two or more layers.

[0116] [Transistor 20A] Figure 2A is a cross-sectional perspective view of transistor 20A. Transistor 20A shown in Figure 2A is a modified example of transistor 20 shown in Figure 1B.

[0117] The transistor 20A shown in Figure 2A differs from the transistor 20 shown in Figure 1B in that the oxide 30 has a three-layer stacked structure consisting of oxide 30a, oxide 30b, and oxide 30c.

[0118] Oxide 30b functions as the channel-forming region of transistor 20A, oxide 30a functions as one of the source and drain regions of transistor 20A, and oxide 30c functions as the other of the source and drain regions of transistor 20A.

[0119] As oxide 30b, any metal oxide that can be used for oxide 30 as described above may be used.

[0120] It is preferable to use materials with higher conductivity for oxides 30a and 30c compared to oxide 30b. Furthermore, it is preferable to use degenerate oxide semiconductors for oxides 30a and 30c.

[0121] For example, as oxide 30a and oxide 30c, materials to which nitrogen has been added to a metal oxide that can be used for oxide 30b can be used. Specifically, it is preferable to use a metal oxide (also called a metal oxynitride) having indium, the aforementioned element M, zinc, and nitrogen. More specifically, oxides containing indium (In), gallium (Ga), zinc (Zn), and nitrogen (also called oxynitride having In, Ga, and Zn, or nitrogen-added IGZO), oxides containing indium (In), aluminum (Al), zinc (Zn), and nitrogen (also called oxynitride having In, Al, and Zn, or nitrogen-added IAZO), or oxides containing indium (In), aluminum (Al), gallium (Ga), zinc (Zn), and nitrogen (also called oxynitride having In, Al, Ga, and Zn, nitrogen-added IAGZO, nitrogen-added IGAZO, or nitrogen-added AGIZO) can be used.

[0122] For example, nitrogen-doped IGZO tends to have a wurtzite-type crystal structure. The wurtzite-type crystal structure has high lattice compatibility with the crystal structure of In-M-Zn oxide. Therefore, by using a metal oxynitride having a wurtzite-type crystal structure as oxide 30a, the crystallinity of oxide 30b can be increased. In other words, it becomes easier to form a metal oxide having a CAAC structure as oxide 30b.

[0123] Furthermore, as mentioned above, when CAAC-OS is used as oxide 30b, the crystals of oxide 30b are c-axis oriented with respect to the substrate surface. Note that impurities in CAAC-OS tend not to diffuse in the c-axis direction. In other words, by using CAAC-OS as oxide 30b, the incorporation of impurities into oxide 30b can be suppressed. For example, the incorporation of nitrogen into oxide 30b can be suppressed. Therefore, the increased conductivity of oxide 30b can be suppressed.

[0124] Although the above description refers to a material in which nitrogen is added to a metal oxide that can be used as oxide 30b, the element added to the metal oxide that can be used as oxide 30b can be any element that enhances the conductivity of the metal oxide. For example, one or more of the following elements can be used: hydrogen, Group 15 elements (typically nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb)), boron (B), aluminum (Al), argon (Ar), helium (He), neon (Ne), indium (In), fluorine (F), chlorine (Cl), titanium (Ti), and zinc (Zn).

[0125] Furthermore, the metal oxides used for oxides 30a and 30c only need to have higher conductivity than oxide 30b. For example, oxides 30a and 30c may be metal oxides that have elements other than oxygen as their main components, but have different chemical compositions.

[0126] When oxides 30a and 30c and oxide 30b have a common element other than oxygen as their main component, it is preferable that oxide 30 has a layered structure of multiple oxide layers with different chemical compositions. For example, when In-M-Zn oxide is used as oxide 30b, it is preferable that the atomic ratio of indium to the main component metal element in the metal oxide used in oxide 30a or oxide 30c is greater than the atomic ratio of indium to the main component metal element in the metal oxide used in oxide 30b. Furthermore, it is preferable that the atomic ratio of indium to element M in the metal oxide used in oxide 30a or oxide 30c is greater than the atomic ratio of indium to element M in the metal oxide used in oxide 30b.

[0127] Because oxides 30a and 30c and oxide 30b share a common element other than oxygen as their main component, the defect level density at the interface between oxide 30a or oxide 30c and oxide 30b can be reduced. Since the defect level density at the interface between oxide 30a or oxide 30c and oxide 30b can be reduced, the influence of interfacial scattering on carrier conduction is small, and a high on-current can be obtained.

[0128] Alternatively, titanium oxide, molybdenum oxide, zinc oxide, indium oxide, tungsten oxide, magnesium oxide, calcium oxide, tin oxide, indium zinc oxide, indium tin oxide, or silicon-containing indium tin oxide may be used as oxide 30a and oxide 30c.

[0129] Figure 2A shows a configuration in which the contour of the conductor 42a coincides with or roughly coincides with the outer contour of the oxide 30 in a top view, but the present invention is not limited thereto. If the conductor 42a has a region in contact with the oxide 30, the contour of the conductor 42a does not have to coincide with the outer contour of the oxide 30 in a top view.

[0130] [Transistor 20B] Figure 2B is a cross-sectional perspective view of transistor 20B. Here, transistor 20B shown in Figure 2B is a modified version of transistor 20A shown in Figure 2A.

[0131] The transistor 20B shown in Figure 2B differs from the transistor 20A shown in Figure 2A in that, when viewed from above, the center of the conductor 42a does not coincide with the center of the hollow cylindrical shape of the oxide 30.

[0132] To miniaturize semiconductor devices, it is necessary to reduce the diameter of the conductor 42a and the diameter of the hollow portion of the oxide 30 when viewed from above. When processing to minimize the diameter of the conductor 42a and the diameter of the hollow portion of the oxide 30, the diameter of the conductor 42a and the diameter of the hollow portion of the oxide 30 will be the same or approximately the same. In this case, when viewed from above, there is a risk that the conductor 42a and the oxide 30 will not overlap and will not be in contact with each other.

[0133] Therefore, as shown in Figure 2B, it is preferable that the conductor 42a is positioned offset from the center of the hollow cylindrical shape of the oxide 30 and the conductor 42b in a top view, and has a region that overlaps with the oxide 30 and the conductor 42b. With this configuration, the conductor 42a can have a region that is in contact with the oxide 30a. In addition, the conductor 42a and the oxide 30 and the conductor 42b can be formed independently. Thus, the degree of freedom in the layout of the semiconductor device can be increased.

[0134] Here, the arrangement of the conductor 42a relative to the oxide 30 in a top view will be explained using Figures 3A to 3E. Figures 3A to 3E are top views of the transistor 20B. Note that in the top views of Figures 3A to 3E, the conductor 60, oxide 30, and conductor 42a are shown, while some elements are omitted for clarity.

[0135] As shown in Figure 3A, the conductor 42a may have a region that overlaps with the oxide 30 and may be positioned offset in the X direction from the center of the hollow cylindrical shape of the oxide 30. Furthermore, the contour of the conductor 42a is located inside the outer circumference of the hollow cylindrical shape of the oxide 30.

[0136] Furthermore, as shown in Figure 3B, the conductor 42a may have a region that overlaps with the oxide 30 and may be positioned at a location offset in the Y direction from the center of the hollow cylindrical shape of the oxide 30. Also, the contour of the conductor 42a is located inside the outer circumference of the hollow cylindrical shape of the oxide 30.

[0137] In the configurations shown in Figures 3A and 3B, if the conductor 42a has a region that overlaps with the oxide 30, then a portion of the contour of the conductor 42a may be located outside the outer circumference of the hollow cylindrical shape of the oxide 30.

[0138] Furthermore, as shown in Figure 3C, the conductor 42a may have a region that overlaps with the oxide 30 and may be positioned at a location offset in the X and Y directions from the center of the hollow cylindrical shape of the oxide 30. Also, as shown in Figure 3C, a portion of the contour of the conductor 42a may be located outside the outer circumference of the hollow cylindrical shape of the oxide 30.

[0139] In Figures 3A to 3C, the upper surface of the oxide 30 is shown as a hollow circular shape, but the present invention is not limited to this. For example, the upper surface of the oxide 30 may be a hollow ellipse, a hollow polygon, or a hollow polygon with rounded corners.

[0140] For example, in Figure 3D, the upper surface of the oxide 30 has a hollow square shape with rounded corners, and the upper surfaces of the conductor 42a and conductor 60 also have a square shape with rounded corners. Furthermore, in Figure 3D, the conductor 42a has a region that overlaps with the oxide 30 and is positioned offset in the X and Y directions from the center of the hollow cylindrical shape of the oxide 30. Note that, as shown in Figure 3D, a part of the contour of the conductor 42a may be located outside the outer circumference of the hollow cylindrical shape of the oxide 30.

[0141] Figures 3A to 3D show the configuration when the diameter of the conductor 42a matches the diameter of the hollow portion of the oxide 30. However, a similar configuration can be used when the diameter of the conductor 42a is smaller than the diameter of the hollow portion of the oxide 30.

[0142] In addition, since the conductor 42a and the oxide 30 can be formed independently in transistor 20B, the upper surface shape of the conductor 42a and the upper surface shape of the hollow portion of the oxide 30 may be different. For example, the upper surface of the oxide 30 may have a hollow circular shape, and the upper surface of the conductor 42a may have a polygonal shape with rounded corners (sometimes referred to as a roughly polygonal shape).

[0143] In a top view, if the conductor 42a is larger than the hollow portion of the hollow cylindrical shape of the oxide 30, the center of the conductor 42a may be positioned to coincide with the center of the hollow cylindrical shape of the oxide 30. For example, as shown in Figure 3E, the conductor 42a has a region that overlaps with the oxide 30, and the contour of the conductor 42a is located inside the outer circumference of the hollow cylindrical shape of the oxide 30. Note that the contour of the conductor 42a only needs to be located inside the outer circumference of the hollow cylindrical shape of the oxide 30, and the conductor 42a may be positioned offset from the center of the hollow cylindrical shape of the oxide 30 in one or both of the X and Y directions.

[0144] [Transistor 20C] Figure 4A shows an example configuration different from the transistor 20A described above. Figure 4A is a cross-sectional perspective view of transistor 20C. Transistor 20C shown in Figure 4A is a modified version of transistor 20A shown in Figure 2A.

[0145] The transistor 20C shown in Figure 4A differs from the transistor 20A shown in Figure 2A in that it does not have a conductor 42b.

[0146] In transistor 20C, the conductor 46 also performs the functions of the conductor 42b. That is, the conductor 46 has the function of wiring and the function of the other of the source electrode and drain electrode. By eliminating the conductor 42b, the transistor manufacturing process can be simplified and productivity can be improved.

[0147] [Transistor 20D] Figure 4B shows an example configuration different from the transistor 20A described above. Figure 4B is a cross-sectional perspective view of transistor 20D. Transistor 20D shown in Figure 4B is a modified version of transistor 20A shown in Figure 2A.

[0148] The transistor 20D shown in Figure 4B differs from the transistor 20A shown in Figure 2A in the shape of its conductor 46.

[0149] Region 64a shown in Figure 4B is the region where conductors 46 and 42b overlap in a top view. Region 64a does not overlap with conductor 62. Region 64b shown in Figure 4B is the region where conductors 46, 42b, and 62 overlap in a top view.

[0150] The conductor 46 has a convex-shaped portion 46a in the region overlapping with regions 64a and 64b. The conductor 46 is in contact with the conductor 42b at the convex-shaped portion 46a.

[0151] The convex-shaped portion 46a is formed when forming the conductor 46 on an insulator (not shown in Figure 4B) that has an opening in the region overlapping with the conductor 42b. The method for forming the conductor 46 having the convex-shaped portion will be described in Embodiment 2.

[0152] In Figure 4B, the conductor 46 is shown having a convex-shaped portion 46a in the region overlapping with regions 64a and 64b. However, the present invention is not limited to this, and it is sufficient that the convex-shaped portion 46a is in contact with at least a part of the upper surface of the conductor 42b.

[0153] [Transistor 20E] Figure 4C is a cross-sectional perspective view of transistor 20E. Transistor 20E shown in Figure 4C is a modified example of transistor 20D shown in Figure 4B.

[0154] The transistor 20E shown in Figure 4C has a different shape of conductor 46 compared to the transistor 20D shown in Figure 4B.

[0155] The conductor 46 of transistor 20E does not overlap with the conductor 62 when viewed from above. Furthermore, the conductor 46 has a convex shape portion 46a in the region that overlaps with region 64a. In other words, the convex shape portion 46a does not overlap with region 64b shown in Figure 4B. Note that if the conductor 46 is in contact with a part of the upper surface of the conductor 42b, the conductor 46 may or may not have a region that is in contact with the insulator 50.

[0156] The above configuration allows for a larger distance between the conductor 62 and the conductor 46. Therefore, leakage current and short circuits between the conductor 62 and the conductor 46 can be prevented. In addition, as long as leakage current and short circuits between the conductor 62 and the conductor 46 can be prevented, the conductor 62 and the conductor 46 may have overlapping regions, as shown in Figures 1B and 4B.

[0157] According to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, a semiconductor device with good reliability can be provided. Alternatively, a semiconductor device with good electrical characteristics can be provided. Alternatively, a semiconductor device with a large on-current can be provided.

[0158] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0159] (Embodiment 2) In this embodiment, using Figures 5A to 16B, we will describe an example of the configuration of a semiconductor device according to one aspect of the present invention, an example of the configuration of a transistor in a semiconductor device according to one aspect of the present invention, a method for manufacturing a transistor, and a method for manufacturing a semiconductor device.

[0160] <Example of semiconductor device configuration> Figures 5A to 5E illustrate an example of the configuration of a semiconductor device according to one aspect of the present invention. The semiconductor device according to one aspect of the present invention has a plurality of transistors.

[0161] Figures 5A to 5E are top views and cross-sectional views of a semiconductor device according to one embodiment of the present invention. Figures 5A and 5D are top views of the said semiconductor device. Figures 5B, 5C, and 5E are cross-sectional views of the said semiconductor device. Here, Figure 5B is a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 5A. Figure 5C is a cross-sectional view of the area indicated by the dashed line B1-B2 in Figure 5A. Figure 5D is a top view of the region enclosed by the double-dash line in Figure 5A, including the cross-section of the area indicated by the dashed line C1-C2 in Figure 5B. Figure 5E is a cross-sectional view of the area indicated by the dashed line B3-B4 in Figure 5A. Note that in the top views of Figures 5A and 5D, some elements have been omitted for clarity.

[0162] The semiconductor devices shown in Figures 5A to 5E have multiple transistors 200. Figure 5A shows an example in which the semiconductor device has multiple transistors 200 arranged in a matrix. Note that the area enclosed by the dashed line in Figure 5A shows four transistors 200.

[0163] The semiconductor device shown in Figures 5A to 5E includes an insulator 216 on a substrate (not shown), a transistor 200, an insulator 275b, an insulator 250b, and an insulator 274 on the substrate and the insulator 216, an insulator 277 and an insulator 278 on the transistor 200, an insulator 275b, an insulator 250b, and an insulator 274, and an insulator 285 on the insulators 277 and 278. The insulators 216, 274, 277, 278, and 285 function as interlayer films. The semiconductor device also includes a conductor 246 and a conductor 262.

[0164] Conductors 246 are provided on transistor 200, insulator 275b, insulator 250b, and insulator 274, which are electrically connected to transistor 200 and function as wiring. In addition, conductors 262 (conductors 262a and 262b) are provided on insulator 276, insulator 278, and transistor 200, which are electrically connected to transistor 200 and function as wiring.

[0165] Conductor 262 extends in the X direction. Conductor 246 extends in the Y direction. Therefore, it can be said that the direction in which conductor 262 extends is perpendicular to the direction in which conductor 246 extends.

[0166] In the top view of the semiconductor device shown in Figures 5A to 5E, the conductor 246 and the conductor 262 do not overlap.

[0167] The transistor 200 is located below the region where the conductor 262 and the region between adjacent conductors 246 in the Y direction intersect.

[0168] Transistor 200 corresponds to transistor 20 or a modified version thereof described in Embodiment 1. Therefore, the configuration of transistor 200 can be considered in reference to the details of transistor 20 and its modified version described in Embodiment 1. Figures 5B to 5E illustrate transistor 200 to which the configuration of transistor 20E is applied.

[0169] <Transistor 200> As shown in Figures 5B and 5C, the transistor 200 includes a conductor 242a (conductor 242a1 and conductor 242a2) arranged to be embedded in the insulator 216, an oxide 230a on the insulator 216 and the conductor 242a, an oxide 230b on the oxide 230a, an oxide 230c on the oxide 230b, a conductor 242b on the oxide 230c, an insulator 275a, an insulator 250a on the insulator 275a, and a conductor 260 on the insulator 250a.

[0170] In the following, oxides 230a, 230b, and 230c may be collectively referred to as oxide 230.

[0171] The oxide 230 and the conductor 242b have a cylindrical shape extending in the Z direction and have an opening. In other words, the oxide 230 and the conductor 242b have a cylindrical shape with a hollow portion (also called a hollow cylindrical shape). To put it another way, the upper surfaces of the oxide 230 and the conductor 242b have a hollow circular shape. Furthermore, the opening in the oxide 230 and the opening in the conductor 242b overlap.

[0172] The insulators 275a, 250a, and 260 are arranged inside the openings provided in the oxide 230 and conductor 242b. The insulator 250a has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260. The insulator 275a has a region in contact with the side surface of the insulator 250a, a region in contact with the bottom surface of the insulator 250a, a region in contact with the side surface of the opening in the oxide 230, and a region in contact with the side surface of the opening in the conductor 242b. In this configuration, it can also be said that each of the insulators 275a and 250a has a recess.

[0173] Figure 5D corresponds to the XY plane at or near the center of oxide 230b. In Figure 5D, if the cross-sectional shape of conductor 260 is circular, insulator 250a is provided concentrically on the outside of conductor 260, insulator 275a is provided concentrically on the outside of insulator 250a, oxide 230b is provided concentrically on the outside of insulator 275a, and insulator 275b is provided concentrically on the outside of oxide 230b.

[0174] Here, the width of oxide 230b in the direction from the center of the hollow portion of oxide 230b toward the outer circumference of the cylindrical shape is defined as width H1. In other words, width H1 is half the difference between the outer diameter and the inner diameter of the hollow cylindrical shape.

[0175] To prevent adjacent oxide 230b particles from touching each other, the width H1 must be less than half of the minimum processing dimension (F). On the other hand, to form a hollow cylindrical oxide 230b, the width H1 must be of a certain size. If the minimum processing dimension (F) is, for example, 15 nm, the width H1 is preferably 1 nm to 7 nm, more preferably 1.5 nm to 6 nm, and even more preferably 2 nm to 5 nm. With this configuration, adjacent oxide 230b particles do not touch each other, and at least an insulator 275b can be provided between adjacent oxide 230b particles. Note that the preferred range for the width H1 is not limited to the above. The width H1 should be set appropriately considering the minimum processing dimension and the film thickness of the insulator 275b.

[0176] In Figure 5D, the upper surfaces of the oxide 230 and the conductor 242b are shown as hollow circular shapes, but the present invention is not limited to this. For example, the upper surfaces of the oxide 230 and the conductor 242b may be hollow elliptical shapes, hollow polygonal shapes, or hollow polygonal shapes with rounded corners.

[0177] Oxide 230 has a region that overlaps with conductor 242a. More specifically, oxide 230a has a region that is in contact with the upper surface of conductor 242a. Also, oxide 230 overlaps with conductor 242b. More specifically, oxide 230c is in contact with the lower surface of conductor 242b. Also, conductor 242b has a region that is in contact with conductor 246. Also, conductor 260 has a region that is in contact with conductor 262.

[0178] The top of insulator 250a is in the same or approximately the same height as the top of insulator 275a, the top of insulator 275b, and the top of insulator 250b.

[0179] An insulator 276 is provided on insulators 275a and 250a. A conductor 262 is located on insulator 276. In other words, insulator 276 is provided between insulators 275a and 250a and conductor 262. Insulator 276 has a region that overlaps with insulators 275a and 250a. Insulator 276 also has a region that is in contact with the lower surface of conductor 262. In other words, at least a portion of the lower surface of conductor 262 is in contact with the upper surface of insulator 276.

[0180] The insulator 276 functions as an interlayer film. The insulator 276 has a cylindrical shape and an opening. In other words, the insulator 276 has a cylindrical shape with a hollow portion. To put it another way, the upper surface of the insulator 276 has a hollow circular shape. The conductor 260 is provided in the hollow portion of the insulator 276. Furthermore, if the cross-sectional shape of the conductor 260 is circular, the insulator 276 is provided concentrically on the outside of the conductor 260.

[0181] In a top view, it is preferable that the outer circumference of the hollow portion of the insulator 276 is the same as or larger than the outer circumference of the region overlapping with the oxide 230b of the conductor 260. This configuration allows the conductor 260 to be more reliably embedded in the recess of the insulator 250a.

[0182] Furthermore, it is preferable that the cylindrical contour of the insulator 276 matches or roughly matches the contour of the insulator 275a. With this configuration, the contact area between the conductor 242b and the conductor 246 can be increased compared to a configuration in which the cylindrical contour of the insulator 276 is larger than the contour of the insulator 275a. Also, with this configuration, the distance between the conductor 262 and the conductor 246 can be increased compared to a configuration in which the cylindrical contour of the insulator 276 is smaller than the contour of the insulator 275a. Therefore, leakage current and short circuits between the conductor 262 and the conductor 246 can be prevented.

[0183] Furthermore, it is preferable that the insulator 276 extends in the Z direction such that the upper surface of the conductor 246 is located between the lower and upper surfaces of the insulator 276. In other words, it is preferable that the insulator 276 extends in the Z direction such that the upper surface of the conductor 246 is located above the lower surface of the insulator 276 and below the upper surface of the insulator 276. This configuration prevents contact between the conductor 262 and the conductor 246, thereby preventing leakage current and short circuits between the conductor 262 and the conductor 246.

[0184] An insulator 277 is provided on the conductor 246. As shown in Figure 5E, the ends of the insulator 277 and the conductor 246 coincide or substantially coincide.

[0185] Conductor 260 functions as a gate electrode. Insulators 275a and 250a function as gate insulators. Conductor 242a functions as one of the source and drain electrodes, and conductor 242b functions as the other of the source and drain electrodes. At least a portion of the region of oxide 230 that overlaps with conductor 260 functions as a channel-forming region. The region of oxide 230 that overlaps with conductor 260 can be rephrased as the region of oxide 230 that faces conductor 260 via insulators 275a and 250a. For example, oxide 230b functions as a channel-forming region, oxide 230a functions as one of the source and drain regions, and oxide 230c functions as the other of the source and drain regions.

[0186] In transistor 200, it is preferable to use a semiconductor-functioning metal oxide for the oxide 230b, which includes the channel-forming region. In some cases, a portion of the regions of oxide 230a and oxide 230c that overlap with the conductor 260 may function as the channel-forming region.

[0187] In the transistor 200 shown in Figure 5B, the oxide 230 is shown as a stacked structure of oxide 230a, oxide 230b, and oxide 230c, but the present invention is not limited to this. For example, the oxide 230 may be a single layer, or a stacked structure of two or four or more layers.

[0188] Here, oxide 230 corresponds to oxide 30 described in Embodiment 1. Specifically, oxide 230a corresponds to oxide 30a described in Embodiment 1, oxide 230b corresponds to oxide 30b described in Embodiment 1, and oxide 230c corresponds to oxide 30c described in Embodiment 1. Therefore, the materials and composition of oxide 230 (oxide 230a, oxide 230b, and oxide 230c) can be considered in reference to the contents of oxide 30 (oxide 30a, oxide 30b, and oxide 30c) described in Embodiment 1.

[0189] Insulators 216, 274, 276, 277, 278, and 285 preferably have a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. For example, as insulators 216, 274, 276, 277, 278, and 285, silicon oxide, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, porous silicon oxide, or resin may be used as appropriate. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, or acrylic.

[0190] The conductor 242a has a region that overlaps with the oxide 230. More specifically, the conductor 242a is arranged to be in contact with at least a portion of the oxide 230a. Here, it is preferable that the conductor 242a is embedded in an opening formed in the insulator 216. Also, as shown in Figure 5A, in a top view, the center of the conductor 242a does not coincide with the center of the hollow cylindrical shape of the oxide 230. However, the center of the conductor 242a may coincide with the center of the hollow cylindrical shape of the oxide 230.

[0191] The conductor 242a comprises conductor 242a1 and conductor 242a2. Conductor 242a1 is provided in contact with the bottom surface and side wall of an opening formed in the insulator 216. Conductor 242a2 is provided so as to be embedded in a recess formed in conductor 242a1. Here, the height of the upper surface of conductor 242a2 is equal to or approximately equal to the height of the upper surface of conductor 242a1 and the height of the upper surface of the insulator 216.

[0192] Here, it is preferable that the conductor 242a1 is a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom or oxygen molecule). Alternatively, it is preferable that the conductor 242a1 is a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms.

[0193] By using a conductive material that has the function of suppressing oxygen diffusion for the conductor 242a1, it is possible to suppress the oxidation of the conductor 242a2 and the decrease in conductivity. Preferably, the conductive material that has the function of suppressing oxygen diffusion is titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide. Therefore, the conductive material 242a1 can be a single layer or a laminate of the above-mentioned conductive material. For example, titanium nitride can be used for the conductor 242a1.

[0194] Furthermore, it is preferable that the conductor 242a2 be a conductive material mainly composed of tungsten, copper, or aluminum. For example, tungsten may be used for the conductor 242a2.

[0195] The electrical resistivity of the conductor 242a is designed considering the potential applied to the conductor 242a, and the film thickness of the conductor 242a is set to match this electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 242a. Here, it is preferable to reduce the film thickness of both the conductor 242a and the insulator 216 as much as the design of the conductor 242a allows. By reducing the film thickness of the insulator 216, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thereby reducing the diffusion of these impurities into the oxide 230.

[0196] Although Figure 5B shows a configuration in which the conductor 242a is made up of stacked conductors 242a1 and 242a2, the present invention is not limited to this. For example, the conductor 242a may be provided as a single layer or as a stacked structure of three or more layers.

[0197] Note that the conductor 242a corresponds to the conductor 42a described in Embodiment 1. Therefore, the material and structure of the conductor 242a can be considered in reference to the contents of the conductor 42a described in Embodiment 1.

[0198] The conductor 242b is superimposed on the oxide 230. More specifically, the conductor 242b is provided in contact with the upper surface of the oxide 230c.

[0199] As the conductor 242b, it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferred. Alternatively, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0200] Although Figure 5B shows a configuration in which the conductor 242b is a single layer, the present invention is not limited to this, and the conductor 242b may be in a laminated structure of two or more layers. For example, the conductor 242b may be in a two-layer laminated structure consisting of a lower layer of conductor 242b on the oxide 230c and an upper layer of conductor 242b.

[0201] Preferably, the layer beneath the conductor 242b is composed of a conductive material that is resistant to oxidation. This prevents oxidation of the layer beneath the conductor 242b and a decrease in the conductivity of the conductor 242b. The layer beneath the conductor 242b may also have properties that easily absorb (extract) hydrogen. This allows hydrogen from the oxide 230 to diffuse into the layer beneath the conductor 242b, reducing the hydrogen concentration of the oxide 230. Thus, stable electrical characteristics can be imparted to the transistor 200.

[0202] The upper layer of the conductor 242b is preferably composed of a conductive material with higher conductivity than the lower layer of the conductor 242b. In this case, the upper layer of the conductor 242b only needs to have a region with higher conductivity than the lower layer of the conductor 242b in at least a portion of it. Furthermore, it is preferable that the upper layer of the conductor 242b is composed of a conductive material with lower resistivity than the lower layer of the conductor 242b. This makes it possible to manufacture a semiconductor device with suppressed wiring delay.

[0203] Furthermore, the upper layer of the conductor 242b may have properties that readily absorb hydrogen. This allows hydrogen absorbed into the lower layer of the conductor 242b to diffuse into the upper layer of the conductor 242b, further reducing the hydrogen concentration in the oxide 230. Thus, stable electrical characteristics can be imparted to the transistor 200.

[0204] Here, it is preferable to use conductive materials for the lower layer and the upper layer of the conductor 242b that have the same constituent elements but different chemical compositions. In this case, the lower layer and the upper layer of the conductor 242b can be continuously deposited without exposure to the atmospheric environment. By depositing the film without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the surface of the lower layer of the conductor 242b, and the vicinity of the interface between the lower layer and the upper layer of the conductor 242b can be kept clean.

[0205] Furthermore, it is preferable to use a tantalum-containing nitride with a high atomic ratio of nitrogen to tantalum in the lower layer of the conductor 242b, and a tantalum-containing nitride with a low atomic ratio of nitrogen to tantalum in the upper layer of the conductor 242b. For example, as the lower layer of the conductor 242b, a tantalum-containing nitride with an atomic ratio of nitrogen to tantalum of 1.0 or more and 2.0 or less, preferably 1.1 or more and 1.8 or less, and more preferably 1.2 or more and 1.5 or less, is used. Alternatively, for example, as the upper layer of the conductor 242b, a tantalum-containing nitride with an atomic ratio of nitrogen to tantalum of 0.3 or more and 1.5 or less, preferably 0.5 or more and 1.3 or less, and more preferably 0.6 or more and 1.0 or less, is used.

[0206] In tantalum-containing nitrides, increasing the atomic ratio of nitrogen to tantalum can suppress oxidation of the tantalum-containing nitride. Furthermore, it can improve the oxidation resistance of the tantalum-containing nitride. Additionally, it can suppress the diffusion of oxygen into the tantalum-containing nitride. Therefore, it is preferable to use a tantalum-containing nitride with a high atomic ratio of nitrogen to tantalum as the layer beneath the conductor 242b. This prevents the formation of an oxide layer between the layer beneath the conductor 242b and the oxide 230, or reduces the thickness of the oxide layer.

[0207] Furthermore, in tantalum-containing nitrides, the resistivity of the nitride can be reduced by lowering the atomic ratio of nitrogen to tantalum. Therefore, it is preferable to use a tantalum-containing nitride with a low atomic ratio of nitrogen to tantalum as the upper layer of the conductor 242b. This makes it possible to manufacture a semiconductor device with suppressed wiring delay.

[0208] Furthermore, in the conductor 242b, it may be difficult to clearly detect the boundary between the upper and lower layers. When a nitride containing tantalum is used for the conductor 242b, the tantalum and nitrogen concentrations detected within each layer may not be limited to stepwise changes within each layer, but may also change continuously (also called a gradient) in the region between the upper and lower layers. In other words, the closer the region of the conductor 242b is to the oxide 230, the higher the atomic ratio of nitrogen to tantalum should be. Therefore, it is preferable that the atomic ratio of nitrogen to tantalum in the region located below the conductor 242b is higher than the atomic ratio of nitrogen to tantalum in the region located above the conductor 242b.

[0209] The film thickness of the lower layer of conductor 242b is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, more preferably 1.0 nm or more and 3.0 nm or less. In this case, the lower layer of conductor 242b only needs to have a region with the above-mentioned film thickness in at least a part of it. Furthermore, it is preferable that the film thickness of the lower layer of conductor 242b is thinner than the film thickness of the upper layer of conductor 242b. In this case, the lower layer of conductor 242b only needs to have a region with a film thickness thinner than the upper layer of conductor 242b in at least a part of it.

[0210] Although the present invention has shown an example in which the lower layer and the upper layer of the conductor 242b are made of conductive materials with the same constituent elements but different chemical compositions, the present invention is not limited to this, and the lower layer and the upper layer of the conductor 242b may be formed using different conductive materials. For example, a nitride containing tantalum may be used as the lower layer of the conductor 242b, and a nitride containing titanium may be used as the upper layer of the conductor 242b.

[0211] Note that the conductor 242b corresponds to the conductor 42b described in Embodiment 1. Therefore, the material and structure of the conductor 242b can be considered in reference to the contents of the conductor 42b described in Embodiment 1.

[0212] In a top view, the insulator 275a is positioned inside the openings in the oxide 230 and the conductor 242b (the hollow portion between the oxide 230 and the conductor 242b). The insulator 275a functions as part of the gate insulator.

[0213] In a top view, the insulator 275b is positioned outside the cylindrical shapes of the oxide 230 and the conductor 242b.

[0214] As will be explained in detail later, insulators 275a and 275b are formed in the same process. Therefore, insulators 275a and 275b are made of the same material.

[0215] As the insulators 275a and 275b, it is preferable to use a barrier insulating film against oxygen. As the insulators 275a and 275b, for example, an insulator containing one or both of oxides of aluminum and hafnium may be used. As such an insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), etc. can be used. In the present embodiment, aluminum oxide is used as the insulators 275a and 275b. In this case, the insulators 275a and 275b have at least oxygen and aluminum.

[0216] As shown in FIG. 5D, the insulator 275a is provided in contact with the side surface at the opening of the oxide 230. Further, the insulator 275b is provided in contact with the outer side surface of the oxide 230. That is, the oxide 230 is covered with the insulators 275a and 275b. Thereby, when heat treatment or the like is performed, the desorption of oxygen by the oxide 230 can be blocked by the insulators 275a and 275b having barrier properties against oxygen. Therefore, the formation of oxygen deficiency in the oxide 230 can be reduced. Thereby, the oxygen deficiency and V O H formed in the oxide 230 can be reduced. Therefore, the electrical characteristics of the transistor 200 can be improved and the reliability can be enhanced.

[0217] Conversely, even if the insulators 274 and 250a etc. contain an excessive amount of oxygen, the supply of the oxygen to the oxide 230 can be suppressed excessively. Therefore, it is possible to suppress the excessive oxidation of the oxides 230a and 230c and the occurrence of a decrease in the on-current or a decrease in the field-effect mobility of the transistor 200.

[0218] Furthermore, as shown in Figure 5B, the insulator 275a is provided in contact with the side surface of the conductor 242b at the opening, and the insulator 275b is provided in contact with the outer side surface of the conductor 242b. In other words, the conductor 242b is covered by the insulators 275a and 275b. This reduces oxidation of the side surface of the conductor 242b and the formation of an oxide film on that surface. This suppresses a decrease in the on-current of the transistor 200 or a decrease in the field-effect mobility.

[0219] When aluminum oxide is used as insulators 275a and 275b, aluminum may be added to the region of oxide 230b that is in contact with insulator 275a and its vicinity, and to the region of oxide 230b that is in contact with insulator 275b and its vicinity. For example, when IGZO is used as oxide 230b, the region of oxide 230b that is in contact with insulator 275a and its vicinity, and to the region of oxide 230b that is in contact with insulator 275b and its vicinity, may contain indium, gallium, aluminum, and zinc.

[0220] Furthermore, as shown in Figure 5B and other figures, by providing an insulator 275a made of aluminum oxide or the like in contact with the side surface of the opening of the oxide 230b, the indium contained in the oxide 230b may be unevenly distributed at and near the interface between the oxide 230b and the insulator 275a. As a result, the atomic ratio near the surface on the opening side of the oxide 230b becomes close to that of indium oxide, or close to that of In-Zn oxide. By increasing the atomic ratio of indium in the oxide 230b, particularly near the surface on the opening side of the oxide 230b, the field-effect mobility of the transistor 200 can be improved.

[0221] The insulator 275a, together with the insulator 250a and the conductor 260, must be provided within the opening formed in the conductor 242b and the oxide 230. In order to miniaturize the transistor 200, it is preferable that the film thickness of the insulator 275a be thin. The film thickness of the insulator 275a should be 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and less than 3.0 nm. In this case, the insulator 275a should have at least a portion of a region with the above-mentioned film thickness. Furthermore, it is preferable that the film thickness of the insulator 275a be thinner than that of the insulator 250a. In this case, the insulator 275a should have at least a portion of a region with a thinner film thickness than the insulator 250a.

[0222] To achieve the thin film thickness of insulator 275a as described above, it is preferable to deposit insulator 275a using the ALD method. ALD methods include thermal ALD, which uses only thermal energy for the reaction between the precursor and reactant, and plasma-enhanced ALD (PEALD), which uses plasma-excited reactants. The PEALD method is preferable in some cases because the use of plasma allows for film deposition at lower temperatures.

[0223] The ALD method allows for the deposition of atoms layer by layer, resulting in several advantages: the ability to deposit extremely thin films, films on structures with high aspect ratios, films with fewer defects such as pinholes, films with excellent coverage, and films at low temperatures. Therefore, the insulator 275a can be deposited with good coverage on the sides of openings formed in the conductor 242b and oxide 230, with the thin film thickness described above.

[0224] Note that precursors used in the ALD method may contain carbon and other impurities. Therefore, films formed by the ALD method may contain more carbon and other impurities compared to films formed by other deposition methods. The quantity of impurities can be quantified using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0225] As described above, insulators 275a and 275b are formed in the same process. Therefore, the film thickness of insulator 275b is equal to the film thickness of insulator 275a.

[0226] Insulator 250a is placed in the recess of insulator 275a. Insulator 250a functions as part of the gate insulator.

[0227] The insulator 250b is positioned in contact with the upper surface of the insulator 275b.

[0228] As will be explained in detail later, insulators 250a and 250b are formed in the same process. Therefore, insulators 250a and 250b are made of the same material.

[0229] It is preferable to use insulators 250a and 250b that have the function of suppressing oxygen diffusion. By using such a configuration, oxidation of the conductor 260 by oxygen contained in the oxide 230 can be suppressed. For example, insulators 250a and 250b may be insulators containing oxides of aluminum and hafnium, or both. As such insulators, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or an oxide containing hafnium and silicon (hafnium silicate) can be used.

[0230] Furthermore, insulators 250a and 250b may be made of high-dielectric constant (high-k) materials. In this case, it becomes possible to thin the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator. Therefore, the dielectric breakdown voltage of the gate insulator can be increased.

[0231] Furthermore, the insulators 250a and 250b may be silicon oxide, silicon oxide nitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide with vacancies.

[0232] In this embodiment, hafnium oxide is used as insulator 250a and insulator 250b. In this case, insulator 250a and insulator 250b have at least oxygen and hafnium.

[0233] As described above, insulators 250a and 250b are formed in the same process. Therefore, the film thickness of insulator 250b is equal to the film thickness of insulator 250a.

[0234] Insulators 250a and 275a correspond to the two-layer laminated insulator 50 described in Embodiment 1. Therefore, the materials and configuration of insulators 250a and 275a can be considered in reference to the insulator 50 described in Embodiment 1.

[0235] The conductor 260 is placed in the recess of the insulator 250a. The conductor 260 functions as the gate electrode of the transistor 200.

[0236] As the conductor 260, it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, or ruthenium nitride. Alternatively, for example, ruthenium oxide, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are conductive materials that are resistant to oxidation, or materials that maintain conductivity even when absorbing oxygen, and are therefore suitable when an insulating material containing oxygen is used as the insulator 250a that comes into contact with the conductor 260.

[0237] Furthermore, it is preferable to use a conductive material for the conductor 260 that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules) may be used. Examples of conductive materials that have the function of suppressing the diffusion of oxygen include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide.

[0238] In transistor 200, the conductor 260 is formed self-aligned to fill the openings formed in the oxide 230 and the conductor 242b.

[0239] Figure 5B shows a configuration in which the conductor 260 is a single layer, but the present invention is not limited to this. For example, the conductor 260 may be a laminated structure of two or more layers.

[0240] Note that the conductor 260 corresponds to the conductor 60 described in Embodiment 1. Therefore, the material and structure of the conductor 260 can be considered in reference to the conductor 60 described in Embodiment 1.

[0241] The conductor 246 is placed on the conductor 242b. Furthermore, the conductor 246 is positioned in contact with at least a portion of the upper surface of the conductor 242b. The conductor 246 also has a convex shape in the region overlapping with the conductor 242b. The conductor 246 functions as wiring.

[0242] The conductor 246 is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 246 may also be in a laminated structure, for example, a laminate of titanium or titanium nitride with the above conductive material.

[0243] Note that the conductor 246 corresponds to the conductor 46 described in Embodiment 1. Therefore, the material and structure of the conductor 246 can be considered in reference to the conductor 46 described in Embodiment 1.

[0244] The conductor 262 is placed on the conductor 260. Furthermore, the conductor 262 is placed in contact with the upper surface of the conductor 260. The conductor 262 functions as wiring.

[0245] The conductor 262 preferably comprises a conductor 262a and a conductor 262b disposed on top of the conductor 262a. For example, it is preferable that the conductor 262a is arranged to enclose the bottom and sides of the conductor 262b. Also, as shown in Figure 5B, the top surface of the conductor 262 is approximately the same height as the top surface of the insulator 285. In Figure 5B, the conductor 262 is shown as a two-layer structure of conductor 262a and conductor 262b, but it may also be a single-layer structure or a laminated structure of three or more layers.

[0246] It is preferable to use a conductive material for the conductor 262a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0247] Furthermore, because the conductor 262a has the function of suppressing oxygen diffusion, it is possible to suppress the oxidation of the conductor 262b by the oxygen contained in the insulator 285, which would otherwise reduce its conductivity. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0248] Furthermore, since the conductor 262 functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 262b can be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 262b may also be in a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0249] Note that the conductor 262 corresponds to the conductor 62 described in Embodiment 1. Therefore, the material and structure of the conductor 262 can be considered in reference to the contents of the conductor 62 described in Embodiment 1.

[0250] <Component materials for semiconductor devices> The following describes the constituent materials that can be used in semiconductor devices.

[0251] [substrate] As the substrate for forming transistor 200, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon and germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides or metal oxides. Furthermore, there are substrates on which a conductor or semiconductor is provided on an insulating substrate, substrates on which a conductor or insulator is provided on a semiconductor substrate, and substrates on which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates with elements mounted on them may be used. Examples of elements mounted on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0252] [Insulator] Insulators include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0253] For example, as transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0254] Furthermore, examples of insulators with high dielectric constants include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0255] Insulators with low dielectric constants include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with vacancies, or resins.

[0256] Furthermore, the electrical properties of transistors using metal oxides can be stabilized by surrounding them with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxide nitride, and silicon nitride can be used.

[0257] Furthermore, the insulator that functions as a gate insulator is preferably an insulator that has a region containing oxygen that is desorbed by heating. For example, by having a silicon oxide or silicon oxynitride having a region containing oxygen that is desorbed by heating in contact with the oxide 230, the oxygen deficiency of the oxide 230 can be compensated for.

[0258] [conductor] As the conductor, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metallic elements, or an alloy combining the above metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0259] Furthermore, multiple conductive layers formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with a nitrogen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material.

[0260] In the case of using an oxide in the channel formation region of a transistor, it is preferable to use a laminated structure in which a conductor functioning as a gate electrode is a combination of a material containing the above-described metal element and a conductive material containing oxygen. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is likely to be supplied to the channel formation region.

[0261] In particular, as the conductor functioning as a gate electrode, it is preferable to use a metal element contained in a metal oxide in which a channel is formed and a conductive material containing oxygen. Further, a conductive material containing the above-described metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Further, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon may be used. Further, indium gallium zinc oxide containing nitrogen may be used. By using such a material, it may be possible to capture hydrogen contained in the metal oxide in which a channel is formed. Or, it may be possible to capture hydrogen mixed from an external insulator or the like.

[0262] [Metal Oxide] As the oxide 230, it is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor. Hereinafter, metal oxides applicable to the oxide 230 according to the present invention will be described.

[0263] Examples of the crystal structure of the oxide semiconductor include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), single crystal, and poly crystal.

[0264] Note that the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. For example, it can be evaluated using the XRD spectrum obtained by grazing-incidence XRD (GIXD) measurement. Note that the GIXD method is also referred to as the thin-film method or the Seemann-Bohlin method. In the following, the XRD spectrum obtained by GIXD measurement may sometimes be simply referred to as the XRD spectrum.

[0265] For example, in the case of a quartz glass substrate, the shape of the peak in the XRD spectrum is almost symmetric about the left and right. On the other hand, in an In-Ga-Zn oxide film having a crystal structure, the shape of the peak in the XRD spectrum is asymmetric about the left and right. The fact that the shape of the peak in the XRD spectrum is asymmetric about the left and right indicates the presence of crystals in the film or the substrate. In other words, if the shape of the peak in the XRD spectrum is not symmetric about the left and right, it cannot be said that the film or the substrate is in an amorphous state.

[0266] Also, the crystal structure of the film or substrate can be evaluated by the diffraction pattern (also referred to as the nano-beam electron diffraction pattern) observed by the nano-beam electron diffraction (NBED) method. For example, in the diffraction pattern of a quartz glass substrate, a halo is observed, and it can be confirmed that the quartz glass is in an amorphous state. Also, in the diffraction pattern of an In-Ga-Zn oxide film formed at room temperature, a spot-like pattern is observed instead of a halo. Therefore, it is estimated that the In-Ga-Zn oxide film formed at room temperature is in an intermediate state that is neither single crystal nor polycrystal nor amorphous, and it cannot be concluded that it is in an amorphous state.

[0267] It should be noted that oxide semiconductors may be classified differently from those described above when considering their structure. For example, oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the aforementioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors also include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0268] Here, we will explain the details of the CAAC-OS, nc-OS, and a-like OS mentioned above.

[0269] < <caac-os>> CAAC-OS is an oxide semiconductor having multiple crystalline regions, the c-axis of which is oriented in a specific direction. This specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If we consider the atomic arrangement as a lattice arrangement, then a crystalline region is also a region with a aligned lattice arrangement. Furthermore, CAAC-OS has regions where multiple crystalline regions are connected in the ab-plane direction, and these regions may exhibit distortion. Distortion refers to a point in the connected region where the orientation of the lattice arrangement changes between a region with a aligned lattice arrangement and another region with a aligned lattice arrangement. In short, CAAC-OS is an oxide semiconductor that is c-axis oriented and does not exhibit clear orientation in the ab-plane direction.

[0270] Each of the above-mentioned crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of that crystalline region will be less than 10 nm. When a crystalline region is composed of many minute crystals, the maximum diameter of that crystalline region may be around several tens of nm.

[0271] Furthermore, in In-Ga-Zn oxides, CAAC-OS tends to have a layered crystalline structure (also called a layered structure) consisting of layers containing indium (In) and oxygen (hereinafter referred to as the In layer) and layers containing gallium (Ga), zinc (Zn), and oxygen (hereinafter referred to as the (Ga,Zn) layer). Note that indium and gallium are mutually substitutable. Therefore, the (Ga,Zn) layer may contain indium. Also, the In layer may contain gallium. Also, the In layer may contain zinc. This layered structure can be observed, for example, as a lattice image in high-resolution TEM (Transmission Electron Microscope) images.

[0272] When structural analysis of a CAAC-OS film is performed using an XRD instrument, for example, out-of-plane XRD measurements using θ / 2θ scanning show a peak indicating c-axis orientation at 2θ = 31° or nearby. Note that the position of the c-axis orientation peak (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0273] Furthermore, for example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film. These spots are observed at point-symmetric positions with respect to the incident electron beam spot (also called the direct spot) that passed through the sample.

[0274] When the crystal region is observed from the specific direction described above, the lattice arrangement within that crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the strain may have lattice arrangements such as pentagons or heptagons. Moreover, in CAAC-OS, clear grain boundaries cannot be observed even near the strain. In other words, it can be seen that the formation of grain boundaries is suppressed by the strain in the lattice arrangement. This is thought to be because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction, and the bond distance between atoms changes due to the substitution of metal atoms.

[0275] Furthermore, a crystal structure in which clear grain boundaries can be observed is called a polycrystalline material. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in transistor on-current and field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries cannot be observed, is one of the crystalline oxides with a suitable crystal structure for the semiconductor layer of a transistor. In addition, a structure containing Zn is preferred for the composition of CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are preferred because they can suppress the generation of grain boundaries more effectively than In oxide.

[0276] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. Furthermore, since the crystallinity of oxide semiconductors can decrease due to the inclusion of impurities and the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. In addition, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in transistors with metal oxide in the channel formation region (sometimes called OS transistors) allows for greater flexibility in the manufacturing process.

[0277] < <nc-os>> nc-OS exhibits periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). In other words, nc-OS contains minute crystals. These minute crystals are also called nanocrystals because their size is, for example, between 1 nm and 10 nm, particularly between 1 nm and 3 nm. Furthermore, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductors. For example, when structural analysis of an nc-OS film is performed using an XRD instrument, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the nanocrystals (e.g., 50 nm or larger), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystal (for example, 1 nm to 30 nm), an electron diffraction pattern may be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0278] <<a-like OS> > a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS. Also, a-like OS has a higher hydrogen concentration in the film compared to nc-OS and CAAC-OS.

[0279] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention may include two or more of the following: amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, nc-OS, and CAAC-OS.

[0280] <<Transistor containing an oxide semiconductor>> Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0281] By using the above-mentioned oxide semiconductor in transistors, it is possible to realize transistors with high field-effect mobility. Furthermore, it is possible to realize highly reliable transistors.

[0282] It is preferable to use an oxide semiconductor with a low carrier concentration for the transistor. For example, the carrier concentration of an oxide semiconductor is 1 × 10⁻⁶. 17 cm -3 The following is preferably 1 × 10 15 cm -3 More preferably 1 × 10 13 cm -3 More preferably 1 × 10 11 cm -3 More preferably 1 × 10 10 cm -3 It is less than 1 × 10 -9 cm -3 This concludes the explanation. Furthermore, when lowering the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film should be lowered to reduce the defect level density. In this specification, a low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that oxide semiconductors with low carrier concentrations are sometimes referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors.

[0283] Furthermore, oxide semiconductor films that are high-purity intrinsic or substantially high-purity intrinsic may have a low trap level density due to their low defect level density.

[0284] Furthermore, charges trapped in the trap levels of oxide semiconductors can take a long time to disappear, sometimes behaving like fixed charges. Therefore, transistors in which channel formation regions are formed in oxide semiconductors with a high trap level density may exhibit unstable electrical properties.

[0285] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Further, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc. Note that the impurities in the oxide semiconductor refer to, for example, components other than the main components constituting the oxide semiconductor. For example, an element with a concentration less than 0.1 atomic% can be said to be an impurity. Also, the main component in the oxide semiconductor refers to, for example, an element contained in the oxide semiconductor at 1 atomic% or more.

[0286] <<Impurities>> Here, the influence of each impurity in the oxide semiconductor will be described.

[0287] In the oxide semiconductor, when silicon or carbon, which is one of the Group 14 elements, is contained, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) is set to 2×10 18 atoms / cm 3 or less, preferably 2×10 17 atoms / cm 3 or less.

[0288] Also, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normal-on characteristics. For this reason, the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0289] Furthermore, in oxide semiconductors, the presence of nitrogen generates electrons, which act as carriers, increasing the carrier concentration and making it easier for the semiconductor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Alternatively, the presence of nitrogen in oxide semiconductors can lead to the formation of trap levels. As a result, the electrical properties of the transistor may become unstable. For this reason, the nitrogen concentration in oxide semiconductors obtained by SIMS should be set to 5 × 10⁻⁶. 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 Do the following:

[0290] Furthermore, hydrogen contained in oxide semiconductors can react with oxygen bonded to metal atoms to form water, potentially creating oxygen vacancies. Hydrogen can then fill these vacancies, generating electrons as carriers. Additionally, some of the hydrogen can combine with oxygen bonded to metal atoms to generate electrons. Therefore, transistors using oxide semiconductors containing hydrogen tend to exhibit normally-on characteristics. For this reason, it is preferable to reduce the hydrogen content in oxide semiconductors as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor obtained by SIMS should be 1 × 10⁻⁶. 20 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Make it less than.

[0291] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0292] <Modified version of transistor 200> Below, we will describe a configuration example different from the transistor 200 mentioned above, using Figures 6A to 7B.

[0293] [Transistor 200A] Figure 6A is a cross-sectional view of a semiconductor device having transistor 200A. Transistor 200A shown in Figure 6A is a modified example of transistor 200 shown in Figure 5B.

[0294] The transistor 200A shown in Figure 6A differs from the transistor 200 shown in Figure 5B in that the oxide 230 has a two-layer stacked structure of oxide 230a and oxide 230b.

[0295] Oxide 230a functions as either a source region or a drain region. Oxide 230b has a channel-forming region and a region 230bc that functions as the other of the source region and drain region.

[0296] When heat treatment is performed with the conductor 242b and oxide 230b in contact, the sheet resistance of the oxide 230b near the conductor 242b may decrease. Also, the carrier concentration may increase. Therefore, the oxide 230b near the conductor 242b can be self-aligned to become low-resistance, forming region 230bc.

[0297] [Transistor 200B] Figure 6B is a cross-sectional view of a semiconductor device having transistor 200B, and Figure 6C is an enlarged cross-sectional view of the region including the oxide 230b and its surrounding area of ​​transistor 200B. Transistor 200B shown in Figures 6B and 6C is a modified example of transistor 200 shown in Figure 5B.

[0298] The transistor 200B shown in Figure 6B differs from the transistor 200 shown in Figure 5B in the shape of the oxide 230 and the conductor 242b. Specifically, the transistor 200B shown in Figure 6B differs from the transistor 200 shown in Figure 5B in that the sides of the oxide 230 and the conductor 242b have a tapered shape.

[0299] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface. For example, it refers to a shape having a region where the angle between the inclined side surface and the substrate surface (also called the taper angle) is less than 90 degrees. Note that the side surface of the structure and the substrate surface do not necessarily have to be perfectly flat; they may be substantially planar with a fine curvature, or substantially planar with fine irregularities.

[0300] As shown in Figure 6C, in a cross-sectional view of transistor 200B, the side surface of the oxide 230 on the opening side (insulator 275a side) may have a tapered shape with a taper angle θ. Here, the taper angle θ is the angle between the side surface of the oxide 230 on the opening side and the substrate surface. However, one of the two sides extending from the vertex of the taper angle θ is not limited to the substrate surface, but may be the upper surface of the insulator 216 or the lower surface of the oxide 230a, etc. In other words, the taper angle θ may be the angle between the side surface of the oxide 230 and the upper surface of the insulator 216 or the lower surface of the oxide 230a. In this case, the side surface of the oxide 230 on the insulator 275b side also has a tapered shape with a taper angle θ.

[0301] Furthermore, the closer the taper angle θ is to 90 degrees, the deeper the conductor 260 can be positioned to reach the opening in the oxide 230. Therefore, the area of ​​the oxide 230 overlapping with the conductor 260 can be increased, stabilizing the electrical characteristics of the transistor. Additionally, the occupied area of ​​the transistor 200B can be reduced. For example, the taper angle θ may be 80 degrees or more, 85 degrees or more, or 87 degrees or more, and less than 90 degrees.

[0302] In the above configuration, the upper surface of the oxide 230 has a hollow circular shape. In other words, in the above configuration, the oxide 230 has a hollow frustoconical shape. That is, the area of ​​the upper base surface (the surface on the conductor 242b side) of the frustoconical shape of the oxide 230 is smaller than the area of ​​the lower base surface (the surface on the insulator 216 side) of the frustoconical shape of the oxide 230.

[0303] In a cross-sectional view of a transistor, if the side surface of the hollow portion of the oxide 230 has a tapered shape, the channel width in the transistor will not be the same value in all regions. That is, the channel width of the transistor may not be fixed to a single value. Therefore, in this specification, the channel width is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0304] Similar to oxide 230, the side surface of the conductor 242b on the opening side (insulator 275a side) and the side surface of the conductor 242b on the outer side (insulator 275b side) have a tapered shape. The angle between the opening side surface of conductor 242b and the substrate surface, and the angle between the outer side surface of conductor 242b and the substrate surface, coincide with or approximately coincide with the taper angle θ. However, depending on the combination of materials used for oxide 230 and conductor 242b, or the processing conditions of oxide 230 and conductor 242b, the angle between the opening side surface of conductor 242b and the substrate surface, and the angle between the outer side surface of conductor 242b and the substrate surface may not coincide with the taper angle θ.

[0305] Furthermore, the conductor 242b has a hollow frustoconical shape. In other words, the area of ​​the upper base surface (the surface on the conductor 246 side) of the frustoconical shape of the conductor 242b is smaller than the area of ​​the lower base surface (the surface on the oxide 230 side) of the frustoconical shape of the conductor 242b.

[0306] [Transistor 200C] Figure 7A is a cross-sectional view of a semiconductor device having transistor 200C. Transistor 200C shown in Figure 7A is a modified example of transistor 200 shown in Figure 5B.

[0307] The transistor 200C shown in Figure 7A differs from the transistor 200 shown in Figure 5B in that it has insulators 254a and 254b.

[0308] The insulator 254a is located between the insulator 250a and the conductor 260. Specifically, the insulator 254a is provided in a recess of the insulator 250a. It is also provided in contact with a part of the side surface and the bottom surface of the conductor 260. In this configuration, it can be said that the insulator 254a has a recess. Furthermore, the uppermost part of the insulator 254a is at the same or approximately the same height as the uppermost part of the insulator 275a and the uppermost part of the insulator 250a.

[0309] The insulator 254a functions as part of the gate insulator. Preferably, a barrier insulating film against hydrogen is used as the insulator 254a. This prevents impurities such as hydrogen contained in the conductor 260 from diffusing into the oxide 230b. The insulator 254a can be any insulator that can be used for the insulator 277 described above. For example, silicon nitride deposited by the PEALD method can be used as the insulator 254a. In this case, the insulator 254a contains at least nitrogen and silicon.

[0310] Furthermore, the insulator 254a may also have barrier properties against oxygen. This can suppress the diffusion of oxygen contained in the insulator 250a into the conductor 260.

[0311] Furthermore, the insulator 254a, along with the insulator 275a, the insulator 250a, and the conductor 260, must be provided in an opening formed in the oxide 230 or the like. In order to miniaturize the transistor, it is preferable that the film thickness of the insulator 254a be thin. The film thickness of the insulator 254a is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, it is sufficient that the insulator 254a has a region with the above-mentioned film thickness in at least a part of it. Also, it is preferable that the film thickness of the insulator 254a is thinner than the film thickness of the insulator 250a. In this case, it is sufficient that the insulator 254a has a region with a film thickness thinner than the insulator 250a in at least a part of it.

[0312] In a top view, the insulator 254b is positioned outside the oxide 230 and conductor 242b (on the side of insulator 275b). Furthermore, the insulator 254b is located between insulator 250b and insulator 274. Specifically, the insulator 254b is provided in contact with the top surface of insulator 250b. It is also provided in contact with the side and bottom surfaces of insulator 274.

[0313] Insulators 254a and 254b are formed in the same process. Therefore, insulators 254a and 254b are made of the same material. In addition, insulators 254a and 254b have the same film thickness.

[0314] In one embodiment of the present invention, an insulator may be provided so as to be in contact with the side surface of the conductor 262. Furthermore, an insulator may be provided below the conductor 242a and the insulator 216.

[0315] Figure 7B is a cross-sectional view of a semiconductor device having transistor 200C. The semiconductor device shown in Figure 7B differs from the semiconductor device shown in Figure 7A in that it has insulators 247 and 212.

[0316] The insulator 247 is located between the conductor 262 and the insulators 277, 278 (not shown in Figure 7B), and 285. Furthermore, the insulator 247 is provided so as to be in contact with the side surface of the conductor 262.

[0317] The insulator 247 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the conductor 262. This suppresses the diffusion of impurities such as hydrogen contained in the insulator 285 into the oxide 230b via the conductor 262. As the insulator 247, any insulator that can be used for the insulator 277 described above may be used. For example, silicon nitride deposited by the PEALD method may be used as the insulator 247. In this case, the insulator 247 has at least nitrogen and silicon.

[0318] In addition, an insulator made of the same material as the insulator 247 may be formed to cover the side surface of the region of the conductor 260 that is exposed from the insulator 276.

[0319] The insulator 212 is provided on a substrate (not shown) and is located below the insulator 216 and the conductor 242a.

[0320] The insulator 212 functions as an interlayer film. Preferably, the insulator 212 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200. As the insulator 212, any insulator that can be used for the insulator 277 described above may be used. For example, it is preferable to use a silicon-containing nitride such as silicon nitride or silicon nitride oxide as the insulator 212. Specifically, silicon nitride deposited by sputtering may be used as the insulator 212. By depositing the insulator 212 by sputtering, a high-density silicon nitride can be formed. Alternatively, as the insulator 212, silicon nitride deposited by PEALD or CVD may be laminated on top of the silicon nitride deposited by sputtering.

[0321] The above describes examples of semiconductor device configurations and examples of transistor configurations found in semiconductor devices.

[0322] <Method for fabricating semiconductor devices> Next, a method for manufacturing a semiconductor device, which is one embodiment of the present invention as shown in Figures 5A to 5C, will be explained using Figures 8A to 16B.

[0323] Figures A and C show top views. Figure B shows a cross-sectional view corresponding to the area indicated by the dashed line A1-A2 in Figure A. Figure 12B1 shows a cross-sectional view corresponding to the area indicated by the dashed line A1-A2 in Figure 12A. Figure 12B2 shows a cross-sectional view corresponding to the area indicated by the dashed line A3-A4 in Figure 12A. Figure D shows a cross-sectional view corresponding to the area indicated by the dashed line A1-A2 in Figure C. Note that some elements have been omitted from the top views A and C in Figures for clarity.

[0324] In the following, insulating materials for forming an insulator, conductive materials for forming a conductor, or semiconductor materials for forming a semiconductor can be deposited using sputtering, CVD, MBE, PLD, ALD, or other appropriate methods.

[0325] Sputtering methods include RF sputtering, which uses a high-frequency power supply, and DC sputtering, which uses a direct current power supply. DC sputtering further includes pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner. RF sputtering is mainly used for depositing insulating films, while DC sputtering is mainly used for depositing conductive metal films. Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0326] Furthermore, CVD methods can be classified into plasma CVD (PECVD), which utilizes plasma; thermal CVD (TCVD), which utilizes heat; and photo CVD (Photo CVD), which utilizes light. They can also be further divided into metal CVD (MCVD) or metal-organic CVD (MOCVD) depending on the source gas used.

[0327] Plasma CVD (Chemical Vapor Deposition) allows for the production of high-quality films at relatively low temperatures. Thermal CVD, on the other hand, does not use plasma, thus minimizing plasma damage to the workpiece. For example, wiring, electrodes, and elements (such as transistors and capacitive elements) contained in semiconductor devices can be charged up by receiving charge from the plasma. In this case, the accumulated charge can destroy the wiring, electrodes, and elements contained in the semiconductor device. In contrast, thermal CVD, which does not use plasma, does not cause such plasma damage, thus increasing the yield of semiconductor devices. Furthermore, because thermal CVD does not cause plasma damage during film formation, films with fewer defects can be obtained.

[0328] Furthermore, ALD methods that can be used include thermal ALD, which carries out the reaction of the precursor and reactant using only thermal energy, and PEALD, which uses plasma-excited reactants.

[0329] CVD and ALD methods differ from sputtering, where particles emitted from a target or other source are deposited. Therefore, they are less affected by the shape of the workpiece and provide good step-level coating. In particular, the ALD method is suitable for coating the surface of openings with high aspect ratios due to its excellent step-level coating and uniform thickness. However, because the ALD method has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other deposition methods that have a faster deposition rate, such as the CVD method.

[0330] Furthermore, the CVD method allows for the deposition of films with any desired composition by changing the flow rate ratio of the raw material gases. For example, in the CVD method, films with continuously changing compositions can be deposited by changing the flow rate ratio of the raw material gases while the film is being deposited. When depositing films while changing the flow rate ratio of the raw material gases, the time required for film deposition can be shortened compared to depositing films using multiple deposition chambers, because time spent on transport or pressure adjustment is eliminated. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0331] Furthermore, the ALD method allows for the deposition of films of any composition by simultaneously introducing multiple different types of precursors. Alternatively, when introducing multiple different types of precursors, films of any composition can be deposited by controlling the number of cycles for each precursor.

[0332] First, a substrate (not shown) is prepared, and an insulator 216 is deposited on the substrate. It is preferable to deposit the insulator 216 using a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 216 can be reduced. However, the deposition of the insulator 216 is not limited to the sputtering method; CVD, MBE, PLD, or ALD methods may be used as appropriate.

[0333] In this embodiment, silicon oxide is deposited as the insulator 216 using a silicon target in an atmosphere containing oxygen gas by pulsed DC sputtering. By using pulsed DC sputtering, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0334] Furthermore, when providing the insulator 212 shown in Figure 7B, it is preferable to continuously deposit the insulator 212 and the insulator 216 without exposure to the atmosphere. For example, a multi-chamber type deposition apparatus can be used. This allows for the deposition of the insulator 212 and the insulator 216 with reduced hydrogen content in the film, and further reduces the incorporation of hydrogen into the film between each deposition process.

[0335] Next, an opening is formed in the insulator 216. This opening includes, for example, grooves and slits. The term "opening" may also refer to the area where the opening is formed. While wet etching may be used to form the opening, dry etching is preferable for microfabrication.

[0336] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one electrode of the parallel plate electrodes. Alternatively, it may be configured to apply multiple different high-frequency voltages to one electrode of the parallel plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. A dry etching apparatus having a high-density plasma source may be, for example, an inductively coupled plasma (ICP) etching apparatus.

[0337] Furthermore, it is preferable to provide an insulator that functions as an etching stopper film when etching the insulator 216 to form an opening, in contact with the lower surface of the insulator 216. For example, if silicon oxide or silicon oxynitride is used for the insulator 216 that forms the opening, the insulator may be silicon nitride, aluminum oxide, or hafnium oxide. For example, the insulator 212 shown in Figure 7B may be provided as the insulator. In other words, it is preferable that the insulator 212 has this function.

[0338] After the opening is formed, a conductive film that will become the conductor 242a1 is deposited. It is desirable that the conductive film contains a conductor that has the function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, or titanium nitride can be used. Alternatively, a laminated film can be formed of a conductor that has the function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film can be deposited using sputtering, CVD, MBE, PLD, or ALD methods.

[0339] In this embodiment, a titanium nitride film is formed as the conductive film that will become the conductor 242a1. By using such a metal nitride as the layer beneath the conductor 242a2, oxidation of the conductor 242a2 by the insulator 216 and the like can be suppressed. Furthermore, even if a highly diffusive metal such as copper is used as the conductor 242a2, it is possible to prevent the metal from diffusing out of the conductor 242a1.

[0340] Next, a conductive film to form the conductor 242a2 is deposited. This conductive film can be made of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film can be deposited using methods such as plating, sputtering, CVD, MBE, PLD, or ALD. In this embodiment, a tungsten film is deposited as the conductive film.

[0341] Next, by performing a CMP treatment, a portion of the conductive film that will become conductor 242a1 and the conductive film that will become conductor 242a2 is removed, exposing the insulator 216 (see Figures 8A and 8B). As a result, conductor 242a (conductor 242a1 and conductor 242a2) is formed only in the openings formed in the insulator 216, thereby forming conductor 242a. Note that a portion of the insulator 216 may be removed by this CMP treatment.

[0342] Next, oxide films 230A, 230B, and 230C are sequentially deposited on the insulator 216 and the conductor 242a (see Figures 8A and 8B). It is preferable to deposit oxide films 230A, 230B, and 230C continuously without exposing them to the atmosphere. By depositing the films without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmosphere from adhering to oxide films 230A, 230B, and 230C, and to keep the interfaces between oxide films 230A and 230B, and the interfaces between oxide films 230B and 230C, and the surrounding areas clean.

[0343] The oxide films 230A, 230B, and 230C can be deposited using sputtering, CVD, MBE, PLD, or ALD.

[0344] For example, when depositing oxide films 230A, 230B, and 230C by sputtering, oxygen or a mixture of oxygen and a noble gas is used as the sputtering gas. By increasing the proportion of oxygen in the sputtering gas, the excess oxygen in the deposited oxide film can be increased. Furthermore, when depositing the above oxide films by sputtering, targets such as the In-M-Zn oxide mentioned above can be used.

[0345] Furthermore, when depositing a nitrogen-added metal oxide film as oxide film 230A by sputtering, by including nitrogen gas in the sputtering gas during film formation, a nitrogen-added metal oxide film can be deposited even if the target does not contain nitrogen. When depositing a metal oxide film with nitrogen gas, a higher nitrogen flow rate ratio can increase the carrier mobility of the metal oxide film.

[0346] The nitrogen flow rate ratio can be appropriately set within a range of 10% to 100% to match the desired characteristics of oxide 230a and oxide 230c. In this case, for example, the sputtering gas can be a mixture of nitrogen gas and argon gas. Alternatively, the sputtering gas may be a mixture of nitrogen gas and oxygen gas, or a mixture of nitrogen gas, oxygen gas, and argon gas.

[0347] Furthermore, when using a target containing nitrogen, it is possible to configure the system so that nitrogen is not used as the sputtering gas, even when depositing a nitrogen-doped metal oxide film.

[0348] If the sputtering gas for the oxide film 230A contains oxygen gas, some of the oxygen contained in the sputtering gas may be supplied to the insulator 216. Therefore, the proportion of oxygen contained in the sputtering gas may be 70% or more, preferably 80% or more, and more preferably 100%.

[0349] The sputtering gas described above is preferably highly purified. For example, by using oxygen, nitrogen, or argon gas used as a sputtering gas that has been purified to a dew point of -40°C or lower, preferably -80°C or lower, more preferably -100°C or lower, and more preferably -120°C or lower, it is possible to prevent moisture and other substances from being incorporated into the metal oxide film as much as possible.

[0350] When oxide film 230B is formed by sputtering, if the proportion of oxygen in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably between 70% and 100%, an oxygen-rich oxide semiconductor is formed. Transistors using oxygen-rich oxide semiconductors in the channel formation region can achieve relatively high reliability. However, one aspect of the present invention is not limited to this. When oxide film 230B is formed by sputtering, if the proportion of oxygen in the sputtering gas is set to 1% to 30%, preferably between 5% and 20%, an oxygen-deficient oxide semiconductor is formed. Transistors using oxygen-deficient oxide semiconductors in the channel formation region can achieve relatively high field-effect mobility. Furthermore, the crystallinity of the oxide film can be improved by performing film formation while heating the substrate.

[0351] The method for forming oxide film 230C can be based on the method for forming oxide film 230A.

[0352] Furthermore, it is preferable to deposit oxide films 230A, 230B, and 230C by sputtering without exposure to the atmosphere. For example, a multi-chamber deposition apparatus can be used. This reduces the incorporation of hydrogen into the films between each deposition step for oxide films 230A, 230B, and 230C.

[0353] Furthermore, when depositing metal oxide films with nitrogen added as oxide film 230A and oxide film 230C by sputtering, and depositing a metal oxide film as oxide film 230B by sputtering, oxide film 230B is deposited by switching the type of gas introduced into the sputtering apparatus after oxide film 230A is deposited, i.e., by stopping the introduction of nitrogen. After oxide film 230B is deposited, oxide film 230C is deposited by switching the type of gas introduced into the sputtering apparatus, i.e., by introducing nitrogen. This makes it possible to continuously deposit oxide film 230A, oxide film 230B, and oxide film 230C, resulting in excellent mass productivity.

[0354] The oxide films 230A, 230B, and 230C may be formed using the ALD method. Using the ALD method allows for the formation of films with uniform thickness. Furthermore, using the PEALD method allows for the formation of oxide films 230A, 230B, and 230C at lower temperatures compared to the thermal ALD method.

[0355] In this embodiment, nitrogen-added metal oxide films are deposited as oxide films 230A and 230C by sputtering. Furthermore, oxide film 230B is deposited by sputtering using an oxide target with an In:Ga:Zn ratio of 4:2:4.1, an In:Ga:Zn ratio of 1:1:1, an In:Ga:Zn ratio of 1:1:1.2, or an In:Ga:Zn ratio of 1:1:2. Note that each oxide film may be formed according to the desired properties of oxide films 230a, 230b, and 230c by appropriately selecting the deposition conditions and atomic ratios.

[0356] Next, it is preferable to perform a heat treatment. The heat treatment should be performed within a temperature range in which oxide films 230A, 230B, and 230C do not undergo polycrystallization, and should be performed between 250°C and 650°C, preferably between 400°C and 600°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas should be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen.

[0357] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from the incorporation of water or other substances into the oxide film 230A, oxide film 230B, and oxide film 230C.

[0358] In this embodiment, the heat treatment involves a nitrogen gas to oxygen gas flow rate ratio of 4:1 and a treatment at a temperature of 400°C for 1 hour. This heat treatment including oxygen gas can reduce impurities such as carbon, water, and hydrogen in the oxide film 230B. By reducing impurities in the film in this way, the crystallinity of the oxide film 230B can be improved, resulting in a denser, more compact structure. This increases the crystalline region in the oxide film 230B and reduces in-plane variation of the crystalline region within the oxide film 230B. Therefore, in-plane variation in the electrical characteristics of the transistor 200 can be reduced.

[0359] Furthermore, by performing a heat treatment, the hydrogen concentrations in the insulator 216 and the oxide film 230B can be reduced. In particular, the oxide film 230B functions as a channel formation region for the transistor 200. Therefore, a transistor 200 having an oxide film 230B with reduced hydrogen concentration is preferable because it has good reliability.

[0360] Next, a conductive film 242B is deposited on the oxide film 230C (see Figures 8A and 8B). The conductive film 242B can be deposited using sputtering, CVD, MBE, PLD, or ALD. For example, a tantalum nitride film can be deposited as the conductive film 242B using sputtering. Before depositing the conductive film 242B, a heat treatment may be performed. This heat treatment may be carried out under reduced pressure, and the conductive film 242B may be deposited continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230C can be removed, and the moisture and hydrogen concentrations in the oxide film 230A, oxide film 230B, and oxide film 230C can be further reduced. The temperature of the heat treatment is preferably between 100°C and 400°C. In this embodiment, the temperature of the heat treatment is set to 200°C.

[0361] Next, an insulating film 291A is deposited on the conductive film 242B (see Figures 8A and 8B). The insulating film 291A can be deposited using sputtering, CVD, MBE, PLD, or ALD. It is preferable to use an insulating film 291A that has the function of suppressing oxygen permeation. For example, an aluminum oxide film or a silicon nitride film can be deposited as the insulating film 291A by sputtering.

[0362] Furthermore, it is preferable to deposit the conductive film 242B and the insulating film 291A by sputtering without exposure to the atmosphere. For example, a multi-chamber deposition apparatus may be used. This reduces the amount of hydrogen in the films when depositing the conductive film 242B and the insulating film 291A, and also reduces the amount of hydrogen introduced into the films between each deposition process. In addition, if a hard mask is provided on the insulating film 291A, the hard mask film may also be deposited continuously without exposure to the atmosphere.

[0363] Next, using lithography, oxide films 230A, 230B, 230C, conductive film 242B, and insulating film 291A are processed into a hollow cylindrical shape to form oxide 230 (oxide 230a, oxide 230b, and oxide 230c), conductor 242b, and insulator 291. Here, oxide 230a, oxide 230b, oxide 230c, conductor 242b, and insulator 291 are formed so that at least a portion overlaps with conductor 242a. The above processing can be performed using either dry etching or wet etching.

[0364] In lithography, the resist is first exposed through a mask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Then, the conductor, semiconductor, or insulator can be processed into a desired shape by etching through the resist mask. For example, the resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV light, etc. Alternatively, immersion technology can be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. In addition, an electron beam or ion beam may be used instead of the aforementioned light. When using an electron beam or ion beam, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0365] Furthermore, a hard mask made of an insulator or conductor may be used beneath the resist mask. When using a hard mask, an insulating film or conductive film that serves as the hard mask material is formed on the conductive film 242B, a resist mask is formed on top of it, and a hard mask of the desired shape can be formed by etching the hard mask material. Etching of the conductive film 242B, etc., may be performed after removing the resist mask, or it may be performed while the resist mask remains. In the latter case, the resist mask may disappear during etching. The hard mask may also be removed by etching after etching of the conductive film 242B, etc. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not always necessary to remove the hard mask. In this embodiment, an insulator 291 is used as the hard mask.

[0366] In the following section, an example of a method for forming a hollow cylindrical oxide 230 (oxide 230a, oxide 230b, and oxide 230c), a conductor 242b, and an insulator 291 using lithography will be described.

[0367] First, a resist mask 292 is formed on the insulating film 291A (see Figures 8A and 8B). The resist mask 292 is provided in a region where at least a portion of the resist mask 292 overlaps with the conductor 242a.

[0368] Although the top surface of the resist mask 292 is circular in this example, the present invention is not limited to this. For example, the top surface may be elliptical, triangular, or quadrilateral. Furthermore, if the top surface is polygonal, the corners of the polygon may be rounded.

[0369] The resist mask 292 can be formed, for example, by exposing the resist through the mask and then removing or leaving the exposed area using a developer. Alternatively, the resist mask 292 may be shrunk by isotropic etching with oxygen plasma. Shrinking the resist mask is sometimes called resist slimming or resist trimming. By shrinking the resist mask 292, the resist mask 292 can be miniaturized.

[0370] Alternatively, the resist mask 292 may be formed, for example, by exposing the resist through a mask on which a line pattern can be formed, exposing the resist again through the mask rotated 90 degrees on the Z axis, and removing or leaving the exposed area using a developer. This process results in the upper surface of the resist mask 292 having a rounded corner or a circular shape.

[0371] Furthermore, for forming the resist mask 292, it is preferable to use double patterning techniques such as LELE and SADP, quadruple patterning techniques such as SAQP, and multi-patterning techniques such as octave patterning. For example, the resist mask 292 may be formed by using a multi-patterning technique to form a resist mask with a line pattern extending in the X direction, and then using a multi-patterning technique to process the resist mask with a line pattern extending in the Y direction. As a result of this processing, the upper surface of the resist mask 292 will have a shape with rounded corners or a circular shape.

[0372] Next, an insulating film 293A is deposited on the resist mask 292 (see Figures 8A and 8B). The insulating film 293A can be deposited using sputtering, CVD, MBE, PLD, or ALD. The thickness of the insulating film 293A corresponds to the width H1 shown in Figure 5D. Therefore, the thickness of the insulating film 293A can be set appropriately according to the design of the transistor 200.

[0373] Next, the insulating film 293A is anisotropically etched to form an insulator 293 (see Figures 8C and 8D). For anisotropic etching of the insulating film 293A, for example, a dry etching method can be used. By anisotropically etching the insulating film 293A, an insulator 293 is provided on the side surface of the resist mask 292. In other words, the insulator 293 can be referred to as a sidewall.

[0374] Next, the resist mask 292 is removed (see Figures 8C and 8D). By removing the resist mask 292, the insulator 293 remains on the insulating film 291A. The shape of the top surface of the opening in the insulator 293 corresponds to the shape of the top surface of the resist mask 292. For example, if the top surface of the resist mask 292 is circular, the top surface of the insulator 293 will be hollow cylindrical, as shown in Figure 8C. Also, if the top surface of the resist mask 292 is elliptical as described above, the top surface of the insulator 293 will be hollow elliptical. Furthermore, if the top surface of the resist mask 292 is polygonal with rounded corners as described above, the top surface of the insulator 293 will be hollow polygonal with rounded corners.

[0375] Next, using the insulator 293 as a hard mask, a portion of the insulating film 291A, a portion of the conductive film 242B, a portion of the oxide film 230C, a portion of the oxide film 230B, and a portion of the oxide film 230A are processed until the upper surfaces of the insulator 216 and the conductor 242a are exposed (see Figures 9A and 9B). The above processing can be performed using either a dry etching method or a wet etching method. Dry etching is suitable for microfabrication. Furthermore, the processing of the insulating film 291A, the conductive film 242B, the oxide film 230C, the oxide film 230B, and the oxide film 230A may be carried out under different conditions.

[0376] As a result of the above processing, insulator 291, conductor 242b, oxide 230c, oxide 230b, and oxide 230a are formed, whose upper surface shape is the same as or approximately the same as the upper surface shape of insulator 293 (see Figures 9A and 9B). In other words, the ends of insulator 291, conductor 242b, oxide 230c, oxide 230b, and oxide 230a coincide or approximately coincide. In addition, oxide 230 (oxide 230a, oxide 230b, and oxide 230c), conductor 242b, and insulator 291 each have a hollow cylindrical shape. As mentioned above, the upper surface shapes of insulator 291, oxide 230, conductor 242b, and insulator 291 correspond to the upper surface shape of resist mask 292. Therefore, the above hollow cylindrical shape can be appropriately rephrased to match the upper surface shape of resist mask 292.

[0377] The above is an example of a method for forming a hollow cylindrical oxide 230 (oxide 230a, oxide 230b, and oxide 230c), a conductor 242b, and an insulator 291 using lithography.

[0378] Furthermore, it is preferable that the sides of the oxide 230 and the conductor 242b be perpendicular to the upper surface of the insulator 216. This configuration makes it possible to reduce the area and increase the density when providing multiple transistors 200.

[0379] However, the configuration is not limited to the above, and as shown in Figures 6B and 6C, the cross-sections of the oxide 230 and the conductor 242b may be tapered. By making the cross-section tapered, the coverage of the insulating film that will become the insulator 275a in subsequent processes is improved, and defects such as porosity can be reduced.

[0380] Next, remove the insulator 293 (see Figures 9C and 9D).

[0381] During the processes up to this point, impurities may adhere to the sides of oxides 230a, 230b, 230c, conductor 242b, and insulator 291, or diffuse into their interiors. A process to remove such impurities may be performed. Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.

[0382] In order to remove impurities and other contaminants adhering to the surface of oxide 230b during the etching process described above, a cleaning treatment is performed. Cleaning methods include wet cleaning using a cleaning solution (which can also be called wet etching), plasma treatment using plasma, and cleaning by heat treatment. These cleaning methods may be combined as appropriate.

[0383] Wet cleaning may be performed using aqueous solutions of ammonia water, oxalic acid, phosphoric acid, or hydrofluoric acid diluted with carbonated water or distilled water, or distilled water or carbonated water. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, distilled water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0384] In this specification, an aqueous solution obtained by diluting hydrofluoric acid with pure water is sometimes referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting ammonia water with pure water is sometimes referred to as diluted ammonia water. The concentration and temperature of the aqueous solution may be adjusted as appropriate depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water should be 0.01% to 5%, preferably 0.1% to 0.5%. The hydrogen fluoride concentration of the diluted hydrofluoric acid should be 0.01 ppm to 100 ppm, preferably 0.1 ppm to 10 ppm.

[0385] Furthermore, it is preferable to use a frequency of 200 kHz or higher, preferably 900 kHz or higher, for ultrasonic cleaning. Using this frequency can reduce damage to oxides such as 230b.

[0386] Furthermore, the above cleaning process may be performed multiple times, and the cleaning solution may be changed each time. For example, the first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and the second cleaning process may be performed using pure water or carbonated water.

[0387] Heat treatment may be performed after the etching or cleaning described above. The heat treatment should be performed at a temperature of 100°C to 450°C, preferably 350°C to 400°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This allows oxygen to be supplied to oxide 230a, oxide 230b, and oxide 230c, thereby reducing oxygen deficiency. Furthermore, such heat treatment can improve the crystallinity of oxide 230b. The heat treatment may also be performed under reduced pressure. Alternatively, after heat treatment in an oxygen atmosphere, continuous heat treatment in a nitrogen atmosphere may be performed without exposure to the atmosphere.

[0388] The above cleaning and heating treatments may be performed before removing the insulator 293.

[0389] Next, insulating film 275A is deposited on insulator 216, conductor 242a, and insulator 291 (see Figures 9C and 9D). In other words, insulating film 275A is deposited over oxide 230a, oxide 230b, oxide 230c, conductor 242b, and insulator 291. The insulating film 275A can be deposited using sputtering, CVD, MBE, PLD, or ALD.

[0390] The insulating film 275A is preferably deposited using the ALD method. As mentioned above, it is preferable to deposit the insulating film 275A with a thin film thickness, and it is necessary to minimize variations in film thickness. In contrast, the ALD method is a film deposition method that alternately introduces a precursor and a reactant (e.g., an oxidizing agent), and the film thickness can be adjusted by the number of times this cycle is repeated, thus enabling precise film thickness adjustment. Furthermore, as shown in Figures 9C and 9D, the insulating film 275A needs to be deposited with good coverage on the sides of the openings formed in the oxide 230, conductor 242b, and insulator 291, as well as on the upper surfaces of the conductor 242a and insulator 216. In particular, it is preferable to deposit the film with good coverage on the sides of the oxide 230 and the sides of the conductor 242b. Since the ALD method can deposit layers of atoms one by one on the bottom and sides of the openings, the insulating film 275A can be deposited with good coverage on the openings.

[0391] Furthermore, when the insulating film 275A is deposited by the ALD method, ozone (O3), oxygen (O2), water (H2O), etc., can be used as oxidizing agents. By using hydrogen-free oxidizing agents such as ozone (O3) and oxygen (O2), the incorporation of hydrogen into the oxide 230 can be suppressed.

[0392] It is preferable to use an insulating film 275A that has the function of suppressing oxygen permeation. For example, an aluminum oxide film can be formed as the insulating film 275A using the ALD method. In this way, the oxide 230 (oxide 230a, oxide 230b, and oxide 230c) and the conductor 242b can be covered with an insulating film 275A that has the function of suppressing oxygen diffusion. This makes it possible to suppress the direct diffusion of oxygen from the insulator 274, etc., into the oxide 230 and the conductor 242b in a later process.

[0393] Next, microwave processing may be performed in an oxygen-containing atmosphere. Here, microwave processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example. In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0394] For microwave processing, it is preferable to use a microwave processing apparatus that has a power supply for generating a high-density plasma using microwaves. Here, the frequency of the microwave processing apparatus should be 300 MHz or more and 300 GHz or less, preferably 2.4 GHz or more and 2.5 GHz or less, for example, 2.45 GHz. By using a high-density plasma, a high density of oxygen radicals can be generated. The power of the power supply that applies microwaves to the microwave processing apparatus should be 1000 W or more and 10000 W or less, preferably 2000 W or more and 5000 W or less. The microwave processing apparatus may also have a power supply for applying RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by the high-density plasma can be efficiently guided into the oxide 230b.

[0395] Furthermore, the above microwave treatment is preferably performed under reduced pressure, with a pressure of 10 Pa to 1000 Pa, preferably 300 Pa to 700 Pa. The treatment temperature should be 750°C or lower, preferably 500°C or lower, for example, around 400°C. Alternatively, after oxygen plasma treatment, heat treatment may be performed continuously without exposure to the outside air. For example, the temperature should be 100°C to 750°C, preferably 300°C to 500°C.

[0396] Furthermore, for example, the above microwave treatment may be carried out using oxygen gas and argon gas. Here, the oxygen flow rate ratio (O2 / (O2+Ar)) should be greater than 0% and 100% or less, preferably greater than 0% and 50% or less, more preferably 10% to 40%, and even more preferably 10% to 30%. In this way, by performing microwave treatment in an oxygen-containing atmosphere, the carrier concentration in oxide 230b can be reduced. In addition, by preventing an excessive amount of oxygen from being introduced into the chamber during microwave treatment, it is possible to prevent an excessive reduction in the carrier concentration in oxide 230a and oxide 230c.

[0397] By performing microwave treatment in an oxygen-containing atmosphere, the oxygen gas can be plasmaized using microwaves or high-frequency waves such as RF, and this oxygen plasma can be applied to oxide 230b. At this time, microwaves or high-frequency waves such as RF can also be irradiated onto oxide 230b. In other words, oxide 230b can be subjected to microwaves, high-frequency waves such as RF, or oxygen plasma. The V of oxide 230b is affected by the action of plasma or microwaves. O H can be cleaved and hydrogen can be removed from oxide 230b. In other words, the V contained in oxide 230b O H can be reduced. Therefore, oxygen deficiency in oxide 230b, and V O This reduces H and lowers the carrier concentration. Furthermore, by supplying oxygen radicals generated in the oxygen plasma or oxygen contained in the insulator 275a to the oxygen vacancies formed in the oxide 230b, the oxygen vacancies in the oxide 230b can be further reduced, and the carrier concentration can be lowered.

[0398] Furthermore, an insulating film 275A, which has barrier properties against oxygen, is provided in contact with the side surface of the conductor 242b. This suppresses the formation of an oxide film on the side surface of the conductor 242b due to microwave processing.

[0399] Furthermore, since the film quality of the insulating film 275A can be improved, the reliability of the transistor 200 is enhanced.

[0400] Next, an insulating film 250A is deposited on the insulating film 275A (see Figures 9C and 9D). The insulating film 250A can be deposited using sputtering, CVD, MBE, PLD, or ALD. It is preferable to form the insulating film 250A using an insulator that has the function of suppressing oxygen diffusion. By using such a configuration, oxidation of the conductor 260 by oxygen contained in the oxide 230 can be suppressed. For example, a hafnium oxide film can be deposited as the insulating film 250A using the thermal ALD method.

[0401] Furthermore, the insulating film 250A may be made of a high-dielectric constant (high-k) material. In this case, it becomes possible to thin the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator. Therefore, the dielectric breakdown voltage of the gate insulator can be increased.

[0402] It is preferable to deposit insulating film 275A and insulating film 250A continuously without exposing them to the atmospheric environment. By depositing the films without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to insulating film 275A and insulating film 250A, and to keep the interface between insulating film 275A and insulating film 250A and its vicinity clean.

[0403] Next, an insulating film 274A is deposited on the insulating film 250A (see Figures 10A and 10B). The insulating film 274A can be deposited using sputtering, CVD, MBE, PLD, or ALD. For example, a silicon oxide film can be deposited as the insulating film 274A using the sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating film 274A can be reduced. Note that a heat treatment may be performed before depositing the insulating film 274A. In this embodiment, a silicon oxide film is deposited as the insulating film 274A using the CVD method.

[0404] Next, the insulating films 274A, 250A, and 275A are processed by CMP until the insulator 291 is exposed. Through this CMP process, insulators 274 and 274c are formed from the insulating film 274A, insulators 250a and 250b are formed from the insulating film 250A, and insulators 275a and 275b are formed from the insulating film 275A (see Figures 10C and 10D).

[0405] As described above, the oxide 230, conductor 242b, and insulator 291 each have a hollow cylindrical shape. In other words, the laminate of oxide 230, conductor 242b, and insulator 291 has a hollow cylindrical shape. Insulator 275a is provided in contact with the inner wall of the hollow portion of the laminate, a part of the upper surface of insulator 216, and at least a part of the upper surface of conductor 242a, insulator 250a is provided in contact with the inner wall of a recess formed in insulator 275a, and insulator 274c is provided so as to fill the recess formed in insulator 250a.

[0406] Furthermore, the insulator 275b is provided so as to be in contact with the outer side surface of the laminate and a portion of the upper surface of the insulator 216. Note that the insulator 275b may have a region in contact with the conductor 242a. In addition, the insulator 250b is provided so as to be in contact with the upper surface of the insulator 275b, and the insulator 274 is provided so as to be in contact with the upper surface of the insulator 250b.

[0407] The above CMP process may remove a portion of the upper surface of the insulator 291.

[0408] The upper surface of insulator 274 is at the same or approximately the same height as the upper surface of insulator 291 and the upper surface of insulator 274c. In addition, the uppermost heights of insulators 250a, 250b, 275a, and 275b are at the same or approximately the same height.

[0409] Next, the insulator 291 is removed to expose the upper surface of the conductor 242b (see Figures 11A and 11B). Dry etching or wet etching can be used to remove the insulator 291.

[0410] By removing the insulator 291, the upper surface of the conductor 242b can be exposed in a self-aligned manner. Therefore, the conductor 246 to be formed later can be reliably positioned to be in contact with the conductor 242b without the need for alignment. When removing the insulator 291 by etching, it is preferable to use etching conditions with a high selectivity ratio so that the insulator 274c is not removed by the etching. This allows the insulator 274c to remain after the insulator 291 has been removed.

[0411] Next, a conductive film that will become the conductor 246 and an insulating film that will become the insulator 277 are deposited in sequence. The deposition of the conductive film and the insulating film can be carried out using methods such as sputtering, CVD, MBE, PLD, or ALD.

[0412] Next, a portion of the conductive film that will become the conductor 246 and a portion of the insulating film that will become the insulator 277 are processed by lithography (see Figures 11C and 11D). This process allows the conductor 246 and the insulator 277 to be formed. The conductor 246 also has a convex shape in the region that overlaps with the conductor 242b. Although wet etching may be used for this process, dry etching is preferable for fine processing.

[0413] Next, an insulating film that will become an insulating film 278 is deposited on the insulator 277 and the insulator 274. The insulating film can be deposited using sputtering, CVD, MBE, PLD, or ALD. The insulating film may be deposited using the same material as the insulating film that will become the insulating film 277, or it may be deposited using a different material.

[0414] Next, the insulating film that will become the insulator 278 is processed by CMP until the insulator 277 is exposed. This CMP process forms an insulator 278 with a flattened upper surface.

[0415] The above CMP process may remove a portion of the upper surface of the insulator 277.

[0416] Next, an opening is formed in the region of the insulator 278 that overlaps with insulators 274c, 250a, and 275a (see Figures 12A to 12B2). When the resist mask 292 is formed using the multi-patterning technique described above, the same multi-patterning technique is also used to form the opening in the insulator 278.

[0417] Next, an insulating film 276A is deposited on the insulators 277 and 278 (see Figures 13A and 13B). The insulating film 276A can be deposited using sputtering, CVD, MBE, PLD, or ALD.

[0418] The insulating film 276A is preferably deposited using the ALD method. The insulating film 276A needs to be deposited with good coverage on the bottom and side surfaces of the openings formed in the insulator 278. Since the ALD method allows for the deposition of atomic layers one by one on the bottom and side surfaces of the openings, the insulating film 276A can be deposited with good coverage on the openings. In this embodiment, a silicon nitride film is deposited as the insulating film 276A using the PEALD method.

[0419] Next, the insulating film 276A is anisotropically etched to form an insulator 276 (see Figures 13C and 13D). By forming the insulator 276, a portion of the upper surface of the insulator 250a and the upper surface of the insulator 274c are exposed.

[0420] For the anisotropic etching described above, for example, a dry etching method may be used. By providing an insulator 276 on the side wall of the opening, the physical distance between the conductor 246 and the conductor 260 to be formed later can be maintained. Therefore, it is possible to prevent the conductor 246 and the conductor 260 from making electrical contact. In other words, it is possible to prevent the conductor 246 and the conductor 260 from making electrical contact.

[0421] Next, remove the insulator 274c (see Figures 14A and 14B). Dry etching or wet etching can be used to remove the insulator 274c.

[0422] Furthermore, when removing the insulator 274c by etching, it is preferable to use etching conditions with a high selectivity ratio so that the insulators 250a and 276 are not removed by the etching. This allows the insulators 250a and 276 to remain after the insulator 274c has been removed.

[0423] Next, conductive films 260A and 261A are deposited in sequence (see Figures 14C and 14D). Conductive films 260A and 261A can be deposited using sputtering, CVD, MBE, PLD, or ALD. In this embodiment, a titanium nitride film is deposited as conductive film 260A using the ALD method, and a tungsten film is deposited as conductive film 261A using the CVD method.

[0424] Next, conductive films 260A and 261A are processed by CMP treatment until insulators 277 and 278 are exposed, thereby forming the conductor 260 (see Figures 15A and 15B). As a result, the conductor 260 is positioned to fill the openings in insulator 276 and the recesses in insulator 250a. In other words, the conductor 260 is positioned to fill the openings formed in the oxide 230 through insulators 275a and 250a.

[0425] In Figure 15B, the conductor 260 is formed by a portion of the conductive film 260A remaining in the openings of the insulator 276 and the recesses of the insulator 250a, but the present invention is not limited to this. Depending on the conditions of the CMP treatment described above, or the size or depth of the openings of the insulator 276, a portion of the conductive film 260A and a portion of the conductive film 261A may remain in the openings of the insulator 276 and the recesses of the insulator 250a. In this case, the conductor 260 has a laminated structure of a conductor formed from the conductive film 260A and a conductor formed from the conductive film 261A. Also, as shown in Figure 15B, if only the conductive film 260A is left in the openings of the insulator 276 and the recesses of the insulator 250a, it is not necessary to deposit the conductive film 261A.

[0426] As a result of the CMP treatment described above, a portion of the insulator 277 and a portion of the insulator 278 may be removed. In addition, a portion of the conductive film 261A may remain within the openings in the insulator 276.

[0427] Next, an insulator 285 is formed on the insulators 276, 277, 278, and 260 (see Figures 15C and 15D). The insulator 285 can be deposited using sputtering, CVD, MBE, PLD, or ALD. It is preferable to deposit the insulator 285 using sputtering. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 285 can be reduced.

[0428] In this embodiment, silicon oxide is deposited as the insulator 285 by sputtering.

[0429] Next, an opening is formed in the insulator 285 (see Figures 16A and 16B). By forming this opening, the upper surface of the insulator 276 and the upper surface of the conductor 260 are exposed. The opening may be formed using wet etching, but dry etching is preferable for microfabrication.

[0430] When forming an opening in the insulator 285, a portion of the insulator 276 may be removed, as shown in Figure 16B.

[0431] Next, a conductive film to become conductor 262a and a conductive film to become conductor 262b are deposited in sequence, and the conductive films to become conductor 262a and conductor 262b are processed by CMP treatment until the insulator 285 is exposed. This forms the conductor 262 (conductor 262a and conductor 262b) (see Figures 16A and 16B). The conductive films to become conductor 262a and conductor 262b can be deposited using sputtering, CVD, MBE, PLD, or ALD methods. In this embodiment, a titanium nitride film is deposited as the conductive film to become conductor 262a using the ALD method, and a tungsten film is deposited as the conductive film to become conductor 262b using the CVD method.

[0432] Furthermore, if the conductor 260 and the conductor 262a are formed from the same material, it may be difficult to clearly detect the boundary between the conductor 260 and the conductor 262a.

[0433] Based on the above, a semiconductor device having the transistor 200 shown in Figures 5A to 5C can be fabricated. As shown in Figures 8A to 16B, the transistor 200 can be fabricated using the semiconductor device fabrication method shown in this embodiment.

[0434] One aspect of the present invention can provide a semiconductor device that can be miniaturized or highly integrated. Alternatively, it can provide a semiconductor device with less variation in the electrical characteristics of transistors. Alternatively, it can provide a semiconductor device with good reliability. Alternatively, it can provide a semiconductor device with good electrical characteristics. Alternatively, it can provide a semiconductor device with a large on-current.

[0435] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0436] (Embodiment 3) In this embodiment, a memory device, which is one form of the semiconductor device of the present invention, will be described with reference to Figures 17A to 18E.

[0437] Figure 17A shows an example of a memory device, which is one embodiment of the semiconductor device of the present invention. The memory device 400 includes a transistor 200 and a capacitive element 100. The transistor 200 is located above the capacitive element 100. Note that the transistor 200 can be the transistor 20 described in Embodiment 1 or the transistor 200 described in Embodiment 2.

[0438] The memory device 400 shown in Figure 17A has conductors 246 and 262 that are electrically connected to the transistor 200. Conductor 246 corresponds to conductor 46 described in Embodiment 1 or conductor 246 described in Embodiment 2. Conductor 262 corresponds to conductor 62 described in Embodiment 1 or conductor 262 described in Embodiment 2. In other words, the memory device 400 shown in Figure 17A can be said to have the semiconductor device described in Embodiment 1 or Embodiment 2 and the capacitive element 100. The semiconductor device is provided above the capacitive element 100.

[0439] Transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Because transistor 200 has a small off-current, it can be used in a memory device to retain stored data for a long period of time. In other words, because refresh operations are not required, or are performed very infrequently, the power consumption of the memory device can be significantly reduced.

[0440] The memory device 400 shown in Figure 17A consists of one transistor 200 and one capacitive element 100. By arranging the memory devices 400 in a matrix, a memory cell array can be constructed.

[0441] In this specification and other documents, a DRAM using a 1OS transistor, 1 capacitance element type memory cell may be referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory).

[0442] The conductor 242a is electrically connected to the capacitive element 100. As described in the previous embodiment, the conductor 242a can be positioned at an offset location from the center of the hollow cylindrical shape of the oxide 230. This configuration allows for a miniaturized layout without the need for self-aligned contacts, and 4F 2 This can be achieved.

[0443] Furthermore, by positioning the transistor 200 above the capacitive element 100, the transistor 200 is not affected by the thermal history of the capacitive element 100 during its fabrication. Therefore, it is possible to suppress degradation of the electrical characteristics of the transistor 200, such as fluctuations in the threshold voltage and an increase in parasitic resistance, as well as the increase in variations in electrical characteristics that accompany such degradation.

[0444] The memory device 400 shown in Figure 17A includes an insulator 140 on a substrate 101, an insulator 142 on the insulator 140, a capacitive element 100 on the substrate 101, the insulator 140, and the insulator 142, an insulator 216 on the capacitive element 100, and a transistor 200 on the insulator 216. Openings are formed in the insulator 140 and the insulator 142.

[0445] The configuration above the transistor 200 shown in Figure 17A (conductor 246, conductor 262, insulator 276, insulator 277, and insulator 285, etc.) is the same as the configuration of the semiconductor device described in Embodiment 2. Therefore, the configuration above the transistor 200 shown in Figure 17A should be considered in reference to the description in Embodiment 2. In addition, in the memory device 400 shown in Figure 17A, the semiconductor device described in Embodiment 2 can be considered to be provided above the capacitive element 100.

[0446] As the substrate 101, a substrate having at least sufficient heat resistance to withstand subsequent heat treatment can be used. When an insulating substrate is used as the substrate 101, glass substrates, quartz substrates, sapphire substrates, ceramic substrates, organic resin substrates, etc., can be used. In addition, semiconductor substrates such as single-crystal semiconductor substrates made of silicon, silicon carbide, etc., polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, and SOI substrates can be used.

[0447] In particular, it is preferable to use a substrate 101 on which a semiconductor circuit including semiconductor elements such as transistors is formed on the semiconductor substrate or insulating substrate. It is preferable that the semiconductor circuit constitutes, for example, a pixel circuit, a gate line driving circuit (gate driver), a source line driving circuit (source driver), etc. In addition to the above, an arithmetic circuit, a memory circuit, etc. may also be configured.

[0448] <Capacitive element 100> The capacitive element 100 is located below the transistor 200. The capacitive element 100 shown in Figure 17A has a cylindrical shape.

[0449] The capacitive element 100 shown in Figure 17A includes a conductor 110 disposed within openings formed in the insulators 140 and 142, and on the substrate 101, an insulator 130 on the conductor 110, and a conductor 120 on the insulator 130. Here, at least a portion of the conductors 110, 130, and 120 are disposed within openings formed in the insulators 140 and 142.

[0450] The conductor 110 functions as the lower electrode of the capacitive element 100, the conductor 120 functions as the upper electrode of the capacitive element 100, and the insulator 130 functions as the dielectric of the capacitive element 100. In the openings of the insulators 140 and 142, the upper electrode and the lower electrode face each other with the dielectric in between, not only on the bottom surface but also on the sides, allowing for a large capacitance per unit area. Therefore, the deeper the opening, the larger the capacitance of the capacitive element 100 can be. By increasing the capacitance per unit area of ​​the capacitive element 100 in this way, miniaturization or high integration of semiconductor devices can be promoted.

[0451] The insulator 142 preferably functions as an etching stopper when forming an opening in the insulator 140, and any insulator that can be used for the insulator 212 described in Embodiment 2 may be used.

[0452] The shape of the openings formed in the insulators 140 and 142 when viewed from above may be a circular shape including an ellipse, a quadrilateral, a polygon other than a quadrilateral, or a polygon with curved corners. In this case, it is preferable that the area overlapping between the opening and the transistor 200 is large when viewed from above. By adopting such a configuration, the occupied area of ​​the semiconductor device having the capacitive element 100 and the transistor 200 can be reduced.

[0453] The conductor 110 is positioned in contact with the insulator 142, the openings formed in the insulator 140, and the upper surface of the substrate 101. The conductor 110 is preferably formed using the ALD method or the CVD method, and for example, a conductor that can be used for the conductor 242a described in Embodiment 2 may be used. The conductor 110 may be provided in common for adjacent capacitive elements 100. Alternatively, the conductor 110 may be provided for each capacitive element 100. In other words, the conductor 110 may be separated at positions between adjacent capacitive elements 100.

[0454] The insulator 130 is arranged to cover the conductor 110. For example, it is preferable to deposit the insulator 130 using the ALD method or the CVD method. The insulator 130 can be made of, for example, silicon oxide, silicon oxide nitride, silicon nitride, silicon, zirconium oxide, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, aluminum nitride, hafnium oxide, hafnium oxide nitride, hafnium nitride, hafnium nitride, etc., and can be provided in a laminated or single layer. For example, an insulating film laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used as the insulator 130.

[0455] Furthermore, it is preferable to use a material with high dielectric strength, such as silicon oxidiznitride, or a high-dielectric-constant (high-k) material for the insulator 130. Alternatively, a laminated structure of a material with high dielectric strength and a high-dielectric-constant (high-k) material may be used.

[0456] High-dielectric constant (high-k) materials include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. By using such high-k materials, the capacitance of the capacitive element 100 can be sufficiently secured even if the insulator 130 is made thicker. By making the insulator 130 thicker, leakage current between the conductor 110 and the conductor 120 can be suppressed.

[0457] On the other hand, materials with high dielectric strength include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, porous silicon oxide, and resins. For example, an insulating film can be used in which silicon nitride deposited using the PEALD method, silicon oxide deposited using the PEALD method, and silicon nitride deposited using the PEALD method are layered in that order. Alternatively, an insulating film can be used in which zirconium oxide, silicon oxide deposited using the ALD method, and zirconium oxide are layered in that order. By using such an insulator with high dielectric strength, the dielectric strength can be improved, and electrostatic discharge breakdown of the capacitive element 100 can be suppressed.

[0458] The conductor 120 is positioned to fill the openings formed in the insulator 142 and the insulator 140. The conductor 120 is also electrically connected to the conductor 242a. The conductor 120 is preferably formed using the ALD method or the CVD method, and for example, a conductor that can be used for the conductor 242a described in Embodiment 2 may be used.

[0459] In Figure 17A, the sides of the openings formed in the insulators 140 and 142 are shown to be perpendicular to the substrate 101, but the present invention is not limited to this. For example, as shown in Figure 17B, the sides of the openings formed in the insulators 140 and 142 may be tapered. By making the sides of the openings tapered, the coverage of the conductor 110 and the insulator 130 can be improved in subsequent processes, and defects such as porosity can be reduced.

[0460] Furthermore, although Figures 17A and 17B show a configuration in which the conductor 120 is a single layer, the present invention is not limited to this, and the conductor 120 may be a laminated structure of two or more layers. For example, as shown in Figure 17C, the conductor 120 may be a two-layer laminated structure of conductor 120a and conductor 120b on conductor 120a.

[0461] The conductor 120a may be, for example, a conductor that can be used for the conductor 242a1 described in Embodiment 2. Similarly, the conductor 120b may be, for example, a conductor that can be used for the conductor 242a2 described in Embodiment 2.

[0462] In Figure 17C, the bottom of the conductor 120b is located on the transistor 200 side of the top surface of the insulator 140 or insulator 142. However, as shown in Figure 17D, depending on the diameter of the opening, the taper angle of the side surface of the opening, and the film thickness of the conductor 110, insulator 130, and conductor 120a, it may be located on the substrate side of the top surface of the insulator 140 or insulator 142.

[0463] <Variable example of capacitive element 100> In the following section, we will describe a configuration example different from the capacitive element 100 described above, using Figures 18A to 18E.

[0464] [Capacitive element 100A] Figure 18A is a cross-sectional view of the capacitive element 100A. The capacitive element 100A shown in Figure 18A is a modified example of the capacitive element 100 shown in Figure 17C.

[0465] The capacitive element 100A shown in Figure 18A differs from the capacitive element 100 shown in Figure 17C in that it has insulators 141a and 141b.

[0466] Insulator 141a is provided in contact with the inner wall of the opening formed in insulators 140 and 142, and insulator 141b is provided in contact with the side surface of insulator 141a. In the following, insulators 141a and 141b may be collectively referred to as insulator 141.

[0467] The conductor 110 is provided in contact with the side surface of the insulator 141b and the upper surface of the substrate 101. The insulator 130 is provided inside the conductor 110. The conductor 120 is provided inside the insulator 130 so as to fill the openings formed in the insulators 140 and 142.

[0468] As the insulator 141, a barrier insulating film that can be used for the insulator 275a described in Embodiment 2 may be used. For example, as the insulator 141, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used. Since the insulator 141 is provided in contact with the insulator 142, it is possible to suppress the mixing of impurities such as water and hydrogen contained in the insulator 140, etc., into the oxide 230 via the conductor 110. In particular, silicon nitride is preferred because it has high blocking properties for hydrogen. In addition, it is possible to prevent oxygen contained in the insulator 140 from being absorbed by the conductor 110.

[0469] When the insulator 141 is made into a laminated structure as shown in Figure 18A, it is preferable that the insulator 141a that is in contact with the inner wall of the opening such as the insulator 140 and the insulator 141b inside it use a combination of an oxygen barrier insulating film and a hydrogen barrier insulating film.

[0470] For example, aluminum oxide deposited by the ALD method can be used as the insulator 141a, and silicon nitride deposited by the PEALD method can be used as the insulator 141b. This configuration suppresses oxidation of the conductor 110 and further reduces the incorporation of hydrogen into the conductor 110.

[0471] Although the capacitive element 100A is shown with a configuration in which insulators 141a and 141b are stacked, the present invention is not limited to this. For example, the insulator 141 may be provided as a single layer or as a stacked structure of three or more layers.

[0472] [Capacitive element 100B] Figure 18B is a cross-sectional view of the capacitive element 100B. The capacitive element 100B shown in Figure 18B is a modified example of the capacitive element 100 shown in Figure 17A.

[0473] The capacitive element 100B shown in Figure 18B differs from the capacitive element 100 shown in Figure 17A in the shape of the insulator 130 and the conductor 120.

[0474] The insulator 130 is in contact with the inside of the recess in the conductor 110 and with the upper surface of the conductor 110. Furthermore, the insulator 130 has a region that is in contact with a part of the outer side surface of the conductor 110. In addition, the insulator 130 has a region that is in contact with the insulator 142.

[0475] The conductor 120 is provided to fill the opening in the conductor 110. Furthermore, the conductor 120 has a region that overlaps with a portion of the outer side surface of the conductor 110 via the insulator 130.

[0476] By using the above configuration, the capacitance per unit area can be increased.

[0477] [Capacitive element 100C] Figure 18C is a cross-sectional view of the capacitive element 100C. The capacitive element 100C shown in Figure 18C is a modified example of the capacitive element 100 shown in Figure 17A.

[0478] The capacitive element 100C shown in Figure 18C differs from the capacitive element 100 shown in Figure 17A in the shape of its conductor 110.

[0479] The conductor 110 has a conductor 110a on the substrate 101 and a conductor 110b on the conductor 110a. The conductor 110b has a cylindrical shape with a hollow portion. The cylindrical conductor 110b with a hollow portion can be manufactured by referring to the method for manufacturing the conductor 242b described in Embodiment 2.

[0480] The insulator 130 is provided so as to be in contact with the side and top surfaces of the conductor 110b, and the top surface of the conductor 110a.

[0481] The conductor 120 is provided so as to fill the hollow portion of the conductor 110b via the insulator 130.

[0482] This configuration allows the same mask to be used when manufacturing the transistor 200 and when manufacturing the capacitive element 100C, thereby reducing the manufacturing cost of the memory device 400.

[0483] [Capacity: 100D] Figure 18D is a cross-sectional view of the capacitive element 100D. The capacitive element 100D shown in Figure 18D is a modified example of the capacitive element 100 shown in Figure 17A.

[0484] The capacitive element 100D shown in Figure 18D differs from the capacitive element 100 shown in Figure 17A in the shape of its conductor 110.

[0485] The conductor 110 has a conductor 110a on the substrate 101 and a conductor 110b on the conductor 110a. The conductor 110b has a cylindrical shape.

[0486] The insulator 130 is provided so as to be in contact with the side and top surfaces of the conductor 110b, and the top surface of the conductor 110a.

[0487] The conductor 120 is provided so as to cover the top and side surfaces of the conductor 110b via the insulator 130.

[0488] Although Figure 18D shows a configuration in which the side surface of the conductor 110b is perpendicular to the substrate 101, the present invention is not limited to this. For example, as shown in Figure 18E, the side surface of the conductor 110b may be tapered. By making the side surface of the opening tapered, the coverage of the insulator 130 and the conductor 120 can be improved in subsequent processes, and defects such as porosity can be reduced.

[0489] The above is a description of a modified version of the capacitive element 100.

[0490] In a memory device which is one embodiment of the semiconductor device of the present invention, one or more of the following may be provided: below the layer containing the capacitive element 100, between the layer containing the transistor 200 and the layer containing the capacitive element 100, and above the layer containing the transistor 200, a wiring layer provided with an interlayer film, wiring, and a plug.

[0491] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0492] (Embodiment 4) In this embodiment, a transistor using an oxide as a semiconductor (hereinafter sometimes referred to as an OS transistor) and a memory device to which a capacitive element is applied (hereinafter sometimes referred to as an OS memory device) according to one aspect of the present invention will be described with reference to Figures 19A to 21. The OS memory device is a memory device having at least a capacitive element and an OS transistor that controls the charging and discharging of the capacitive element. Since the off-current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a non-volatile memory. Note that the transistor 20 described in Embodiment 1 or the transistor 200 described in Embodiment 2 can be used as the OS transistor.

[0493] <Example of storage device configuration> Figure 19A shows an example of the configuration of an OS memory device. The storage device 1400 has peripheral circuits 1411 and a memory cell array 1470. The peripheral circuits 1411 have row circuits 1420, column circuits 1430, output circuits 1440, and control logic circuits 1460.

[0494] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, etc. The precharge circuit has the function of precharging the wiring. The sense amplifier has the function of amplifying the data signal read from the memory cell. The above wiring is connected to the memory cells of the memory cell array 1470, and will be described in more detail later. The amplified data signal is output to the outside of the storage device 1400 as the data signal RDATA via the output circuit 1440. The row circuit 1420 includes, for example, a row decoder, a word line driver circuit, etc., and can select the row to access.

[0495] The storage device 1400 is supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 from an external source. The storage device 1400 also receives control signals (CE, WE, RES), an address signal ADDR, and a data signal WDATA from an external source. The address signal ADDR is input to the row decoder and column decoder, and the data signal WDATA is input to the write circuit.

[0496] The control logic circuit 1460 processes externally input control signals (CE, WE, RES) to generate control signals for the row decoder and column decoder. Control signal CE is the chip enable signal, control signal WE is the write enable signal, and control signal RES is the read enable signal. The signals processed by the control logic circuit 1460 are not limited to these; other control signals may be input as needed.

[0497] The memory cell array 1470 has multiple memory cells MC arranged in a matrix and multiple wirings. The number of wirings connecting the memory cell array 1470 to the row circuit 1420 is determined by the configuration of the memory cells MC and the number of memory cells MC in each row. Similarly, the number of wirings connecting the memory cell array 1470 to the column circuit 1430 is determined by the configuration of the memory cells MC and the number of memory cells MC in each row.

[0498] Although Figure 19A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, this embodiment is not limited to this. For example, as shown in Figure 19B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap the memory cell array 1470.

[0499] Alternatively, multiple memory cell arrays 1470 can be stacked. By stacking multiple memory cell arrays 1470, memory cells can be integrated and arranged without increasing the area occupied by the memory cell array 1470. In other words, a 3D cell array can be constructed. In this way, high integration of memory cells can be achieved, and a semiconductor device with a large storage capacity can be provided.

[0500] Using Figure 20A, we will explain an example of a memory cell configuration that can be applied to the memory cell MC described above.

[0501] Figure 20A shows an example of the circuit configuration of a DOSRAM memory cell. The memory cell 1473 shown in Figure 20A includes a transistor M1 and a capacitive element CA. Note that transistor M1 is a single-gate transistor.

[0502] The first terminal of transistor M1 is connected to the first terminal of capacitive element CA, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL. The second terminal of capacitive element CA is connected to wiring LL.

[0503] Wiring BIL functions as a bit line, and wiring WOL functions as a word line. Wiring LL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CA. During data writing and reading, wiring LL may be at ground potential or a low-level potential.

[0504] Here, the memory cell 1473 shown in Figure 20A corresponds to the memory device 400 shown in Figure 17A. In other words, transistor M1 corresponds to transistor 200, and capacitive element CA corresponds to capacitive element 100. Also, wiring BIL corresponds to conductor 246, and wiring WOL corresponds to conductor 262.

[0505] Furthermore, the memory cell MC is not limited to memory cell 1473, and the circuit configuration can be changed.

[0506] When the semiconductor device shown in the above embodiment is used as the memory cell 1473, transistor 200 can be used as transistor M1 and capacitive element 100 can be used as capacitive element CA. By using an OS transistor as transistor M1, the off-current of transistor M1 can be made very small. In other words, the written data can be held by transistor M1 for a long time, so the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. In addition, because the off-current is very small, multi-level data or analog data can be held in the memory cell 1473.

[0507] Furthermore, in DOSRAM, by configuring the sense amplifier to overlap the memory cell array 1470 as described above, the bit lines can be shortened. This reduces the bit line capacitance and thus the memory cell retention capacity can be reduced.

[0508] By using an OS transistor as transistor M1, transistor M1 can be formed during the BEOL process, which forms the wiring of the memory device. Furthermore, when using Si transistors in the peripheral circuit 1411 that overlaps the memory cell array 1470, a technique can be applied to directly form the OS transistor on top of the Si transistor. By using this technique, 3D functional circuits can be constructed while maintaining the design rules, enabling high functionality with low power consumption and low cost.

[0509] Figure 20B shows a perspective view of the storage device 1400. The storage device 1400 has layers 1480 and 1490. Figure 20C is a perspective view illustrating the configuration of the storage device 1400, showing layers 1480 and 1490 separately.

[0510] Layer 1480 is a layer containing a transistor. The semiconductor layer containing the channel formation region of the transistor may be formed using semiconductor materials such as single-crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, or amorphous semiconductors, either individually or in combination. Examples of such semiconductor materials include silicon or germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors may also be used. Furthermore, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, or silicon germanium, which are applicable to HEMTs (High Electron Mobility Transistors), may also be used.

[0511] Layer 1490 is a layer containing a transistor. The semiconductor layer containing the channel formation region of the transistor may be provided using an oxide semiconductor or a semiconductor material capable of forming a thin film, such as silicon. By using BEOL-Tr technology, layer 1490 can be provided on layer 1480. Thus, a miniaturized memory device 1400 can be realized.

[0512] For example, the transistors included in layer 1480 are Si transistors. In this case, a peripheral circuit 1411 can be provided in layer 1480. Alternatively, the transistors included in layer 1490 are OS transistors. In this case, a memory cell array 1470 can be provided in layer 1480.

[0513] Based on the above, the memory device 1400 can be manufactured using BEOL-Tr technology. Therefore, the occupied area of ​​the memory device 1400 can be reduced.

[0514] The configuration of the peripheral circuit 1411, memory cell array 1470, etc., as shown in this embodiment is not limited to the above. The arrangement or function of these circuits, and the wiring, circuit elements, etc. connected to them, may be changed, deleted, or added as necessary.

[0515] Figure 21 shows an example of the cross-sectional configuration of the storage device 1400 shown in Figure 19A. Figure 21 shows a part of the storage device 1400 shown in Figure 19A.

[0516] As shown in Figure 21, the storage device 1400 has a layer 1480 and a layer 1490 on top of layer 1480. Peripheral circuits 1411 are provided on layer 1480. A memory cell array 1470 is provided on layer 1490.

[0517] Figure 21 shows the transistor 300 included in layer 1480. The transistor 300 functions as part of the sense amplifier described above. In this case, layer 1480 can be considered as a substrate on which a semiconductor circuit including the transistor is formed. In other words, layer 1480 corresponds to the substrate 101 described in Embodiment 3.

[0518] Furthermore, Figure 21 shows a portion of the memory cell array 1470 located in layer 1490. Specifically, Figure 21 illustrates three memory cell MCs located in layer 1490. The capacitive elements 100 included in the memory cell MCs may be located in layer 1490 as shown in Figure 21, or they may be located in layer 1480.

[0519] Conductor 262 corresponds to the WOL wiring. Conductor 246 corresponds to the BIL wiring. Conductor 110 corresponds to the LL wiring. Conductor 110 also functions as the lower electrode of the capacitive element 100.

[0520] In the storage device 1400 shown in Figure 21, one layer 1490 is provided. As mentioned above, a configuration in which multiple memory cell arrays 1470 are stacked may also be used. An example of a storage device having a configuration in which multiple memory cell arrays 1470 are stacked is shown in Figure 25.

[0521] In the memory device 1400 shown in Figure 25, n layers of layer 1490 (layers 1490[1] to 1490[n]) are provided. Note that in Figure 25, layers 1490[1] and 1490[2] are shown, while layers 1490[3] to 1490[n] and layer 1480 are omitted.

[0522] Each of layers 1490[1] to 1490[n] has a plurality of memory cells MC. Each of the plurality of memory cells MC has a transistor 200 and a capacitive element 100. A memory cell array 1470 is formed in each of layers 1490[1] to 1490[n].

[0523] By arranging layers 1490[1] to 1490[n] perpendicular to the substrate surface, the memory density of memory cells can be improved. Furthermore, layers 1490 can be repeatedly manufactured in the perpendicular direction using the same manufacturing process. The storage device 1400 shown in Figure 25 can reduce the manufacturing cost of the memory cell array 1470.

[0524] <Transistor 300> The transistor 300 is provided on a substrate 311 and includes a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or drain region. The transistor 300 may be either a p-channel or an n-channel type.

[0525] In Figure 21, the transistor 300 has a convex shape in the semiconductor region 313 (part of the substrate 311) where the channel is formed. Furthermore, the sides and top surface of the semiconductor region 313 are covered by a conductor 316 via an insulator 315. The conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. It may also have an insulator in contact with the top of the convex portion, functioning as a mask for forming the convex portion. While this example shows the formation of the convex portion by processing a part of the semiconductor substrate, a semiconductor film with a convex shape may also be formed by processing an SOI substrate.

[0526] Note that the transistor 300 shown in Figure 21 is just one example, and its structure is not limited to that; any appropriate transistor can be used depending on the circuit configuration or driving method.

[0527] <Wiring layer> A wiring layer containing interlayer films, wiring, and plugs may be provided between each structure. Furthermore, multiple wiring layers may be provided depending on the design. Here, a conductor functioning as a plug or wiring may be grouped together and assigned the same reference numeral. Also, in this specification, the wiring and the plug that electrically connects to the wiring may be an integrated unit. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug.

[0528] For example, on the transistor 300, insulators 320, 322, 324, and 326 are sequentially stacked as interlayer films. Insulators 320, 322, 324, and 326 also have embedded conductive elements such as conductors 328 and 330 that are electrically connected to the capacitive element 100 or the transistor 200. Conductors 328 and 330 function as plugs or wiring.

[0529] Furthermore, the insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape beneath it. For example, the upper surface of the insulator 322 may be planarized by a planarizing treatment such as chemical mechanical polishing (CMP) to improve its flatness.

[0530] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Figure 21, insulators 350, 352, and 354 are stacked in order. Conductors 356 are formed on insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring.

[0531] Insulators that can be used as interlayer films include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0532] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0533] For example, it is preferable that insulators 322, 352, and 354 have an insulator with a low dielectric constant. For example, it is preferable that the insulator has fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, porous silicon oxide, or a resin. Alternatively, it is preferable that the insulator has a laminated structure of silicon oxide, silicon oxynitride, silicon nitride, silicon oxide, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide, and a resin. Since silicon oxide and silicon oxynitride are thermally stable, combining them with a resin can create a thermally stable laminated structure with a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, or acrylic.

[0534] Furthermore, the electrical characteristics of a transistor using an oxide semiconductor can be stabilized by surrounding it with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, the insulator 350, etc., should be an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen.

[0535] As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon nitride or silicon nitride, etc., can be used.

[0536] Conductors that can be used for wiring and plugs may include materials containing one or more metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0537] For example, conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials can be used as conductors 328, conductor 330, and conductor 356, either in a single layer or in a laminated form. It is preferable to use high-melting-point materials such as tungsten or molybdenum that provide both heat resistance and conductivity, with tungsten being preferable. Alternatively, it is preferable to form them with low-resistance conductive materials such as aluminum or copper. Using low-resistance conductive materials can reduce wiring resistance.

[0538] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0539] (Embodiment 5) In this embodiment, a semiconductor device having an OS transistor according to one aspect of the present invention will be described with reference to Figures 22A and 22B. This semiconductor device has an OS transistor between the logic circuit and the power line. Since the off-current of the OS transistor is extremely small, the power consumption of the semiconductor device can be reduced.

[0540] Examples of logic circuits include combinational circuits such as OR, AND, NAND, and NOR circuits, sequential circuits such as flip-flop circuits, latch circuits, counter circuits, register circuits, and shift register circuits, and buffer circuits.

[0541] A buffer circuit is a circuit whose logic is fixed in a standby state (also called a non-operating state or non-selected state). Therefore, when a buffer circuit is used as the logic circuit in the semiconductor device described above, the power consumption of the semiconductor device can be further reduced. Hereafter, a semiconductor device according to one aspect of the present invention will be described, with a buffer circuit as an example of the logic circuit. Note that the logic circuit in the semiconductor device is not limited to a buffer circuit, and the logic circuits described above may be used.

[0542] Figure 22A shows an example of a semiconductor device configuration in which an OS transistor is provided between the buffer circuit and the power line.

[0543] The semiconductor device 1700 shown in Figure 22A includes transistors 1701 to 1703, a buffer circuit 1710, wiring VDD, wiring LL, an input terminal IN, and an output terminal OUT.

[0544] In the semiconductor device 1700, the number of transistors electrically connected to the buffer circuit 1710 is the same as the number of inverter circuits in the buffer circuit 1710. Since the buffer circuit 1710 shown in Figure 22A consists of three inverter circuits (inverter circuits 1711 to 1713), the semiconductor device 1700 shown in Figure 22A has three transistors (transistors 1701 to 1703). Note that the number of inverter circuits in the buffer circuit 1710 may be one, two, or four or more. In this case, the number of transistors electrically connected to the buffer circuit 1710 can be set as appropriate.

[0545] Furthermore, the inverter circuits 1711 through 1713 shown in Figure 22A are each constructed using CMOS technology. These inverter circuits can also be described as CMOS inverter circuits.

[0546] Inverter circuit 1711 has transistors 1711a and 1711b. Inverter circuit 1712 has transistors 1712a and 1712b. Inverter circuit 1713 has transistors 1713a and 1713b. Transistors 1711a, 1712a, and 1713a are p-channel transistors. Transistors 1711b, 1712b, and 1713b are n-channel transistors.

[0547] The gate of transistor 1711a is electrically connected to the gate of transistor 1711b and to the input terminal IN. Additionally, one source or drain of transistor 1711a is electrically connected to one source or drain of transistor 1711b, the gate of transistor 1712a, and the gate of transistor 1712b. Furthermore, the other source or drain of transistor 1711a is electrically connected to one source or drain of transistor 1701.

[0548] The source or drain of transistor 1711b is electrically connected to wiring LL.

[0549] One source or drain of transistor 1712a is electrically connected to one source or drain of transistor 1712b, the gate of transistor 1713a, and the gate of transistor 1713b. The other source or drain of transistor 1712a is electrically connected to the wiring VDD.

[0550] The other source or drain of transistor 1712b is electrically connected to one source or drain of transistor 1702.

[0551] One source or drain of transistor 1713a is electrically connected to one source or drain of transistor 1712b and to the output terminal OUT. The other source or drain of transistor 1713b is electrically connected to one source or drain of transistor 1703.

[0552] The source or drain of transistor 1713b is electrically connected to wiring LL.

[0553] The other end of either the source or drain of transistor 1701, and the other end of either the source or drain of transistor 1703, are electrically connected to the wiring VDD. Additionally, the other end of either the source or drain of transistor 1702 is electrically connected to the wiring LL.

[0554] A potential H is supplied to the wiring VDD. A potential L is supplied to the wiring LL. It is preferable that potential H is higher than potential L. In this specification, "potential H" is the potential at which an n-channel transistor turns on when input to its gate, and a p-channel transistor turns off when input to its gate. "Potential L" is the potential at which an n-channel transistor turns off when input to its gate, and a p-channel transistor turns on when input to its gate.

[0555] Transistors 1701 to 1703 are transistors that have a smaller off-current compared to the transistors in the buffer circuit 1710. With this configuration, when the input terminal IN is at a high potential and a potential that can turn off transistors 1701 to 1703 is supplied to the gates of each transistor, the leakage current of transistors 1711a, 1712b, and 1713a can be suppressed. Therefore, the power consumption of the semiconductor device 1700 when it is not operating can be reduced.

[0556] When using Si transistors for the transistors in the buffer circuit 1710, it is preferable to use OS transistors as transistors 1701 to 1703. OS transistors are preferable because they have an extremely small off-current. The OS transistors can be either transistor 20 described in Embodiment 1 or transistor 200 described in Embodiment 2.

[0557] The semiconductor device 1700, which has Si transistors and OS transistors, can be to which BEOL-Tr technology can be applied.

[0558] Figure 22B is a perspective view of the semiconductor device 1700. When Si transistors are applied to the transistors in the buffer circuit and OS transistors are applied to transistors 1701 to 1703, transistor 1701 can be formed above inverter circuit 1711. Similarly, transistor 1702 can be formed above inverter circuit 1712. Similarly, transistor 1703 can be formed above inverter circuit 1713.

[0559] In other words, the semiconductor device 1700 can be configured by stacking a layer having a buffer circuit and a layer having transistors 1701 to 1703. By using this configuration, the occupied area of ​​the semiconductor device 1700 can be reduced.

[0560] In the above configuration, the layer having the buffer circuit can be said to be a layer having Si transistors. Also, the layers having transistors 1701 to 1703 can be said to be layers having OS transistors.

[0561] Furthermore, the semiconductor device 1700 may be applied to the storage device 1400 described in Embodiment 4. For example, the configuration of the semiconductor device 1700 may be applied to the logic circuit included in the peripheral circuit of the storage device 1400. That is, a transistor is provided between the logic circuit and the power line in the layer 1490 described in Embodiment 4. This makes it possible to provide a storage device that is miniaturized and has reduced power consumption.

[0562] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0563] (Embodiment 6) This embodiment describes application examples of a semiconductor device using the storage device shown in the previous embodiment. The storage device shown in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memory, and SSDs (solid-state drives). Figures 23A to 23E schematically show some configuration examples of removable storage devices. For example, the semiconductor device shown in the previous embodiment can be processed into a packaged memory chip and used in various storage devices and removable memory.

[0564] Figure 23A is a schematic diagram of a USB memory device. The USB memory device 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a circuit board 1104. The circuit board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the circuit board 1104. A storage device or semiconductor device as shown in the above embodiment can be incorporated into the memory chip 1105, etc.

[0565] Figure 23B is a schematic diagram of the external appearance of an SD card, and Figure 23C is a schematic diagram of the internal structure of an SD card. The SD card 1110 has a housing 1111, a connector 1112, and a circuit board 1113. The circuit board 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the circuit board 1113. The capacity of the SD card 1110 can be increased by also providing a memory chip 1114 on the back side of the circuit board 1113. Alternatively, a wireless chip with wireless communication functionality may be provided on the circuit board 1113. This allows for reading and writing data to the memory chip 1114 via wireless communication between the host device and the SD card 1110. The memory chip 1114 and other components can be incorporated into the storage device or semiconductor device shown in the above embodiment.

[0566] Figure 23D is a schematic diagram of the external appearance of the SSD, and Figure 23E is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a circuit board 1153. The circuit board 1153 is housed in the housing 1151. For example, memory chips 1154, 1155, and a controller chip 1156 are mounted on the circuit board 1153. Memory chip 1155 is the work memory for the controller chip 1156, and for example, a DOSRAM chip can be used. The capacity of the SSD 1150 can be increased by also providing memory chips 1154 on the back side of the circuit board 1153. The storage device or semiconductor device shown in the above embodiment can be incorporated into the memory chip 1154, etc.

[0567] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0568] (Embodiment 7) Figures 24A to 24G show specific examples of electronic devices equipped with a storage device or semiconductor device according to one aspect of the present invention.

[0569] <Electronic Equipment and Systems> A storage device or semiconductor device according to one aspect of the present invention can be mounted on various electronic devices. Examples of electronic devices include, for example, information terminals, computers, smartphones, e-book readers, television equipment, digital signage, large game machines such as pachinko machines, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, recording and playback devices, navigation systems, and sound playback devices. Here, "computer" includes not only tablet computers, notebook computers, and desktop computers, but also large computers such as server systems.

[0570] An electronic device according to one aspect of the present invention may have an antenna. By receiving signals with the antenna, the display unit can display images and information. Furthermore, if the electronic device has an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0571] An electronic device according to one aspect of the present invention may have sensors (including those with the function of measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0572] An electronic device according to one aspect of the present invention can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on.

[0573] [Information terminal] A memory device or semiconductor device according to one aspect of the present invention can be used to form a memory device for holding the program of a microcontroller. Therefore, according to one aspect of the present invention, the microcontroller chip can be made smaller.

[0574] Figure 24A illustrates a mobile phone (smartphone), a type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102. A touch panel is provided on the display unit 5102 as an input interface, and buttons are provided on the housing 5101. By using a miniaturized microcontroller according to one aspect of the present invention, the limited space inside the mobile phone can be effectively utilized. Furthermore, a storage device according to one aspect of the present invention may be used for the storage of the mobile phone. This makes it possible to increase the storage capacity per unit area of ​​the storage device.

[0575] Figure 24B illustrates a notebook-type information terminal 5200. The notebook-type information terminal 5200 comprises a terminal body 5201, a display unit 5202, and a keyboard 5203. By using a miniaturized microcontroller according to one aspect of the present invention, the limited space inside the notebook-type information terminal can be effectively utilized. Furthermore, a storage device according to one aspect of the present invention may be used for the storage of the notebook-type information terminal. This makes it possible to increase the storage capacity per unit area of ​​the storage device.

[0576] In the above, smartphones and notebook computers were used as examples of electronic devices, illustrated in Figures 24A and 24B, respectively. However, other types of information devices can also be used. Examples of other types of information devices include PDAs (Personal Digital Assistants), desktop computers, and workstations.

[0577] [Game console] Figure 24C shows a portable game console 5300, which is an example of a game console. The portable game console 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, operation keys 5306, etc. Housings 5302 and 5303 can be detached from housing 5301. By attaching the connection unit 5305 provided on housing 5301 to another housing (not shown), the video output from the display unit 5304 can be output to another video device (not shown). At this time, housings 5302 and 5303 can each function as operation units. This allows multiple players to play the game simultaneously. A memory device or semiconductor device according to one aspect of the present invention can be incorporated into chips or the like provided on the circuit boards of housings 5301, 5302, and 5303.

[0578] Figure 24D also shows a home console 5400, which is an example of a game console. A controller 5402 is connected to the home console 5400 either wirelessly or via a wired connection.

[0579] By using a miniaturized microcontroller according to one aspect of the present invention in game consoles such as the portable game console 5300 and the home game console 5400, the limited space inside the game console can be effectively utilized. Furthermore, a storage device or semiconductor device according to one aspect of the present invention may be used for the storage of the portable game console. This makes it possible to increase the storage capacity per unit area of ​​the storage device.

[0580] Figures 24C and 24D illustrate a portable game console and a home game console as examples of game consoles, but the game consoles to which the microcontroller according to one aspect of the present invention is applied are not limited to these. Examples of game consoles to which the microcontroller according to one aspect of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0581] [Large computer] A storage device or semiconductor device according to one aspect of the present invention can be applied to a large-scale computer.

[0582] Figure 24E shows the supercomputer 5500, an example of a large-scale computer. Figure 24F shows the rack-mount computer 5502, which is part of the supercomputer 5500.

[0583] The supercomputer 5500 comprises a rack 5501 and a plurality of rack-mount type computers 5502. The plurality of computers 5502 are housed in the rack 5501. Furthermore, each computer 5502 is provided with a plurality of circuit boards 5504, on which a microcontroller according to one aspect of the present invention can be mounted. By using a miniaturized microcontroller according to one aspect of the present invention, the limited space of the large computer can be effectively utilized. Additionally, a storage device or semiconductor device according to one aspect of the present invention may be used for the storage of the large computer. This increases the storage capacity per unit area of ​​the storage device.

[0584] Figures 24E and 24F illustrate a supercomputer as an example of a large computer, but the large computers to which the microcontroller according to one aspect of the present invention is applied are not limited to this. Examples of large computers to which the microcontroller according to one aspect of the present invention is applied include service-providing computers (servers) and large general-purpose computers (mainframes).

[0585] [electric appliances] Figure 24G shows an example of an electrical appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 includes a casing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0586] A memory device or semiconductor device according to one aspect of the present invention can also be applied to an electric refrigerator 5800. For example, by applying a miniaturized microcontroller according to one aspect of the present invention to the electric refrigerator 5800, the limited space of the electric refrigerator can be effectively utilized.

[0587] While electric refrigerators and freezers were described as an example of electrical appliances, other examples of electrical appliances include vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cooktops, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0588] The electronic devices described in this embodiment, their functions, and their effects can be appropriately combined with descriptions of other electronic devices.

[0589] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0590] [Explanation of symbols] 20A: Transistor, 20B: Transistor, 20C: Transistor, 20D: Transistor, 20E: Transistor, 20: Transistor, 30a: Oxide, 30b: Oxide, 30c: Oxide, 30i: Region, 30: Oxide, 42a: Conductor, 42b: Conductor, 42: Conductor, 46: Conductor, 46a: Convex shape, 50: Insulator, 60: Conductor, 62: Conductor, 64a: Region, 64b: Region, 100A: Capacitive element, 100B: Capacitive element, 100C: Capacitive element, 100D: Capacitive element, 100: Capacitive element, 101: Substrate, 110a: Conductor, 110b : Conductor, 110: Conductor, 120a: Conductor, 120b: Conductor, 120: Conductor, 130: Insulator, 140: Insulator, 141a: Insulator, 141b: Insulator, 141: Insulator, 142: Insulator, 200A: Transistor, 200B: Transistor, 200C: Transistor, 200: Transistor, 212: Insulator, 216: Insulator, 230a: Oxide, 230A: Oxide film, 230b: Oxide, 230B: Oxide film, 230bc: Region, 230c: Oxide, 230C: Oxide film, 230: Oxide, 242a: Conductor, 242b: Conductor, 242B: Conductive film 246: Conductor, 247: Insulator, 250a: Insulator, 250A: Insulating film, 250b: Insulator, 254a: Insulator, 254b: Insulator, 260A: Conductive film, 260: Conductor, 261A: Conductive film, 262a: Conductor, 262b: Conductor, 262: Conductor, 274A: Insulating film, 274c: Insulator, 274: Insulator, 275a: Insulator, 275A: Insulating film, 275b: Insulator, 276A: Insulating film, 276: Insulator, 277: Insulator, 278: Insulator, 285: Insulator, 291A: Insulating film, 291: Insulator, 292: Resist mask, 293A: Insulating film, 293 :Insulator, 300:Transistor, 311:Substrate, 313:Semiconductor area, 314a:Low resistance area, 314b:Low resistance area, 315:Insulator, 316:Conductor, 320:Insulator, 322:Insulator, 324:Insulator, 326:Insulator, 328:Conductor, 330:Conductor, 350:Insulator, 352:Insulator, 354:Insulator, 356:Conductor, 400:Storage device, 1100:USB memory, 1101:Enclosure, 1102:Cap, 1103:USB connector, 1104:Substrate, 1105:Memory chip, 1106:Controller chip, 1110:SD card,1111: Enclosure, 1112: Connector, 1113: Circuit board, 1114: Memory chip, 1115: Controller chip, 1150: SSD, 1151: Enclosure, 1152: Connector, 1153: Circuit board, 1154: Memory chip, 1155: Memory chip, 1156: Controller chip, 1400: Storage device, 1411: Peripheral circuit, 1420: Row circuit, 1430: Column circuit, 1440: Output circuit, 1460: Control logic circuit, 1470: Memory cell array, 1473: Memory cell, 1480: Layer, 1490: Layer, 1700: Semiconductor device, 1701: Transistor, 1702: Transistor, 1703: Transistor, 1710: Buffer circuit, 1711a: Transistor, 1711b: Transistor, 1711: Inverter Transistor circuit, 1712a: Transistor, 1712b: Transistor, 1712: Inverter circuit, 1713a: Transistor, 1713b: Transistor, 1713: Inverter circuit, 5100: Information terminal, 5101: Enclosure, 5102: Display unit, 5200: Notebook-type information terminal, 5201: Main unit, 5202: Display unit, 5203: Keyboard, 5300: Portable game console, 5301: Enclosure, 5302: Enclosure, 5303: Enclosure, 5304: Display unit, 5305: Connection unit, 5306: Operation keys, 5400: Home game console, 5402: Controller, 5500: Supercomputer, 5501: Rack, 5502: Calculator, 5504: Circuit board, 5800: Electric refrigerator / freezer, 5801: Enclosure, 5802: Door for refrigerator compartment, 5803: Door for freezer compartment,

Claims

1. A first conductor having the function of one of the source electrode and drain electrode of a transistor, A metal oxide having a region located on the first conductor and overlapping with the first conductor, A second conductor having a region located on the metal oxide and functioning as the other of the source electrode and drain electrode of the transistor, The metal oxide has a hollow cylindrical shape, The second conductor is a semiconductor device having a hollow cylindrical shape, In a top view, the metal oxide has a first opening, In a top view, the second conductor has a second opening that overlaps with the first opening. A first insulator having regions located inside the first opening and the second opening, and having a recess in cross-sectional view, A second insulator having a region located inside the recess of the first insulator and having a recess in cross-sectional view, A third conductor having a region disposed in the recess of the second insulator and functioning as the gate electrode of the transistor, A semiconductor device wherein, in a top view, the center of the first conductor does not coincide with the center of the hollow cylindrical shape of the metal oxide.

2. In claim 1, In cross-sectional view, the first opening side surface of the metal oxide has a tapered shape. In a cross-sectional view, the side surface of the second conductor on the second opening side has a tapered shape, wherein the semiconductor device.

3. In claim 2, A semiconductor device wherein the uppermost part of the second insulator is at the same or approximately the same height as the uppermost part of the first insulator.

4. In claim 3, A semiconductor device wherein the first insulator has a region where its film thickness is smaller than that of the second insulator.

5. A semiconductor device according to claim 1, and a capacitive element, The semiconductor device is a memory device provided above the capacitive element.

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