Imaging device and electronic equipment

Abstract

To provide an imaging device that has high imaging quality and can be manufactured at low cost.SOLUTION: A first circuit including a first transistor and a second transistor, and a second circuit including a second transistor and a photodiode are provided. The first transistor is provided on a first surface of a silicon substrate. The second transistor is provided over the first surface of the silicon substrate with a first insulating layer interposed therebetween. The silicon substrate includes a second insulating layer. The second insulating layer is provided so as to surround a side surface of the photodiode. The first transistor is a p-channel type transistor having an active region in the silicon substrate. The second transistor is an n-channel type transistor using an oxide semiconductor layer as an active layer. The photodiode has, as a light-receiving surface, a surface on the opposite side to the first surface of the silicon substrate.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to an imaging device using an oxide semiconductor.

[0002] Furthermore, one aspect of the present invention is not limited to the above-described technical field. The technical field of one aspect of the present invention disclosed in the details includes semiconductor devices, display devices, and their drivers. A method of operation, or a method of manufacturing such a method, can be given as an example.

[0003] In this specification, a semiconductor device refers to a device that can function by utilizing semiconductor properties. This refers to the general term. Transistors and semiconductor circuits are forms of semiconductor devices. Also, memory devices, Display devices, imaging devices, and electronic devices include semiconductor devices. [Background technology]

[0004] A technology for constructing transistors using semiconductor thin films formed on a substrate having an insulating surface. It is attracting attention. The transistor in question is used in integrated circuits (ICs) and image display devices (simply as a display device and It is widely applied to electronic devices such as (also written as) transistors. Silicon-based semiconductor materials are widely known as conductive thin films, but other materials include oxidative materials. Semiconductors are attracting attention.

[0005] For example, using zinc oxide or an In-Ga-Zn-based oxide semiconductor as the oxide semiconductor Techniques for fabricating transistors have been disclosed (see Patent Documents 1 and 2).

[0006] Furthermore, Patent Document 3 describes a transistor having an oxide semiconductor and having an extremely low off-current. It is used in at least part of the pixel circuit, CMOS (Complementary Metal Having a silicon semiconductor capable of fabricating an Oxide Semiconductor circuit. By using transistors in peripheral circuits, it is possible to fabricate high-speed and low-power imaging devices. This has been disclosed. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2007-123861 [Patent Document 2] Japanese Patent Publication No. 2007-96055 [Patent Document 3] Japanese Patent Publication No. 2011-119711 [Overview of the project] [Problems that the invention aims to solve]

[0008] The imaging device is intended for use in a variety of environments, including low-light environments and for capturing moving subjects. Even in such cases, high imaging quality is required. Therefore, there is a need for imaging devices that can be manufactured at a lower cost.

[0009] Therefore, one aspect of the present invention provides an imaging device capable of imaging under low light conditions. One of the objectives is to provide an imaging device with a wide dynamic range. One of the objectives is to provide a high-resolution imaging device. Alternatively, one of the objectives is to provide an imaging device with a high degree of integration. Or, a wide temperature range. One of the objectives is to provide an imaging device that can be used in the following environment. Alternatively, for high-speed operation. One of the objectives is to provide a suitable imaging device, or to provide a low-power imaging device. One of the objectives is to provide an imaging device with a high aperture ratio. One of the objectives is to provide a low-cost imaging device. One of the objectives is to provide a highly reliable imaging device.

[0010] Furthermore, the description of these problems does not preclude the existence of other problems. The approach does not need to solve all of these problems. This will become clear from the description in the specification, drawings, claims, etc., and the specification, drawings It is possible to extract other issues from the descriptions in the surfaces, claims, etc. [Means for solving the problem]

[0011] One aspect of the present invention is a pixel circuit having a transistor formed using an oxide semiconductor, A photoelectric conversion element formed using silicon and a transient formed using oxide semiconductor An imaging device including peripheral circuits having transistors formed using silicon and To relate to.

[0012] One aspect of the present invention is an imaging device having a first circuit and a second circuit, wherein the first circuit is The first transistor and the second transistor are present, and the second circuit has a third transistor and It has a photodiode, and the first transistor is provided on the first surface of the silicon substrate, The photodiode is mounted on a silicon substrate, and the second transistor is connected to the first transistor. The silicon substrate is provided on top of the photodiode, and the silicon substrate has a first insulating layer, and the first insulating layer is a photodiode It is provided so as to surround the side, and the first transistor is a p-channel type transistor, The transistor has an active region on the silicon substrate, and the second transistor and the third transistor A transistor is an n-channel type transistor, and consists of a second transistor and a third transistor. The active layer of the photodiode has an oxide semiconductor, and the light-receiving surface of the photodiode is the first surface of the silicon substrate. It is characterized by being located on the opposite side.

[0013] The first and second transistors can constitute a CMOS circuit. .

[0014] The second circuit described above further has a fourth to sixth transistor, and the fourth to sixth transistor The transistor is an n-channel type transistor, and the active layer of the 4th to 6th transistors is made of oxide semiconductor material. Having a conductor, one of the sources or drains of the third transistor is the photodiode Electrically connected to the node or cathode, and to the source or drain of the third transistor. The other end is electrically connected to either the source or drain of the fourth transistor, and the third The source or drain of the transistor is electrically connected to the gate of the fifth transistor. The source or drain of the fifth transistor is connected to the source of the sixth transistor. It may be electrically connected to either the spool or the drain.

[0015] The oxide semiconductor layer consists of In, Zn, and M (where M is Al, Ti, Ga, Sn, Y, Zr, La). It is preferable that it has Ce, Nd or Hf.

[0016] Furthermore, it is preferable that the crystal orientation on the first surface of the silicon substrate is the (110) plane. . [Effects of the Invention]

[0017] According to one aspect of the present invention, an imaging device capable of imaging under low light conditions can be provided. Alternatively, it is possible to provide an imaging device with a wide dynamic range. Alternatively, resolution It is possible to provide an imaging device with a high degree of precision. Or, it is possible to provide an imaging device with a high degree of integration. This is possible. Alternatively, an imaging device that can be used over a wide temperature range can be provided. Alternatively, an imaging device suitable for high-speed operation can be provided. Or, a low-power imaging device can be provided. We can provide an imaging device. Or, we can provide an imaging device with a high aperture ratio. Alternatively, a low-cost imaging device can be provided. Alternatively, a highly reliable imaging device can be provided. It can be provided.

[0018] Furthermore, the description of these effects does not preclude the existence of other effects. The embodiment does not necessarily have to have all of these effects. Furthermore, other effects are... This will become clear from the description in the specification, drawings, claims, etc., and the specification, drawings Furthermore, it is possible to extract other effects from the descriptions in the claims and other documents. [Brief explanation of the drawing]

[0019] [Figure 1] Cross-sectional and circuit diagrams illustrating the imaging device. [Figure 2] A cross-sectional view illustrating the imaging device. [Figure 3] A diagram illustrating the configuration of the imaging device. [Figure 4] A diagram illustrating the drive circuit of the imaging device. [Figure 5] A diagram illustrating the configuration of a pixel circuit. [Figure 6] A timing chart illustrating the operation of the pixel circuit. [Figure 7] A diagram illustrating the configuration of a pixel circuit. [Figure 8]A diagram illustrating the configuration of a pixel circuit. [Figure 9] A diagram illustrating the configuration of a pixel circuit. [Figure 10] A diagram to explain an integrating circuit. [Figure 11] A diagram illustrating the configuration of a pixel circuit. [Figure 12] A diagram illustrating the configuration of a pixel circuit. [Figure 13] A diagram illustrating the configuration of a pixel circuit. [Figure 14] A diagram illustrating the configuration of a pixel circuit. [Figure 15] A diagram illustrating the configuration of a pixel circuit. [Figure 16] A timing chart illustrating the operation of global shutter and rolling shutter systems. [Figure 17] Top view and cross-sectional view illustrating a transistor. [Figure 18] Top view and cross-sectional view illustrating a transistor. [Figure 19] Top view and cross-sectional view illustrating a transistor. [Figure 20] Top view and cross-sectional view illustrating a transistor. [Figure 21] Top view and cross-sectional view illustrating a transistor. [Figure 22] Top view and cross-sectional view illustrating a transistor. [Figure 23] A diagram illustrating the cross-section of a transistor in the channel width direction. [Figure 24] A diagram illustrating the cross-section of a transistor along its channel length. [Figure 25] A diagram illustrating the cross-section of a transistor along its channel length. [Figure 26] A diagram illustrating the cross-section of a transistor in the channel width direction. [Figure 27] Top view and cross-sectional view illustrating the semiconductor layer. [Figure 28] Top view and cross-sectional view illustrating the semiconductor layer. [Figure 29] Top view and cross-sectional view illustrating a transistor. [Figure 30] Top view and cross-sectional view illustrating a transistor. [Figure 31] Top view and cross-sectional view illustrating a transistor. [Figure 32] Top view and cross-sectional view illustrating a transistor. [Figure 33] Top view and cross-sectional view illustrating a transistor. [Figure 34] Top view and cross-sectional view illustrating a transistor. [Figure 35] A diagram illustrating the cross-section of a transistor in the channel width direction. [Figure 36] A diagram illustrating the cross-section of a transistor along its channel length. [Figure 37] A diagram illustrating the cross-section of a transistor along its channel length. [Figure 38] A diagram illustrating the cross-section of a transistor in the channel width direction. [Figure 39] A top view illustrating a transistor. [Figure 40] A diagram illustrating the method for manufacturing transistors. [Figure 41] A diagram illustrating the method for manufacturing transistors. [Figure 42] A diagram illustrating the method for manufacturing transistors. [Figure 43] A diagram illustrating the method for manufacturing transistors. [Figure 44] A diagram illustrating the cross-sectional view and band structure of a transistor. [Figure 45] A diagram illustrating the computational model. [Figure 46] A diagram illustrating the initial and final states. [Figure 47] A diagram illustrating the activation barrier. [Figure 48] A diagram illustrating the initial and final states. [Figure 49] A diagram illustrating the activation barrier. [Figure 50] A diagram illustrating the transition levels of VoH. [Figure 51] A diagram illustrating electronic devices. [Figure 52]A cross-sectional diagram illustrating a transistor. [Figure 53] A cross-sectional diagram illustrating a transistor. [Figure 54] A cross-sectional diagram illustrating a transistor. [Figure 55] A diagram illustrating the image processing engine of an imaging device. [Figure 56] A cross-sectional view illustrating the imaging device. [Figure 57] A cross-sectional view illustrating the imaging device. [Figure 58] A cross-sectional view illustrating the imaging device. [Figure 59] A top view illustrating the photodiode section. [Figure 60] A top view illustrating the photodiode section. [Figure 61] A cross-sectional view illustrating the imaging device. [Figure 62] A top view illustrating the imaging device. [Modes for carrying out the invention]

[0020] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Without departing from the spirit and scope of the present invention, its form and details may be changed in various ways. Those skilled in the art will readily understand that further improvements are possible. Therefore, the present invention can be implemented as follows: The description of the form is not to be interpreted as being limited to the content of the description. Furthermore, the structure of the invention described below In this context, the same reference numeral is used for identical parts or parts having similar functions across different drawings. It is used in this way, and the explanation of its repetition may be omitted. Note that the same elements that make up the figure Matching may be omitted or modified as appropriate between different drawings.

[0021] Furthermore, in this specification, etc., when it is explicitly stated that X and Y are connected, X When X and Y are electrically connected, and when X and Y are functionally connected, This includes the case where X and Y are directly connected. Here, X and Y are objects (for example) For example, it is assumed to be a device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc. Therefore And, not limited to predetermined connection relationships, for example, connection relationships shown in a diagram or text, but also including diagrams or This includes relationships other than those explicitly stated in the text.

[0022] One example of a case where X and Y are electrically connected is the ability to make an electrical connection between X and Y possible. Elements such as switches, transistors, capacitive elements, inductors, resistive elements, and dies. One or more devices (such as diodes, display elements, light-emitting elements, and loads) are connected between X and Y. Yes, it is possible. Furthermore, a switch has the function of being controlled to be on or off. In other words, a switch The switch can be in a conductive (on) or non-conductive (off) state, allowing current to flow. It has a function to control whether or not current flows. Alternatively, the switch selects the path through which current flows. It has a function to switch between modes.

[0023] One example of a functional connection between X and Y is enabling a functional connection between X and Y. Circuits that perform this function (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signal transformers) Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (electric (Source circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of a signal, etc.) Voltage source, current source, switching circuit, amplification circuit (which can increase signal amplitude or current amount, etc.) Circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc., signal generation One or more circuits (such as memory circuits and control circuits) can be connected between X and Y. For example, even if another circuit is placed between X and Y, the signal output from X If the signal is transmitted to Y, then X and Y are assumed to be functionally connected.

[0024] Note that if it is explicitly stated that X and Y are connected, it means that X and Y are electrically connected. If this is the case (i.e., if X and Y are connected with another element or circuit in between) (when X and Y are functionally connected) and when X and Y are functionally connected (i.e., when there is no other circuit between X and Y) (When they are functionally connected with a sash in between) and when X and Y are directly connected (that is (including cases where X and Y are connected without another element or circuit in between) Therefore, if you explicitly state that they are electrically connected, then simply state that they are connected. This is equivalent to the case where it is explicitly stated only that it is.

[0025] Note that, in circuit diagrams, independent components are shown as being electrically connected to each other. Even in such cases, one component may possess the functions of multiple components. For example, if part of the wiring also functions as an electrode, one conductive film will function as the wiring, and It possesses the functions of both components of the electrode. Therefore, in this specification Electrically connected means that a single conductive film combines the functions of multiple components. This also falls under that category.

[0026] For example, the source (or first terminal, etc.) of the transistor is connected via Z1 (and (Without intervening), electrically connected to X, and the drain of the transistor (or second terminal, etc.) However, if Y is electrically connected via (or without) Z2, or if a transistor The source (or first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 It is directly connected to X, and the drain (or second terminal, etc.) of the transistor is connected to Z2. If one part is directly connected to Z2, and another part of Z2 is directly connected to Y, then: It can be expressed as follows.

[0027] For example, "X and Y and the source (or first terminal, etc.) and drain (or The second terminal, etc., is electrically connected to each other, and X is the source of the transistor ( (or the first terminal, etc.), the transistor's drain (or the second terminal, etc.), and Y in that order. It can be expressed as, "It is electrically connected." Or, "The source of the transistor." (or the first terminal, etc.) is electrically connected to X and the drain of the transistor (or The second terminal (or other terminal) is electrically connected to Y, and X is the source of the transistor (or the first terminal). Y is electrically connected to the drain (or second terminal, etc.) of the transistor in this order. It can be expressed as "X is connected to the source of the transistor ( or via the first terminal (or the second terminal, etc.) and the drain (or the second terminal, etc.), Y is electrically connected. Connected, X, the source of the transistor (or the first terminal, etc.), the slave of the transistor It can be expressed as "N (or the second terminal, etc.), Y are provided in this connection order." Yes, it is possible. Using similar notation to these examples, the order of connections in a circuit configuration can be specified. By defining the source (or first terminal, etc.) and drain (and The technical scope can be determined by distinguishing between (the second terminal, etc.) and other components. The methods of representation are examples only and are not limited to these methods. Here, X, Y, Z1, Z2 is the object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.) Let's assume there is.

[0028] (Embodiment 1) In this embodiment, an imaging device, which is one aspect of the present invention, will be described with reference to the drawings.

[0029] Figure 1 is a cross-sectional view showing the configuration of an imaging device according to one embodiment of the present invention. The imaging device shown in Figure 1(A) The structure consists of a transistor 51 having an active region on a silicon substrate 40, and an oxide semiconductor layer as the active layer. Transistors 52 and 53, and provided on the silicon substrate 40 Includes a photodiode 60. Each transistor and photodiode 60 is enclosed in an insulating layer. It has an embedded conductor 70 and electrical connections with each wiring layer. The anode 61 of the cord 60 has an electrical connection with the conductor 70 via a low-resistance region 63. .

[0030] Furthermore, the low-resistance region 63 is formed in a p-type region where impurities are added to the silicon substrate 40. It is possible, but as shown in Figure 58(A), metal may be used instead. Also, Figure 58(B) As shown in ( ), the metal may be provided so as to penetrate the p-type region.

[0031] Note that the electrical connection configuration in the above elements is just one example. Also, they are provided on the same plane. Alternatively, wiring and electrodes provided in the same process shall use the same reference numeral, and only representative parts shall be indicated. A symbol is assigned to each component. Furthermore, the entire conductor 70 embedded in the insulating layer is assigned the same symbol. The number shall be used. Also, on the drawing, each wiring, each electrode, and the conductor 70 shall be shown as individual components. Although they are shown as individual elements, those that are electrically connected are considered to be the same element. In some cases, it may be established in this way.

[0032] Furthermore, the imaging device includes a transistor 51 and a photodiode provided on the silicon substrate 40. A first layer 1100 having a code 60 and an optical control layer 64, and a wiring layer 71 and an insulating layer 81 A second layer 1200 having 82, transistor 52, transistor 53 and insulating layer A third layer 1300 having 83, and a wiring layer 72, a wiring layer 73, and insulating layers 84, 85. It comprises a fourth layer 1400. (First layer 1100, second layer 1200, third layer 1) Layers 300 and the fourth layer 1400 are stacked in that order.

[0033] Furthermore, if some of the above wiring components are not provided, or if other wiring components or transistors are not provided, It may also be included in each layer. In addition, layers other than those mentioned above may be included in the laminated structure. Furthermore, some of the above layers may not be included. Also, insulating layers 81 to 85 are interlayer It functions as an insulating film.

[0034] Furthermore, the side surface of the photodiode 60 in the first layer 1100 is surrounded by the light control layer 64. The optical control layer 64 also acts as an element isolation layer between adjacent photodiodes. Light incident on the photodiode 60 from the light-receiving surface toward the side is reflected by the light control layer 64. Or it can be attenuated. Therefore, the photodiode 60 of the adjacent pixel This prevents light from entering, allowing for the acquisition of images with less noise.

[0035] For the light control layer 64, it is preferable to use a material with a lower refractive index than silicon. For example, For example, aluminum oxide, magnesium oxide, silicon oxide, silicon oxide nitride, silicon nitride Silicon, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, dioxide Examples of lanthanum oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide Insulators can be used. Additionally, organic materials such as acrylic resin and polyimide can be used. This is also good. By using a material with a lower refractive index than silicon, the side of the photodiode 60 Light incident on it is more likely to undergo total internal reflection. Also, instead of the above materials, air, nitrogen, oxygen, aluminum... Gases such as gon and helium may also be used, and in this case, the pressure may be lower than atmospheric pressure. stomach.

[0036] As the light control layer 64, a material that easily absorbs light may be used. For example, carbon black Carbon-based black pigments such as cucumber, titanium-based black pigments such as titanium black, iron oxides, copper Materials such as chromium composite oxides and copper, chromium, and zinc composite oxides are added. Resins and the like can be used.

[0037] Furthermore, as shown in Figure 58(C), a portion of the side surface of the photodiode 60 is the light control layer 64. It is not necessary to include it. Here, tungsten, tantalum, titanium, aluminum are used in the low-resistance region 63. By using metals such as aluminum, incident light is reflected, allowing it to function as a light control layer. This can be done. Alternatively, metals with low reflectivity, such as molybdenum or chromium, may be used.

[0038] Furthermore, as shown in Figure 58(D), a metal can be provided so as to penetrate the optical control layer 64. Furthermore, a portion of the metal in the light control layer 64 is electrically connected to the anode 61 of the photodiode 60. It can be connected.

[0039] Furthermore, the depth direction of the portion (photodiode section) shown by the dashed line A1-A2 in Figure 1(A) The top view is shown, for example, in Figures 59(A), (B), (C), (D), (E), and (F). It can take on such a form.

[0040] Figure 59(A) shows that the upper surface shape of the light-receiving portion 60p of the photodiode 60 is approximately rectangular, and A light control layer 64 is provided around it.

[0041] Figure 59(B) shows that the upper surface shape of the light-receiving section 60p is roughly rectangular, with a fragmentary optical control layer around it. 64 is provided. Note that the light receiving section 60p in Figures 59(A) and (B) is shown as a roughly square. However, a roughly rectangular or trapezoidal shape is also acceptable.

[0042] Figure 59(C) is an example of a top view of the photodiode section in the configuration shown in Figure 58(C). .

[0043] Figure 59(D) shows that the upper surface shape of the light-receiving section 60p is approximately hexagonal, and a light control layer 64 is provided around it. It's being kicked.

[0044] Figure 59(E) shows that the upper surface shape of the light-receiving section 60p is approximately triangular, and a light control layer 64 is provided around it. It's being kicked.

[0045] Figure 59(F) shows that the upper surface shape of the light-receiving section 60p is approximately circular, and a light control layer 64 is provided around it. It is being done.

[0046] Furthermore, even in the configurations shown in Figures 59(C) to 59(F), the optical control layer 64 is provided in fragments. It may also be configured to allow for this. Furthermore, even if the light-receiving part 60p is a polygon or ellipse other than those described above. good.

[0047] Furthermore, the low-resistance region 63 is replaced with a configuration having metal, as shown in Figure 58(B). This is possible. In addition, the light control layer 64 has a configuration that includes metal, as shown in Figure 58(D). It can be replaced.

[0048] As described above, the side of the photodiode is covered with the light control layer 64, etc., so various angles Light incident from a certain angle toward the side of the photodiode 60 is reflected inside the photodiode 60. It can be projected or attenuated.

[0049] Furthermore, the low-resistance region 63 can be shared by multiple photodiodes (multiple pixels). By sharing the low-resistance region 63, the amount of wiring can be reduced. For example, see Figure 59. If the upper surface shape of the light-receiving section 60p is approximately rectangular, as shown in Figure 60(A) In this way, the low-resistance region 63 can be shared by four photodiodes.

[0050] Furthermore, if the upper surface shape of the light-receiving section 60p is approximately hexagonal, as shown in Figure 59(D), then Figure 6 As shown in 0(B), the low-resistance region 63 can be shared by three photodiodes. ru.

[0051] Furthermore, if the upper surface shape of the light-receiving section 60p is approximately triangular, as shown in Figure 59(E), then Figure 6 As shown in 0(C), the low-resistance region 63 can be shared by six photodiodes. ru.

[0052] Note that the silicon substrate 40 is not limited to a bulk silicon substrate, but may also be an SOI substrate. In addition, germanium, silicon germanium, and silicon carbide can be used instead of the silicon substrate 40. Gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, organic semiconductors It is also possible to use substrates made from human body material.

[0053] In the above stacked structure, the first layer has a transistor 51 and a photodiode 60. Between 1100 and the third layer 1300 having transistors 52 and 53 An insulating layer 80 is provided therein.

[0054] Hydrogen in the insulating layer located near the active region of transistor 51 is dangling of silicon The bond is terminated. Therefore, the hydrogen has the effect of improving the reliability of transistor 51. There is also the oxide semiconductor which is the active layer of transistors 52 and 53, etc. Hydrogen in the insulating layer located near the layer is one of the factors that generate carriers in the oxide semiconductor. Therefore, the hydrogen will improve the reliability of transistors 52 and 53, etc. Transitions using silicon-based semiconductor materials can sometimes be a factor that causes a decrease. One layer having a transistor and the other layer having a transistor made of an oxide semiconductor are stacked. In such cases, it is preferable to provide an insulating layer 80 between them that has the function of preventing the diffusion of hydrogen. The insulating layer 80 confines hydrogen in one layer, thereby improving the reliability of the transistor 51. This can improve the process. Furthermore, the diffusion of hydrogen from one layer to the other is suppressed. This also allows for simultaneous improvement of the reliability of transistors 52 and 53, etc. .

[0055] Examples of insulating layer 80 include aluminum oxide, aluminum oxide nitride, gallium oxide, Gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, nitrogen oxide Hafnium oxide, yttria-stabilized zirconia (YSZ), etc., can be used.

[0056] The transistor 52 and photodiode 60 above form a circuit 91, and transistor 5 1 and transistor 53 form circuit 92. Circuit 91 functions as a pixel circuit. This allows circuit 92 to function as a drive circuit for driving circuit 91. It is possible.

[0057] Circuit 91 can be configured, for example, as shown in the circuit diagram in Figure 1(B). The source or drain of the zista 52 and the cathode 62 of the photodiode 60 are electrically connected. They are connected in a manner, with the source or drain of transistor 52 being the other, and transistor 54 (Figure The gate of transistor 1(A) (not shown in Figure 1(A)), and the socket of transistor 55 (not shown in Figure 1(A)) Either the casing or the drain is electrically connected to the charge storage unit (FD).

[0058] The charge storage unit specifically includes the sources of transistors 52 and 53. This is composed of the depletion layer capacitance of the drain, the gate capacitance of transistor 54, and the wiring capacitance, etc. It will be done.

[0059] Here, transistor 52 controls the charge storage unit (FD) in response to the output of photodiode 60. It can function as a transfer transistor for controlling the potential. Rangista 54 is an amplifying transistor that outputs a signal corresponding to the potential of the charge storage unit (FD). It can also function as a charge storage unit (FD). It can function as a reset transistor that initializes the potential.

[0060] Circuit 92 has a configuration that includes a CMOS inverter, for example, as shown in the circuit diagram in Figure 1(C). It is possible. The gates of transistors 51 and 53 are electrically connected. Also, either the source or drain of transistor 51 is connected to the source of transistor 53. It is electrically connected to either the source or the drain of both transistors. The other end of the drain is electrically connected to a separate wire, i.e., a silicon substrate. A transistor 51 having an active region and a transistor 53 having an oxide semiconductor layer as its active layer. This forms a CMOS circuit.

[0061] In the above imaging device, the transistor 51 having an active region on the silicon substrate 40 is pc Transistors 52 to 55 are of the h-type, with an oxide semiconductor layer as the active layer, and are n- Let's assume it's of type ch.

[0062] In circuit 91, all transistors included in circuit 91 are formed in the third layer 1300. This makes the electrical connection configuration easier and simplifies the manufacturing process. can.

[0063] Furthermore, transistors with oxide semiconductors have extremely low off-current characteristics, so imaging The dynamic range can be expanded. In the circuit configuration shown in Figure 1(B), the photo When the intensity of light incident on diode 60 is high, the potential of the charge storage unit (FD) is low. Yes. Transistors using oxide semiconductors have extremely low off-currents, so the gate potential is polar. Even at very low gate potentials, it is possible to accurately output a current corresponding to the gate potential. Therefore, the range of illuminance that can be detected, i.e., the dynamic range, is expanded. It is possible.

[0064] Furthermore, the low off-current characteristics of transistors 52 and 55 allow for charge storage. (FD) allows for an extremely long period during which charge can be held. Therefore, the circuit configuration and A global shutter that performs charge accumulation operation simultaneously at all pixels without complicating the operating method. The method can be applied. Therefore, even if the subject is moving, it is possible to obtain an image with minimal distortion. It can be easily obtained. Also, the global shutter method allows for a shorter exposure time (charge accumulation operation). Since the duration of the imaging process can be extended, it is also suitable for imaging in low-light environments.

[0065] Furthermore, transistors using oxide semiconductors are more electrically efficient than transistors using silicon. Because the temperature dependence of the characteristic changes is small, it can be used over an extremely wide temperature range. Therefore, imaging devices and semiconductor devices having transistors made of oxide semiconductors are automatic It is also suitable for installation in cars, aircraft, spacecraft, and other similar devices.

[0066] Furthermore, transistor 52 and transistor for controlling the potential of the charge storage unit (FD) For transistors like the 55, low-noise transistors are preferable. Two-layer or three-layer oxide semiconductors will be used as described later. Transistors with a conductive layer have an embedded channel and exhibit extremely noise-resistant characteristics. It possesses. Therefore, by using this transistor, it is possible to obtain an image with less noise. can.

[0067] Furthermore, in circuit 91, the photodiode 60 provided in the first layer 1100 and the third layer Since the transistors provided at 1300 can be formed to overlap, pixel integration The degree can be increased. In other words, the resolution of the imaging device can be increased. Also, the number In path 91, no transistor is formed on the silicon substrate, therefore the photodiode The area can be increased. Therefore, images with less noise can be produced even in low-light environments. It can be obtained.

[0068] Furthermore, in circuit 92, an n-channel type transient having an active region is present on the silicon substrate 40. Since the saturation process is unnecessary, the formation process of p-wells and n-type impurity regions can be omitted. This allows for a significant reduction in the number of steps involved. Furthermore, the n-channel type transistors in CMOS circuits... The transistor can be fabricated at the same time as the transistor included in the circuit 91 described above.

[0069] The imaging device shown in Figure 1 has a silicon substrate 40 with a surface on which the transistor 51 is formed and It has the light-receiving surface of the photodiode 60 on the opposite side. Therefore, various transistors and This allows for securing an optical path without being affected by wiring, and enables the formation of pixels with a high aperture ratio. Yes, it is possible. Furthermore, the light-receiving surface of the photodiode 60 is the same as the surface on which the transistor 51 is formed. It can also be done this way.

[0070] Furthermore, the structure of the transistor and photodiode in the imaging device in this embodiment This is just one example. Therefore, for example, if the circuit 91 has silicon or the like in the active region or active layer It can also be constructed using transistors. Furthermore, the circuit 92 has an oxide semiconductor layer as the active layer. It can also be constructed with a transistor having [a specific feature]. Alternatively, the photodiode 60 can be made of amorphous material. The recon layer can also be configured as a photoelectric conversion layer. Furthermore, an active region can be formed on the silicon substrate 40. The transistor 51 having this feature can also be an n-channel type.

[0071] Figure 2(A) is a cross-sectional view of an example of the imaging device shown in Figure 1(A) with the addition of a color filter, etc. This is a view. The cross-sectional view shows the region (region 91a, region 91b) having a circuit 91 with 3 pixels. The region 91c) and region 92a, which has part of the circuit 92, are shown. First layer 11 An insulating layer 1500 is formed on the photodiode 60 formed on 00. 00 can use silicon oxide films or the like that have high light transmittance to visible light. A configuration in which silicon nitride films are laminated as the suction film may also be used. Alternatively, a configuration in which dielectric films such as hafnium oxide are stacked may be used. See Figure 56(A As shown in (), a configuration without an insulating layer 1500 is also possible.

[0072] A light-shielding layer 1510 is formed on the insulating layer 1500. The light-shielding layer 1510 is the upper color It has the effect of preventing the mixing of colors of light passing through the filter. Also, the light-shielding layer 1 on region 92a 510 is a silicon substrate 40 that has a transistor whose characteristics change due to light irradiation. It also has a preventative effect. The light-shielding layer 1510 contains metal layers such as aluminum and tungsten. Alternatively, the metal layer and a dielectric film having the function of an anti-reflective coating can be laminated together. It is possible. Furthermore, as shown in Figure 56(B), it is also possible to have a configuration without the light-shielding layer 1510. Cut.

[0073] An organic resin layer 1520 is formed as a planarization film on the insulating layer 1500 and the light-shielding layer 1510. Then, color filters 153 are applied to regions 91a, 91b, and 91c, respectively. 0a, color filter 1530b, and color filter 1530c are formed in pairs. This is done. Color filter 1530a, color filter 1530b and color filter 1 By assigning colors such as R (red), G (green), and B (blue) to each of the 530c units, A color image can be obtained. As shown in Figure 56(C), the organic resin layer 152 It is also possible to have a configuration without 0. Also, as shown in Figure 56(D), the insulating layer 150 0. It is also possible to omit the light-shielding layer 1510 and the organic resin layer 1520. Although not shown, two of the following are used: insulating layer 1500, light-shielding layer 1510, and organic resin layer 1520. It is also possible to configure the system without including this feature.

[0074] Color filter 1530a, color filter 1530b, and color filter 1530c A microlens array 1540 is provided on top. Therefore, the microlens array The light passing through each lens of the 1540 passes through the color filter directly below, and the photodiode It will be irradiated to the dot.

[0075] Furthermore, as shown in Figure 57(A), a light-shielding layer 1510 is provided between each color filter. You can leave it.

[0076] Furthermore, as shown in Figure 57(B), the boundaries of each lens in the microlens array 1540 A light-shielding layer 1510 may be provided to cover the boundary.

[0077] Furthermore, as shown in Figure 57(C), the light-shielding layer 1510 is omitted, and the light control layer 64 is each The configuration may extend even between the color filters.

[0078] Furthermore, as shown in Figure 57(D), the light-shielding layer 1510 is omitted, and the light control layer 64 is micro-ray The configuration may extend to the spaces between each lens in the 1540 lens array.

[0079] Furthermore, as shown in Figure 61(A), the optical control layer 64 extends across the entire depth of the photodiode 60. Instead, it is formed to cover the side surface of the photodiode 60 in a portion of the side closest to the light-receiving surface. It may also be done. Also, as shown in Figure 61(B), in a part on the side farther from the light-receiving surface It may be formed to cover the side surface of the photodiode 60. Note that region 66 is silica It may be part of the capacitor substrate 40 and part of the configuration of the photodiode 60.

[0080] Figure 62(A) shows a top view of the photodiode 60 and the optical control layer 64. Figure 62 (B) shows the top view of the light-shielding layer 1510. Figure 62(C) shows the top view of the color filter 1530. A diagram is shown. Figure 62(D) is included in Figures 62(A), (B), (C) and circuit 91. This is a diagram showing the transistor 50 superimposed. The transistor 50 included in circuit 91 is Since it can be formed in overlap with the photodiode 60, the aperture ratio of the photodiode 60 It can be increased.

[0081] A support substrate 1600 is provided in contact with the fourth layer 1400. , semiconductor substrates such as silicon substrates, glass substrates, metal substrates, ceramic substrates and other hard substrates A plate can be used. Furthermore, an adhesive layer is provided between the fourth layer 1400 and the support substrate 1600. An inorganic insulating layer or an organic resin layer may be formed therein.

[0082] Furthermore, circuits 91 and 92 and external power supply circuits and control circuits are separated by the fourth layer 1400. The connection can be made using wiring layer 72 or wiring layer 73.

[0083] In the configuration of the imaging device described above, color filter 1530a, color filter 1530b Furthermore, instead of the color filter 1530c, an optical conversion layer 1550 (see Figure 2(B)) is used. This allows for the creation of an imaging device that can obtain images in various wavelength ranges.

[0084] For example, if a filter that blocks light with wavelengths below visible light is used in the optical conversion layer 1550, infrared It can be used as an imaging device. Furthermore, the optical conversion layer 1550 blocks light with wavelengths below near-infrared. By using a filter, it can be made into a far-infrared imaging device. Also, the optical conversion layer 1550 By using a filter that blocks light with wavelengths greater than visible light, it can be converted into an ultraviolet imaging device. .

[0085] Furthermore, when using an infrared imaging device, the bandgear of the photoelectric conversion layer of the photodiode 60 Germanium may be added to narrow the opening and improve sensitivity to infrared radiation. Furthermore, when used as an ultraviolet imaging device, a wide bandgap oxide semiconductor layer, etc., is used for photoelectric imaging. It may be used in the conversion layer to improve sensitivity to ultraviolet light.

[0086] Furthermore, if a scintillator is used in the optical conversion layer 1550, radiation can be used in X-ray imaging devices, etc. It can be used as an imaging device to obtain an image that visualizes the strength of the lines. When radiation enters a scintillator, a phenomenon called photoluminescence occurs. It is converted into light (fluorescence) such as visible light and ultraviolet light. Then, this light is converted into a photodiode 6 Image data is acquired by detecting a value of 0. Furthermore, this configuration is used to capture images of radiation detectors, etc. An imaging device may be used.

[0087] When a scintillator is irradiated with radiation such as X-rays or gamma rays, it absorbs that energy. It consists of a substance that emits visible light or ultraviolet light, or a material containing such a substance. For example, Gd2O 2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, C Materials such as sI, CaF2, BaF2, CeF3, LiF, LiI, ZnO, and those materials It is known to be dispersed in resins and ceramics.

[0088] Figure 3 is a conceptual diagram showing the configuration of the imaging device. The pixel matrix 1700 has circuit 91. Circuits 1730 and 1740 are located on the side. Circuit 1730 is, for example, a reset It can be used as a drive circuit for a transistor. In this case, circuit 1730 and Figure The transistor 55 in 1(B) is electrically connected. Circuit 1740 is, for example, It can be used as a drive circuit for a transfer transistor. In this case, circuit 1740 and In Figure 1(B), transistor 52 is electrically connected. Note that in Figure 3, circuit 17 The diagram shows a configuration in which circuit 30 and circuit 1740 are separated and arranged, but circuit 1 is in one area The 730 and circuit 1740 may be arranged together in a configuration that combines them.

[0089] Furthermore, a circuit 1750 is connected to the pixel matrix 1700. The circuit 1750 is, for example, It functions as a drive circuit that selects the vertical output line electrically connected to transistor 54. It is possible.

[0090] Furthermore, a circuit 1760 may be connected to the pixel matrix 1700. The circuit 1760 is For example, the circuit 1750 may have functions such as being divided into circuits, power supply circuits, or memory circuits. This is possible. Furthermore, it is also possible to configure the system without circuit 1760.

[0091] An example of the specific positional relationship of each of the above circuits is shown in FIG. 3(B). For example, each of circuit 1730, circuit 1740, circuit 1750, and circuit 1760 is provided in, for example, four regions. Note that the position and occupied area of each circuit are not limited to the illustrated example. And a pixel matrix 1700 is provided inside the region where these circuits are arranged. The signal lines, power supply lines, etc. connected to each of the pixels of circuit 1730, circuit 1740, circuit 1750, circuit 1760, and pixel matrix 1700 are electrically connected to the wiring formed on the silicon substrate 40. Also, the wiring is electrically connected to a terminal 1 770 formed around the silicon substrate 40. The terminal 1770 formed on the silicon substrate 40 can be electrically connected to an external circuit by wire bonding or the like. Circuit 1730 and circuit 1740 are drive circuits with a binary output of "Low" or "High". Therefore, as shown in FIG. 4(A), it can be driven by a combination of a shift register 1800 and a buffer circuit

[0092] 1900. Also, as shown in FIG. 4(B), circuit 1750 can be constituted by a shift register 1810, a buffer circuit 1910, and an analog switch 2100. Each vertical output line 21

[0093] 10 is selected by the analog switch 2100, and the potential of the selected vertical output line 2110 is output to the output line 2200. The analog switch 2100 is sequentially selected by the shift register 1810 and the buffer circuit 1910. of the selected vertical output line 2110 is output to the output line 2200. The analog switch 2100 is sequentially selected by the shift register 1810 and the buffer circuit 1910.

[0094] <00009s to be sequentially selected. In one aspect of the present invention, all or part of circuit 1730, circuit 1740, and circuit 1750 The configuration includes circuit 92. That is, the above shift register 1800, buffer circuit 1900, shift register 1810, buffer circuit 1910, and analog switch 2 All or any of the 100 are p-ch type transients having an active region on the silicon substrate 40. CMOS circuits are formed using n-channel transistors with a stylus and an oxide semiconductor layer as the active layer. It holds.

[0095] In this embodiment, one aspect of the present invention has been described. Or, other embodiments may be described. In this section, one aspect of the present invention will be described. However, this aspect of the present invention is not limited to these. It is not possible. For example, one aspect of the present invention has been shown as an example of its application to an imaging device, but this invention One aspect of the present invention is not limited thereto. Depending on the circumstances, the present invention may also be described in some cases or situations. One embodiment does not need to be applied to an imaging device. For example, one embodiment of the present invention has another function. It may also be applied to semiconductor devices.

[0096] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0097] (Embodiment 2) In this embodiment, the circuit 91 described in Embodiment 1 will be explained.

[0098] Figure 5(A) shows the detailed configuration of the circuit 91 and its connections to various wires, as shown in Figure 1(B). The circuit shown in (A) includes a photodiode 60, transistor 52, transistor 54, and The configuration includes a transistor 55 and a transistor 56.

[0099] The anode of photodiode 60 is connected to wire 316, and the cathode is connected to transistor 52. Connected to either the source or drain of transistor 52. The other end is connected to the charge storage unit (FD), and the gate is connected to wiring 312 (TX). Either the source or drain of the transistor 54 is connected to wiring 314 (GND), and the source The other end of either the source or drain is connected to either the source or drain of transistor 56. The gate is connected to the charge storage unit (FD). The source or drain of transistor 55 One end is connected to the charge storage unit (FD), and the other end of the source or drain is connected to wiring 317. The gate is then connected to wiring 311 (RS). The source or drain of transistor 56 The other end of the input is connected to wiring 315 (OUT), and the gate is connected to wiring 313 (SE). All of the above connections are electrical connections.

[0100] Furthermore, potentials such as GND, VSS, and VDD may be supplied to wiring 314. Therefore, potential and voltage are relative. Thus, the magnitude of the potential of GND is not necessarily It is not necessarily true that the voltage is 0 volts.

[0101] The photodiode 60 is a light-receiving element that generates a current corresponding to the light incident on the pixel circuit. It can have a function. Transistor 52 stores charge by photodiode 60. It can have the function of controlling the charge accumulation in the part (FD). Transistor 54 is an electric It can have a function to output a signal corresponding to the potential of the load storage unit (FD). Transistor 55 has the function of resetting the potential of the charge storage unit (FD). Transistor 56 performs an operation to control the selection of the pixel circuit during readout. It can have a function.

[0102] Note that the charge storage unit (FD) is a charge holding node and holds charges that change according to the amount of light received by the photodiode 60.

[0103] Note that the transistor 54 and the transistor 56 can be connected in series between the wiring 315 and the wiring 314. They may be arranged in the order of the wiring 314, the transistor 54, the transistor 56, and the wiring 315, or in the order of the wiring 314, the transistor 56, the transistor 54, and the wiring 315.

[0104] The wiring 311 (RS) can function as a signal line for controlling the transistor 55. The wiring 312 (TX) can function as a signal line for controlling the transistor 52. The wiring 313 (SE) can function as a signal line for controlling the transistor 56. The wiring 314 (GND) can function as a signal line for setting a reference potential (e.g., GND). The wiring 315 (OUT) can function as a signal line for reading out the signal output from the transistor 54. The wiring 316 can function as a signal line for outputting charges from the charge storage unit (FD) via the photodiode 60 and is a low potential line in the circuit of FIG. 5(A). Also, the wiring 317 can function as a signal line for resetting the potential of the charge storage unit (FD) and is a high potential line in the circuit of FIG. 5(A).

[0105] Also, the circuit 91 may have the configuration shown in FIG. 5(B). The circuit shown in FIG. 5(B) has the same components as the circuit shown in FIG. 5(A), but the anode of the photodiode 60 is the tra ​ The photodiode 60 is electrically connected to either the source or drain of the converter 52. It differs in that its cathode is electrically connected to wiring 316. In this case, wiring 316 is As a signal line for supplying charge to the charge storage unit (FD) via the diode 60, It has the ability to be a high-potential line in the circuit of Figure 5(B). Also, wiring 317 is a low-potential line. Yes.

[0106] Next, we will explain the configuration of each element shown in Figures 5(A) and (B).

[0107] The photodiode 60 has pn-type or pin-type junctions formed on the silicon substrate. Elements can be used.

[0108] Transistors 52, 54, 55, and 56 are Silicon semiconductors such as amorphous silicon, microcrystalline silicon, polycrystalline silicon, and monocrystalline silicon It is possible to form it using a body, but it is formed using an oxide semiconductor transistor. This is preferable. Transistors in which a channel formation region is formed with an oxide semiconductor are extremely It has the characteristic of exhibiting low current.

[0109] In particular, transistors 52 and 55 connected to the charge storage unit (FD) If the leakage current is large, the time for which the charge stored in the charge storage unit (FD) can be held is insufficient. Therefore, transistors using oxide semiconductors in at least these two transistors will disappear. By using a charge generator, unwanted charge outflow from the charge storage unit (FD) is prevented. It is possible.

[0110] Furthermore, in transistors 54 and 56, if the leakage current is large, the distribution Unnecessary charge output occurs in line 314 or wiring 315, so these transistors and Therefore, it is preferable to use a transistor in which a channel formation region is formed with an oxide semiconductor. .

[0111] An example of the operation of the circuit in Figure 5(A) will be explained using the timing chart shown in Figure 6(A). I will reveal it.

[0112] In Figure 6(A), for simplicity, the potential of each wire is given as a binary signal. However, since each potential is an analog signal, in reality, it can be a variety of values, not just binary, depending on the situation. It is possible to obtain this. Note that signal 701 shown in the figure is the potential of wiring 311 (RS), and signal 702 is the wiring The potential of 312(TX) is signal 703, the potential of wiring 313(SE) is signal 704, and the charge storage is signal 704. The potential of section (FD), signal 705 corresponds to the potential of wiring 315 (OUT). Note that wiring 3 The potential of 16 is always "Low," and the potential of wiring 317 is always "High."

[0113] At time A, the potential of wiring 311 (signal 701) is set to "High", and the potential of wiring 312 ( When signal 702) is set to "High", the potential of the charge storage unit (FD) (signal 704) is... The potential is initialized to 317 ("High"), and the reset operation begins. Note that wiring 3 The potential of 15 (signal 705) should be pre-charged to "High".

[0114] At time B, setting the potential of wiring 311 (signal 701) to "Low" triggers a reset operation. The process ends and the storage operation begins. At this point, the photodiode 60 is marked with a reverse bias. As a result of the applied reverse current, the potential (signal 704) of the charge storage unit (FD) begins to decrease. When light is shone on the photodiode 60, the reverse current increases, so when light is shone on it... The rate at which the potential (signal 704) of the charge storage unit (FD) decreases changes depending on the amount of light. In other words, depending on the amount of light irradiated onto the photodiode 60, the source and destination of the transistor 54 are controlled. The channel resistance between the rains changes.

[0115] At time C, setting the potential of wiring 312 (signal 702) to "Low" terminates the storage operation. And the potential (signal 704) of the charge storage unit (FD) remains constant. Here, the potential is the stored It is determined by the amount of charge generated by the photodiode 60 during operation. It changes depending on the amount of light shining on the 60. Also, transistor 52 and transistor The 55 is a transistor with an extremely low off-current, formed by creating a channel formation region in an oxide semiconductor layer. Because it is composed of transistors, charge storage occurs until the subsequent selection operation (readout operation) is performed. It is possible to maintain a constant potential in the FD (Functional Diode).

[0116] Furthermore, when the potential of wiring 312 (signal 702) is set to "Low", wiring 312 and charge storage Due to the parasitic capacitance between the charge storage area (FD) and the surrounding area, a change occurs in the potential of the charge storage area (FD). There is a possibility that if the change in the potential is large, a photodiode 60 will be generated during the storage operation. This means that the amount of charge cannot be accurately obtained. To reduce the amount of change in the potential, Reduces the gate-source (or gate-drain) capacitance of ZISTA 52, Trans Measures include increasing the gate capacitance of sta54 and providing a holding capacitance in the charge storage unit (FD). This is effective. In this embodiment, these measures allow the change in potential to be ignored. It is assumed to be so.

[0117] At time D, when the potential of wiring 313 (signal 703) is set to "High", transistor 56 When conductivity is established, the selection operation begins, and wiring 314 and wiring 315 connect to transistor 54 and transistor 54. It conducts through the zista 56. Then the potential of the wiring 315 (signal 705) decreases. Let's go. Also, the pre-charging of wiring 315 should be completed before time D. Here, The rate at which the potential of wiring 315 (signal 705) decreases depends on the source and slave of transistor 54. It depends on the current between the terminals. That is, the photodiode 60 is irradiated during the storage operation. It changes depending on the amount of light.

[0118] At time E, when the potential of wiring 313 (signal 703) is set to "Low", the transistor When 56 is interrupted, the selection operation ends, and the potential of wiring 315 (signal 705) becomes constant. That value changes depending on the amount of light irradiated onto the photodiode 60. Therefore, By obtaining the potential of wiring 315, the photodiode 60 is illuminated during the storage operation. It is possible to determine the amount of light.

[0119] More specifically, if the light irradiating the photodiode 60 is strong, the charge storage unit (FD) The potential of ) that is, the gate voltage of transistor 54 decreases. Therefore, the transistor The current flowing between the source and drain of 54 decreases, and the potential of wiring 315 (signal 705) It decreases slowly. Therefore, a relatively high potential can be read from wiring 315. can.

[0120] Conversely, if the light irradiating the photodiode 60 is weak, the potential of the charge storage unit (FD) In other words, the gate voltage of transistor 54 increases. Therefore, the so The current flowing between the drain increases, and the potential of wiring 315 (signal 705) decreases rapidly. Lower the voltage. Therefore, a relatively low potential can be read from wiring 315.

[0121] Next, using the timing chart shown in Figure 6(B), we will explain an example of the operation of the circuit in Figure 5(B). Let me explain. Note that the potential of wiring 316 is always "High", and the potential of wiring 317 is always "L". Let's call it "ow".

[0122] At time A, the potential of wiring 311 (signal 701) is set to "High", and the potential of wiring 312 ( When signal 702) is set to "High", the potential of the charge storage unit (FD) (signal 704) is... The potential is initialized to 317 ("Low"), and the reset operation begins. Note that wiring 31 The potential of point 5 (signal 705) should be pre-charged to "High".

[0123] At time B, setting the potential of wiring 311 (signal 701) to "Low" triggers a reset operation. The process ends and the storage operation begins. At this point, the photodiode 60 is marked with a reverse bias. As a result of the applied current, the potential (signal 704) of the charge storage unit (FD) begins to rise due to the reverse current. Mel.

[0124] For operations from time C onward, please refer to the explanation of the timing chart in Figure 6(A). At time E, by acquiring the potential of wiring 315, the photodiode 60 during the storage operation It is possible to determine the amount of light that was shining on it.

[0125] Furthermore, circuit 91 may have the configuration shown in Figures 7(A) and (B).

[0126] The circuit shown in Figure 7(A) has the same configuration as the circuit shown in Figure 5(A), but with transistor 55 and wiring 31 This configuration omits wiring 6 and wiring 317, and wiring 311(RS) is for photodiode 60 It is electrically connected to the anode. The rest of the configuration is the same as the circuit shown in Figure 5(A).

[0127] The circuit shown in Figure 7(B) has the same components as the circuit shown in Figure 7(A), but the photodiode The anode of Ode 60 is electrically connected to either the source or drain of transistor 52. And, at the point where the cathode of the photodiode 60 is electrically connected to wiring 311(RS) different.

[0128] The circuit in Figure 7(A) is similar to the circuit in Figure 5(A) in that it follows the timing chart shown in Figure 6(A). It can be made to work.

[0129] At time A, the potential of wiring 311 (signal 701) is set to "High", and the potential of wiring 312 ( When signal 702) is set to "High", a forward bias is applied to the photodiode 60. Then, the potential (signal 704) of the charge storage unit (FD) becomes "High". The potential of the integrand (FD) is initialized to the potential of wiring 311 (RS) ("High"), and then reset. The state becomes "T". This completes the reset operation. Note that the potential of wiring 315 (signal 705) ) should be precharged to "High".

[0130] At time B, setting the potential of wiring 311 (signal 701) to "Low" triggers a reset operation. The process ends and the storage operation begins. At this point, the photodiode 60 is marked with a reverse bias. As a result of the applied reverse current, the potential (signal 704) of the charge storage unit (FD) begins to decrease. Mel.

[0131] For the operation after time C, please refer to the circuit operation explanation in Figure 5(A), and at time E... By obtaining the potential of wiring 315, the photodiode 60 is illuminated during the storage operation. It is possible to determine the amount of light present.

[0132] The circuit in Figure 7(B) can be operated using the timing chart shown in Figure 6(C).

[0133] At time A, the potential of wiring 311 (signal 701) is set to "Low", and the potential of wiring 312 (signal When parameter 702) is set to "High", a forward bias is applied to the photodiode 60. Then, the potential (signal 704) of the charge storage unit (FD) resets to "Low". The reset operation has begun. Note that the potential of wiring 315 (signal 705) is set to "High". Precharge it.

[0134] At time B, setting the potential of wiring 311 (signal 701) to "High" triggers a reset operation. The process ends and the storage operation begins. At this point, the photodiode 60 is given a reverse bias. Because a current is applied, the potential (signal 704) of the charge storage unit (FD) rises due to the reverse current. start.

[0135] For the operation after time C, please refer to the circuit operation explanation in Figure 5(A), and at time E... By obtaining the potential of wiring 315, the photodiode 60 is illuminated during the storage operation. It is possible to determine the amount of light present.

[0136] Note that in Figures 5(A), (B) and 7(A), (B), transistor 52 is provided. An example of such a case has been shown, but one aspect of the present invention is not limited thereto. Figures 8(A), (B As shown in (), it is also possible to omit transistor 52.

[0137] Furthermore, the transistor used in circuit 91 is as shown in Figure 9(A) or Figure 9(B), The transistors 52, 54, and 56 are equipped with back gates. It may be a configuration. Figure 9(A) shows a configuration in which a constant potential is applied to the back gate, and the threshold The voltage can be controlled. Also, Figure 9(B) shows that the back gate has the same potential as the front gate. This configuration is applied to the circuit and can increase the on-current. Note that Figure 9(A) In this example, the back gate is electrically connected to wiring 314 (GND). It may also be electrically connected to another wiring to which a constant potential is supplied. Note that, as shown in Figure 9(A), B) shows an example in which a back gate is provided to the transistor in the circuit shown in Figure 7(A). The same configuration is also applicable to the circuits shown in Figures 5(A), (B), 7(B), and 8(A), (B). It can also be used as a front gate for a transistor included in a single circuit. A configuration in which the same potential is applied to the back gate, a configuration in which a constant potential is applied to the back gate, Alternatively, a circuit configuration can be arbitrarily combined as needed, including a configuration without a back gate. stomach.

[0138] In the circuit example described above, wiring 315 (OUT) is connected to Figures 10(A), (B), ( An integrating circuit as shown in C) may be connected. This circuit will integrate the readout signal. This improves the signal-to-noise ratio, allowing for the detection of even weaker light. In other words, the imaging device It can increase the sensitivity of the sensor.

[0139] Figure 10(A) shows an integration circuit using an operational amplifier (also called an op-amp). The inverting input terminal of the width circuit is connected to wiring 315 (OUT) via a resistor R. The non-inverting input terminal of the amplifier circuit is connected to ground potential. The output terminal of the operational amplifier circuit is connected to a capacitance. The inverting input terminal of the operational amplifier circuit is connected via element C.

[0140] Figure 10(B) shows an integral circuit using an operational amplifier circuit with a different configuration than that of Figure 10(A). The inverting input terminal of the operational amplifier circuit is wired to 315 (OUT) via a resistor R and a capacitor C1. The non-inverting input terminal of the operational amplifier circuit is connected to ground potential. The output terminal of the circuit is connected to the inverting input terminal of the operational amplifier circuit via the capacitive element C2.

[0141] Figure 10(C) uses an operational amplifier circuit with a different configuration than those in Figures 10(A) and 10(B). This is an integral circuit. The non-inverting input terminal of the operational amplifier circuit is wired 315 through a resistor R. It is connected to the OUT terminal. The output terminal of the operational amplifier is connected to the inverting input terminal of the operational amplifier. It is done. Furthermore, the resistive element R and the capacitive element C constitute a CR integral circuit. Also, the operational amplifier circuit... The path constitutes a unity-gain buffer.

[0142] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0143] (Embodiment 3) In this embodiment, a transistor is used to initialize the potential of the charge storage unit (FD), and the charge storage unit ( A transistor that outputs a signal corresponding to the potential of the FD, and each wire (signal line) between pixels ( The circuit configuration when the circuit (91) is used for both purposes will be explained.

[0144] The pixel circuit shown in Figure 11 is similar to the circuit shown in Figure 5(A) in that it uses transistor 52 (transfer transistor (Functions as a transistor), transistor 54 (Functions as an amplifying transistor), transistor 55 (functions as a reset transistor), transistor 56 (functions as a selection transistor) Each pixel has a function, and one photodiode 60. Also, wiring 311 ( Wiring 312 (which functions as a signal line to control transistor 55) to transistor 52 Wiring 313 (functions as a signal line for control), signal to control transistor 56 Wiring 314 (functions as a line), Wiring 315 (functions as a high-potential line), Transistor 54 (Functions as a signal line for reading the signal output from), wiring 316 (reference potential line (G The ND (Nutrient Distortion) is electrically connected to the pixel circuit.

[0145] In the circuit shown in Figure 5(A), wire 314 is connected to GND and wire 317 is connected to a high-potential line. As shown in the example, in the pixel circuit, wiring 314 is a high-potential line (for example, VDD), and wiring By connecting the other of the source or drain of transistor 56 to 314, wiring 317 It has been omitted. Also, wiring 315 (OUT) is reset to a low potential.

[0146] Between the first line of pixel circuitry and the second line of pixel circuitry, wiring 3 is used as shown below. 14. Wiring 315 and 316 can be shared, and depending on the operation method, wiring 31 It is also possible to share 1.

[0147] Figure 12 shows transistor 5 for four pixels in vertically adjacent lines 1 through 4. 4. Vertical 4-pixel sharing, which also serves as transistor 55, transistor 56, and wiring 311. The type configuration is shown. By reducing the number of transistors and wiring, the pixel area is reduced. Miniaturization and yield can be improved. The other side of the source or drain of transistor 52, and the source or drain of transistor 55 One side of the input and the gate of transistor 54 are electrically connected to the charge storage unit (FD). The transistor 52 of each pixel is operated sequentially, and the storage operation and readout operation are repeated. This allows data to be acquired from all pixels.

[0148] Figure 13 shows the transistor 54 for four adjacent pixels in the horizontal and vertical directions. Transistor 55, transistor 56, wiring 313, and wiring 311 are shared vertical and horizontal 4 This shows a pixel-sharing configuration. Similar to the vertical 4-pixel sharing configuration, the transistors and wiring are... Reducing the number of pixels allows for miniaturization by shrinking the pixel area and improving yield. and the source or drain of transistor 52 in four vertically adjacent pixels On the other hand, either the source or drain of transistor 55, and the source of transistor 54. The Pixel is electrically connected to the Charge Storage Unit (FD). The transistor 52 of each pixel is sequentially connected. By operating the system and repeatedly performing storage and reading operations, data can be acquired from all pixels. It is possible.

[0149] Figure 14 shows the transistor 54 for four adjacent pixels in the horizontal and vertical directions. A structure that combines transistor 55, transistor 56, wiring 311, and wirings 312 and 314. This demonstrates success. It is a circuit that further shares wiring 312 in addition to the previously mentioned vertical and horizontal 4-pixel shared type. The four pixels adjacent horizontally and vertically (the first row consists of two pixels adjacent horizontally). The source or drain of transistor 52, and the other side of the source of transistor 55. Alternatively, one of the drains and the gate of transistor 54 can electrically connect to the charge storage unit (FD). It is connected to. Also, this circuit configuration has two transfer transistors positioned vertically. (Transistor 52) shares wiring 312, so not only horizontally but also vertically A key feature is that there are transistors operating simultaneously in both directions.

[0150] Note that, although it differs from the configuration described above which shares transistors and signal lines, photodiode It is also possible to configure a pixel circuit with multiple pixels.

[0151] For example, as shown in the pixel circuit in Figure 15(A), the wiring 316 and the source of transistor 52 Or between one of the drains, the photodiodes 60a, 60b, 60c and the transistor Transistors 58a, 58b, 58c, etc. are provided. Transistors 58a, 58b, 58c are A switch to select the photodiodes 60a, 60b, and 60c that are connected to each of them. It has the function of a photodiode and a switch. The example uses three transistor combinations, but is not limited to this. For example, as shown in Figure 15(B), it can also be configured with two units. Of course, four or more units are also possible. But that's fine.

[0152] For example, photodiodes 60a, 60b, and 60c have different sensitivity levels to illuminance. Different types with varying characteristics can be used, and they can be adapted to different environments from low to high light levels. A photodiode suitable for imaging in various conditions is selected. For example, a photodiode for high-light conditions is selected for its suitability for imaging in various light conditions. A combination of light-reducing filters can be used so that the output is linear. Furthermore, multiple photodiodes may be selected and operated.

[0153] Furthermore, photodiodes 60a, 60b, and 60c each have different sensitivities to different wavelengths. It is possible to use materials that have the following characteristics, and in each wavelength from ultraviolet to far infrared A filter suitable for imaging is selected. For example, a filter that transmits the wavelength range to be detected and a photo By combining diodes, imaging can be performed using ultraviolet light, visible light, and infrared light. It is possible to switch between imaging and other functions.

[0154] Furthermore, the photodiodes in the pixel circuit use multiple photodiodes with different light-receiving area sizes. This is also good. In a configuration with two photodiodes, for example, if the light-receiving area is 1:10 or 1: Different values ​​can be used, such as 100, depending on the ratio. In photodiodes, the series resistance is The output current value may saturate due to influences, etc. In this case, Ohm's law The smaller the current value, the better the linearity with respect to illuminance. Therefore, sensitivity is usually high. To achieve this, imaging is performed using a photodiode with a large light-receiving area, and in environments with high illumination, light reception is performed. Imaging is performed using a photodiode with a small surface area. This allows for high sensitivity and This allows for an imaging device with a wide dynamic range.

[0155] Furthermore, in the configuration of pixels having photodiodes with different light-receiving area areas, see Figure 15( As shown in C), one pixel 90 has photodiodes 60a and 60b with different areas. In addition to the above configuration, as shown in Figure 15(D), there are photodiodes 6 with different areas for every 90 pixels. 0a and 60b may be arranged alternately.

[0156] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0157] (Embodiment 4) This embodiment describes an example of a method for driving a pixel circuit.

[0158] As described in Embodiment 2, the operation of the pixel circuit is a reset operation, an accumulation operation, and a selection It is a repetition of selection operations. As an imaging method that controls the entire pixel matrix, global Shutter shutter and rolling shutter shutter methods are known.

[0159] Figure 16(A) is a timing chart for the global shutter system. 16(A) has multiple pixel circuits arranged in a matrix, and the circuit shown in Figure 5(A) is located in the pixel circuit. As an example of an imaging device having the following, the pixel circuits from the first row to the nth row (where n is a natural number greater than or equal to 3) This explains the operation of [the device]. Note that the operation description below is based on Figures 5(B), 7(A), and 7(B). ), and it can also be applied to the circuits shown in Figures 8(A) and (B).

[0160] In Figure 16(A), signals 501, 502, and 503 are in the first row, the second row, This is the signal input to wiring 311(RS) connected to each pixel circuit in the nth row. Signals 504, 505, and 506 are transmitted to the pixel circuits of the first row, second row, and nth row. This is the signal input to the connected wiring 312 (TX). Also, signals 507 and 508 Signal 509 is connected to wiring 313 ( connected to each pixel circuit of the 1st row, 2nd row, and nth row). This is the signal input to SE.

[0161] Furthermore, period 510 is the time required for one image capture. Also, period 511 is the time required for each row of pixels. This is the period during which the circuit is simultaneously performing a reset operation. Also, period 520 is the number of pixels in each row. This is the period during which the path is simultaneously performing the accumulation operation. The selection operation is performed sequentially by the pixel circuit of each row. For example, period 531 is the period during which the pixel circuit of the first row is performing a selection operation. Yes. In this way, in the global shutter system, the reset operation is performed almost simultaneously in all pixel circuits. After this, the storage operation is performed almost simultaneously in all pixel circuits, and the read operation is performed sequentially for each row. It can be done.

[0162] In other words, in a global shutter system, the accumulation operation is performed almost simultaneously in all pixel circuits. Therefore, the simultaneity of imaging in the pixel circuit of each row is ensured. Even with moving objects, it is possible to obtain images with minimal distortion.

[0163] On the other hand, Figure 16(B) is a timing chart when using a rolling shutter method. For details on signals 501 to 509, please refer to the explanation in Figure 16(A). Period 6 10 is the time required for one imaging. Periods 611, 612, and 613 are respectively This is the reset period for the first row, the second row, and the nth row. Also, period 621, period 622 Periods 623 represent the accumulation operation periods for the first, second, and nth rows, respectively. Period 631 is the period during which the pixel circuit in the first row is performing a selection operation. In the ring shutter method, the accumulation operation is not performed simultaneously in all pixel circuits, but sequentially row by row. Therefore, the simultaneity of imaging in the pixel circuit of each row cannot be ensured. Therefore, the first row And in the last row, the timing of the image capture is different, so if the subject is a moving object, the image will be highly distorted. It will turn into a statue.

[0164] In order to implement a global shutter system, the reading of signals from each pixel must be completed sequentially. Until then, the potential of the charge storage unit (FD) needs to be maintained for a long time. The long-term retention is achieved by forming a channel formation region in an oxide semiconductor in transistor 52, etc. This can be achieved by using a transistor with extremely low off-current. On the other hand, transistor 52 When a transistor with a channel formation region formed in silicon or the like is applied, it turns off. Due to the high current, the potential of the charge storage unit (FD) cannot be maintained for a long time, and the global shutter method It becomes difficult to use the formula.

[0165] As described above, the pixel circuit uses a transistor in which the channel formation region is formed of an oxide semiconductor. This makes it easy to implement a global shutter system.

[0166] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0167] (Embodiment 5) In this embodiment, a transient having an oxide semiconductor that can be used in one aspect of the present invention The sta will be explained using drawings. Note that in the drawings of this embodiment, for clarity, Some elements are enlarged, reduced, or omitted in the illustration for illustrative purposes.

[0168] Figures 17(A) and (B) show a top view and a cross-sectional view of a transistor 101 according to one embodiment of the present invention. Yes. The cross-section in the direction of the dashed line B1-B2 shown in Figure 17(A) corresponds to Figure 17(B). Furthermore, the cross-section in the direction of the dashed line B3-B4 shown in Figure 17(A) corresponds to Figure 23(A). The direction of the dashed line B1-B2 is the channel length direction, and the direction of the dashed line B3-B4 is the channel width direction. It is sometimes referred to as such.

[0169] The transistor 101 has an insulating layer 120 that is in contact with the substrate 115, and an oxide layer that is in contact with the insulating layer 120. A monocrystalline semiconductor layer 130, a conductive layer 140 that is electrically connected to the oxide semiconductor layer 130, and a conductive Layer 150, oxide semiconductor layer 130, conductive layer 140, and insulating layer 1 in contact with conductive layer 150 60, conductive layer 170 in contact with insulating layer 160, conductive layer 140, conductive layer 150, insulating layer 1 60 and an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175 , and also, if necessary, an insulating layer 190 (planarized film) in contact with the insulating layer 180. It is acceptable to have it.

[0170] Here, the conductive layer 140 is the source electrode layer, the conductive layer 150 is the drain electrode layer, and the insulating layer 160 is The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0171] Furthermore, region 231 shown in Figure 17(B) is the source region, region 232 is the drain region, and region 2 Region 33 can function as a channel-forming region. Regions 231 and 232 are guided The conductive layer 140 and the conductive layer 150 are in contact with each other, and the conductive layer 140 and the conductive layer 150 By using a conductive material that readily bonds with oxygen, the resistance of regions 231 and 232 can be reduced. It is possible.

[0172] Specifically, the oxide semiconductor layer 130 and the conductive layer 140 and conductive layer 150 come into contact with each other. Oxygen vacancies occur within the oxide semiconductor layer 130, and these oxygen vacancies remain within the oxide semiconductor layer 130. Due to interactions with hydrogen that is either distilled or diffused from the outside, regions 231 and 232 have low resistance. It becomes an n-type resistance.

[0173] Furthermore, the "source" and "drain" functions of a transistor are related to transistors with different polarities. When adopting a circuit, or when the direction of current changes during circuit operation, the configuration may be reversed. Therefore, in this specification, the terms "source" and "drain" are interchangeable. It may be used in this manner. Also, "electrode layer" can be replaced with "wiring." can.

[0174] Furthermore, the diagram illustrates an example in which the conductive layer 170 is formed of two layers, conductive layer 171 and conductive layer 172. However, it may be a single layer or a stack of three or more layers. This configuration will be explained in this embodiment. This can also be applied to other transistors.

[0175] Furthermore, although the diagram shows examples where the conductive layer 140 and conductive layer 150 are formed as a single layer, two or more layers are also shown. The above stacking may also be used. This configuration is also applicable to other transistors described in this embodiment. can.

[0176] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 18(A) and (B). Figure 18(A) is a top view of transistor 102, and the dashed line C shown in Figure 18(A) The cross-section in the direction of 1-C2 corresponds to Figure 18(B). Also, the dashed line C3 shown in Figure 18(A) -The cross-section in the C4 direction corresponds to Figure 23(B). Also, the dashed line C1-C2 direction is channeled The direction of the channel length and the direction of the dashed line C3-C4 are sometimes referred to as the channel width direction.

[0177] The transistor 102 has an insulating layer 160 that acts as a gate insulating film and a gate electrode layer. Except for the fact that it does not coincide with the edge of the conductive layer 170 which acts as a transistor, it is the same as transistor 101. It has the following configuration. The structure of transistor 102 is such that conductive layer 140 and conductive layer 150 are insulated Because it is broadly covered by the edge layer 160, the conductive layer 140 and conductive layer 150 and conductive layer 170 It has the characteristic of high resistance between the terminals and low gate leakage current.

[0178] Transistors 101 and 102 have conductive layers 170 and 140 and This is a top gate structure having a region where the electrochemical layer 150 overlaps. The width is preferably 3 nm or more and less than 300 nm in order to reduce parasitic capacitance. On the other hand, since no offset region is formed in the oxide semiconductor layer 130, the on-current is high. It easily forms a radiator.

[0179] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 19(A) and (B). Figure 19(A) is a top view of transistor 103, and the dashed line D shown in Figure 19(A) The cross-section in the 1-D2 direction corresponds to Figure 19(B). Also, the dashed line D3 shown in Figure 19(A) -The cross-section in the D4 direction corresponds to Figure 23(A). Also, the dashed line D1-D2 direction is channeled The direction of the channel length and the direction of the dashed line D3-D4 are sometimes referred to as the channel width direction.

[0180] Transistor 103 has an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. A material semiconductor layer 130, an insulating layer 160 in contact with the oxide semiconductor layer 130, and an insulating layer 160 in contact with The conductive layer 170, the oxide semiconductor layer 130, the insulating layer 160, and the insulating layer covering the conductive layer 170 are all connected. Edge layer 175, insulating layer 180 in contact with insulating layer 175, insulating layer 175 and insulating layer 180 A conductive layer 140 is electrically connected to the oxide semiconductor layer 130 through an opening provided therein. It also has a conductive layer 150. Furthermore, an insulating layer 180, a conductive layer 140, and a conductive layer may be added as needed. It may have an insulating layer 190 (planarized film) in contact with 150.

[0181] Here, the conductive layer 140 is the source electrode layer, the conductive layer 150 is the drain electrode layer, and the insulating layer 160 is The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0182] Furthermore, region 231 shown in Figure 19(B) is the source region, region 232 is the drain region, and region 2 Region 33 can function as a channel-forming region. Regions 231 and 232 are absolute It is in contact with the edge layer 175, and if, for example, an insulating material containing hydrogen is used as the insulating layer 175, the region Regions 231 and 232 can be made to have lower resistance.

[0183] Specifically, the process up to forming the insulating layer 175 generates in regions 231 and 232 The interaction between the oxygen deficiency and the hydrogen diffusing from the insulating layer 175 to regions 231 and 232 As a result of this action, regions 231 and 232 become low-resistance n-type. Note that this is an insulating material containing hydrogen. Materials such as silicon nitride films and aluminum nitride films can be used.

[0184] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 20(A) and (B). Figure 20(A) is a top view of transistor 104, and the dashed line E shown in Figure 20(A) The cross-section in the direction of 1-E2 corresponds to Figure 20(B). Also, the dashed line E3 shown in Figure 20(A) -The cross-section in the E4 direction corresponds to Figure 23(A). Also, the dashed line E1-E2 direction is channeled The direction of the channel length and the direction of the dashed line E3-E4 are sometimes referred to as the channel width direction.

[0185] Transistor 104 has conductive layers 140 and 150 at the edges of oxide semiconductor layer 130. Except for the fact that it is in contact with the other element in a way that covers it, it has the same configuration as transistor 103.

[0186] Furthermore, regions 331 and 334 shown in Figure 20(B) are the source region, region 332 and Region 335 can function as a drain region, and region 333 can function as a channel-forming region. Regions 331 and 332 are regions 231 and 23 in transistor 101. Similar to 2, the resistance can be reduced. Also, regions 334 and 335 are transistors Similar to regions 231 and 232 in Ta 103, the resistance can be reduced. Preferably, the lengths of regions 334 and 335 in the channel length direction are 100 nm or less. For wavelengths of 50 nm or less, the on-current does not decrease significantly due to the contribution of the gate field. Alternatively, a configuration that does not involve the resistance reduction described above can also be used.

[0187] Transistors 103 and 104 have conductive layers 170 and 140 and It is a self-aligned structure in which the electrolytic layer 150 does not have any overlapping regions. The lampistor has extremely low parasitic capacitance between the gate electrode layer and the source and drain electrode layers. Therefore, it is suitable for high-speed operation applications.

[0188] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 21(A) and (B). Figure 21(A) is a top view of transistor 105, and the dashed line F shown in Figure 21(A) The cross-section in the 1-F2 direction corresponds to Figure 21(B). Also, the dashed line F3 shown in Figure 21(A) -The cross-section in the F4 direction corresponds to Figure 23(A). Also, the channel length is in the direction of the dashed line F1-F2. The direction indicated by the dashed line F3-F4 is sometimes referred to as the channel width direction.

[0189] Transistor 105 has an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. A monocrystalline semiconductor layer 130, a conductive layer 141 that is electrically connected to the oxide semiconductor layer 130, and a conductive Layer 151, oxide semiconductor layer 130, conductive layer 141, insulating layer 160 in contact with conductive layer 151 And, a conductive layer 170 in contact with the insulating layer 160, an oxide semiconductor layer 130, a conductive layer 141, and a conductive layer. An insulating layer 175 that is in contact with layer 151, insulating layer 160 and conductive layer 170, and an insulating layer 175 that is in contact with The insulating layer 180 and the insulating layer 175 and the insulating layer 180 are conductive through openings provided in them. Conductive layers 142 and 15 are electrically connected to layer 141 and conductive layer 151, respectively. It has 2. It also comes into contact with the insulating layer 180, the conductive layer 142 and the conductive layer 152 as needed. It may have an insulating layer 190 (planarized film), etc.

[0190] Here, conductive layers 141 and 151 are in contact with the upper surface of the oxide semiconductor layer 130, and the sides The configuration is such that it does not come into contact with anything.

[0191] The transistor 105 has conductive layers 141 and 151, and insulating layers 175 and The insulating layer 180 has an opening, and the conductive layer 14 is accessible through the opening. It has conductive layers 142 and 152 that are electrically connected to conductive layer 151 and conductive layer 151, respectively. It has the same configuration as transistor 101, except for the following point. Conductive layer 140 (conductive layer 141 The conductive layer 142) can be used as a source electrode layer, and the conductive layer 150 (conductive Layer 151 and conductive layer 152 can be used as drain electrode layers.

[0192] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 22(A) and (B). Figure 22(A) is a top view of transistor 106, and the dashed line G shown in Figure 22(A) The cross-section in the 1-G2 direction corresponds to Figure 22(B). Also, the dashed line G3 shown in Figure 22(A) -The cross-section in the G4 direction corresponds to Figure 23(A). Also, the dashed line G1-G2 direction is channeled. The direction of the channel length and the direction of the dashed line G3-G4 are sometimes referred to as the channel width direction.

[0193] Transistor 106 has an insulating layer 120 that is in contact with the substrate 115 and an oxide layer that is in contact with the insulating layer 120. A monocrystalline semiconductor layer 130, a conductive layer 141 that is electrically connected to the oxide semiconductor layer 130, and a conductive Layer 151, an insulating layer 160 in contact with the oxide semiconductor layer 130, and a conductive layer in contact with the insulating layer 160. Layer 170, insulating layer 120, oxide semiconductor layer 130, conductive layer 141, conductive layer 151, insulating An insulating layer 175 in contact with layer 160, conductive layer 170, and an insulating layer 180 in contact with insulating layer 175. Through openings provided in the insulating layer 175 and the insulating layer 180, the conductive layer 141 and the conductive It has conductive layers 142 and 152 that are electrically connected to layer 151, respectively. If necessary, an insulating layer 180, an insulating layer 142, and an insulating layer 190 in contact with the conductive layer 152 (flat It may have a fading film, etc.

[0194] Here, conductive layers 141 and 151 are in contact with the upper surface of the oxide semiconductor layer 130, and the sides The configuration is such that it does not come into contact with anything.

[0195] Transistor 106 has conductive layers 141 and 151, except that the transistor It has the same configuration as Ta 103. The conductive layer 140 (conductive layer 141 and conductive layer 142) is - It can be used as an electrode layer, conductive layer 150 (conductive layer 151 and conductive layer 15 2) can be used as a drain electrode layer.

[0196] In the configuration of transistors 105 and 106, conductive layer 140 and conductive layer 1 Since 50 is not in contact with the insulating layer 120, oxygen in the insulating layer 120 enters the conductive layer 140. Furthermore, it becomes less likely for the conductive layer 150 to absorb acid, and acid from the insulating layer 120 into the oxide semiconductor layer 130 This makes it easier to supply raw materials.

[0197] Furthermore, regions 231 and 232 in transistor 103, and transistor 104 Furthermore, regions 334 and 335 in transistor 106 form oxygen vacancies and conduct Impurities may be added to increase the charge. Impurities that form oxygen vacancies in the oxide semiconductor layer. Examples of materials include phosphorus, arsenic, antimony, boron, aluminum, silicon, and nitrogen. Helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, One or more selected from tungsten, zinc, and carbon may be used. Methods for adding impurities include plasma treatment, ion implantation, ion doping, and plastic Methods such as Smaimerjon ion implantation can be used.

[0198] When the above elements are added to the oxide semiconductor layer as impurity elements, the metal in the oxide semiconductor layer The bonds between elements and oxygen are broken, and an oxygen vacancy is formed. Due to the interaction between elementary defects and hydrogen remaining in or later added in the oxide semiconductor layer, The conductivity of the semiconductor layer can be increased.

[0199] Furthermore, when hydrogen is added to an oxide semiconductor in which an oxygen vacancy has been formed by the addition of impurity elements, Hydrogen enters the oxygen-deficient site, and a donor level is formed near the conduction band. As a result, oxide conduction An electric body can be formed. Here, a conductive oxide semiconductor is used as an oxide conductive semiconductor. It's called an electrostatic body.

[0200] Oxide conductors are degenerate semiconductors in which the conduction band edge and the Fermi level coincide or nearly coincide. It is presumed that there is an oxide conductor layer, a source electrode layer and a drain electrode layer. The contact with the conductive layer that functions is ohmic contact, and the oxide conductive layer and the source electrode layer This reduces the contact resistance with the conductive layer that functions as the drain electrode layer.

[0201] Furthermore, a transistor according to one aspect of the present invention is shown in Figures 24(A), (B), (C) and Figure 25( A), (B), (C) are cross-sectional views in the channel length direction, and Figures 26(A), (B) are shown below. As shown in the cross-sectional view in the channel width direction, there is a conductive gap between the oxide semiconductor layer 130 and the substrate 115. The conductive layer 173 may be a second gate electrode layer (back gate). By using it in this way, it is possible to further increase the on-current and control the threshold voltage. Note that the cross-sections shown in Figures 24(A), (B), (C) and 25(A), (B), (C) are also relevant. In the figure, the width of the conductive layer 173 may be shorter than that of the oxide semiconductor layer 130. Furthermore, The width of the conductive layer 173 may be shorter than the width of the conductive layer 170.

[0202] To increase the ON current, for example, the conductive layer 170 and conductive layer 173 are set to the same potential, double It can be driven as a gate transistor. Also, to control the threshold voltage, A constant potential different from that of the conductive layer 170 should be supplied to the conductive layer 173. To make 73 at the same potential, for example, as shown in Figure 26(B), conductive layer 170 and conductive layer 1 73 can be electrically connected via the contact hole.

[0203] Furthermore, in transistors 101 to 106 in Figures 17 to 22, oxidation Although an example where the material semiconductor layer 130 is a single layer is shown, the oxide semiconductor layer 130 can also be stacked. Good. The oxide semiconductor layer 130 of transistors 101 to 106 is shown in Figure 27. Alternatively, it can be replaced with the oxide semiconductor layer 130 shown in Figure 28.

[0204] Figures 27(A), (B), and (C) show the top view of the two-layer oxide semiconductor layer 130 and This is a cross-sectional view. The cross-section in the direction of the dashed line A1-A2 shown in Figure 27(A) corresponds to Figure 27(B). Furthermore, the cross-section in the direction of the dashed line A3-A4 shown in Figure 27(A) corresponds to Figure 27(C). ru.

[0205] Furthermore, Figures 28(A), (B), and (C) are top views of the oxide semiconductor layer 130, which has a three-layer structure. And a cross-sectional view. The cross-section in the direction of the dashed line A1-A2 shown in Figure 28(A) is shown in Figure 28(B). This corresponds to... Also, the cross-section in the direction of the dashed line A3-A4 shown in Figure 28(A) is shown in Figure 28(C). It corresponds to.

[0206] In oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c, Oxide semiconductor layers with different compositions can be used.

[0207] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 29(A) and (B). Figure 29(A) is a top view of transistor 107, and the dashed line H shown in Figure 29(A) The cross-section in the 1-H2 direction corresponds to Figure 29(B). Also, the dashed line H3 shown in Figure 29(A) -The cross-section in the H4 direction corresponds to Figure 35(A). Also, the dashed line H1-H2 direction is channeled. The direction in the longitudinal direction, or the direction of the dashed line H3-H4, is sometimes referred to as the channel width direction.

[0208] Transistor 107 has an insulating layer 120 that is in contact with the substrate 115, and an oxide layer that is in contact with the insulating layer 120. A stack consisting of a monocrystalline semiconductor layer 130a and an oxide semiconductor layer 130b, and electrically connected to the stack Connecting conductive layer 140 and conductive layer 150, and the laminate, conductive layer 140 and conductive layer 15 The oxide semiconductor layer 130c in contact with 0, and the insulating layer 160 in contact with the oxide semiconductor layer 130c , conductive layer 170 in contact with insulating layer 160, conductive layer 140, conductive layer 150, oxide semiconductor layer 130c, an insulating layer 175 in contact with the insulating layer 160 and the conductive layer 170, and an insulating layer 175 in contact with It has an insulating layer 180 and an insulating layer 190 in contact with the insulating layer 180 as needed. It may have a (planarization film), etc.

[0209] In transistor 107, the oxide semiconductor layer 130 is divided into two regions 231 and 232. In region 233, where the layers are oxide semiconductor layer 130a and oxide semiconductor layer 130b The oxide semiconductor layer 130 consists of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The point is that it is a semiconductor layer 130c), and conductive layer 140 and conductive layer 150 and insulating layer 160 Except for the fact that a portion of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between them, It has the same configuration as the Ranjista 101.

[0210] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 30(A) and (B). Figure 30(A) is a top view of transistor 108, and the dashed line I shown in Figure 30(A) The cross-section in the direction of 1-I2 corresponds to Figure 30(B). Also, the dashed line I3 shown in Figure 30(A) -The cross-section in the I4 direction corresponds to Figure 35(B). Also, the dashed line I1-I2 direction is channel The direction in the longitudinal direction, or the direction of the dashed line I3-I4, is sometimes referred to as the channel width direction.

[0211] The transistor 108 has an insulating layer 160 and an oxide semiconductor layer 130c, with the edges connected to the conductive layer 17. It differs from transistor 107 in that its terminals do not coincide with the zero point.

[0212] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 31(A) and (B). Figure 31(A) is a top view of transistor 109, and the dashed line J shown in Figure 31(A) is the same as the dotted line J. The cross-section in the direction of 1-J2 corresponds to Figure 31(B). Also, the dashed line J3 shown in Figure 31(A) -The cross-section in the J4 direction corresponds to Figure 35(A). Also, the dashed line J1-J2 direction is the channel. The direction in the longitudinal direction, or the direction of the dashed line J3-J4, is sometimes referred to as the channel width direction.

[0213] The transistor 109 has an insulating layer 120 that is in contact with the substrate 115, and an oxide layer that is in contact with the insulating layer 120. A stack consisting of a monocrystalline semiconductor layer 130a and an oxide semiconductor layer 130b, and an acid in contact with the stack. A oxide semiconductor layer 130c, an insulating layer 160 in contact with the oxide semiconductor layer 130c, and an insulating layer 16 A conductive layer 170 in contact with 0, the laminate, oxide semiconductor layer 130c, insulating layer 160 and conductive An insulating layer 175 covering the electrical layer 170, an insulating layer 180 in contact with the insulating layer 175, and the insulating layer 175 and conductive layer 14 which is electrically connected to the laminate through an opening provided in the insulating layer 180. It has a conductive layer 150 and an insulating layer 180, conductive layer 140 and as needed. The conductive layer 150 may have an insulating layer 190 (planarized film) or the like in contact with it.

[0214] In transistor 109, the oxide semiconductor layer 130 is divided into two regions 231 and 232. In region 233, where the layers are oxide semiconductor layer 130a and oxide semiconductor layer 130b The oxide semiconductor layer 130 consists of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide It has the same configuration as transistor 103, except that it is a physical semiconductor layer 130c.

[0215] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 32(A) and (B). Figure 32(A) is a top view of transistor 110, and the dashed line K shown in Figure 32(A) The cross-section in the 1-K2 direction corresponds to Figure 32(B). Also, the dashed line K3 shown in Figure 32(A) -The cross-section in the K4 direction corresponds to Figure 35(A). Also, the dashed line K1-K2 direction is the channel. The direction in the longitudinal direction, or the direction of the dashed line K3-K4, is sometimes referred to as the channel width direction.

[0216] In transistor 110, the oxide semiconductor layer 130 is divided into two regions 331 and 332. In region 333, where the layers are oxide semiconductor layer 130a and oxide semiconductor layer 130b The oxide semiconductor layer 130 consists of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide It has the same configuration as transistor 104, except that it is a solid semiconductor layer (130c).

[0217] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 33(A) and (B). Figure 33(A) is a top view of transistor 111, and the dashed line L shown in Figure 33(A) is the same as the line L The cross-section in the 1-L2 direction corresponds to Figure 33(B). Also, the dashed line L3 shown in Figure 33(A) -The cross-section in the L4 direction corresponds to Figure 35(A). Also, the dashed line L1-L2 direction is the channel. The direction in the longitudinal direction, or the direction of the dashed line L3-L4, is sometimes referred to as the channel width direction.

[0218] The transistor 111 has an insulating layer 120 that is in contact with the substrate 115, and an oxide layer that is in contact with the insulating layer 120. A stack consisting of a monocrystalline semiconductor layer 130a and an oxide semiconductor layer 130b, and electrically connected to the stack Connecting conductive layers 141 and 151, and the laminate, conductive layer 141 and conductive layer 15 A 1 oxide semiconductor layer 130c in contact with 1, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , conductive layer 170 in contact with insulating layer 160, said lamination, conductive layer 141, conductive layer 151, oxidation A semiconductor layer 130c, an insulating layer 160, and an insulating layer 175 in contact with the conductive layer 170, and an insulating layer The insulating layer 180 is in contact with 175, and the openings provided in the insulating layer 175 and the insulating layer 180 Conductive layers 142 and 151 are electrically connected through conductive layer 141 and conductive layer 151, respectively. It has a conductive layer 152. Additionally, an insulating layer 180, a conductive layer 142, and a conductive layer 1 may be provided as needed. It may have an insulating layer 190 (planarized film) in contact with 52.

[0219] In transistor 111, the oxide semiconductor layer 130 is divided into two regions 231 and 232. In region 233, where the layers are oxide semiconductor layer 130a and oxide semiconductor layer 130b The oxide semiconductor layer 130 consists of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The point is that it is a semiconductor layer 130c), and conductive layer 141 and conductive layer 151 and insulating layer 160 Except for the fact that a portion of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between them, It has the same configuration as the Ranjista 105.

[0220] Furthermore, a transistor according to one aspect of the present invention may have the configuration shown in Figures 34(A) and (B). Figure 34(A) is a top view of transistor 112, and the dashed line M shown in Figure 34(A) The cross-section in the 1-M2 direction corresponds to Figure 34(B). Also, the dashed line M3 shown in Figure 34(A) -The cross-section in the M4 direction corresponds to Figure 35(A). Also, the dashed line M1-M2 direction is the channel. The direction in the longitudinal direction, or the direction of the dashed line M3-M4, is sometimes referred to as the channel width direction.

[0221] Transistor 112 is located in regions 331, 332, 334, and 335. The oxide semiconductor layer 130 consists of two layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b). At point 333, the oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide Except for the fact that it is a monocrystalline semiconductor layer 130b and an oxide semiconductor layer 130c, transistor 106 and They have a similar configuration.

[0222] Furthermore, a transistor according to one aspect of the present invention is shown in Figures 36(A), (B), (C) and Figure 37( A), (B), (C) are cross-sectional views in the channel length direction, and Figures 38(A), (B) are shown below. As shown in the cross-sectional view in the channel width direction, there is a conductive gap between the oxide semiconductor layer 130 and the substrate 115. The conductive layer may be used as a second gate electrode layer (back gate). By using this, it is possible to further increase the on-current and control the threshold voltage. In the cross-sectional views shown in Figures 36(A), (B), (C) and 37(A), (B), (C) Furthermore, the width of the conductive layer 173 may be shorter than that of the oxide semiconductor layer 130. The width of 173 may be shorter than the width of the conductive layer 170.

[0223] Furthermore, the conductive layer 140 (source electrode layer) and conductive in a transistor according to one aspect of the present invention Layer 150 (drain electrode layer) has the configuration shown in the top view in Figures 39(A) and (B). This is possible. Note that in Figures 39(A) and (B), the oxide semiconductor layer 130 and the conductive layer 140 And only the conductive layer 150 is shown. As shown in Figure 39(A), the conductive layer 140 and Width (W) of conductive layer 150 SD ) is the width (W) of the oxide semiconductor layer. OS ) is formed to be longer than It may be there. Also, as shown in Figure 39(B), W SD is W OS It is formed to be shorter than That's fine. OS ≥W SD (W SD is W OS By doing the following, the gate electric field becomes oxide semi This makes it easier to apply the coating to the entire conductor layer 130, improving the electrical characteristics of the transistor. ru.

[0224] In one embodiment of the present invention, a transistor (transistors 101 to 112) is Even in the misaligned configuration, the conductive layer 170, which is the gate electrode layer, is an insulating layer, which is the gate insulating film. The oxide semiconductor layer 130 is electrically surrounded in the channel width direction via 160, and the on current is This can be improved. Such a transistor structure is called a surrounded channel This is called an (s-channel) structure.

[0225] Furthermore, a transistor having an oxide semiconductor layer 130b and an oxide semiconductor layer 130c, Furthermore, oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c In a transistor having the oxide semiconductor layer 130, the two or three layers of material By appropriately selecting the material, an electric current can be passed through the oxide semiconductor layer 130b. The current flowing through the conductive layer 130b reduces the effects of interfacial scattering, resulting in a high on-current. This can be achieved. Furthermore, increasing the thickness of the oxide semiconductor layer 130b improves the on-current. This is possible. For example, if the thickness of the oxide semiconductor layer 130b is 100 nm to 200 nm That's good too.

[0226] By using a transistor with the above configuration, good electrical characteristics can be imparted to the semiconductor device. It is possible.

[0227] In this specification, channel length refers, for example, to the half-length of a top view of a transistor. Conductor (or the part of the semiconductor through which current flows when the transistor is ON) and gate In the region where the electrode overlaps, or in the region where the channel is formed, the source (up to the source region) This refers to the distance between the source electrode and the drain (drain region or drain electrode). Note that the channel length in a single transistor is not necessarily the same across all regions. In other words, the channel length of a single transistor may not be fixed to a single value. Therefore, in this specification, the channel length is any one of the regions in which the channel is formed. This can be defined as a value, maximum value, minimum value, or average value.

[0228] Furthermore, channel width refers to, for example, the semiconductor (or transistor) when it is in the ON state. The region where the part through which current flows and the gate electrode overlap, or the region where a channel is formed. This refers to the length of the portion in the region where the source and drain face each other. In a transistor, the channel width is not necessarily the same across all regions. That is, The channel width of a transistor may not be fixed to a single value. Therefore, this specification In the book, the channel width is any one value, the maximum value, in the region where the channel is formed. Use the minimum or average value.

[0229] Furthermore, depending on the transistor structure, the channel may actually be formed in the region where the channel is formed. The channel width (hereinafter referred to as the effective channel width) and the top view of the transistor are shown. The channel width (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, When the gate electrode covers the side of the semiconductor, the effective channel width is greater than the apparent channel width. The effect can become so large that it can no longer be ignored. For example, in a minute gate electrode In transistors where the semiconductor covers the sides, the proportion of the channel region formed on the top surface of the semiconductor is... In contrast, the proportion of the channel region formed on the side surface of the semiconductor can become larger. In this case, the effective channel width will be larger than the apparent channel width.

[0230] In such cases, it can be difficult to estimate the effective channel width through actual measurements. For example, in order to estimate the effective channel width from the design value, the shape of the semiconductor is known. An assumption is necessary. Therefore, if the shape of the semiconductor is not precisely known, the effective method is It is difficult to accurately measure channel width.

[0231] Therefore, in this specification, the apparent channel width is referred to as the "enclosed channel width (SCW:Su It is sometimes referred to as "rounded channel width." Also, in this specification... So, when simply referring to channel width, it means the enclosed channel width or apparent channel width It may refer to the channel width. Or, in this specification, when it is simply referred to as channel width, it refers to the actual It may refer to the effective channel width. Note that channel length, channel width, and effective channel Width, apparent channel width, enclosed channel width, etc., can be determined by analyzing the cross-sectional TEM image. The value can be determined by these factors.

[0232] Furthermore, the field-effect mobility of the transistor and the current value per channel width are calculated to determine this. In some cases, the calculation may be performed using the enclosed channel width. In that case, the effective channel The values ​​may differ from those obtained when calculating using the channel width.

[0233] This embodiment can be appropriately combined with other embodiments shown herein. .

[0234] (Embodiment 6) In this embodiment, the components of the transistor shown in Embodiment 5 will be described in detail. ru.

[0235] The substrate 115 is a silicon substrate on which transistors and photodiodes are formed, and A conductive material that functions as an insulating layer, wiring, and contact plug is formed on the silicon substrate. It is equivalent to the first layer 1100 and the second layer 1200 in Fig. 1(A). When forming a p-ch type transistor on a silicon substrate, it is - preferred to use a silicon substrate having an n type conductivity type. Alternatively, it may be an SOI substrate having an n - type or i-type silicon layer. Also, the surface orientation of the surface on which the transistor is formed in the silicon substrate is preferably the (110) surface. By forming a p-ch type transistor on the (110) surface, the mobility can be increased. The insulating layer 120 has a role of preventing the diffusion of impurities from the elements contained in the substrate 115. In addition, it can play a role of supplying oxygen to the oxide semiconductor layer 130. Therefore, the insulating layer 120 is preferably an insulating film containing oxygen, and more preferably an insulating film containing more oxygen than the stoichiometric composition. For example, by the TDS method performed by heat treatment at a film surface temperature of 100°C or higher and 700°C or lower, preferably 100°C or higher and 500°C or lower, the oxygen release amount in terms of oxygen atoms is 1.0×10 The insulating layer 120 also has a function as an interlayer insulating film, and may be planarized by a method such as CMP (Chemical Mechanical Polishing) so that the surface becomes flat.

[0236] <​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​, nitrous oxide such as silicon nitride, silicon nitride, aluminum nitride, aluminum nitride A dielectric insulating film or a mixture thereof can be used. Furthermore, a lamination of the above materials is also possible. That's fine.

[0238] In this embodiment, the oxide semiconductor layer 130 of the transistor is an oxide semiconductor layer 130a, oxide semiconductor layer 130b and oxide semiconductor layer 130c from the insulating layer 120 side This explanation will primarily focus on the case of a three-layer structure where layers are stacked sequentially.

[0239] In the case of a single layer oxide semiconductor layer 130, the oxide semiconductor layer 13 shown in this embodiment You can use the layer corresponding to 0b.

[0240] Furthermore, if the oxide semiconductor layer 130 consists of two layers, the oxide semiconductor layer 13 shown in this embodiment... The layer corresponding to 0b and the layer corresponding to the oxide semiconductor layer 130c are arranged in order from the insulating layer 120 side. A stacked layer can be used. In this configuration, the oxide semiconductor layer 130b and the oxide semiconductor layer It can also be swapped with 130c.

[0241] Furthermore, if there are four or more oxide semiconductor layers 130, for example, as described in this embodiment... The configuration involves adding another oxide semiconductor layer to the three-layer oxide semiconductor layer 130. It is possible.

[0242] For example, the oxide semiconductor layer 130b contains the oxide semiconductor layer 130a and the oxide semiconductor layer Acids with a higher electron affinity (energy from the vacuum level to the bottom of the conduction band) than body layer 130c. Ion semiconductors are used. Electron affinity is the energy difference between the vacuum level and the top of the valence band (ions). From the potential, the energy difference between the lower end of the conduction band and the upper end of the valence band (energy gap) It can be calculated by subtracting (P).

[0243] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c constitute the oxide semiconductor layer 130b. It contains one or more metallic elements, for example, the energy at the lower end of the conduction band is the oxide semiconductor layer 13 Greater than 0b, at least 0.05eV, 0.07eV, 0.1eV, or 0.15eV. If present, it approaches the vacuum level within the range of 2eV, 1eV, 0.5eV, or 0.4eV. It is preferable to form it with an oxide semiconductor.

[0244] In such a structure, when an electric field is applied to the conductive layer 170, the oxide semiconductor layer 130 A channel is formed in the oxide semiconductor layer 130b, which has the lowest energy at the lower end of the conduction band. ru.

[0245] Furthermore, the oxide semiconductor layer 130a contains one or more of the metal elements that make up the oxide semiconductor layer 130b. Because it is composed of the above, the interface when the oxide semiconductor layer 130b and the insulating layer 120 are in contact In comparison, interface states are formed at the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130a. This becomes less likely to occur. The interface level may form a channel, so the transistor The key voltage may fluctuate. Therefore, an oxide semiconductor layer 130a is provided. This can reduce variations in electrical characteristics such as the threshold voltage of transistors. Furthermore, the reliability of the transistor can be improved.

[0246] Furthermore, the oxide semiconductor layer 130c contains one or more of the metal elements that make up the oxide semiconductor layer 130b. Because it is composed of the above, the oxide semiconductor layer 130b and the gate insulating film (insulating layer 160) are in contact. Compared to the interface in the case of [the other case], the interface between oxide semiconductor layer 130b and oxide semiconductor layer 130c This reduces the likelihood of carrier scattering. Therefore, an oxide semiconductor layer 130c is provided. This allows for an increase in the field-effect mobility of the transistor.

[0247] For example, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c contain Al, Ti, Ga Ge, Y, Zr, Sn, La, Ce, or Hf are used in a material higher than the oxide semiconductor layer 130b. Materials containing the atoms in a specific ratio can be used. Specifically, materials with an atomic ratio of 1.5 times or more are preferred. The ratio should be at least twice, and more preferably at least three times. The aforementioned elements bond strongly with oxygen. Therefore, it has the function of suppressing the occurrence of oxygen vacancies in the oxide semiconductor layer. The monocrystalline semiconductor layer 130a and the oxide semiconductor layer 130c are more acidic than the oxide semiconductor layer 130b. It can be said that primary defects are less likely to occur.

[0248] Furthermore, oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130 The oxide semiconductor that can be used as c contains at least In or Zn. Preferably, it contains both In and Zn. To reduce variations in the electrical characteristics of the transistors, stabilizers were added along with them. It is preferable to include it.

[0249] Stabilizers include Ga, Sn, Hf, Al, or Zr. The tranquilizers include lanthanides such as La, Ce, Pr, Nd, Sm, Eu, and Gd Examples include Tb, Dy, Ho, Er, Tm, Yb, Lu, etc.

[0250] For example, as oxide semiconductors, indium oxide, tin oxide, gallium oxide, zinc oxide, I n-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg Oxides, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al- Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide Materials, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In -Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm- Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In -Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn- Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, I n-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn Oxides can be used.

[0251] For example, in-Ga-Zn oxide is a material whose main components are In, Ga, and Zn. It means an oxide containing In, Ga, and Zn. Good. Also, in this specification, a film composed of In-Ga-Zn oxide is referred to as an IGZO film. They also call them that.

[0252] Also, InMO3(ZnO) m Materials represented as (m>0, and m is not an integer) It may be included. Note that M is one selected from Ga, Y, Zr, La, Ce, or Nd. This indicates a metallic element or multiple metallic elements. Also, In2SnO5(ZnO) n(n>0, and You may also use materials represented by n (where n is an integer).

[0253] Furthermore, oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c are At least indium, zinc, and M(Al, Ti, Ga, Ge, Y, Zr, Sn, La) When it is an In-M-Zn oxide containing a metal such as Ce or Hf, the oxide semiconductor layer 1 30a is In:M:Zn=x1:y1:z1 [atomic ratio], oxide semiconductor layer 130b is I n:M:Zn=x2:y2:z2 [atomic ratio], oxide semiconductor layer 130c is In:M:Z If n = x3:y3:z3 [atomic ratio], then y1 / x1 and y3 / x3 become y2 / x2 It is preferable that y1 / x1 and y3 / x3 are 1 greater than y2 / x2. The ratio should be 5 times or more, preferably 2 times or more, and even more preferably 3 times or more. At this time, the oxide semi In the conductor layer 130b, if y2 is greater than or equal to x2, the electrical characteristics of the transistor are stabilized. This is possible. However, when y2 becomes more than 3 times x2, the field-effect mobility of the transistor Because this would cause a decrease in the value, it is preferable that y2 be less than three times x2.

[0254] In the oxide semiconductor layer 130a and oxide semiconductor layer 130c, the fields excluding Zn and O In the mixture, the atomic ratio of In and M is preferably such that In is less than 50 atomic%, M is 50 atomic% or more, more preferably In is less than 25 atomic%, and M is 7 The atomic content should be 5% or more. Also, the oxide semiconductor layer 130b should be excluding Zn and O. The atomic ratio of In and M is preferably 25 atomic% or more for In and 75 atomic% for M. Less than 0 omic%, more preferably In is 34 atomic% or more, and M is 66 atomic%. It should be less than c%.

[0255] Furthermore, the oxide semiconductor layer 130b is composed of oxide semiconductor layer 130a and oxide semiconductor layer 130 It is desirable to have a higher indium content than carbon. In oxide semiconductors, heavy metals are primarily used for the s-railway. The pathway contributes to carrier conduction, and by increasing the In content, more s-trajectories are formed. Because the pathways overlap, oxides with more In than M are compared to oxides with the same or less In than M. This increases mobility. Therefore, the oxide semiconductor layer 130b has a high indium content. By using oxides, transistors with high field-effect mobility can be realized.

[0256] The thickness of the oxide semiconductor layer 130a is 3 nm or more and 100 nm or less, preferably 5 nm or more. The oxide semiconductor layer 1 is 0 nm or less, more preferably 5 nm to 25 nm. The thickness of 30b is 3 nm to 200 nm, preferably 10 nm to 150 nm. More preferably, the oxide semiconductor layer 130c The thickness is 1 nm to 50 nm, preferably 2 nm to 30 nm, and more preferably The wavelength shall be between 3 nm and 15 nm. In addition, oxide semiconductor layer 130b shall be oxide semiconductor layer 1 It is preferable that the 30a layer is thicker than the oxide semiconductor layer 130c.

[0257] Furthermore, in order to impart stable electrical characteristics to transistors using an oxide semiconductor layer as the channel This involves reducing the impurity concentration in the oxide semiconductor layer and making the oxide semiconductor layer intrinsic (type i) or pure Making it qualitatively intrinsic is effective. Here, substantially intrinsic means the capacitance of the oxide semiconductor layer. Rear density is 1×10 15 / cm 3 It must be less than 1 × 10 13 / cm3 It is less than and 8 x 10 11 / cm 3 Being less than, or 1 × 10 8 / cm 3 It is less than, 1 x 10 -9 / cm 3 The above is sufficient.

[0258] Furthermore, in the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and metals other than the main component are present. Elements act as impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels, making them carrier-dense. This increases the degree of the problem. Furthermore, silicon contributes to the formation of impurity levels in the oxide semiconductor layer. These impurity levels can act as traps, potentially degrading the electrical characteristics of the transistor. Therefore, oxide semiconductor layer 130a, oxide semiconductor layer 130b and oxide semiconductor layer It is preferable to reduce the impurity concentration in the 130c layer and at each interface.

[0259] To make an oxide semiconductor layer intrinsically or substantially intrinsically, SIMS (Secondary The silicon concentration estimated by ion mass spectrometry analysis is 1 x 10 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 less than More preferably 1 × 10 18 atoms / cm 3 Control to have a region that is less than Also, the hydrogen concentration is 2 × 10 20 atoms / cm 3 The following is preferably 5 × 10 1 9 atoms / cm 3 More preferably 1 × 10 19 atoms / cm3 The following, Preferably 5 × 10 18 atoms / cm 3 Control the region to have the following characteristics. Furthermore, the nitrogen concentration is, for example, at a certain depth in the oxide semiconductor layer, or in the oxide semiconductor In a layered region, 5 × 10 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 Below, further Preferably 5 × 10 17 atoms / cm 3 The following applies:

[0260] High concentrations of silicon or carbon can reduce the crystallinity of oxide semiconductor layers. To avoid reducing the crystallinity of the oxide semiconductor layer, for example, the silicon concentration should be set to 1 × 10⁻⁶. 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 Less than, even more preferred Or 1 x 10 18 atoms / cm 3 Control the system so that it has a region that is less than [a certain value]. Carbon concentration 1 × 10 19 atoms / cm 3 Less than 5 × 10 18 atom / cm 3 Less than 1 × 10 18 atoms / cm 3 It has a region that is less than Control it in that way.

[0261] Furthermore, as mentioned above, a transient using a highly purified oxide semiconductor film in the channel formation region The off-current of the sta is extremely small. For example, if the voltage between the source and drain is 0.1V, 5 When set to V or approximately 10V, the off-current per channel width of the transistor is several y. It is possible to reduce the level to A / μm or even a few zA / μm.

[0262] Furthermore, silicon-containing insulating films are often used as gate insulating films for transistors. Therefore, for the reasons stated above, the region that becomes the channel of the oxide semiconductor layer is a transient in one aspect of the present invention. It can be said that a structure that does not come into contact with the gate insulating film, like a sta, is preferable. When a channel is formed at the interface between the insulating film and the oxide semiconductor layer, carrier scattering occurs at the interface. This occurs, and the field-effect mobility of the transistor decreases. From this perspective as well, oxide semiconductors It is preferable to keep the channel region of the conductive layer away from the gate insulating film.

[0263] Therefore, the oxide semiconductor layer 130 is divided into oxide semiconductor layer 130a and oxide semiconductor layer 130b By using a stacked structure of oxide semiconductor layer 130c, channels are formed in oxide semiconductor layer 130b. A transistor can be formed that has high field-effect mobility and stable electrical characteristics. It can form a ta.

[0264] Band structure of oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c In this structure, the energy at the lower end of the conduction band changes continuously. This is because the oxide semiconductor layer 1 By making the compositions of 30a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c similar, This can also be understood from the fact that oxygen readily diffuses between them. Therefore, oxide semiconductor layer 130a The oxide semiconductor layer 130b and oxide semiconductor layer 130c are laminates of layers with different compositions. However, it can also be said that it is continuous in terms of physical properties, and in the drawing, each interface of the laminate It is represented by a dotted line.

[0265] The oxide semiconductor layers 130, which are stacked with a common main component, are not simply stacked one layer at a time. Continuous junctions (in this case, U-shaped junctions where the energy at the lower end of the conduction band changes continuously between each layer) The structure is prepared so that a well structure (U-shaped well) is formed. That is, each layer If impurities that form defect levels such as trap centers or recombination centers are present at the interface A layered structure is formed in such a way. If impurities are mixed between the layers of the stacked oxide semiconductor layers, When this occurs, the continuity of the energy band is lost, and carriers are trapped or re-established at the interface. It disappears due to the combination.

[0266] For example, oxide semiconductor layer 130a and oxide semiconductor layer 130c have In:Ga:Zn= 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4 or 1: In-Ga-Zn oxides such as 9:6 (atomic ratio) can be used. Also, acid The ion semiconductor layer 130b has In:Ga:Zn=1:1:1, 2:1:3, 5:5:6, Alternatively, In-Ga-Zn oxides such as those in an atomic ratio of 3:1:2 can be used. Note that oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130 The atomic ratios of c each include a variation of plus or minus 20% of the above atomic ratios as an error. nothing.

[0267] In the oxide semiconductor layer 130, the oxide semiconductor layer 130b becomes a well, and channel The band is formed in the oxide semiconductor layer 130b. Note that the oxide semiconductor layer 130 is at the lower end of the conduction band. Because the energy changes continuously, it can also be called a U-shaped well. A channel formed with such a configuration can also be called an embedded channel.

[0268] Furthermore, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c, and the silicon oxide film, etc. Near the interface with the insulating layer, trap levels can form due to impurities and defects. Due to the presence of the semiconductor layer 130a and the oxide semiconductor layer 130c, the oxide semiconductor layer 13 This allows us to move 0b away from the trap level.

[0269] However, the energy at the lower end of the conduction band of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c - When the difference between this and the energy at the lower end of the conduction band of the oxide semiconductor layer 130b is small, the oxide semiconductor Electrons in the conductive layer 130b may exceed the energy difference and reach the trap level. When it is trapped in a trap level, a negative charge is generated at the insulating layer interface, and the transistor The threshold voltage shifts in the positive direction.

[0270] The oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c contain: It is preferable that the crystalline portion is included. In particular, using a crystal oriented along the c-axis allows for the creation of transistors. It can impart stable electrical properties. Furthermore, crystals oriented along the c-axis are resistant to distortion. This can improve the reliability of semiconductor devices using flexible substrates.

[0271] Conductive layer 140 acting as source electrode layer and conductive layer 1 acting as drain electrode layer 50 includes, for example, Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc , and a single layer or laminate of a material selected from the alloy of the metal material can be used. Typical examples include Ti, which readily combines with oxygen, and materials that allow for relatively high subsequent processing temperatures. For these reasons, it is preferable to use W, which has a high melting point. Also, low-resistance Cu or Cu-M A laminate of an alloy such as n and the above material may also be used. Note that transistor 105, Trans In transistors 106, 111, and 112, for example, the conductive layer 14 W is used for conductive layer 1 and conductive layer 151, and Ti and Al are used for conductive layer 142 and conductive layer 152. You can use these.

[0272] The above material has the property of extracting oxygen from the oxide semiconductor layer. Therefore, when in contact with the above material... In some regions of the oxide semiconductor layer, oxygen is desorbed from the oxide semiconductor layer, forming an oxygen vacancy. The region becomes n-type when the small amount of hydrogen contained in the layer combines with the oxygen vacancy. Therefore, the n-type region is constructed to function as the source or drain of a transistor. It can be used.

[0273] The insulating layer 160, which acts as a gate insulating film, contains aluminum oxide, magnesium oxide, Silicon oxide, silicon oxide nitride, silicon nitride, silicon nitride, gallium oxide, acid Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, An insulating film containing one or more hafnium oxide and tantalum oxide can be used. The insulating layer 160 may be a laminate of the above materials. Furthermore, the insulating layer 160 may contain La, nitrogen, and Z. It may contain impurities such as r.

[0274] Furthermore, an example of the laminated structure of the insulating layer 160 will be described. The insulating layer 160 is, for example, oxygen It contains nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide, and oxide It is preferable that the material contains silicon or silicon oxide nitride.

[0275] Hafnium oxide and aluminum oxide are compared to silicon oxide and silicon oxide-nitride. It has a high dielectric constant. Therefore, it can be used to make larger films compared to silicon oxide, which is useful for tunnel electricity. This can reduce leakage current due to current. In other words, a transistor with a small off-current can be used. This can be achieved. Furthermore, hafnium oxide having a crystalline structure has an amorphous structure. It has a higher dielectric constant compared to hafnium oxide. Therefore, transistors with low off-current To form the zista, it is preferable to use hafnium oxide having a crystalline structure. Examples of structures include monoclinic and cubic crystal systems. However, one aspect of the present invention is This is not limited to these.

[0276] Incidentally, the surface of hafnium oxide having a crystalline structure has interface states due to defects. This can occur. The interface level functions as a trap center. Therefore, hafny oxide When the element is positioned in close proximity to the channel region of the transistor, the interface level causes the transistor to... The electrical properties of the transistor deteriorate. Therefore, in order to reduce the influence of the interface state, By placing another film between the channel region of the star and the hafnium oxide, they can be separated from each other. It is preferable to leave a gap. This film has a buffering function. The film having a buffering function is an insulating layer. It may be a film contained in 160, or a film contained in an oxide semiconductor film. Examples of films with buffering properties include silicon oxide, silicon oxide nitride, and oxide semiconductors. This can be used. Furthermore, a membrane having a buffering function may have, for example, a channel region. Use a semiconductor or insulator with a larger energy gap than the semiconductor. Alternatively, use a buffer. A film with this capability may, for example, be made of a semiconductor with a lower electron affinity than the semiconductor that forms the channel region. A body or insulator is used. Alternatively, a film having a buffering function may have, for example, a channel region and A semiconductor or insulator with a higher ionization energy than the semiconductor is used.

[0277] On the other hand, the interface state (trap) on the surface of hafnium oxide having the above-described crystal structure By trapping charge at the center, the threshold voltage of the transistor can be controlled. There is a combination. In order to keep the charge stable, for example, the channel region and the hafny oxide Between the um and the hafnium oxide, a semiconductor or insulator with a larger energy gap than hafnium oxide is placed. Simply arrange them. Alternatively, use a semiconductor or insulator with a lower electron affinity than hafnium oxide. Alternatively, for a membrane with buffering function, ionized esters are better than hafnium oxide. A semiconductor or insulator with high energy should be placed. By using this method, the release of charges trapped in interface levels becomes less likely, and over a long period of time... It can retain electric charge.

[0278] Examples of such insulators include silicon oxide and silicon oxide nitride. In order to trap charge in the interface state within layer 160, gate charge must be transmitted from oxide semiconductor layer 130. The electrons should be moved toward the polar layer (conductive layer 170). A specific example is high temperature Under degrees (for example, between 125°C and 450°C, typically between 150°C and 300°C) The potential of the gate electrode layer (conductive layer 170) is higher than the potential of the source electrode and drain electrode. You just need to maintain it for more than one second, or more typically, more than one minute.

[0279] In this way, a transistor that has captured a desired amount of electrons at interface levels such as the insulating layer 160, The threshold voltage shifts to the positive side. The voltage of the gate electrode layer (conductive layer 170) and the voltage By adjusting the application time, the amount of electrons captured (the amount of variation in threshold voltage) can be controlled. It can be controlled. Furthermore, if it is possible to capture the charge, not within the insulating layer 160 It is permissible to do so. A laminated film having a similar structure may be used for other insulating layers.

[0280] Furthermore, in the insulating layer 120 and insulating layer 160 that are in contact with the oxide semiconductor layer 130, nitrogen It may have regions with low energy level densities due to oxides. Low energy level densities due to nitrogen oxides. As an oxide insulating layer, a silicon oxidizride film with low nitrogen oxide emission, or a nitrogen oxide film. Aluminum oxide nitride films with low emission levels of substances can be used.

[0281] Furthermore, silicon oxidnitride films with low nitrogen oxide emissions can be analyzed using the temperature-dependent desorption gas analysis method (TDS). In (Thermal Desorption Spectroscopy), nitrogen This is a membrane that releases more ammonia than oxides, and is typically characterized by ammonia release. Quantity 1 × 10 18 pieces / cm 3 The above 5 x 10 19 pieces / cm 3 The following applies. Note that ammonia The amount released is when the film surface temperature is 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower. This refers to the amount released due to the heat treatment described below.

[0282] By using the above oxide insulating layer as the insulating layer 120 and insulating layer 160, the transient This makes it possible to reduce the threshold voltage shift of the transistor and the variation in the transistor's electrical characteristics. This can be reduced.

[0283] The conductive layer 170 acting as the gate electrode layer may be made of, for example, Al, Ti, Cr, Co, or Ni. Conductive films such as Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta, and W It can be used. Furthermore, alloys of the above materials or conductive nitrides of the above materials may also be used. Furthermore, a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials Layers of materials are also possible. Typical examples include tungsten and tungsten and titanium nitride layers. Laminated layers of tungsten and tantalum nitride can be used. Also, low-resistance Cu can be used. Alternatively, using alloys such as Cu-Mn or laminates of the above materials with Cu or Cu-Mn alloys may also be used. Good. In this embodiment, tantalum nitride is used for the conductive layer 171 and tungsten for the conductive layer 172. A conductive layer 170 is formed using this method.

[0284] The insulating layer 175 may be made of a silicon nitride film or an aluminum nitride film containing hydrogen. This is possible. Transistors 103, 104, and 2 shown in Embodiment 2 In transistors 106, 109, 110, and 112: By using a hydrogen-containing insulating film as the insulating layer 175, a portion of the oxide semiconductor layer is converted to n-type. It is possible. In addition, the nitride insulating film also acts as a blocking film for moisture, etc. This can improve the reliability of the transistor.

[0285] Furthermore, an aluminum oxide film can also be used as the insulating layer 175. In particular, the embodiment Transistors 101, 102, 105, and 2 shown in state 2 In transistors 107, 108, and 111, the insulating layer 175 has an oxide layer It is preferable to use a luminium film. The aluminum oxide film contains impurities such as hydrogen and water. It has a high barrier effect that prevents both aluminum oxide and oxygen from permeating the membrane. The nium film contains impurities such as hydrogen and water during and after the transistor fabrication process. Prevention of contamination into the oxide semiconductor layer 130, prevention of oxygen release from the oxide semiconductor layer, insulating layer 1 It is suitable for use as a protective film that prevents the unnecessary release of oxygen from 20°C. Furthermore, it is also possible to diffuse the oxygen contained in the aluminum oxide film into the oxide semiconductor layer. ru.

[0286] Furthermore, it is preferable that an insulating layer 180 is formed on the insulating layer 175. This includes magnesium oxide, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride Cone, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, rayon oxide Using an insulating film containing one or more of tantalum, neodymium oxide, hafnium oxide, and tantalum oxide This is possible. Furthermore, the insulating layer may be a laminate of the above-mentioned materials.

[0287] Here, the insulating layer 180, like the insulating layer 120, has more oxygen than its stoichiometric composition. This is preferable. Oxygen released from the insulating layer 180 passes through the insulating layer 160 to the oxide semiconductor Since it can diffuse into the channel-forming region of layer 130, it can form a shape in the channel-forming region. The oxygen deficiency that has occurred can be compensated for by oxygen. Therefore, a stable transistor Electrical properties can be obtained.

[0288] Miniaturization of transistors is essential for highly integrating semiconductor devices. It is known that miniaturization degrades the electrical characteristics of transistors, and the channel width shrinks. Reducing the ON current decreases the ON current.

[0289] In transistors 107 to 112 of one aspect of the present invention, a channel is formed An oxide semiconductor layer 130c is formed so as to cover the oxide semiconductor layer 130b, The channel-forming layer and the gate insulating film are not in contact. This suppresses carrier scattering at the interface with the insulating film, thus reducing the on-voltage of the transistor. The flow can be made larger.

[0290] Furthermore, in a transistor according to one aspect of the present invention, as described above, the oxide semiconductor layer 130 is A gate electrode layer (conductive layer 170) is formed so as to electrically surround the width direction of the fiber. Therefore, for the oxide semiconductor layer 130, in addition to the gate electric field from the direction perpendicular to the top surface, the side surface A gate electric field is applied from a perpendicular direction. That is, the entire channel formation layer The gate field is applied, which expands the effective channel width, and therefore the on-current can be increased further. It can be seen.

[0291] Furthermore, in one aspect of the present invention, the oxide semiconductor layer 130 is a two- or three-layer transistor. This involves forming an oxide semiconductor layer 130b on an oxide semiconductor layer 130a in which a channel is formed. This has the effect of making it difficult for interfacial states to form. Furthermore, oxidation in one aspect of the present invention In a transistor with three semiconductor layers 130, the oxide semiconductor layer 130b is an intermediate layer in the three-layer structure. By positioning it as a layer, it has the added benefit of eliminating the influence of impurities from above and below. Therefore, in addition to improving the on-current of the transistor as described above, the threshold voltage stabilization is also important. This allows for the reduction of the S value (subthreshold value). Therefore, Icu This allows us to lower t (current when gate voltage VG is 0V) and reduce power consumption. Yes, it is possible. Furthermore, because the threshold voltage of the transistor is stabilized, the long-term reliability of the semiconductor device is improved. Reliability can be improved. Furthermore, the transistor according to one aspect of the present invention can be miniaturized. Because the degradation of electrical properties is suppressed, it is suitable for forming highly integrated semiconductor devices. It can be said that...

[0292] This embodiment can be appropriately combined with other embodiments shown herein. .

[0293] (Embodiment 7) In this embodiment, the transistor 101 and transistor 1 described in Embodiment 5 are used. I will now explain how to make 07.

[0294] First, we will explain an example of a method for fabricating silicon transistors included in substrate 115. As for the substrate, n - A single-crystal silicon substrate of a certain type is used, and an insulating layer (field oxide film) is applied to the surface. The element formation region is formed by the LOCOS method (also known as the LOCOS method). Local Oxidation of Silicon) and STI method (Shallow Trench isolation, etc., can be used.

[0295] Here, the substrate is not limited to a single-crystal silicon substrate, but also SOI (Silicon on Insul A rator (a type of substrate) can also be used.

[0296] Next, a gate insulating film is formed to cover the element formation region. For example, heat treatment is performed to form the element shape A silicon oxide film is formed by oxidizing the surface of the region. The surface of the silicon oxide film may be nitrided by performing a nitriding treatment after the film has been formed.

[0297] Next, a conductive film is formed to cover the gate insulating film. The conductive film can be made of Ta, W, or Ti. Elements selected from Mo, Al, Cu, Cr, Nb, etc., or elements that are the main component of these elements It can be formed from alloy materials or compound materials. Also, gold nitrided from these elements. It can also be formed as a nitride film. Alternatively, it can be formed as a polycrystalline film doped with impurity elements such as phosphorus. It can also be formed from semiconductor materials such as silicon.

[0298] Next, by selectively etching the conductive film, the gate electrode layer is created on the gate insulating film. To form.

[0299] Next, an insulating film, such as a silicon oxide film or a silicon nitride film, is formed to cover the gate electrode layer. Then, etch-back is performed to form sidewalls on the sides of the gate electrode layer.

[0300] Next, a resist mask is selectively formed to cover areas other than the element formation region, and the resist mask By introducing impurity elements using the screen and gate electrode layers as masks, p + Impurity of the type A material region is formed. Here, in order to form a p-channel type transistor, impurity elements and For this purpose, impurity elements such as B and Ga, which impart the p-type, can be used.

[0301] Next, a resist mask is selectively formed to fabricate the photodiode. , on a single-crystal silicon substrate, a photodiode is formed on the same surface as the transistor. To form the cathode of the ode, impurity elements such as phosphorus (P) and arsenic ( By introducing As) + It forms a shallow impurity region in the mold. Also, photodiode p for making an electrical connection between the anode of the cord and the wiring. + Forms a deep impurity region of the type This is also acceptable. Note that the anode (p + The shallow impurity region of the mold is in a later process. On a single-crystal silicon substrate, a shape is formed on the side opposite to the side where the photodiode cathode is formed. To accomplish.

[0302] Here, as shown in Figure 1(A), the region in contact with the side surface of the photodiode is etched An opening is made, and an insulating layer is provided in the opening. The insulating layer is a silicon oxide layer, silicon nitride It is possible to use layers such as CVD (Chemical Vapor Deposit). It can be formed by methods such as the ionization method or thermal oxidation method.

[0303] The above describes a p-channel type transistor and a photodiode having an active region on a silicon substrate. The transistor is completed. Note that a passivation film such as a silicon nitride film is applied to the transistor. It is preferable to form a film.

[0304] Next, an interlayer insulating film, such as a silicon oxide film, is formed on the silicon substrate on which the transistors are formed. This forms various conductors and various wiring layers. Also, as described in Embodiment 1, hydrogen An insulating layer such as aluminum oxide is formed to prevent diffusion. The substrate 115 has the above-mentioned tra A silicon substrate on which a diode and a photodiode are formed, formed on the silicon substrate This includes an interlayer insulating layer, a wiring layer, and a conductor, etc.

[0305] Next, the method for fabricating transistor 102 will be explained using Figures 40 and 41. The left side of the diagram shows a cross-section of the transistor in the channel length direction, and the right side shows a cross-section in the channel width direction. A cross-section is shown. Also, the drawing in the channel width direction is an enlarged view, so the apparent film thickness of each element is shown on the left. The diagram on the right is different.

[0306] The oxide semiconductor layer 130 consists of oxide semiconductor layer 130a, oxide semiconductor layer 130b and oxide An example is given of a three-layer structure of the material semiconductor layer 130c. In this case, two layers, an oxide semiconductor layer 130a and an oxide semiconductor layer 130b, can be used. Furthermore, if the oxide semiconductor layer 130 has a single-layer structure, then the oxide semiconductor layer 130b will be a single layer. Yes.

[0307] First, an insulating layer 120 is formed on the substrate 115. The type of substrate 115 and the insulating layer 120 The material can be described in the description of Embodiment 6. The insulating layer 120 is made by sputtering. Using methods such as CVD and MBE (Molecular Beam Epitaxy) It can be formed.

[0308] Furthermore, ion implantation, ion doping, and plasma immersion ions can be applied to the insulating layer 120. Oxygen may be added using methods such as implantation or plasma treatment. By adding this, the supply of oxygen from the insulating layer 120 to the oxide semiconductor layer 130 is further facilitated. It can be made easy.

[0309] Furthermore, the surface of the substrate 115 is an insulator, and impurities spread to the oxide semiconductor layer 130 that will be provided later. If there is no effect from dispersion, the insulating layer 120 can be omitted.

[0310] Next, an oxide semiconductor film 130A, which will become an oxide semiconductor layer 130a, is placed on the insulating layer 120. The oxide semiconductor film 130B becomes the semiconductor layer 130b, and the oxide semiconductor film 130c becomes the oxide semiconductor layer 130c. Oxide semiconductor films 130C are deposited using sputtering, CVD, MBE, etc. (Figure 4) 0(A)).

[0311] When the oxide semiconductor layer 130 has a stacked structure, the oxide semiconductor film has a load lock chamber. Using a multi-chamber type film deposition apparatus (e.g., a sputtering apparatus), each layer is exposed to the atmosphere. It is preferable to continuously laminate without interruption. Each chamber in the sputtering apparatus is acid To remove as much water and other impurities as possible from the semiconductor, a cryopump is used. High vacuum evacuation using an adsorption type vacuum pump (5 × 10 -7 Pa~1×10 -4 Pa degree It is possible to heat the substrate to a temperature of 100°C or higher, preferably 500°C or higher. It is preferable to combine a turbomolecular pump and a cold trap to channel the exhaust system away from the champ. It is preferable to prevent gases containing carbon components or moisture from flowing back into the bar. An exhaust system combining a molecular pump and a cryopump may also be used.

[0312] To obtain high-purity intrinsic oxide semiconductors, not only is the chamber evacuated to a high vacuum, but spa It is preferable to purify the sputtering gas. The oxygen gas or algonium used as the sputtering gas... The gas has a dew point of -40°C or lower, preferably -80°C or lower, more preferably -100°C or lower. By achieving high purity down to the bottom, it is possible to prevent moisture and other substances from being incorporated into the oxide semiconductor film as much as possible. It is possible to do so.

[0313] Oxide semiconductor film 130A, oxide semiconductor film 130B, and oxide semiconductor film 130C include The materials described in Embodiment 6 can be used. This allows for the deposition of a film using the material described in Embodiment 6 as a target.

[0314] However, as described in detail in Embodiment 6, the oxide semiconductor film 130B contains an oxide semiconductor A material with a higher electron affinity than film 130A and oxide semiconductor film 130C is used.

[0315] Furthermore, it is preferable to use the sputtering method for depositing oxide semiconductor films. For this purpose, RF sputtering, DC sputtering, AC sputtering, etc., can be used.

[0316] After the formation of the oxide semiconductor film 130C, a first heat treatment may be performed. The first heat treatment is At a temperature of 250°C to 650°C, preferably 300°C to 500°C, an inert gas is used. This can be done in a smoky atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or under reduced pressure. The atmosphere for the heat treatment in step 1 is an inert gas atmosphere, followed by replenishing the desorbed oxygen. For this purpose, the process may be carried out in an atmosphere containing 10 ppm or more of an oxidizing gas. The first heat treatment is performed as follows: The oxide semiconductor film 130A, oxide semiconductor film 130B, and oxide semiconductor film 130C are bonded together. Crystallinity is enhanced, and further, the insulating layer 120, oxide semiconductor film 130A, oxide semiconductor film 130B, Furthermore, impurities such as hydrogen and water can be removed from the oxide semiconductor film 130C. The first heat treatment involves the oxide semiconductor layer 130a, oxide semiconductor layer 130b, and This may be performed after etching to form the oxide semiconductor layer 130c.

[0317] Next, a first conductive layer is formed on the oxide semiconductor film 130A. The first conductive layer is, for example, It can be formed using the following method.

[0318] First, a first conductive film is formed on the oxide semiconductor film 130A. The first conductive film is A l, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc, and the metallic material A single layer or a laminate of a material selected from the alloy can be used.

[0319] Next, a resist film is formed on the first conductive film, and the resist film is subjected to electron beam exposure. The first resist is obtained by exposing it using methods such as immersion lithography or EUV lithography, followed by development. A mask is formed. An organic coating film is applied as an adhesion agent between the first conductive film and the resist film. It is preferable to form the first resist using nanoimprint lithography. A tomask may be formed.

[0320] Next, the first conductive film is selectively etched using the first resist mask, and the first resist mask is removed. A conductive layer is formed by ashing the dystomask.

[0321] Next, the above conductive layer is used as a hard mask, and oxide semiconductor film 130A, oxide semiconductor film 130B and the oxide semiconductor film 130C are selectively etched to remove the conductive layer. k, oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c An oxide semiconductor layer 130 is formed by stacking the above (see Figure 40(B)). Alternatively, the oxide semiconductor layer 130 may be formed using the first resist mask without forming a layer. Oxygen ions may be implanted into the oxide semiconductor layer 130.

[0322] Next, a second conductive film is formed so as to cover the oxide semiconductor layer 130. This refers to a material that can be used for the conductive layer 140 and conductive layer 150 described in Embodiment 6. The second conductive film can be formed using methods such as sputtering, CVD, or MBE. It is possible to be there.

[0323] Next, a second resist mask is formed on the source and drain regions. Then, a portion of the second conductive film is etched to form conductive layer 140 and conductive layer 150. (See Figure 40(C)).

[0324] Next, a gate insulating film is formed on the oxide semiconductor layer 130, the conductive layer 140, and the conductive layer 150. An insulating film 160A is formed. The insulating film 160A is formed on the insulating layer 160 described in Embodiment 6. It should be formed using materials that can be used. For the formation of insulating film 160A, sputtering method, C Methods such as VD and MBE can be used.

[0325] Next, a second heat treatment may be performed. The second heat treatment is performed under the same conditions as the first heat treatment. This can be done. The second heat treatment removes the oxygen injected into the oxide semiconductor layer 130. It can be diffused throughout the entire ion semiconductor layer 130. Furthermore, without performing a second heat treatment... Alternatively, the above effect may be obtained by a third heat treatment.

[0326] Next, a third conductive film 171A and a fourth conductive film which form a conductive layer 170 are placed on the insulating film 160A. Forms 172A. The third conductive film 171A and the fourth conductive film 172A are in the embodiment. It is acceptable to form them using materials that can be used for the conductive layers 171 and 172 as described in 6. The third conductive film 171A and the fourth conductive film 172A were formed by sputtering and CVD. Methods such as the law and the MBE method can be used.

[0327] Next, a third resist mask 156 is formed on the fourth conductive film 172A (Figure 41(A)). (See reference). Then, using the third resist mask 156, the third conductive film 171A, the fourth The conductive film 172A and the insulating film 160A are selectively etched, and the conductive layer 171 and conductive A conductive layer 170 and an insulating layer 160 are formed, consisting of layer 172 (see Figure 41(B)).

[0328] Next, oxide semiconductor layer 130, conductive layer 140, conductive layer 150, insulating layer 160 and conductive layer An insulating layer 175 is formed on 170. Refer to the description of Embodiment 6 for the material of the insulating layer 175. This is possible. In the case of transistor 101, it is preferable to use an aluminum oxide film. The insulating layer 175 can be formed by sputtering, CVD, MBE, etc. .

[0329] Next, an insulating layer 180 is formed on the insulating layer 175 (see Figure 41(C)). The material can be described in the description of Embodiment 6. Furthermore, the insulating layer 180 is sputtered. It can be formed using methods such as CVD, MBE, etc.

[0330] In addition, ion implantation, ion doping, Using plasma immersion ion implantation, plasma treatment, etc. It may be added. By adding oxygen, insulating layer 175 and / or insulating layer 1 This makes it even easier to supply oxygen from 80 to the oxide semiconductor layer 130.

[0331] Next, a third heat treatment may be performed. The third heat treatment is performed under the same conditions as the first heat treatment. This can be done. By the third heat treatment, the insulating layer 120, insulating layer 175, insulating layer 18 This makes it easier for excess oxygen to be released from 0, reducing oxygen vacancies in the oxide semiconductor layer 130. It is possible.

[0332] Next, the method for fabricating transistor 107 will be explained. Note that the above-mentioned transistor 1 Detailed explanations of steps that overlap with the manufacturing method for 01 will be omitted.

[0333] An insulating layer 120 is formed on the substrate 115, and an oxide semiconductor layer 130a is formed on the insulating layer. The oxide semiconductor film 130A and the oxide semiconductor film 130B which will become the oxide semiconductor layer 130b are The film is deposited using methods such as sputtering, CVD, or MBE (see Figure 42(A)).

[0334] Next, the first conductive film is formed on the oxide semiconductor film 130B, and the first film is formed in the same manner as described above. A conductive layer is formed using a resist mask. Then, this conductive layer is used as a hard mask for acid The oxide semiconductor film 130A and the oxide semiconductor film 130B are selectively etched, and the above conductive By removing the layers, a stack consisting of oxide semiconductor layer 130a and oxide semiconductor layer 130b is formed. This is achieved (see Figure 42(B)). Note that the first resist mask is formed without creating a hard mask. The laminate may be formed using the following: Here, oxygen ions to the oxide semiconductor layer 130 It may be injected.

[0335] Next, a second conductive film is formed to cover the above laminate. Then, the source region and the drain A second resist mask is formed on the area that will become the resist mask, and the second resist mask is used Then, a portion of the second conductive film is etched to form conductive layer 140 and conductive layer 150. See Figure 42(C).

[0336] Next, on the stack of oxide semiconductor layer 130a and oxide semiconductor layer 130b, and conductive layer An oxide semiconductor film 130C, which will become an oxide semiconductor layer 130c, is placed on the conductive layer 140 and the conductive layer 150. Formed. Furthermore, an insulating film 160A, which will serve as a gate insulating film, is formed on the oxide semiconductor film 130C. A third conductive film 171A and a fourth conductive film 172A, which will become the conductive layer 170, are formed.

[0337] Next, a third resist mask 156 is formed on the fourth conductive film 172A (Figure 43(A)). (See reference). Then, using the resist mask, the third conductive film 171A and the fourth conductive film 1 72A, insulating film 160A, and oxide semiconductor film 130C are selectively etched to create a conductive material. A conductive layer 170 consisting of layer 171 and conductive layer 172, an insulating layer 160, and an oxide semiconductor. Layer 130c is formed (see Figure 43(B)). Note that insulating film 160A and oxide semiconductor By etching film 130C using a fourth resist mask, transistor 108 It is possible to produce this.

[0338] Next, insulating layer 120, oxide semiconductor layer 130 (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c), conductive layer 140, conductive layer 150, insulating layer 160 An insulating layer 175 and an insulating layer 180 are formed on the conductive layer 170 (see Figure 43(C)).

[0339] Transistor 107 can be fabricated through the above process.

[0340] In this embodiment, various films such as metal films, semiconductor films, and inorganic insulating films are typically... These can be formed by sputtering or plasma CVD, but other methods, such as heat It may also be formed by the CVD method. An example of the thermal CVD method is MOCVD (Metal Oxide). (Germanic Chemical Vapor Deposition) method and ALD (A Examples include the tomic layer deposition method.

[0341] Thermal CVD is a film deposition method that does not use plasma, so defects are generated by plasma damage. It has the advantage of not being affected.

[0342] Furthermore, in the thermal CVD method, the raw material gas and oxidizer are simultaneously introduced into the chamber, and the contents of the chamber are processed By using atmospheric pressure or reduced pressure, the reaction is carried out near or on the substrate, causing the deposit to be deposited on the substrate. Film deposition may be performed.

[0343] The ALD method involves maintaining atmospheric pressure or reduced pressure inside the chamber and supplying the raw material gas for the reaction to the chamber. - The material is introduced and reacted with, and this process is repeated to form a film. Along with the raw material gas, an inert gas is also used. Argon or nitrogen may be introduced as a carrier gas. For example, two or more types The raw material gases may be supplied to the chamber in sequence. In this case, multiple types of raw material gases must not be mixed. As described above, after the reaction of the first raw material gas, an inert gas is introduced, and then the second raw material gas is introduced. Instead of introducing an inert gas, the first raw material gas is discharged by vacuum evacuation, and then the A second raw material gas may be introduced. The first raw material gas is adsorbed and reacts with the surface of the substrate to form the first layer. A film is formed, and a second raw material gas introduced later is adsorbed and reacts, causing the second layer to form on top of the first layer. The layers are stacked to form a thin film. This process is repeated while controlling the gas introduction sequence until the desired thickness is achieved. By repeating the process several times, a thin film with excellent step coverage can be formed. The thickness of the thin film is Because it can be adjusted by the number of times the injection is repeated, precise film thickness adjustment is possible. It is suitable for fabricating miniature FETs.

[0344] Thermal CVD methods such as MOCVD and ALD are disclosed in the embodiments described above. It can form various films such as metal films, semiconductor films, and inorganic insulating films, for example, In-Ga -When forming a Zn-O film, trimethylindium (In(CH3)3), trimethyl Tilgarium (Ga(CH3)3) and dimethylzinc (Zn(CH3)2) are used. This is possible. It is not limited to these combinations, and trimethylgallium can be substituted with triethyl Lugarium (Ga(C2H5)3) can also be used, and diethyl can be used instead of dimethylzinc. Zinc (Zn(C2H5)2) can also be used.

[0345] For example, when forming a hafnium oxide film using an ALD-based film deposition apparatus, the solvent and Liquids containing hafnium precursors (such as hafnium alkoxide or tetrakisdimethylamide) Fnium (TDMAH, Hf[N(CH3)2]4) and tetrakis (ethylmethylamide) (The raw material gas is a vaporized hafnium amide such as hafnium, and ozone is used as an oxidizer.) Two types of gases (O3) are used.

[0346] For example, when forming an aluminum oxide film using a film deposition apparatus that utilizes ALD, the solvent and a liquid containing an aluminum precursor (trimethylaluminum (TMA, Al(CH3)3) Two types of gases are used: a raw material gas obtained by vaporizing (such as) and H2O as an oxidizing agent. The materials include tris(dimethylamide)aluminum, triisobutylaluminum, and Luminium tris(2,2,6,6-tetramethyl-3,5-heptanedione), etc. There is.

[0347] For example, when forming a silicon oxide film using a film deposition apparatus that utilizes ALD, hexa Rolologysilane is adsorbed onto the film-forming surface, and radicals of oxidizing gases (O2, nitrous oxide) are supplied. It is supplied and reacted with the adsorbed material.

[0348] For example, when depositing a tungsten film using an ALD-based film deposition apparatus, WF6 gas The initial tungsten film is formed by sequentially introducing S and B2H6 gas, and then WF6 gas and H Two gases are introduced sequentially to form a tungsten film. Note that SiH4 gas is used instead of B2H6 gas. Gas may be used.

[0349] For example, oxide semiconductor films, such as In-Ga-Zn-O, can be deposited using an ALD (Advanced Laser Deposition) system. When forming a film, In(CH3)3 gas and O3 gas are introduced sequentially to form an In-O layer. Then, Ga(CH3)3 gas and O3 gas are sequentially introduced to form a GaO layer, and further Subsequently, Zn(CH3)2 and O3 gas are introduced sequentially to form a ZnO layer. The order of the layers is not limited to this example. These gases can be used to create In-Ga-O layers and In-Zn-O layers. A mixed compound layer such as a Ga-Zn-O layer may be formed. Alternatively, A can be used instead of O3 gas. H2O gas obtained by bubbling with an inert gas such as r may be used, but it does not contain H. It is preferable to use O3 gas.

[0350] This embodiment can be appropriately combined with other embodiments shown herein. .

[0351] (Embodiment 8) The following describes the structure of an oxide semiconductor film that can be used in one aspect of the present invention. .

[0352] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. This refers to the state in which something is positioned. Therefore, it also includes cases where the angle is between -5° and 5°. Also, "Perpendicular" refers to a state where two lines are positioned at an angle between 80° and 100°. Therefore, this also includes cases where the angle is between 85° and 95°.

[0353] Furthermore, in this specification, if a crystal is trigonal or rhombohedral, it will be represented as a hexagonal crystal system. .

[0354] Oxide semiconductor films are broadly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. A single-crystal oxide semiconductor film is a CAAC-OS (C Axis Aligned Crystals Polycrystalline oxide semiconductor film This refers to microcrystalline oxide semiconductor films, amorphous oxide semiconductor films, etc.

[0355] First, let's explain the CAAC-OS membrane.

[0356] CAAC-OS film is an oxide semiconductor film having multiple c-axis oriented crystalline regions.

[0357] Transmission Electron Microscope (TEM) A composite analysis image of the CAAC-OS film's bright-field image and diffraction pattern (using a scope) Also known as a high-resolution TEM image, multiple crystalline regions can be identified by observing it. On the other hand, high-resolution TEM images also clearly show the boundaries between crystalline parts, i.e., grain boundaries. Also called boundary.) It is not possible to confirm. Therefore, the CAAC-OS membrane is This means that a decrease in electron mobility due to grain boundaries is less likely to occur.

[0358] When observing a high-resolution TEM image of the cross-section of the CAAC-OS film from a direction roughly parallel to the sample surface, In the crystalline region, it can be confirmed that the metal atoms are arranged in layers. Each layer of metal atoms is This reflects the unevenness of the surface (also called the surface to be formed) or the upper surface of the CAAC-OS film. It has a specific shape and is arranged parallel to the surface or top surface of the CAAC-OS film to be formed.

[0359] On the other hand, a high-resolution TEM image of the CAAC-OS film plane was observed from a direction roughly perpendicular to the sample surface. Then, it was confirmed that the metal atoms in the crystalline region are arranged in a triangular or hexagonal shape. Yes, it is possible. However, no regularity is observed in the arrangement of metal atoms between different crystalline regions.

[0360] X-ray diffraction (XRD) applied to the CAAC-OS film. When structural analysis is performed using this method, for example, a CAAC-OS film having InGaZnO4 crystals is found. In the out-of-plane analysis, the diffraction angle (2θ) shows a peak near 31°. This peak may appear. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is generally aligned with the surface to be formed or the upper surface. It can be confirmed that it is facing in a nearly vertical direction.

[0361] Furthermore, the out-of-plane method for CAAC-OS films containing InGaZnO4 crystals. Analysis revealed that in addition to a peak near 2θ = 31°, a peak also appeared near 2θ = 36°. In some cases, this may occur. Peaks near 36° 2θ indicate c-axis orientation in a portion of the CAAC-OS film. This indicates that it contains crystals that do not have [the specified characteristic]. The CAAC-OS film has 2θ near 31°. It is preferable that a peak is observed, and that no peak is observed near 36° for 2θ.

[0362] CAAC-OS films are oxide semiconductor films with low impurity concentrations. The impurities include hydrogen, carbon, These are elements other than silicon and transition metal elements, which are the main components of oxide semiconductor films. In particular, silicon Elements such as ions, which have a stronger bonding force with oxygen than the metal elements that make up oxide semiconductor films, By removing oxygen from the material semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. This is a contributing factor. Also, heavy metals such as iron and nickel, argon, and carbon dioxide have a certain atomic radius. Because of its large molecular radius, when it is contained within an oxide semiconductor film, the oxide semiconductor film This disrupts the atomic arrangement and reduces crystallinity. Furthermore, these impurities are present in oxide semiconductor films. Objects can sometimes act as carrier traps or carrier sources.

[0363] Furthermore, CAAC-OS films are oxide semiconductor films with a low defect level density. For example, oxide Oxygen vacancies in semiconductor films can act as carrier traps or capture hydrogen. It can be a source of carrier activity.

[0364] A low impurity concentration and low defect level density (few oxygen vacancies) is referred to as high-purity intrinsic or This is essentially called high-purity intrinsic. High-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film Because there are fewer carrier sources, the carrier density can be kept low. Therefore, The transistor using this oxide semiconductor film exhibits an electrical characteristic in which the threshold voltage becomes negative. Also called normally-on.) It rarely becomes high-purity intrinsic or substantially high-purity. Highly intrinsic oxide semiconductor films have few carrier traps. Transistors using body membranes exhibit less variation in electrical characteristics and are highly reliable. Furthermore, the charge trapped in the carrier trap of the oxide semiconductor film requires time to be released. It can remain dormant for a long time, behaving almost like a fixed charge. Therefore, the impurity concentration Transistors using oxide semiconductor films with high defect level density have unstable electrical properties. It can happen.

[0365] Furthermore, transistors using CAAC-OS films exhibit electrical characteristics under irradiation with visible light and ultraviolet light. The fluctuations are small.

[0366] Next, we will explain microcrystalline oxide semiconductor films.

[0367] Microcrystalline oxide semiconductor films have areas where crystalline regions can be confirmed in high-resolution TEM images. It has regions where a clear crystalline structure cannot be observed, and regions where a clear crystalline structure cannot be identified. Microcrystalline oxide semiconductor film The crystalline portion contained therein is between 1 nm and 100 nm in size, or between 1 nm and 10 nm in size. This is often the case. In particular, the minute particles are between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor film having nanocrystals (nc) which are crystalline, -OS(nanocrystalline oxide semiconductor) It is called a film. Furthermore, nc-OS films, for example, clearly show grain boundaries in high-resolution TEM images. There may be cases where it cannot be recognized.

[0368] nc-OS films are used in minute regions (for example, regions between 1 nm and 10 nm, especially regions larger than 1 nm). The atomic arrangement has periodicity in the region of 3 nm or less. Also, the nc-OS film is different No regularity in crystal orientation is observed between the crystalline regions. Therefore, no orientation is observed throughout the entire film. Therefore, depending on the analytical method, nc-OS films may be indistinguishable from amorphous oxide semiconductor films. There are cases where this is not possible. For example, when using X-rays with a diameter larger than that of the crystalline region on an nc-OS film, XR When structural analysis is performed using instrument D, the out-of-plane method shows that the crystal plane No peaks indicating this are detected. Also, for the nc-OS film, probes larger than the crystalline region are detected. Electron diffraction (also called limited-area electron diffraction) using an electron beam with a diameter (e.g., 50 nm or more) When this is done, a diffraction pattern resembling a halo pattern is observed. On the other hand, for nc-OS films... Nanobeam electron beams with a probe diameter close to or smaller than the size of the crystal region are used. When diffraction is performed, spots are observed. Furthermore, nanobeam electron diffraction is performed on nc-OS films. When this is done, circularly distributed spots may be observed. Also, for nc-OS films When nanobeam electron diffraction is performed, multiple spots may be observed within a ring-shaped region. ru.

[0369] nc-OS films are oxide semiconductor films with higher orderliness than amorphous oxide semiconductor films. Therefore, nc-OS films have a lower defect level density than amorphous oxide semiconductor films. However, In nc-OS films, no regularity is observed in the crystal orientation between different crystalline regions. Therefore, nc-O The S film has a higher defect level density compared to the CAAC-OS film.

[0370] Next, we will explain amorphous oxide semiconductor films.

[0371] Amorphous oxide semiconductor films have an irregular atomic arrangement within the film and do not contain crystalline regions. These are physical semiconductor films. One example is an oxide semiconductor film that has an amorphous state, such as quartz.

[0372] In amorphous oxide semiconductor films, crystalline regions cannot be observed in high-resolution TEM images.

[0373] When structural analysis of amorphous oxide semiconductor films is performed using an XRD device, out-of-p Analysis using the Lane method did not detect any peaks indicating crystal planes. Furthermore, amorphous oxide semi-crystalline materials were found. When electron diffraction is performed on a conductive film, a halo pattern is observed. Furthermore, amorphous oxide semiconductors... When nanobeam electron diffraction is performed on a conductive film, no spots are observed, and a halo pattern is not seen. It is observed.

[0374] Furthermore, oxide semiconductor films exhibit physical properties between nc-OS films and amorphous oxide semiconductor films. It may have such a structure. Oxide semiconductor films having such a structure are particularly amorphous-like oxide Amorphous-like semiconductor (amorphous-like OS: amorphous-like Ox It is called an IDE Semiconductor film.

[0375] Amorphous-like OS films exhibit porosity (also known as voids) in high-resolution TEM images. In some cases, the following may be observed. Also, the crystalline portion can be clearly identified in high-resolution TEM images. It has regions where this can be done and regions where the crystalline part cannot be observed. Phosphorus-like OS films can be bonded by minute electron irradiation, such as that observed by TEM. Crystallization may occur, and growth of crystalline regions may be observed. On the other hand, if the nc-OS film is of good quality... Crystallization is hardly observed even with minute amounts of electron irradiation, such as that observed by TEM.

[0376] Furthermore, the size of the crystalline portion of the amorphous-like OS film and nc-OS film is measured. Measurement can be performed using high-resolution TEM images. For example, an InGaZnO4 crystal is It has a layered structure, with two Ga-Zn-O layers between the In-O layers. (InGaZnO4) The unit cell of this crystal has 3 In-O layers and 6 Ga-Zn-O layers, for a total of 9 It has a structure in which layers are stacked in a layered manner along the c-axis. Therefore, the spacing between these adjacent layers is It is approximately the same as the lattice plane spacing (also called the d value) of the (009) plane, and from crystal structure analysis, The value has been determined to be 0.29 nm. Therefore, we focused on the lattice fringes in the high-resolution TEM image. Furthermore, in areas where the spacing between the grid lines is between 0.28 nm and 0.30 nm, The lattice patterns correspond to the ab-plane of the InGaZnO4 crystal.

[0377] Note that oxide semiconductor films include, for example, amorphous oxide semiconductor films. A multilayer film having two or more of the following: e OS film, microcrystalline oxide semiconductor film, and CAAC-OS film. That's fine.

[0378] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. can.

[0379] (Embodiment 9) The band structure of a transistor according to one embodiment of the present invention will be described below.

[0380] Figure 44(A) is a cross-sectional view of a transistor having an oxide semiconductor layer according to one aspect of the present invention. be.

[0381] The transistor shown in Figure 44(A) has an insulating layer 401 on the substrate 400 and on the insulating layer 401 A conductive layer 404a, a conductive layer 404b on the conductive layer 404a, and a conductive layer 40 on the insulating layer 401 Insulating layer 402a on 4a and conductive layer 404b, and insulating layer 402b on insulating layer 402a And, the semiconductor layer 406a on the insulating layer 402b, and the semiconductor layer 406b on the semiconductor layer 406a , an insulating layer 412 on semiconductor layer 406b, a conductive layer 414a on insulating layer 412, and a conductive layer 4 The conductive layer 414b on 14a, the insulating layer 402b, the semiconductor layer 406a, and the semiconductor layer 406 The insulating layer 408 on b, on the insulating layer 412, on the conductive layer 414a and on the conductive layer 414b, An insulating layer 418 on the edge layer 408, and conductive layers 416a1 and 416 on the insulating layer 418 b1 and conductive layer 416a2 on conductive layer 416a1 and conductive layer 416b1 respectively and On the conductive layer 416b2, on the insulating layer 418, on the conductive layer 416a2 and on the conductive layer 416b2 It has an insulating layer 428 and

[0382] The insulating layer 401 prevents impurities such as copper from entering the channel formation region of the transistor. It may have a function to control or restrain.

[0383] The laminate of conductive layer 404a and conductive layer 404b is collectively referred to as conductive layer 404. It functions as the gate electrode of the transistor. Also, the conductive layer 404 is the transistor It may also have a function to block light from the channel formation region of the sta.

[0384] The insulating layer 402a and insulating layer 402b together are called the insulating layer 402. The insulating layer 402 is It functions as a gate insulating layer for the transistor. In addition, the insulating layer 402a is a transistor The material may also have a function to suppress the incorporation of impurities such as copper into the channel-forming region.

[0385] Semiconductor layer 406a and semiconductor layer 406b together are called semiconductor layer 406. 6 functions as a channel formation region for the transistor. For example, semiconductor layer 406 a is the oxide semiconductor layer 130b shown in the previous embodiment, and semiconductor layer 406b is the same as in the previous embodiment. This corresponds to the oxide semiconductor layer 130c shown in the diagram.

[0386] Furthermore, the semiconductor layer 406a does not overlap with the insulating layer 412, the conductive layer 414a, and the conductive layer 414b. It has regions 407a1 and 407b1. The semiconductor layer 406b is an insulating layer 4 12. Regions 407a2 and 407b that do not overlap with conductive layer 414a and conductive layer 414b. It has 2. Regions 407a1 and 407b1 are the insulating layer 412 of semiconductor layer 406a. This region has lower resistance than the region overlapping with conductive layers 414a and 414b. Regions 407a2 and 407b2 are the insulating layer 412 and conductive layer 414 of the semiconductor layer 406b. a) A region with lower resistance than the region overlapping with the conductive layer 414b. This can also be called a region with high carrier density.

[0387] Furthermore, regions 407a1 and 407a2 are collectively referred to as region 407a. Regions 07b1 and 407b2 are collectively referred to as region 407b. Regions 407a and 4 07b functions as both the source and drain regions of the transistor.

[0388] The conductive layer 414a and conductive layer 414b together are called the conductive layer 414. The conductive layer 414 is It functions as the gate electrode of a transistor. Alternatively, the conductive layer 414 is a transistor. It may also have a function to block light from channel formation regions and the like.

[0389] The insulating layer 412 functions as the gate insulating layer of the transistor.

[0390] The insulating layer 408 contains impurities such as copper found in the conductive layer 416a2 and conductive layer 416b2. It may also have a function to suppress the intrusion of material into the channel formation region of the transistor.

[0391] The insulating layer 418 may also function as an interlayer insulating layer of the transistor, thereby This reduces parasitic capacitance between each wire in the transistor.

[0392] The conductive layer 416a1 and conductive layer 416a2 together are called the conductive layer 416a. 416b1 and conductive layer 416b2 together are called conductive layer 416b. Furthermore, the conductive layer 416b functions as the source electrode and drain electrode of the transistor. ru.

[0393] The insulating layer 428 is designed to suppress the intrusion of impurities into the channel formation region of the transistor. It is acceptable to possess the ability.

[0394] Here, in Figure 44(B), in the P1-P2 cross section including the channel formation region of the transistor... It shows a band structure. Note that semiconductor layer 406a has a higher energy gauge than semiconductor layer 406b. Let's assume the top is slightly small. Also, insulating layers 402a, 402b and 412 are If the energy gap is sufficiently larger than that of semiconductor layers 406a and 406b Also, semiconductor layer 406a, semiconductor layer 406b, insulating layer 402a, insulating layer 402b The Fermi level (denoted as Ef) of the insulating layer 412 is the intrinsic Fermi level of each. (Denoted as Ei) is the position. Also, the work function of conductive layer 404 and conductive layer 414 This is assumed to be at the same position as the Fermi level.

[0395] When the gate voltage is set to be greater than or equal to the transistor's threshold voltage, semiconductor layer 406a and semiconductor layer Due to the energy difference at the lower end of the conduction band between 406b and 406a, electrons preferentially enter semiconductor layer 406a. It flows through it. In other words, it can be estimated that electrons are embedded in the semiconductor layer 406a. The energy at the bottom of the conduction band is denoted as Ec, and the energy at the top of the valence band is denoted as Ev. .

[0396] Therefore, a transistor according to one aspect of the present invention reduces interfacial scattering by embedding electrons. The impact is reduced. Therefore, the transistor according to one aspect of the present invention has a channel resistance It's small.

[0397] Next, Figure 44(C) shows Q1-Q2 including the source or drain region of the transistor. The band structure in the cross-section is shown. Note that this refers to regions 407a1, 407b1, and 407a Regions 2 and 407b2 are in a degenerate state. Also, in region 407b1, the semiconductor layer The Fermi level in 406a is assumed to be approximately the same as the energy at the bottom of the conduction band. Also, region 407b In step 2, the Fermi level of semiconductor layer 406b is assumed to be approximately the same as the energy of the lower edge of the conduction band. The same applies to regions 407a1 and 407a2.

[0398] At this time, a conductive layer 416b having the function of a source electrode or drain electrode, and a region 407b2 and the region are in ohmic contact because the energy barrier is sufficiently small. 407b2 and region 407b1 are in ohmic contact. Similarly, the source electrode or The conductive layer 416a, which functions as a drain electrode, and region 407a2 are energy Because the barrier is small enough, ohmic contact occurs. Also, region 407a2 and region 407a 1 and , will be in ohmic contact. Therefore, conductive layer 416a and conductive layer 416b, Electrons are smoothly transferred between semiconductor layer 406a and semiconductor layer 406b. This can be understood.

[0399] As described above, the transistor according to one aspect of the present invention has a source electrode and a drain The transfer of electrons between the electrode and the channel-forming region is smooth, resulting in low channel resistance. Furthermore, it is a transistor with extremely low off-current. That is, it has excellent switching characteristics. It can be seen that it is a transistor.

[0400] This embodiment can be appropriately combined with other embodiments shown herein. .

[0401] (Embodiment 10) In this embodiment, the effect of oxygen vacancies in the oxide semiconductor layer and the hydrogen to which said oxygen vacancies are bonded Let's explain the results.

[0402] <(1). V o Formation and stability of H > When an oxide semiconductor film (hereinafter referred to as IGZO) is a perfect crystal, at room temperature, H is preferred. It diffuses along the ab plane. Also, during the heat treatment at 450°C, H diffuses along the ab plane and Diffusion occurs in each direction along the c axis. Therefore, here, oxygen-deficient V is added to IGZO. o A place where Combined, H is oxygen-deficient V o Let's explain whether it's easy to enter or not. Here, oxygen deficiency V o Medium V is the state in which H is present. o It is denoted as H.

[0403] The calculation used the InGaZnO4 crystal model shown in Figure 45. Here, V o H in H V o It exits and activates the reaction pathway that binds to oxygen (E a ) to NEB (Nudg The calculation was performed using the (ed Elastic Band) method. The calculation conditions are shown in Table 1.

[0404] [Table 1]

[0405] Furthermore, in the InGaZnO4 crystal model, the metal elements to which oxygen atoms are bonded and their number Due to the differences, there are four types of oxygen atoms, from 1 to 4, as shown in Figure 45. Here, Oxygen Deficiency V o Calculations were performed for oxygen atom 1 and oxygen atom 2, which are more likely to form a compound.

[0406] First, we performed calculations for one oxygen atom bonded to three in atoms and one zinc atom.

[0407] The initial state model is shown in Figure 46(A), and the final state model is shown in Figure 46(B). In the initial and final states, the calculated activation barrier (E a This is shown in Figure 47. The initial state here refers to the oxygen deficiency V that occurs when oxygen atom 1 is removed. o A hydrogen atom is present inside. (V o H) is the final state, which is oxygen deficiency V o A hydrogen atom moves from one It is in a state (H-O) where it is bonded to an oxygen atom bonded to Ga and two Zn atoms.

[0408] As a result of the calculation, for the hydrogen atom in the oxygen deficiency V o to move and bond to another oxygen atom, about 1.5 2 eV of energy is required, whereas for the hydrogen atom bonded to the oxygen atom to move into the oxygen deficiency V o about 0.46 eV of energy was required.

[0409] Here, from the activation barrier (E a ) obtained by the calculation and Equation 1, the reaction frequency (Γ) was calculated . In Equation 1, k B is the Boltzmann constant and T is the absolute temperature.

[0410]

Equation

[0411] Assuming the frequency factor ν = 10 13 [1 / sec], the reaction frequency at 350 °C was calculated. The frequency of hydrogen atoms moving from the model shown in Fig. 46(A) to the model shown in Fig. 46(B) was 5 .52×10 0 [1 / sec]. Also, the frequency of hydrogen atoms moving from the model shown in Fig. 46(B) to the model shown in Fig. 46( A) was 1.82×10 9 [1 / sec] . From this, it can be said that hydrogen atoms diffusing in IGZO are likely to form V o H, and once V o H is formed, it is difficult to desorb from the oxygen deficiency V o . <​​​​​The model in the initial state is shown in Fig. 48(A), and the model in the final state is shown in Fig. 48(B). Also , in the initial and final states, the calculated activation barrier (E a ) is shown in Fig. 49. Note that , the initial state here refers to the state (V o H) where there is a hydrogen atom in the oxygen vacancy V generated by the desorption of oxygen atom 2 , and the final state refers to the state (H - O) where the hydrogen atom moves from the oxygen vacancy V o and binds to one Ga o and two oxygen atoms bonded to Zn.

[0414] As a result of the calculation, about 1.7 o 5 eV of energy is required for the hydrogen atom in the oxygen vacancy V to move and bind to another oxygen atom, while about 0.35 eV of energy is required for the hydrogen atom bonded to the oxygen atom to move into the oxygen vacancy V o .

[0415] Also, from the activation barrier (E a ) obtained by the calculation and the above formula 1, the reaction frequency (Γ) was calculated .

[0416] Assuming the frequency factor ν = 10 13 [1 / sec], the reaction frequency at 350 °C was calculated. The frequency of hydrogen atom movement from the model shown in Fig. 48(A) to the model shown in Fig. 48(B) was 7 .53 × 10 -2 [1 / sec]. Also, the frequency of hydrogen atom movement from the model shown in Fig. 48(B) to the model shown in Fig. 48 (A) was 1.44 × 10 10 [1 / sec] . From this, it can be said that once V o H is formed, it is difficult for the hydrogen atom to desorb from the oxygen vacancy V o .

[0417] ​​ From the above, it can be concluded that hydrogen atoms in IGZO diffuse easily during annealing, and oxygen deficiency V o There is In the case of oxygen deficiency V o Captured inside, V o It was found that it is more likely to become H.

[0418] <(2). V o H transition level > Oxygen deficiency in IGZO o If present, calculations using the above NEB method show that hydrogen Atoms are stable V o It can be said that H is easily formed. Therefore, V o H is involved in carrier trapping To find out if V o The transition level of H was calculated.

[0419] The calculation used an InGaZnO4 crystal model (112 atoms). The oxygen site is shown in Figure 45. V for oxygen site 1 and site 2 o An H-model was created, and the transition levels were calculated. The conditions are shown in Table 2.

[0420] [Table 2]

[0421] By adjusting the mixing ratio of the exchange term to obtain a band gap close to the experimental value, defect-free The band gap of the InGaZnO4 crystal model is 3.08 eV, which is different from the experimental value of 3.15 eV. The results were similar to those for eV.

[0422] The transition level (ε(q / q')) of a model with defect D is calculated by the following equation 2. Note that ΔE(D q ) is the formation energy at charge q of defect D, and is calculated from equation 3. It will be done.

[0423]

number

[0424]

number

[0425] In equations 2 and 3, E tot (D q ) is the charge q of the model including defect D. Total energy, E tot (bulk) represents the total energy of a flawless model (perfect crystal). Δn i μ is the number of increases or decreases in atom i related to the defect. i ε is the chemical potential of atom i. VBM is missing The energy at the top of the valence band, ΔV, in a model without depressions. q This relates to the electrostatic potential. Correction term, E F This is the Fermi energy.

[0426] Calculated V o The transition levels of H are shown in Figure 50. The values ​​in Figure 50 represent the depth from the lower end of the conduction band. Yes. From Figure 50, V relative to 1 oxygen atom. o The transition level of H is 0.05e below the lower edge of the conduction band. V is present, and V relative to 2 oxygen atoms o The transition level of H is located 0.11 eV below the lower edge of the conduction band. Therefore, each V o H will be involved in the electron trap. That is, V o H It has been revealed that he will act as a donor. Also, V o HSSAGZO is electrically conductive. It became clear that it possesses [this characteristic].

[0427] This embodiment can be combined with other embodiments shown herein as appropriate.

[0428] (Embodiment 11)

[0429] An imaging device and a semiconductor device including the imaging device according to one aspect of the present invention are display devices, part A computer, an image playback device equipped with a recording medium (typically DVD: Digital) A disc capable of playing recording media such as Versatile Discs and displaying their images. It can be used in devices that have a play function. In addition, an imaging device according to one aspect of the present invention And as electronic devices that can use a semiconductor device including the imaging device, mobile phones, Game consoles (including portable models), portable data terminals, e-readers, video cameras, digital stills Cameras such as cameras, goggle-type displays (head-mounted displays), navigation systems Sound systems, audio playback devices (car audio, digital audio players, etc.), Photocopiers, fax machines, printers, multifunction printers, automated teller machines (ATMs) Examples include vending machines. Specific examples of these electronic devices are shown in Figure 51.

[0430] Figure 51(A) shows a portable game console, consisting of a casing 901, casing 902, display unit 903, and display unit. 904, Microphone 905, Speaker 906, Control keys 907, Stylus 908, Camera It has 909, etc. Note that the portable game console shown in Figure 51(A) has two display units 903 It has a display unit 904, but the number of display units that a portable game console has is not limited to this. It is not possible. Camera 909 can use an imaging device according to one aspect of the present invention.

[0431] Figure 51(B) shows a portable data terminal, comprising a first housing 911, a display unit 912, a camera 919, etc. It has a touch panel function on the display unit 912, which allows for information input and output. A camera 919 can be equipped with an imaging device according to one embodiment of the present invention.

[0432] Figure 51(C) shows a digital camera, consisting of a housing 921, a shutter button 922, and a microphone 9 23. It has a light-emitting part 927, a lens 925, etc. The light-emitting part is located at the focal point of the lens 925. An imaging device of one aspect can be provided.

[0433] Figure 51(D) shows a wristwatch-type information terminal, comprising a housing 931, a display unit 932, and a wristband 9 33. It has a camera 939, etc. The display unit 932 may be a touch panel. An imaging device according to one embodiment of the present invention can be used in Ra939.

[0434] Figure 51(E) shows a video camera, comprising a first housing 941, a second housing 942, a display unit 943, It has an operation key 944, a lens 945, a connecting part 946, etc. Operation key 944 and lens 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. And the first housing 941 and the second housing 942 are connected by a connecting part 946. The angle between the first housing 941 and the second housing 942 can be changed by the connecting part 946. The video on the display unit 943 is connected to the first housing 941 and the second housing 94 in the connection unit 946. It may also be configured to switch according to the angle between 2 and 3. The present invention may include an imaging device according to one embodiment of the present invention.

[0435] Figure 51(F) is a mobile phone, and the housing 951 includes a display unit 952, a microphone 957, and a speaker. It has -954, camera 959, input / output terminal 956, operation buttons 955, etc. Camera An imaging device according to one aspect of the present invention can be used for 959.

[0436] This embodiment can be appropriately combined with other embodiments shown herein. .

[0437] (Embodiment 12) Here, we will use Figures 52 to 54 to show a modified version of the transistor shown in the previous embodiment. Let me explain. The transistor shown in Figure 52 is formed on the insulating layer 824 on the substrate 821. The oxide semiconductor layer 828, the insulating layer 837 in contact with the oxide semiconductor layer 828, and the insulating layer 83 It has a conductive layer 840 that is in contact with 7 and superimposed on the oxide semiconductor layer 828. Layer 837 functions as a gate insulating film. Furthermore, the conductive layer 840 is connected to the gate electrode layer. It has the function of being a .

[0438] Furthermore, an insulating layer 846 in contact with the oxide semiconductor layer 828, and an insulating layer in contact with the insulating layer 846 847 is provided on the transistor. Also, the opening of insulating layers 846 and 847 At the opening, conductive layers 856 and 857 that are in contact with the oxide semiconductor layer 828 are connected to the transistor. It is provided. The conductive layers 856 and 857 are the source electrode layer and the drain electrode layer. It has the function of being a .

[0439] Furthermore, the conductive layer, oxide semiconductor layer, and insulating layer included in the transistor shown in this embodiment The layers can be those as shown in the previous embodiment.

[0440] In the transistor shown in Figure 52(A), the oxide semiconductor layer 828 overlaps with the conductive layer 840. Region 828a is formed in the region, and region 828a is flanked by a region containing impurity elements. It has regions 828b and 828c. Also, conductive layers 856 and 857 have regions 828b and 828 It is in contact with c. Region 828a functions as a channel region. Regions 828b and 828c are The resistivity is lower compared to region 828a. Regions 828b and 828c are the source region and the do It functions as a rain area.

[0441] Alternatively, as shown in the transistor in Figure 52(B), in the oxide semiconductor layer 828, No impurity elements are added to the regions 828d and 828e that are in contact with the electroplating 856 and 857. Alternatively, in this case, the regions 828d and 828e that are in contact with the conductive layers 856 and 857 and region 82 Between 8a and region 828b and 828c, there are regions 828b and 828c that contain impurity elements. d, 828e is conductive when a voltage is applied to the conductive layers 856, 857, so It functions as both a drain region and a water region.

[0442] Note that the transistor shown in Figure 52(B) is formed after the conductive layers 856 and 857 are formed. Using layers 840 and conductive layers 856 and 857 as masks, impurity elements are added to the oxide semiconductor layer. It can be formed by doing so.

[0443] In the conductive layer 840, the edges of the conductive layer 840 may be tapered. That is, the insulating layer The angle θ1 between the surface where 837 and the conductive layer 840 are in contact and the side surface of the conductive layer 840 is 90° Less than, or 10° to 85°, or 15° to 85°, or 30° to 8 It may be 5° or less, or 45° to 85°, or 60° to 85°. This improves the coverage of the insulating layer 846 on the sides of the insulating layer 837 and the conductive layer 840. It is possible to do so.

[0444] Next, we will describe modified examples of regions 828b and 828c. (See Figures 52(C) to 5) Figure 2(F) is an enlarged view of the oxide semiconductor layer 828 and its vicinity shown in Figure 52(A). Therefore, the channel length L is the distance between regions containing a pair of impurity elements.

[0445] As shown in Figure 52(C), in the cross-sectional shape in the channel length direction, region 828a and region The boundary between regions 828b and 828c coincides with the edge of the conductive layer 840 via the insulating layer 837. They are almost identical. That is, in the upper surface shape, region 828a and region 828b, 82 The boundary of 8c coincides with or approximately coincides with the edge of the conductive layer 840.

[0446] Alternatively, as shown in Figure 52(D), in the cross-sectional shape in the channel length direction, region 828a However, it has a region that does not overlap with the edge of the conductive layer 840. This region is an offset region. It has the ability to set the length of the offset region in the channel length direction to L. off This indicates that. If there are multiple offset regions, the length of one offset region is L. off That's what they say. Off-line The net region is included in the channel region. Also, L off is less than 20% of the channel length L. Or less than 10%, or less than 5%, or less than 2%.

[0447] Alternatively, as shown in Figure 52(E), in the cross-sectional shape in the channel length direction, region 828b , 828c has a region that overlaps with the conductive layer 840 via the insulating layer 837. - It functions as an overlapping region. Overlapping region in the channel length direction Length L ov This indicates L ov This is less than 20% of the channel length L, or less than 10%, or It is less than 5% or less than 2%.

[0448] Alternatively, as shown in Figure 52(F), in the cross-sectional shape in the channel length direction, region 828a There is region 828f between region 828b and region 828a and region 828c, and region 82 It contains 8g. Regions 828f and 828g have a higher concentration of impurity elements than regions 828b and 828c. The degree is low and the resistivity is high. Here, regions 828f and 828g overlap with the insulating layer 837. However, it may overlap with the insulating layer 837 and the conductive layer 840.

[0449] Note that in Figures 52(C) through 52(F), the explanation of the transistor shown in Figure 52(A) is used. As explained above, the transistor shown in Figure 52(B) also corresponds to Figures 52(C) through 52(F) The structure of ) can be applied as appropriate.

[0450] In the transistor shown in Figure 53(A), the end of the insulating layer 837 extends beyond the end of the conductive layer 840. It is located on the side. That is, the insulating layer 837 has a shape that protrudes from the conductive layer 840. Since it is possible to keep the insulating layer 846 away from 828a, the nitrogen contained in the insulating layer 846 The ability to suppress the entry of elements such as hydrogen into region 828a, which functions as a channel region. can.

[0451] The transistor shown in Figure 53(B) has a tapered shape for the insulating layer 837 and the conductive layer 840. Furthermore, the angles of each tapered portion are different. That is, the insulating layer 837 and the conductive layer 840 The angle θ1 between the contact surface and the side surface of the conductive layer 840, and the oxide semiconductor layer 828 and the insulating layer The angle θ2 between the surface that 837 is in contact with and the side surface of the insulating layer 837 is different. Even if it is less than 90°, or between 30° and 85°, or between 45° and 70°, For example, if angle θ2 is smaller than angle θ1, the coverage of the insulating layer 846 increases. Also, If angle θ2 is greater than angle θ1, it is possible to move the insulating layer 846 away from region 828a. Therefore, the nitrogen, hydrogen, etc. contained in the insulating layer 846 function as a channel region. This can prevent it from entering 828a.

[0452] Next, regarding modified examples of regions 828b and 828c, Figures 53(C) to 53(F) are used. Let me explain. Figures 53(C) to 53(F) show the oxide semiconductor shown in Figure 53(A). This is an enlarged view of layer 828 and its vicinity.

[0453] As shown in Figure 53(C), in the cross-sectional shape in the channel length direction, region 828a and region The boundary between regions 828b and 828c coincides with the edge of the conductive layer 840 and the insulating layer 837. They are roughly in agreement. That is, in the upper surface shape, region 828a and region 828b, 8 The boundary of 28c coincides with or nearly coincides with the edge of the conductive layer 840.

[0454] Alternatively, as shown in Figure 53(D), in the cross-sectional shape in the channel length direction, region 828a However, it has a region that does not overlap with the conductive layer 840. This region functions as an offset region. In other words, in the upper surface shape, the ends of regions 828b and 828c are the ends of the insulating layer 837. It matches or closely matches, and does not overlap with the edge of the conductive layer 840.

[0455] Alternatively, as shown in Figure 53(E), in the cross-sectional shape in the channel length direction, region 828b , 828c has a region that overlaps with the conductive layer 840 via the insulating layer 837. - This is called the burlap region. That is, in the top surface shape, the edges of regions 828b and 828c are It overlaps with conductive layer 840.

[0456] Alternatively, as shown in Figure 53(F), in the cross-sectional shape in the channel length direction, region 828a There is region 828f between region 828b and region 828a and region 828c, and region 82 It contains 8g. Regions 828f and 828g have a higher concentration of impurity elements than regions 828b and 828c. The degree is low and the resistivity is high. Here, regions 828f and 828g overlap with the insulating layer 837. However, it may overlap with the insulating layer 837 and the conductive layer 840.

[0457] Note that in Figures 53(C) through 53(F), the explanation of the transistor shown in Figure 53(A) is used. As explained above, the transistor shown in Figure 53(B) also corresponds to Figures 53(C) through 53(F) The structure of ) can be applied as appropriate.

[0458] The transistor shown in Figure 54(A) has a laminated structure of conductive layer 840 and is in contact with insulating layer 837. It has a conductive layer 840a and a conductive layer 840b in contact with the conductive layer 840a. The end of the electrical layer 840a is located outside the end of the conductive layer 840b. That is, conductive layer 840 'a' has a shape that protrudes from the conductive layer 840b.

[0459] Next, we will describe modified examples of regions 828b and 828c. (See Figures 54(B) to 5) Figure 4(E) is an enlarged view of the oxide semiconductor layer 828 and its vicinity shown in Figure 54(A).

[0460] As shown in Figure 54(B), in the cross-sectional shape in the channel length direction, region 828a and region The boundary between regions 828b and 828c is the edge of conductive layer 840a included in conductive layer 840, and the insulating They coincide or nearly coincide via layer 837. That is, in the upper surface shape, region 828a And the boundaries of regions 828b and 828c coincide with or nearly coincide with the edge of the conductive layer 840. Yes, they are.

[0461] Alternatively, as shown in Figure 54(C), in the cross-sectional shape in the channel length direction, region 828a However, it has a region that does not overlap with the conductive layer 840. This region functions as an offset region. In other words, in the upper surface shape, the edges of regions 828b and 828c are the edges of the conductive layer 840. They don't overlap.

[0462] Alternatively, as shown in Figure 54(D), in the cross-sectional shape in the channel length direction, region 828b , 828c has a region that overlaps with conductive layer 840, in this case conductive layer 840a. This is called the overlapping region. That is, in the top surface shape, the edges of regions 828b and 828c are , overlapping with conductive layer 840a.

[0463] Alternatively, as shown in Figure 54(E), in the cross-sectional shape in the channel length direction, region 828a There is region 828f between region 828b and region 828a and region 828c, and region 82 It contains 8g. Impurity elements are added to regions 828f and 828g after passing through the conductive layer 840a. Therefore, regions 828f and 828g have a higher concentration of impurity elements than regions 828b and 828c. The coefficient of conductivity is low, and the resistivity is high. Note that in this case, regions 828f and 828g are connected to conductive layer 840a. Although they overlap, they may also overlap with conductive layer 840a and conductive layer 840b.

[0464] Furthermore, the end of the insulating layer 837 may be located outside the end of the conductive layer 840a.

[0465] Alternatively, the sides of the insulating layer 837 may be curved.

[0466] Alternatively, the insulating layer 837 may have a tapered shape. That is, the oxide semiconductor layer 828 and The angle between the surface that the insulating layer 837 is in contact with and the side surface of the insulating layer 837 is less than 90°, preferably 3°. An angle between 0° and 90° is also acceptable.

[0467] As shown in Figure 54(E), the oxide semiconductor layer 828 is located in regions 828b and 828c. Having regions 828f and 828g with low concentrations of pure elements and high resistivity, Electric field relaxation in the drain region is possible. Therefore, transistors caused by the electric field in the drain region This makes it possible to reduce degradation such as fluctuations in the threshold voltage.

[0468] This embodiment can be appropriately combined with other embodiments shown herein. .

[0469] (Embodiment 13) In this embodiment, an example of the image processing engine of an imaging device (image sensor) is shown in Figure I will explain using 55.

[0470] The imaging device consists of an imaging unit 4000, an analog memory unit 4010, and an image processing engine unit 4020. It consists of an A / D conversion unit 4030. The imaging unit 4000 is composed of multiple units arranged in a matrix. It has a number of pixels, a driver circuit 4001, and a readout circuit 4002. Each pixel is It is composed of photodiodes and transistors. The analog memory section 4010 has multiple It has an analog memory 4011. Here, each analog memory 4011 is connected to the imaging unit 40 The configuration shall have memory cells that are greater than or equal to the number of pixels in 00. That is, each analog memory Mori 4011 can store one frame of imaging data 4005 acquired by the imaging unit 4000. ru.

[0471] The operation of the imaging device will be described below. In the first step, one frame is taken for each pixel. The first imaging data 4005, which is the data, is acquired. Imaging is performed by sequentially exposing each pixel. The image data 4005 from step 1 can be read out using a so-called rolling shutter method, and each pixel A so-called global shutter method, which involves simultaneous exposure and sequential reading of the image data 4005, is also acceptable. .

[0472] By using a rolling shutter method, the imaging data 4005 of a certain row of pixels is read out. When this is happening, exposure can be performed on pixels in other rows, increasing the frame rate of the image. It is easy. Also, by using a global shutter system, when the subject is moving... Even so, it is possible to obtain captured images with minimal distortion.

[0473] In the second step, the first imaging data 4005 acquired at each pixel is read out by the readout circuit 40 It is stored in the first analog memory 4011 via 02. Here, unlike a normal imaging device, The first imaging data 4005 is stored as analog data in the first analog memory 4011. A configuration that stores the data in this way is effective. In other words, because analog-to-digital conversion processing is unnecessary, It is easy to increase the frame rate of the image capture.

[0474] From here on, the first and second steps are repeated n times. However, in the nth repetition... Then, the nth imaging data 4005 acquired at each pixel is read out via the readout circuit 4002. It is stored in the nth analog memory 4011.

[0475] As the third step, the image processing engine unit 4020 processes multiple analog memories 4 Using the first imaging data 4005 to the nth imaging data 4005 stored in 011, Perform the desired image processing and obtain the post-processed image data 4025.

[0476] As the fourth step, the image-processed captured data 4025 is processed by the A / D conversion unit 4030. Then, an analog-to-digital conversion is performed to acquire image data 4035.

[0477] As one of the image processing methods described above, after image processing to remove focus blur from multiple image data 4005... Acquire the image data 4025. In order to acquire the image data 4025 after image processing, The sharpness of each image data 4005 is calculated, and the image data 4005 with the highest sharpness is selected as the image. A configuration is possible in which the processed image data 4025 is acquired. Also, each image data 400 From 5, the areas with high sharpness are extracted and stitched together to create the image processing image data 4. A configuration of 025 is possible.

[0478] Furthermore, one of the differences in the above image processing is that the brightness is optimized from multiple imaging data 4005. The image data 4025 after image processing is obtained. To do this, the maximum brightness of each imaging data 4005 is calculated, and the maximum brightness reaches the saturation value. Image processing data 4025 is obtained from image data 4005, excluding image data 4005. It is possible to obtain it in this configuration.

[0479] Furthermore, the minimum brightness of each imaging data 4005 is calculated, and the imaging data where the minimum brightness has reached the saturation value Image processing data 4025 is obtained from image data 4005, excluding data 4005. This configuration is possible.

[0480] Furthermore, in conjunction with the activation of the flashlight for imaging, the first and second steps described above are performed. When the program is executed, the imaging data 4005 corresponds to the timing when the optimal amount of light was irradiated. It is possible to obtain it.

[0481] This embodiment can be appropriately combined with other embodiments shown herein. . [Explanation of Symbols]

[0482] 40 silicon substrates 50 transistors 51 Transistors 52 transistors 53 Transistors 54 transistors 55 transistors 56 transistors 58a Transistor 58b Transistor 58c transistor 60 Photodiodes 60A photodiode 60b photodiode 60C photodiode 60p light receiving section 61 Anodes 62 Cathode 63 Low resistance region 64 Light control layer 66 areas 70 Conductors 71 Wiring layer 72 wiring layer 73 Wiring layer 80 Insulating layer 81 Insulating layer 82 Insulating layer 83 Insulating layer 84 Insulating layer 85 Insulating layer 90 pixels 91 circuits 91a area 91b area 91c area 92 circuits 92a area 101 Transistors 102 transistors 103 Transistors 104 transistors 105 transistors 106 transistors 107 transistors 108 transistors 109 transistors 110 transistors 111 transistors 112 transistors 115 circuit boards 120 Insulating layer 130 Oxide semiconductor layer 130a Oxide semiconductor layer 130A Oxide Semiconductor Film 130b Oxide Semiconductor Layer 130B Oxide Semiconductor Film 130c oxide semiconductor layer 130C Oxide Semiconductor Film 140 Conductive layer 141 Conductive layer 142 Conductive layer 150 conductive layer 151 Conductive layer 152 Conductive layer 156 Resist Mask 160 Insulating layer 160A insulating film 170 Conductive layer 171 Conductive layer 171A Conductive film 172 Conductive layer 172A Conductive film 173 Conductive layer 175 Insulating layer 180 Insulating layer 190 Insulating layer 231 areas 232 areas 233 areas 311 Wiring 312 Wiring 313 Wiring 314 Wiring 315 Wiring 316 Wiring 317 Wiring 331 areas 332 areas 333 areas 334 areas 335 areas 400 circuit boards 401 Insulating layer 402 Insulating layer 402a Insulating layer 402b Insulating layer 404 Conductive layer 404a conductive layer 404b conductive layer 406 Semiconductor layer 406a Semiconductor layer 406b semiconductor layer 407a area 407a1 area 407a2 area 407b area 407b1 area 407b2 area 408 Insulating layer 408a Insulating layer 412 Insulating layer 414 Conductive layer 414a conductive layer 414b Conductive layer 416a conductive layer 416a1 conductive layer 416a2 conductive layer 416b Conductive layer 416b1 Conductive layer 416b2 Conductive layer 418 Insulating layer 428 Insulating layer 501 signal 502 signal 503 signal 504 signal 505 signal 506 signal 507 signal 508 signal 509 signal 510 period 511 period 520 period 531 period 610 period 611 period 612 period 621 period 622 period 623 period 631 period 701 signal 702 signal 703 Signal 704 signal 705 signal 821 circuit board 824 Insulating layer 828 Oxide semiconductor layer 828a area 828b area 828c area 828d area 828e area 828f area 828g area 828h area 828i area 837 Insulating layer 840 Conductive layer 840a conductive layer 840b conductive layer 846 Insulating layer 847 Insulating layer 856 Conductive layer 857 Conductive layer 901 cabinet 902 cabinet 903 Display section 904 Display section 905 Microphone 906 Speakers 907 Operation Keys 908 Stylus 909 Camera 911 cabinet 912 Display section 919 Camera 921 cabinet 922 Shutter button 923 Mike 925 lens 927 Light-emitting part 931 cabinet 932 Display section 933 Wristband 939 Camera 941 cabinet 942 cabinets 943 Display section 944 Operation Keys 945 lens 946 Connection part 951 cabinet 952 Display section 954 Speakers 955 Buttons 956 Input / output terminal 957 Mike 959 Camera 1100 layers 1200 layers 1300 layers 1400 layers 1500 Insulating layer 1510 Light blocking layer 1520 Organic resin layer 1530 Color Filters 1530a color filter 1530b color filter 1530c color filter 1540 Microlens Array 1550 Optical conversion layer 1600 Support board 1700 pixel matrix 1730 Circuit 1740 circuits 1750 circuits 1760 circuits 1770 terminal 1800 Shift Register 1810 Shift Register 1900 Buffer Circuit 1910 Buffer Circuit 2100 Analog Switch 2110 Vertical output line 2200 output line 4000 Imaging Unit 4002 Circuit 4005 Imaging data 4010 Analog Memory Section 4011 Analog Memory 4020 Image Processing Engine Unit 4025 Image processing data 4030 A / D Conversion Unit 4035 Image data

Claims

1. An imaging device comprising: a first circuit having at least a first transistor; a second circuit having at least a second transistor; and first to fifth photodiodes provided on a silicon substrate, In a plan view, the first photodiode has a substantially rectangular shape with first to fourth sides, In a plan view, the second photodiode is arranged adjacent to the first photodiode along the first side, In a plan view, the third photodiode is arranged adjacent to the first photodiode along the second side, In a plan view, the fourth photodiode is arranged adjacent to the first photodiode along the third side, In a plan view, the fifth photodiode is arranged adjacent to the first photodiode along the fourth side, In a plan view, a first hollow portion is disposed between the first photodiode and the second photodiode, In a plan view, a second hollow portion is disposed between the first photodiode and the third photodiode, In a plan view, a third hollow portion is disposed between the first photodiode and the fourth photodiode, In a plan view, it has a fourth hollow portion disposed between the first photodiode and the fifth photodiode, The first to fourth hollow sections are arranged spaced apart from each other. In a plan view, the magnitude of the first hollow portion in the direction along the first edge is greater than the magnitude in the direction perpendicular to the first edge. In a plan view, the magnitude of the second hollow portion in the direction along the second edge is greater than the magnitude in the direction perpendicular to the second edge. In a plan view, the magnitude of the third hollow portion in the direction along the third edge is greater than the magnitude in the direction perpendicular to the third edge. In a plan view, the magnitude of the fourth hollow portion in the direction along the fourth edge is greater than the magnitude in the direction perpendicular to the fourth edge. The channel formation region of the first transistor is provided on the silicon substrate, The imaging device wherein the second transistor has a region that overlaps with the first photodiode.

2. An imaging device comprising: a first circuit having at least a first transistor; a second circuit having at least a second transistor; and first to fifth photodiodes provided on a silicon substrate, In a plan view, the first photodiode has a substantially rectangular shape with first to fourth sides, In a plan view, the second photodiode is arranged adjacent to the first photodiode along the first side, In a plan view, the third photodiode is arranged adjacent to the first photodiode along the second side, In a plan view, the fourth photodiode is arranged adjacent to the first photodiode along the third side, In a plan view, the fifth photodiode is arranged adjacent to the first photodiode along the fourth side, In a plan view, a first hollow portion is disposed between the first photodiode and the second photodiode, In a plan view, a second hollow portion is disposed between the first photodiode and the third photodiode, In a plan view, a third hollow portion is disposed between the first photodiode and the fourth photodiode, In a plan view, it has a fourth hollow portion disposed between the first photodiode and the fifth photodiode, The first to fourth hollow sections are arranged spaced apart from each other. In a plan view, the first hollow portion has a shape that extends along the first edge, In a plan view, the second hollow portion has a shape that extends along the second edge, In a plan view, the third hollow portion has a shape that extends along the third edge, In a plan view, the fourth hollow portion has a shape that extends along the fourth edge, The channel formation region of the first transistor is provided on the silicon substrate, The imaging device wherein the second transistor has a region that overlaps with the first photodiode.

3. An electronic device having an imaging device according to claim 1 or 2 and a display unit.

Images