Photoelectric converter

Abstract

To provide a photoelectric conversion device with improved accuracy.SOLUTION: The photoelectric conversion device includes a pixel array in which a plurality of pixels are arranged to form a plurality of columns and a column circuit arranged to correspond to each of the plurality of columns of the pixel array. The column circuit includes a sample hold part and a plurality of potential lines including a potential line for supplying potential to the sample hold part. The plurality of potential lines are common or separate in the photoelectric conversion device.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] This invention relates to a photoelectric conversion device. [Background technology]

[0002] Patent Document 1 discloses a solid-state image sensor equipped with a sample-and-hold section for holding signals output from pixels. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] International Publication No. 2019 / 069614 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] Further improvements in accuracy are required for photoelectric conversion devices such as those described in Patent Document 1.

[0005] Therefore, the present invention aims to provide a photoelectric conversion device with improved accuracy. [Means for solving the problem]

[0006] According to one aspect of the present invention, a photoelectric converter comprising a pixel array in which a plurality of pixels are arranged in a plurality of columns, and a column circuit arranged corresponding to each of the plurality of columns of the pixel array, wherein the column circuit includes a cascaded first inverting amplifier and a first source follower circuit, a first sample-and-hold unit that holds signals output from pixels of the corresponding column, an analog-to-digital converter that converts an analog signal based on the signal into a digital signal, a first potential line that supplies a drive potential to at least one of the first inverting amplifier and the first source follower circuit, and a third potential line that supplies a drive potential to a part of the analog-to-digital converter, wherein the first potential line and the third potential line are separated in the photoelectric converter. Furthermore, a common potential is supplied to the first potential line and the third potential line from outside the photoelectric converter via different external terminals of the photoelectric converter, the analog-to-digital conversion circuit is a delta-sigma type including a digital-to-analog conversion circuit, an integrator and a quantizer, the third potential line supplies a drive potential to the quantizer, the column circuit further has a fourth potential line that supplies a drive potential to the digital-to-analog conversion circuit, the third potential line and the fourth potential line are separated in the photoelectric converter, and the first potential line and the fourth potential line are common in the photoelectric converter.A photoelectric conversion device is provided, which is characterized by...

Advantages of the Invention

[0007] According to the present invention, a photoelectric conversion device with improved accuracy is provided.

Brief Description of the Drawings

[0008] [Figure 1] It is a block diagram showing a schematic configuration of a photoelectric conversion device according to the first embodiment. [Figure 2] It is a circuit diagram of a pixel according to the first embodiment. [Figure 3] It is a timing chart for explaining the signal readout operation from a pixel according to the first embodiment. [Figure 4] It is a block diagram showing the circuit configuration and wiring connection of one column according to the first embodiment. [Figure 5] It is a block diagram showing the configuration of a second sample-and-hold unit for a reset signal according to the first embodiment. [Figure 6] It is a block diagram showing the configuration of a first sample-and-hold unit for a pixel signal according to the first embodiment. [Figure 7] It is a block diagram showing the configuration of an AD conversion unit according to the first embodiment. [Figure 8] It is a block diagram showing the circuit configuration and wiring connection of one column according to the second embodiment. [Figure 9] It is a block diagram showing the circuit configuration and wiring connection of one column according to the third embodiment. [Figure 10] It is a block diagram showing the configuration of an AD conversion unit according to the third embodiment. [Figure 11] It is a block diagram showing the circuit configuration and wiring connection of one column according to the fourth embodiment. [Figure 12] It is a block diagram showing the circuit configuration and wiring connection of one column according to the fifth embodiment. [Figure 13] It is a block diagram showing the circuit configuration and wiring connection of one column according to the sixth embodiment. [Figure 14]This is a block diagram showing the configuration of the AD conversion unit according to the seventh embodiment. [Figure 15] This is a block diagram showing the arrangement of the sample holding section according to the eighth embodiment. [Figure 16] This is a block diagram showing the schematic configuration of the imaging system according to the ninth embodiment. [Figure 17] This figure shows an example configuration of the imaging system and mobile body according to the 10th embodiment. [Modes for carrying out the invention]

[0009] Embodiments of the present invention will be described below with reference to the drawings. Elements identical or corresponding to each other across multiple drawings are denoted by the same reference numerals, and their descriptions may be omitted or simplified.

[0010] [First Embodiment] Figure 1 is a block diagram showing the schematic configuration of the photoelectric converter 100 according to this embodiment. The photoelectric converter 100 includes a pixel array 10, a vertical scanning circuit 20, a load circuit section 30, a signal holding section 40, an analog-to-digital conversion section (AD conversion section) 50, a digital memory section 60, a horizontal scanning circuit 64, a digital signal processing section 70, an output section 80, and a control circuit 90. These circuits can be formed on one or more semiconductor substrates. In this embodiment, the photoelectric converter 100 is assumed to be an imaging device for acquiring images, but is not limited to this. For example, the photoelectric converter may be a focus detection device, a distance measuring device, a TOF (Time-Of-Flight) camera, etc.

[0011] The pixel array 10 comprises a plurality of pixels 12 arranged in a plurality of rows and a plurality of columns. The vertical scanning circuit 20 is a scanning circuit that supplies control signals to control the transistors contained in the pixels 12 to be on (conducting) or off (non-conducting) via control signal lines 14 provided in each row of the pixels 12. The vertical scanning circuit 20 may be composed of a shift register or an address decoder. Here, since the control signals supplied to each pixel 12 may include a plurality of types of control signals, the control signal lines 14 in each row may be composed of a plurality of drive wiring sets. Each column of the pixels 12 is provided with a column signal line 16, and signals from the pixels 12 are read out to the column signal line 16 for each column.

[0012] The load circuit section 30 has a load circuit 32 corresponding to each row of pixels 12. The load circuit 32 supplies a bias current to the column signal line 16 of the corresponding row for reading the signal from the pixels 12. The signal holding section 40 has a sample-and-hold section 42 corresponding to each row of pixels 12. The sample-and-hold section 42 holds the signal output from the pixels 12.

[0013] The AD conversion unit 50 has an analog-to-digital conversion circuit (AD conversion circuit) 52 corresponding to each row of pixels 12. The AD conversion circuit 52 converts an analog signal based on the signal held in the sample-and-hold unit 42 into a digital signal. The digital memory unit 60 has a digital memory 62 corresponding to each row of pixels 12. The digital memory 62 stores the digital signal output from the AD conversion unit 50.

[0014] The horizontal scanning circuit 64 supplies control signals to the digital signal processing unit 70 to control the output of digital signals sequentially column by column from the digital memory unit 60. The horizontal scanning circuit 64 may be composed of a shift register or an address decoder. The digital signal processing unit 70 is a circuit that performs various signal processing on the input digital signals. The output unit 80 outputs the processed digital signals to the outside of the photoelectric converter 100. The control circuit 90 controls the operation timing of the vertical scanning circuit 20, the load circuit unit 30, the signal holding unit 40, the analog-to-digital conversion unit (AD conversion unit) 50, the digital memory unit 60, the horizontal scanning circuit 64, and the output unit 80.

[0015] As described above, a load circuit 32, a sample-and-hold unit 42, an AD conversion circuit 52, and a digital memory 62 are arranged corresponding to each column of the pixel array 10. These signal readout circuits corresponding to each column of the pixel array 10 are sometimes called column circuits.

[0016] Figure 2 is a circuit diagram of the pixel 12 according to this embodiment. The pixel 12 comprises a photoelectric conversion unit PD, a transfer transistor M1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4. These transistors may be composed of N-type MOS transistors having a gate electrode as a control electrode. Control signals PTX, PRES, and PSEL for controlling these transistors are input to the gates of the transfer transistor M1, the reset transistor M2, and the selection transistor M4 from the vertical scanning circuit 20 via the control signal line 14.

[0017] The photoelectric conversion unit PD is a photoelectric conversion element that generates an electric charge corresponding to the incident light through photoelectric conversion and stores that charge. The photoelectric conversion unit PD can be composed of a photodiode formed in a semiconductor substrate. The anode of the photodiode constituting the photoelectric conversion unit PD is connected to a potential line having ground potential GND, and the cathode is connected to the source of the transfer transistor M1.

[0018] The drain of transfer transistor M1, the source of reset transistor M2, and the gate of amplification transistor M3 are interconnected. This connection node is a so-called floating diffusion. When transfer transistor M1 is turned on, it transfers the charge from the photoelectric converter PD to the floating diffusion. The floating diffusion has capacitance, and this capacitance causes the potential of the floating diffusion to change in accordance with the charge transferred from the photoelectric converter PD.

[0019] The drains of reset transistor M2 and amplifier transistor M3 are connected to a potential line having the power supply potential VDD. The source of amplifier transistor M3 is connected to the drain of selector transistor M4. The source of selector transistor M4 is connected to column signal line 16. Amplifier transistor M3, together with a current source in load circuit 32 connected to column signal line 16, constitutes a source follower circuit. This source follower circuit outputs a signal based on the floating diffusion voltage to column signal line 16 via selector transistor M4. Reset transistor M2 resets the floating diffusion potential by turning on.

[0020] Each of the pixels 12 may have a microlens and a color filter arranged in the optical path from the incident light to the photoelectric conversion unit PD. The microlens focuses the incident light towards the photoelectric conversion unit PD. The color filter selectively transmits light of a predetermined color.

[0021] Figure 3 is a timing chart illustrating the signal readout operation from the pixel 12 according to this embodiment. Figure 3 shows the timing of the control signals PSEL, PRES, and PTX output from the vertical scanning circuit 20 to one row of a plurality of pixels 12, and the output potential VOUT output from the pixel 12 to the column signal line 16 of the corresponding column.

[0022] At time T1, the control signal PSEL becomes high level. This turns on the selection transistor M4, selecting the pixel 12 in that row, and a signal based on the floating diffusion voltage is output to the column signal line 16.

[0023] At time T2, the control signal PRES goes high, and then low. This action temporarily turns on the reset transistor M2, resetting the floating diffusion potential to a potential corresponding to the power supply potential VDD. As a result, the output potential VOUT becomes a potential based on the reset state of pixel 12. This potential is held in the sample-and-hold unit 42 as a reset signal (second signal).

[0024] At time T3, the control signal PTX goes to a high level and then to a low level. This operation temporarily turns on the transfer transistor M1, and the charge stored in the photoelectric conversion unit PD is transferred to the floating diffusion. As a result, the output potential VOUT becomes a potential based on the charge stored in the photoelectric conversion unit PD in response to the incident light. This potential is held in the sample-and-hold unit 42 as a pixel signal (first signal).

[0025] At time T4, the control signal PSEL goes to a low level. This turns off the selection transistor M4, and the selection of pixel 12 in that row is deselected.

[0026] Figure 4 is a block diagram showing the configuration and wiring of a single row of circuits according to this embodiment. Figure 4 shows a single row of pixels 12 and a portion of the row of circuits corresponding to pixels 12 described in Figure 1.

[0027] Figure 4 also shows the element region R1 of the photoelectric converter 100, where the pixel array 10, column circuits, etc., are arranged, and the pad region R2, where pads, which are external terminals for supplying a drive potential to the photoelectric converter 100 from the outside, are arranged. The element region R1 and the pad region R2 may be arranged in different regions on the semiconductor substrate. Figure 4 schematically shows that the pixel array 10, load circuit 32, sample-and-hold unit 42, and AD conversion circuit 52 are arranged within the element region R1. Figure 4 also schematically shows that pads P1, P2, P3, and P4 are arranged within the pad region R2. Pads P1, P2, P3, and P4 may be, for example, metal films to which mounting components such as bonding wires and bumps are connected.

[0028] In the following explanation, pads P1, P2, P3, and P4 are assumed to be ground terminals for supplying ground potential; however, these pads may also be power supply terminals for supplying power supply potential or reference potential terminals for supplying reference potential in each circuit. Ground potential, power supply potential, and reference potential are sometimes more generally referred to as drive potential. In other words, pads P1, P2, P3, and P4 may be external terminals that supply drive potential to each circuit of the photoelectric converter 100.

[0029] The pixel array 10 has multiple pixels 12, and the ground wiring of the pixels 12 is connected to pad P1. The load circuit 32 has a current source 34 connected to the column signal line 16. The ground wiring of the current source 34 is connected to pad P2.

[0030] The sample-and-hold unit 42 includes a first sample-and-hold unit 44S, a second sample-and-hold unit 44N, and a resistor R. The column signal line 16 is connected to the first sample-and-hold unit 44S and the second sample-and-hold unit 44N. The first sample-and-hold unit 44S acquires and holds the pixel signal output from the pixel 12 via the column signal line 16. The second sample-and-hold unit 44N acquires and holds the reset signal output from the pixel 12 via the column signal line 16.

[0031] The second sample-and-hold unit 44N is connected to the first sample-and-hold unit 44S via signal line IL1, resistor R, and signal line IL2 in that order. This allows the second sample-and-hold unit 44N to supply a current based on the held reset signal to the first sample-and-hold unit 44S. The first sample-and-hold unit 44S outputs a current based on the difference between the pixel signal and the reset signal to the AD conversion circuit 52 via signal line IL3. This enables correction processing by correlated double sampling of the pixel signal and the reset signal.

[0032] The ground wire GL1 (first potential line) of the first sample-and-hold unit 44S and the ground wire GL2 (second potential line) of the second sample-and-hold unit 44N are common at node N1 outside the element region R1. The common ground wire is connected to pad P3. Note that node N1 may be located in the element region R1 or the pad region R2, and it is sufficient that the ground wires are common at least on the sample-and-hold unit 42 side of pad P3. The ground wire GL3 (third potential line) of the AD conversion circuit 52 is connected to pad P4.

[0033] Figure 5 is a block diagram showing the configuration of the second sample-and-hold unit 44N for the reset signal according to this embodiment. The second sample-and-hold unit 44N includes a sample-and-hold circuit group 46N and an amplification unit 48N.

[0034] The sample-and-hold circuit group 46N consists of N sample-and-hold circuits 462N1 to 462N. n ~462N N It has (N is an integer greater than or equal to 2, and n is an integer greater than or equal to 1 and less than N). The sample-and-hold circuit 462N1 has switches S11, S21 and capacitor C11. Sample-and-hold circuit 462N n Switch S1 n S2 n and capacity C1 n It has the following characteristics: Sample-and-hold circuits 462N1~462N N-1Each of them has two switches and one capacitor. Sample hold circuit 462N N has switch S1 N and capacitor C1 N has.

[0035] Amplifier section 48N has an inverting amplifier 482N, transistor M5, current source 484N, and switches S3, S4, and S5. Transistor M5 is a P-type MOS transistor. A plurality of switches included in sample hold circuit group 46N and amplifier section 48N are controlled to be on or off based on control from control circuit 90.

[0036] Column signal line 16 is connected to the first terminals of switches S11 to S1 N . The second terminal of switch S11 is connected to the first terminal of switch S21 and the first terminal of capacitor Cll. The second terminal of switch S21 is connected to the second terminal of switch S12, the first terminal of switch S22, and the first terminal of capacitor C12 included in adjacent sample hold circuit 462N2. Sample hold circuits 462N2 to 462N N-1 also have the same configuration. The second terminal of switch S1 N is connected to the second terminal of switch S2 N-1 , the first terminal of capacitor C1 N and the first terminal of switch S4. The second terminals of capacitors C11 to C1 N are connected to the input terminal of inverting amplifier 482N and the first terminal of switch S3.

[0037] The output terminal of the inverting amplifier 482N is connected to the second terminal of switch S3 and the first terminal of switch S5. The second terminal of switch S5 is connected to the gate of transistor M5. The second terminal of switch S4 is connected to the sources of current source 484N and transistor M5. The power supply terminal of current source 484N is connected to a potential line having the power supply potential VDD. The connection nodes of the second terminal of switch S4, current source 484N, and transistor M5 source form the output terminal of the second sample-and-hold unit 44N and are connected to signal line IL1. The ground terminal of the inverting amplifier 482N and the drain of transistor M5 are connected to ground wiring GL2.

[0038] Thus, the amplification section 48N is an amplification circuit in which an inverting amplifier 482N (second inverting amplifier) ​​and a source follower circuit (second source follower circuit) composed of a current source 484N and transistor M5 are connected in cascaded order. The amplification section 48N has capacitors C11~C1 N A current corresponding to the voltage held can be output to the signal line IL1.

[0039] Figure 6 is a block diagram showing the configuration of the first sample-and-hold unit 44S for pixel signals according to this embodiment. The first sample-and-hold unit 44S includes a sample-and-hold circuit group 46S and an amplification unit 48S.

[0040] The sample-and-hold circuit group 46S consists of N sample-and-hold circuits 462S1 to 462S n ~462S N The sample-and-hold circuit 462S1 has switches S61, S71 and capacitor C21. n Switch S6 n S7 n and capacity C2 n It has the following characteristics: Sample-and-hold circuits 462S1~462S N-1 It has two switches and one capacitor. Sample-and-hold circuit 462S N Switch S6 N and capacity C2N It has the following. The connection relationships of the circuits within sample-and-hold circuit group 46S are the same as those of sample-and-hold circuit group 46N, so the explanation is omitted.

[0041] The amplification unit 48S includes an inverting amplifier 482S, a transistor M6, a current source 484S, and switches S8, S9, and S10. Transistor M6 is a P-type MOS transistor. Multiple switches included in the sample-and-hold circuit group 46S and the amplification unit 48S are controlled to be on or off based on control from the control circuit 90.

[0042] The connections between the inverting amplifier 482S, transistor M6, current source 484S, and switches S8, S9, and S10 are generally the same as those of the amplification section 48N. Therefore, the differences from the amplification section 48N will be explained below.

[0043] The connection node between the second terminal of switch S9, the current source 484S, and the source of transistor M6 is connected to signal line IL2. Current is input to this node from the second sample-and-hold unit 44N. The ground terminal of the inverting amplifier 482S is connected to ground wiring GL1. The drain of transistor M6 is the output terminal of the first sample-and-hold unit 44S and is connected to signal line IL3.

[0044] The amplification section 48S is an amplification circuit in which an inverting amplifier 482S (first inverting amplifier) ​​and a source follower circuit (first source follower circuit) composed of a current source 484S and transistor M6 are connected in cascaded order. The amplification section 48S has capacitors C21~C2 N A current corresponding to the voltage held in the signal line IL2 and a current corresponding to the difference between the voltage held in the signal line IL2 and the current input from the signal line IL2 can be output to the signal line IL3.

[0045] The operation of the sample-and-hold unit 42 will be explained in general terms with reference to Figures 3 to 6. During the reset signal output period between time T2 and time T3 in Figure 3, switches S11 to S1 N S3, S6 n+1 ~S6N Then, S8 turns ON. During this period, the other switches are OFF. After that, switches S11~S1 N S3, S6 n+1 ~S6 N S8 will be turned off. Due to these operations, capacities C11~C1 N , C2 n+1 ~C2 N A voltage based on the reset signal is maintained.

[0046] Subsequently, during the output period of the pixel signal between time T3 and time T4 in Figure 3, switches S21 to S2 N―1 S4, S5, S61~S6 n S8 turns ON. During this period, the other switches are OFF. This operation causes capacitors C11~C1 N These are connected in parallel, and the second sample-and-hold section 44N has capacitances C11~C1 N The device then outputs a current to signal line IL1 corresponding to the voltage held therein. After that, switches S61~S6 n S8 turns off. Due to these operations, capacity C21~C2 n A voltage based on the pixel signal is maintained.

[0047] After that, switch S21~S2 N―1 S4, S5, S71~S7 N―1 S9 and S10 are turned ON. The other switches are OFF. This operation causes capacitors C21~C2 N These are connected in parallel, and the first sample-and-hold section 44S has capacitances C21~C2 N This results in a state where a current corresponding to the voltage held in the signal line IL3 is output to the signal line IL3, corresponding to the difference between the current held in the signal line IL3 and the current input from the signal line IL2.

[0048] Through the above operation, a current signal that has undergone correction processing by correlated double sampling of the pixel signal and the reset signal can be output to the signal line IL3. In addition, in the sample-and-hold circuit group 46S, n capacitors C21~C2 n The pixel signals held in and Nn capacitors C2n+1 ~C2 N The reset signal held in the capacitor is weighted and averaged according to the number of capacitors. This attenuates the voltage difference between the reset signal and the pixel signal by a factor of n / N. Therefore, the voltage range of the input signal in the column circuit can be extended.

[0049] Figure 7 is a block diagram showing the configuration of the AD conversion circuit 52 according to this embodiment. The AD conversion circuit 52 exemplified in this embodiment is a delta-sigma type AD conversion circuit, but is not limited thereto. For example, the AD conversion circuit 52 may be an AD conversion circuit that compares a ramp signal with an input voltage and measures the time until the magnitude relationship reverses using a counter. Alternatively, the AD conversion circuit 52 may be a successive approximation type AD conversion circuit that obtains a digital value close to the input voltage by repeatedly comparing the output voltage of the DA conversion circuit with the input voltage. In this embodiment, a 1-bit AD conversion circuit is exemplified, but the number of bits is not limited thereto, and in reality, AD conversion with more bits can be performed.

[0050] The AD conversion circuit 52 includes digital-to-analog conversion circuits (DA conversion circuits) 54a and 54b, capacitors Ca and Cb, a voltage-to-current conversion unit 56, a quantizer 58, a decimation filter DF, and buffers B1 and B2. As described above, the AD conversion circuit 52 receives the current signal processed by correlated double sampling from the sample-and-hold unit 42 via the signal line IL3.

[0051] The signal line IL3 is connected to the output terminal of the DA conversion circuit 54a, the first terminal of capacitor Ca, and the input terminal of the voltage-current conversion unit 56. The output terminal of the voltage-current conversion unit 56 is connected to the output terminal of the DA conversion circuit 54b, the first terminal of capacitor Cb, and the input terminal of the quantizer 58. The output terminal of the quantizer 58 is connected to the input terminal of the decimation filter DF and the input terminal of buffer B1. The output terminal of buffer B1 is connected to the input terminal of the DA conversion circuit 54b and the input terminal of buffer B2. The output terminal of buffer B2 is connected to the input terminal of the DA conversion circuit 54a. The ground terminals of the DA conversion circuits 54a and 54b, the second terminals of capacitors Ca and Cb, the ground terminal of the voltage-current conversion unit 56, the ground terminal of the quantizer 58, and the ground terminal of the decimation filter DF are connected to the ground wiring GL3. The output terminal of the decimation filter DF is the output terminal of the AD conversion circuit 52.

[0052] Charge accumulates in the capacitor Ca according to the amount of current flowing through the signal line IL3 and the passage of time. The voltage-to-current conversion unit 56 outputs a current signal from its output terminal corresponding to the potential of the first terminal of the capacitor Ca. In this way, the capacitor Ca functions as an integrator.

[0053] Charge accumulates in the capacitor Cb according to the amount of current output from the voltage-current conversion unit 56 and the passage of time. In this way, the capacitor Cb and the voltage-current conversion unit 56 also function as integrators. The quantizer 58 can be a comparator circuit. The quantizer 58 compares the potential of the first terminal of the capacitor Cb with a predetermined threshold and outputs a 1-bit digital signal indicating the comparison result. In this way, the quantizer 58 performs a 1-bit analog-to-digital conversion. The quantizer 58 also performs oversampling at a frequency higher than the desired sampling frequency.

[0054] The digital signal output from the quantizer 58 is input to buffer B1. This digital signal is fed back to the DA conversion circuits 54a and 54b via buffers B1 and B2. The DA conversion circuits 54a and 54b include a current source, switches, etc. The DA conversion circuit 54a performs a digital-to-analog conversion by flowing a current corresponding to the input digital signal, thereby extracting a charge corresponding to the digital signal from the first terminal of capacitor Ca and flowing it to the ground wiring GL3. Similarly, the DA conversion circuit 54b extracts an amount of charge corresponding to the input digital signal from the first terminal of capacitor Cb and flows it to the ground wiring GL3. In this way, the digital signal output from the quantizer 58 is fed back to the integrator or the input side of the quantizer 58. This feedback loop operates to reduce quantization errors in the low-frequency region.

[0055] As shown in Figure 7, the AD conversion circuit 52 of this embodiment tends to have a circuit arrangement that extends in one direction, which can result in long feedback wiring. The presence of buffers B1 and B2 reduces the effects of voltage drop and other factors caused by long feedback wiring. However, if the effects of the feedback wiring are acceptable, buffers B1 and B2 may not be necessary.

[0056] The decimation filter DF reduces the sampling frequency by downsampling the signal output from the quantizer 58. This reduces noise in the high-frequency range.

[0057] As described above, the AD conversion circuit 52 of this embodiment employs a delta-sigma type, which is suitable for high precision and high resolution. This enables the output of highly accurate digital signals.

[0058] In this embodiment, as shown in Figure 4, the effects of sharing the ground wiring GL1 of the first sample-and-hold unit 44S and the ground wiring GL2 of the second sample-and-hold unit 44N will be explained. The potential of the ground wiring may fluctuate due to the operation of the circuits within the photoelectric converter 100, external noise, and other influences. This potential fluctuation can be a factor that reduces the accuracy of the output signal.

[0059] In this embodiment, the ground wiring GL1 of the first sample-and-hold unit 44S and the ground wiring GL2 of the second sample-and-hold unit 44N are shared. Therefore, the effect of fluctuations in ground potential is superimposed on both the first sample-and-hold unit 44S and the second sample-and-hold unit 44N to the same extent. Here, the reset signal held in the second sample-and-hold unit 44N is a signal used for correlated double sampling with the pixel signal held in the first sample-and-hold unit 44S. Therefore, the effect of noise on the second sample-and-hold unit 44N and the first sample-and-hold unit 44S due to fluctuations in the ground wiring potential is reduced by performing correlated double sampling. Accordingly, this embodiment provides a photoelectric converter 100 with improved accuracy.

[0060] [Second Embodiment] The photoelectric converter 100 of this embodiment is a modified version of the configuration of the first embodiment, in which the position where the ground wiring GL1 of the first sample-and-hold unit 44S and the ground wiring GL2 of the second sample-and-hold unit 44N are shared is changed. Other elements are the same as in the first embodiment, so their description is omitted.

[0061] Figure 8 is a block diagram showing the configuration and wiring connections of a single row of circuits according to this embodiment. As shown in Figure 8, the ground wiring GL1 of the first sample-and-hold unit 44S and the ground wiring GL2 of the second sample-and-hold unit 44N are common at node N2 within the sample-and-hold unit 42. Although only one row is shown in Figure 8, node N2 where the ground wiring is common may be provided for each row of circuits.

[0062] In this embodiment, instead of the ground wiring being shared outside the element region R1 as in the first embodiment, a common node N2 is provided for each row. Since the ground wiring is shared for each unit of correlated double sampling, the noise reduction effect can be further improved.

[0063] In the configuration of the first embodiment, the ground wiring is shared at node N1, which is closer to pad P3. Furthermore, node N1 can be provided in common for multiple row circuits. This configuration reduces the common impedance caused by the wiring between node N1 and pad P3. Therefore, depending on the design, the configuration of the first embodiment may reduce noise more effectively. The configurations of the first and second embodiments can be appropriately selected considering circuit design, layout, and other conditions.

[0064] [Third Embodiment] The photoelectric converter 100 of this embodiment is a modified version of the first embodiment, in which the ground wiring configuration of the AD conversion circuit 52 is changed. Since all other elements are the same as in the first embodiment, their description is omitted.

[0065] Figure 9 is a block diagram showing a single-row circuit configuration and wiring connections according to this embodiment. As shown in Figure 9, the ground wire GL4 (fourth potential line) of some circuits in the AD conversion circuit 52 is shared with the ground wires GL1 and GL2 at node N3.

[0066] Figure 10 is a block diagram showing the configuration of the AD conversion circuit 52 according to this embodiment. As shown in Figure 10, the ground terminal of the DA conversion circuit 54a is connected to the ground wiring GL4. The ground terminal of the DA conversion circuit 54b, the second terminals of capacitors Ca and Cb, the ground terminal of the voltage-current conversion unit 56, the ground terminal of the quantizer 58, and the ground terminal of the decimation filter DF are connected to the ground wiring GL3.

[0067] In this embodiment, the ground wiring GL3 connected to the AD conversion operation part, such as the quantizer 58, within the AD conversion circuit 52 is separated from the ground wiring GL4 of the DA conversion circuit 54a located on the input side of the AD conversion circuit 52. This reduces kickback caused by potential fluctuations resulting from the AD conversion operation affecting the input-side node. Furthermore, since the ground wiring GL3 is also separated from the grounds of the first sample-and-hold unit 44S and the second sample-and-hold unit 44N, kickback to the first sample-and-hold unit 44S and the second sample-and-hold unit 44N is also reduced. Therefore, according to this embodiment, a photoelectric conversion device 100 with improved accuracy is provided.

[0068] Furthermore, in this embodiment as in the first embodiment, the ground wiring GL1 and ground wiring GL2 are shared at node N3. As a result, for the same reasons as in the first embodiment, the influence of noise on the first sample-and-hold unit 44S and the second sample-and-hold unit 44N can be reduced.

[0069] [Fourth Embodiment] The photoelectric converter 100 of this embodiment is a modified version of the configuration of the third embodiment, in which the positions where the ground wirings GL1, GL2, and GL4 are common have been changed. Since the other elements are the same as those of the third embodiment, their description will be omitted.

[0070] Figure 11 is a block diagram showing the configuration and wiring connections of a single row of circuits according to this embodiment. As shown in Figure 11, ground wires GL1, GL2, and GL4 are common at node N4 in the sample-and-hold section 42. Although only one row is shown in Figure 11, node N4, where the ground wires are common, may be provided for each row of circuits.

[0071] In this embodiment, unlike the third embodiment, the ground wiring is not shared outside the element region R1, but rather a common node N4 is provided for each row. Since the ground wiring is shared for each unit of correlated double sampling and AD conversion, the noise reduction effect can be further improved.

[0072] In the configuration of the third embodiment, the ground wiring is shared at node N3, which is closer to pad P3. Furthermore, node N3 can be provided in common for multiple row circuits. This configuration reduces the common impedance caused by the wiring between node N3 and pad P3. Therefore, depending on the design, the configuration of the third embodiment may reduce noise more effectively. The configurations of the third and fourth embodiments can be appropriately selected considering circuit design, layout, and other conditions.

[0073] [Fifth Embodiment] The photoelectric converter 100 of this embodiment is a modified version of the third embodiment, with changes to the configuration of the ground wiring GL1 of the first sample-and-hold unit 44S and the arrangement of the pads. Other elements are the same as in the third embodiment, and therefore their description is omitted.

[0074] Figure 12 is a block diagram showing a single-row circuit configuration and wiring connections according to this embodiment. As shown in Figure 12, the ground wiring GL4 of a part of the AD conversion circuit 52 is shared with the ground wiring GL2 of the second sample-and-hold unit 44N at node N5. Node N5 is connected to pad P3. The ground wiring GL1 of the first sample-and-hold unit 44S is not connected to node N5, but is connected to pad P5.

[0075] In this embodiment, as in the third embodiment, the ground wiring GL3 and ground wiring GL4 are separated, so the effect of noise reduction by reducing kickback can be obtained. Therefore, according to this embodiment, a photoelectric converter 100 with improved accuracy is provided.

[0076] In Figure 12, ground wiring GL4 is shared with ground wiring GL2 at node N5, while ground wiring GL1 is separated from them. However, a configuration in which ground wiring GL4 is shared with ground wiring GL1 and ground wiring GL2 is separated from them is also possible.

[0077] [Sixth Embodiment] The photoelectric converter 100 of this embodiment is a modified version of the configuration of the fifth embodiment, in which the position where the ground wirings GL2 and GL4 are common has been changed. Since the other elements are the same as those of the fifth embodiment, their description will be omitted.

[0078] Figure 13 is a block diagram showing the configuration and wiring connections of a single row of circuits according to this embodiment. As shown in Figure 13, the ground wire GL2 and the ground wire GL4 are common at node N6 in the sample-and-hold section 42. Although only one row is shown in Figure 13, node N6, where the ground wires are common, may be provided for each row of circuits.

[0079] In this embodiment, unlike in the fifth embodiment, the ground wiring is not shared outside the element region R1, but rather a common node N6 is provided for each row. Since the ground wiring is shared for each AD conversion unit, the noise reduction effect can be further improved.

[0080] In the configuration of the fifth embodiment, the ground wiring is shared at node N5, which is closer to pad P3. Furthermore, node N5 can be provided in common for multiple row circuits. This configuration reduces the common impedance caused by the wiring between node N5 and pad P3. Therefore, depending on the design, the configuration of the fifth embodiment may reduce noise more effectively. The configurations of the fifth and sixth embodiments can be appropriately selected considering circuit design, layout, and other conditions.

[0081] In Figure 13, ground wiring GL4 is shared with ground wiring GL2 at node N6, while ground wiring GL1 is separated from them. However, a configuration in which ground wiring GL4 is shared with ground wiring GL1 and ground wiring GL2 is separated from them is also possible.

[0082] [Seventh Embodiment] The photoelectric converter 100 of this embodiment is a modified version of any of the third to sixth embodiments, in which the configuration of the ground wiring in the AD conversion circuit 52 is changed. Since the other elements are the same as those of the third to sixth embodiments, their description is omitted.

[0083] Figure 14 is a block diagram showing the configuration of the AD conversion circuit 52 according to this embodiment. As shown in Figure 14, the ground terminal of the DA conversion circuit 54a and the second terminal of the capacitor Ca are connected to the ground wiring GL4. The ground terminal of the DA conversion circuit 54b, the second terminal of the capacitor Cb, the ground terminal of the voltage-current conversion unit 56, the ground terminal of the quantizer 58, and the ground terminal of the decimation filter DF are connected to the ground wiring GL3.

[0084] In this embodiment, the ground wiring GL3 connected to the AD conversion operation portion, such as the quantizer 58, within the AD conversion circuit 52 is separated from the ground wiring GL4 of the DA conversion circuit 54a and the second terminal of the capacitor Ca, which are located on the input side of the AD conversion circuit 52. This reduces kickback caused by potential fluctuations resulting from the AD conversion operation, which can affect the input-side node. Therefore, according to this embodiment, a photoelectric conversion device 100 with improved accuracy is provided.

[0085] Figures 10 and 14 show two examples of methods for separating the ground wires GL3 and GL4 within the AD conversion circuit 52, but the method is not limited to these. For example, the ground wire may be separated at the node between the ground terminal of the voltage-current conversion unit 56 and the ground terminal of the DA conversion circuit 54b. Alternatively, the ground wire may be separated at the node between the ground terminal of the DA conversion circuit 54b and the second terminal of the capacitor Cb. Furthermore, the ground wire may be separated at the node between the second terminal of the capacitor Cb and the ground terminal of the quantizer 58. In this way, if at least the ground terminal of the quantizer 58 is separated from the ground terminal of the element preceding it, the effect of reducing kickback can be obtained.

[0086] [Eighth Embodiment] The photoelectric converter 100 of this embodiment provides a more concrete arrangement of the sample-hold unit 42 described in the first embodiment. The configuration of the sample-hold unit 42 described in this embodiment is applicable to any of the first to seventh embodiments, and the parts that overlap with the first to seventh embodiments will not be explained.

[0087] Figure 15 is a block diagram showing the arrangement of the sample-hold section 42 according to the eighth embodiment. Figure 15 shows the sample-hold circuits 462N1 to 462N N Amplifier section 48N, sample-and-hold circuit 462S1~462S N The arrangement of the amplifier section 48S is schematically shown. The connection relationships of each section are the same as those shown in Figures 5 and 6, so the explanation is omitted. As shown in Figure 15, the column signal line 16, signal lines IL1, IL2, and IL3 extend in the first direction (vertical direction in Figure 15). And, as shown in Figure 15, the sample-and-hold circuits 462N1~462N N Amplifier section 48N, sample-and-hold circuit 462S1~462S N Each block of the amplification section 48S also extends in the first direction in this order. By arranging each circuit and signal line in parallel in this way, these elements can be laid out efficiently.

[0088] [Ninth Embodiment] An imaging system according to the ninth embodiment of the present invention will be described with reference to Figure 16. Figure 16 is a block diagram showing the schematic configuration of the imaging system according to this embodiment.

[0089] The photoelectric converter 100 described in the first to eighth embodiments above is applicable to various photoelectric conversion systems. An example of a photoelectric conversion system is an imaging system. Examples of imaging systems to which the photoelectric converter 100 can be applied include digital still cameras, digital camcorders, surveillance cameras, photocopiers, fax machines, mobile phones, in-vehicle cameras, and observation satellites. A camera module equipped with an optical system such as a lens and a photoelectric converter is also included in the imaging system. Figure 16 shows a block diagram of a digital still camera as an example of these.

[0090] The imaging system 200 illustrated in Figure 16 includes an imaging device 201, a lens 202 for forming an optical image of a subject onto the imaging device 201, an aperture 204 for varying the amount of light passing through the lens 202, and a barrier 206 for protecting the lens 202. The lens 202 and the aperture 204 are an optical system that focuses light onto the imaging device 201. The imaging device 201 is a photoelectric conversion device 100 described in any of the first to eighth embodiments, which converts the optical image formed by the lens 202 into image data.

[0091] The imaging system 200 also includes a signal processing unit 208 that processes the output signal from the imaging device 201. The signal processing unit 208 generates image data from the digital signal output by the imaging device 201. The signal processing unit 208 also performs various corrections and compressions as needed before outputting the image data.

[0092] The imaging system 200 further includes a memory unit 210 for temporarily storing image data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. Furthermore, the imaging system 200 includes a recording medium 214 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading data from the recording medium 214. The recording medium 214 may be built into the imaging system 200 or it may be detachable.

[0093] Furthermore, the imaging system 200 includes an overall control and calculation unit 218 that performs various calculations and controls the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the imaging device 201 and the signal processing unit 208. Here, the timing signals and the like may be input from an external source, and the imaging system 200 only needs to include at least an imaging device 201 and a signal processing unit 208 that processes the output signals output from the imaging device 201.

[0094] The imaging device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the imaging device 201 and outputs image data. The signal processing unit 208 generates an image using the imaging signal.

[0095] Thus, according to this embodiment, an imaging system can be realized that applies the photoelectric converter 100 according to the first to eighth embodiments.

[0096] [Tenth Embodiment] An imaging system and mobile body according to a 10th embodiment of the present invention will be described with reference to Figure 17. Figure 17 is a diagram showing the configuration of the imaging system and mobile body according to this embodiment.

[0097] Figure 17(a) shows an example of an imaging system for an in-vehicle camera. The imaging system 300 includes an imaging device 310. The imaging device 310 is the photoelectric converter 100 described in any of the first to eighth embodiments above. The imaging system 300 includes an image processing unit 312 that performs image processing on a plurality of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the imaging system 300. The imaging system 300 also includes a distance acquisition unit 316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc. The collision determination unit 318 may use any of this distance information to determine the possibility of collision. The means for acquiring distance information may be implemented by specially designed hardware, or by a software module. It may also be implemented by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a combination thereof.

[0098] The imaging system 300 is connected to the vehicle information acquisition device 320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The imaging system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate braking force on the vehicle based on the judgment result of the collision judgment unit 318. The imaging system 300 is also connected to a warning device 340 that issues a warning to the driver based on the judgment result of the collision judgment unit 318. For example, if the collision judgment result of the collision judgment unit 318 indicates a high probability of collision, the control ECU 330 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 340 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel.

[0099] In this embodiment, the imaging system 300 captures images of the area around the vehicle, for example, the front or rear. Figure 17(b) shows the imaging system when capturing images of the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends instructions to the imaging system 300 or the imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0100] The above example described controlling a vehicle to avoid collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles or automatically drive a vehicle to prevent it from straying from its lane. Furthermore, the imaging system can be applied not only to vehicles such as the vehicle itself, but also to moving objects (mobile devices) such as ships, aircraft, or industrial robots. In addition, it can be applied not only to moving objects, but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS).

[0101] [Modified Embodiment] The present invention is not limited to the embodiments described above and can be modified in various ways. For example, an example in which a part of the configuration of one embodiment is added to another embodiment, or in which a part of the configuration of another embodiment is replaced, is also an embodiment of the present invention.

[0102] Furthermore, the imaging systems shown in the ninth and tenth embodiments described above are examples of imaging systems to which the photoelectric conversion device of the present invention can be applied, and the imaging systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 16 and 17.

[0103] In the embodiments described above, two types of examples are shown: one in which a node for common ground wiring is provided corresponding to each column circuit, and another in which a node is provided in common for multiple column circuits, but the invention is not limited to these. For example, if any two columns among multiple columns are designated as the first column and the second column, the ground wiring of the first column may be common with the ground wiring of the second column. Here, the first column and the second column may be adjacent columns or not adjacent columns. An example of the case where the columns are not adjacent is when both the first column and the second column are even-numbered columns, or when both the first column and the second column are even-numbered columns. Another example is when the first column and the second column are columns in which the same color color filter is placed on the pixel 12. Yet another example is when, in a configuration in which the column circuits extend both upwards and downwards from the pixel array 10, the first column and the second column may be columns arranged in different directions.

[0104] Furthermore, while the embodiments described above include various examples in which the ground wiring supplying the ground potential is common or separate, the system is not limited thereto. For example, the power wiring supplying the power potential may be common or separate in a similar manner to the ground wiring described above, and the reference potential wiring supplying the reference potential may be common or separate. Similar effects can be obtained in these examples as well. Ground wiring, power wiring, and reference potential wiring are sometimes more generally referred to as potential lines.

[0105] The present invention can also be realized by supplying a program that implements one or more of the functions of the above-described embodiments to a system or device via a network or storage medium, and by having one or more processors in the computer of that system or device read and execute the program. It can also be realized by a circuit (e.g., an ASIC) that implements one or more functions.

[0106] It should be noted that the embodiments described above are merely examples of how the present invention can be implemented, and the technical scope of the present invention should not be interpreted as being limited by them. In other words, the present invention can be implemented in various ways without departing from its technical concept or its main features. [Explanation of symbols]

[0107] 10-pixel array 12 pixels 44S First sample holding section 44N Second sample holding section 52 AD conversion circuit 100 Photoelectric converter GL1, GL2, GL3 Ground Wiring

Claims

1. A pixel array in which multiple pixels are arranged in multiple columns, A column circuit is arranged corresponding to each of the multiple columns of the aforementioned pixel array, A photoelectric conversion device having, The aforementioned column circuit is A first sample-and-hold unit, which includes a cascaded first inverting amplifier and a first source follower circuit, holds the signal output from the pixels of the corresponding column, An analog-to-digital conversion circuit that converts an analog signal based on the aforementioned signal into a digital signal, A first potential line that supplies a drive potential to at least one of the first inverting amplifier and the first source follower circuit, A third potential line that supplies a drive potential to a part of the aforementioned analog-to-digital conversion circuit, It has, The first potential line and the third potential line are separated in the photoelectric conversion device. A common potential is supplied to the first potential line and the third potential line from outside the photoelectric converter via different external terminals of the photoelectric converter. The analog-to-digital conversion circuit is a delta-sigma type including a digital-to-analog conversion circuit, an integrator, and a quantizer. The third potential line supplies a driving potential to the quantizer. The aforementioned column circuit further includes a fourth potential line that supplies a drive potential to the digital-to-analog conversion circuit. The third potential line and the fourth potential line are separated in the photoelectric conversion device. The first potential line and the fourth potential line are common to the photoelectric conversion device. A photoelectric conversion device characterized by the following features.

2. The node where the first potential line and the fourth potential line are connected is provided in accordance with each of the multiple column circuits. The photoelectric conversion device according to feature 1.

3. The node where the first potential line and the fourth potential line are connected is provided in common for multiple of the aforementioned column circuits. The photoelectric conversion device according to feature 1.

4. The first potential line and the fourth potential line included in the column circuit of the first column among the plurality of columns are shared with the first potential line and the fourth potential line included in the column circuit of the second column among the plurality of columns. The photoelectric conversion device according to feature 1.

5. The third potential line supplies a driving potential to the integrator. The photoelectric conversion device according to any one of claims 1 to 4.

6. The fourth potential line supplies a driving potential to the integrator. The photoelectric conversion device according to any one of claims 1 to 4.

7. The first sample-and-hold unit holds a first signal based on the light incident on the pixels of the corresponding row. The aforementioned column circuit is A second sample-and-hold unit includes a cascaded second inverting amplifier and a second source follower circuit, which holds a second signal based on the reset state of the pixels in the corresponding column, A second potential line that supplies a drive potential to at least one of the second inverting amplifier and the second source follower circuit, It further possesses, The first potential line and the second potential line are common to the photoelectric conversion device. The photoelectric conversion device according to any one of claims 1 to 6.

8. The aforementioned drive potential is one of the power supply potential, ground potential, or reference potential. The photoelectric conversion device according to any one of claims 1 to 7.

9. A photoelectric conversion device according to any one of claims 1 to 8, A signal processing means for processing the signal output from the aforementioned photoelectric converter, A photoelectric conversion system characterized by having the following features.

10. It is a mobile object, A photoelectric conversion device according to any one of claims 1 to 8, Distance information acquisition means that acquires distance information to an object from a parallax image based on a signal from the aforementioned photoelectric converter, A control means for controlling the moving object based on the distance information, A mobile body characterized by having the following features.

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