Gate drive circuit

Abstract

To remove common mode noise superimposed on an output side and an input side.SOLUTION: A gate drive circuit 100 includes: a signal conversion circuit 2 for converting a gate control signal 11 to a differential signal 21 comprising a positive signal 21A and a negative signal 21B; a first pulse transformer 3 having a primary winding and a secondary winding respectively having a neutral point, wherein the neutral point of the primary winding is set at a first ground potential and the positive signal 21A and the negative signal 21B are respectively inputted to both ends of the primary winding; an input difference voltage generation circuit 6 for generating a pair of input difference voltages 22A, 22B at both ends of a pair of resistance elements based on a both-end voltage of the secondary winding of the first pulse transformer 3; a differential amplifier circuit 7 for differentially amplifying the pair of input difference voltages 22A, 22B and outputting a pair of output difference voltages 23A, 23B; and a gate drive signal generation circuit 9 for generating a gate drive signal 25A based on the pair of output difference voltages 23A, 23B.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] The present invention relates to a gate drive circuit. [Background Art]

[0002] Conventionally, in a gate drive circuit that drives a switching element operating in a floating state, it is known to insulate an input side from an output side. In such cases, common mode noise may occur due to switching of the switching element or the like. Various proposals have been made as countermeasures against this common mode noise. For example, in the gate drive circuit of Patent Document 1, an input side and an output side are insulated by a pulse transformer, the input side is grounded to a first ground potential point, and the output side is grounded to a second ground potential point. A primary-side gate drive signal is input to a primary winding of the pulse transformer, an output on a secondary side of the pulse transformer is differentially amplified by a comparator, and output as a secondary-side gate drive signal. Further, an electrostatic shield plate grounded to the second ground potential point is disposed between the primary winding and the secondary winding of the pulse transformer. [Prior Art Documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2013-074079 [Summary of the Invention] [Problem to be Solved by the Invention]

[0004] The gate drive circuit of Patent Document 1 can remove common mode noise superimposed on the output side, but cannot remove common mode noise superimposed on the input side.

[0005] The present invention has been made to solve such problems, and an object of the present invention is to provide a gate drive circuit capable of removing common mode noise superimposed on an output side and an input side. [Means for solving the problem]

[0006] To achieve the above objective, a gate drive circuit according to one aspect of the present disclosure includes: a signal conversion circuit that operates with the potential of a first ground as the reference potential and converts a gate control signal, which is a single-ended signal, into a differential signal consisting of a positive signal and a negative signal whose signal level difference corresponds to the gate control signal; a first pulse transformer having a primary winding and a secondary winding that are electrically isolated from each other and each having a neutral point, the neutral point of the primary winding being at the potential of the first ground and the positive and negative signals of the differential signal being input to both ends of the primary winding, respectively; and a pair of resistive elements connected in series with respect to both ends and connections of the pair of resistive elements. The device comprises: an input differential voltage generation circuit that is connected directly or electrically to both ends of the secondary winding of the first pulse transformer and to the neutral point of the first pulse transformer, respectively, and generates a pair of input differential voltages at both ends of the pair of resistive elements with reference to the potential of the connection point; a differential amplifier circuit that is electrically connected to the input differential voltage generation circuit and differentially amplifies the pair of input differential voltages to output a pair of output differential voltages; and a gate drive signal generation circuit that is electrically connected to the differential amplifier circuit and generates a gate drive signal, which is a single-ended signal with reference to a predetermined potential, based on the pair of output differential voltages, and outputs the gate drive signal to a switching element that operates with reference to the potential of the second ground. [Effects of the Invention]

[0007] The present invention has the effect of providing a gate drive circuit that can remove common-mode noise superimposed on both the output and input sides. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a circuit diagram showing the configuration of a push-pull amplifier circuit using the gate drive circuit of this disclosure. [Figure 2A]Figure 2A is a block diagram showing a first configuration example of the gate drive circuit shown in Figure 1. [Figure 2B] Figure 2B is a block diagram showing a second configuration example of the gate drive circuit shown in Figure 1. [Figure 3] Figure 3 is a circuit diagram showing a specific example of the circuit configuration of the first configuration example of the gate drive circuit shown in Figure 2A. [Figure 4A] Figure 4A is a waveform diagram showing the waveform of a differential signal superimposed with common-mode noise. [Figure 4B] Figure 4B is a waveform diagram showing the waveform of the differential signal induced in the first pulse transformer by the differential signal in Figure 4A. [Figure 4C] Figure 4C is a waveform diagram showing the waveform of the input differential voltage generated by the input differential voltage generation circuit from the differential signal induced in the first pulse transformer in Figure 4B. [Figure 5] Figure 5 is a circuit diagram showing the operation of a switching power supply using the push-pull amplifier circuit shown in Figure 3. [Figure 6] Figure 6 is a schematic diagram illustrating the switching noise generated by the switching module shown in Figure 5. [Modes for carrying out the invention]

[0009] A gate drive circuit according to one aspect of the present disclosure includes: a signal conversion circuit that operates with the potential of a first ground as the reference potential and converts a gate control signal, which is a single-ended signal, into a differential signal consisting of a positive signal and a negative signal whose signal level difference corresponds to the gate control signal; a first pulse transformer having a primary winding and a secondary winding that are electrically isolated from each other and each having a neutral point, the neutral point of the primary winding being at the potential of the first ground and the positive and negative signals of the differential signal being input to both ends of the primary winding, respectively; and a pair of resistive elements connected in series with each other, wherein both ends and the connection point of the pair of resistive elements are directly electrically The system comprises: an input difference voltage generation circuit connected to both ends of the secondary winding and the neutral point of the first pulse transformer, respectively, via a transmission cable and a second pulse transformer, and which generates a pair of input difference voltages at both ends of the pair of resistive elements with reference to the potential of the connection points; a differential amplifier circuit electrically connected to the input difference voltage generation circuit, which differentially amplifies the pair of input difference voltages to output a pair of output difference voltages; and a gate drive signal generation circuit electrically connected to the differential amplifier circuit, which generates a gate drive signal, which is a single-ended signal with reference to a predetermined potential, based on the pair of output difference voltages, and outputs the gate drive signal to a switching element that operates with reference to the potential of the second ground.

[0010] In this configuration, the input and output sides of the gate drive circuit are isolated from each other by a first pulse transformer. The input side is referenced to the potential of the first ground, while the output side is connected to a switching element and is in a floating state referenced to the potential of the second ground. In this state, the single-ended gate control signal is converted by a signal conversion circuit into a differential signal consisting of a positive signal and a negative signal corresponding to the gate control signal, where the difference in their signal levels is equal. The neutral point of the primary winding of the first pulse transformer is set to the potential of the first ground, and the differential signal is input to both ends of the primary winding. As a result, the positive and negative signals are converted into a pair of single-ended voltage signals, each with twice the amplitude and opposite phase (reverse positive and negative), which are induced as voltages across the windings of the same transformer. Therefore, if common-mode noise is superimposed on these positive and negative signals on the input side, the common-mode noise of the positive signal and the common-mode noise of the negative signal have opposite positive and negative signs, and are therefore canceled out and removed by the first pulse transformer.

[0011] Furthermore, on the output side, both ends and the connection point of a pair of resistive elements in the input differential voltage generation circuit are connected directly or electrically, or via a transmission cable and a second pulse transformer, to both ends and the neutral point of the secondary winding of the first pulse transformer, respectively. A pair of input differential voltages are generated across the ends of the pair of resistive elements, with the potential of the connection point as the reference. These two input differential voltages are then differentially amplified by the differential amplifier circuit. Therefore, if common-mode noise is superimposed on a pair of wires directly or indirectly connected to both ends of the secondary winding of the first pulse transformer on the output side, the common-mode noise of these wires will have their positive and negative signs reversed in the pair of input differential voltages generated by the input differential voltage generation circuit, and will be removed by the differential amplifier circuit. In addition, since the load current of the first pulse transformer flows through the pair of resistive elements in the input differential voltage generation circuit, the impedance of the differential signal transmission path is reduced, improving the ability to remove common-mode noise.

[0012] As a result, a gate drive circuit capable of removing common-mode noise superimposed on both the output and input sides can be provided.

[0013] The second pulse transformer has a primary winding and a secondary winding that are electrically insulated from each other and each has a neutral point, and both ends and the neutral point of the primary winding are electrically connected to both ends and the neutral point of the secondary winding of the first pulse transformer via the transmission cable, and the input differential voltage generation circuit may have both ends and the connection point of the pair of resistive elements connected to both ends and the neutral point of the secondary winding of the second pulse transformer, respectively.

[0014] With this configuration, if common-mode noise is superimposed on the secondary winding of the first pulse transformer and the transmission cable, the second pulse transformer can remove the common-mode noise, similar to the first pulse transformer. As a result, by lengthening the transmission cable, the control device that generates the gate control signal can be positioned away from the switching elements, and the computer constituting the control device can be suitably protected from noise generated by the switching operation of the switching elements.

[0015] The two switching elements constitute a first switching element and a second switching element that are connected to each other in a push-pull configuration. The aforementioned gate drive circuit is The differential amplifier circuit comprises a first differential amplifier circuit and a second differential amplifier circuit. The aforementioned gate drive circuit isAs the gate drive signal generation circuits, first and second gate drive signal generation circuits are provided; the first differential amplifier circuit is a circuit electrically connected to the input differential voltage generation circuit, which differentially amplifies the pair of input differential voltages and outputs a pair of first differential voltages at a high potential; the second differential amplifier circuit is a circuit electrically connected to the input differential voltage generation circuit, which differentially amplifies the pair of input differential voltages and outputs a pair of second differential voltages at a low potential lower than the pair of first differential voltages; the first gate drive signal generation circuit may be a circuit electrically connected to the first differential amplifier circuit, which generates a first gate drive signal that is the gate drive signal with a positive potential as a reference based on the pair of first differential voltages, and outputs the first gate drive signal to the first switching element; and the second gate drive signal generation circuit may be a circuit electrically connected to the second differential amplifier circuit, which generates a second gate drive signal that is the gate drive signal with a negative potential as a reference based on the pair of second differential voltages, and outputs the second gate drive signal to the second switching element.

[0016] According to this configuration, the first switching element and the second switching element which are push-pull connected to each other can be driven while removing common mode noise superimposed on the output side and the input side.

[0017] The gate drive signal generation circuit may be a circuit that includes a flip-flop to which the pair of output differential voltages are input and which outputs a single-ended signal with a predetermined potential as a reference, and outputs the single-ended signal as the gate drive signal.

[0018] According to this configuration, the flip-flop can generate the gate drive signal which is a single-ended signal with a predetermined potential as a reference. Furthermore, the waveforms of the pair of output differential voltages of the differential amplifier circuit can be shaped, thereby further removing common mode noise.

[0019] Specific embodiments of this disclosure will be described below with reference to the drawings. In the following, the same or corresponding elements are denoted by the same reference numerals throughout all drawings, and redundant explanations are omitted. Furthermore, since the following figures are for illustrative purposes of this disclosure, elements unrelated to this disclosure may be omitted, dimensions may be inaccurate due to exaggeration, simplifications may occur, and the forms of corresponding elements may not match across multiple figures. Also, this disclosure is not limited to the following embodiments.

[0020] (Embodiment) First, the operating environment of the gate drive circuit of this disclosure will be described.

[0021] [Usage environment] Figure 1 is a circuit diagram showing the configuration of a push-pull amplifier circuit 500 in which the gate drive circuit 100 of this disclosure is used. Referring to Figure 1, the push-pull amplifier circuit 500 includes a pair of push-pull connected switching elements 60 and the gate drive circuit 100. The pair of switching elements 60 consists of a high-side first switching element 61, composed of, for example, a PMOSFET, and a low-side second switching element 62, composed of, for example, an NMOSFET, connected in series between a positive power supply VDD and a second ground GND2, and the output is taken from their connection point. The gate drive circuit 100 has an insulated input side and an output side, with the input side connected to a first ground GND1 and the output side electrically connected to the pair of switching elements 60. Therefore, the output side is floating relative to the input side's first ground GND1. The gate drive circuit 100 generates a gate drive signal from a gate control signal 11 input from a control board 1, and drives the pair of switching elements 60 with the gate drive signal. Next, the configuration of the gate drive circuit 100 will be described.

[0022] [Configuration of gate drive circuit 100] First, an overview of the configuration of the gate drive circuit 100 will be described. The gate drive circuit 100 includes the first to third configuration examples.

[0023] {overview} Figure 2A is a block diagram showing a first configuration example of the gate drive circuit 100 in Figure 1.

[0024] First, let's describe the first configuration example. The first configuration example is a configuration example of a gate drive circuit 100 when a transmission cable 4 and a second pulse transformer are included. Referring to Figure 2A, the gate drive circuit 100 includes a signal conversion circuit 2, a first pulse transformer 3, a transmission cable 4, a second pulse transformer 5, an input differential voltage generation circuit 6, a first differential amplifier circuit 7, a second differential amplifier circuit 8, a first gate drive signal generation circuit 9, and a second gate drive signal generation circuit 10.

[0025] The signal conversion circuit 2 operates with the potential of the first ground GND1 as the reference potential and converts the gate control signal 11, which is a single-ended signal from the control board 1, into a differential signal 21 consisting of a positive signal 21A and a negative signal 21B, the difference in their respective signal levels corresponding to the gate control signal 11.

[0026] The first pulse transformer 3 transmits the differential signal 21 to the input differential voltage generation circuit 6 via the transmission cable 4 and the second pulse transformer 5. As a result, the input and output sides of the gate drive circuit 100 are isolated by the first pulse transformer 3 and the second pulse transformer 5.

[0027] The input differential voltage generation circuit 6 generates a pair of input differential voltages 22A and 22B based on the transmitted differential signal 21. The first differential amplifier circuit 7 differentially amplifies this pair of input differential voltages 22A and 22B to output a pair of high-potential first output differential voltages 23A and 23B. The first gate drive signal generation circuit 9 generates a first gate drive signal 25A based on this pair of first output differential voltages 23A and 23B, with a predetermined positive potential as the reference, and outputs this first gate drive signal 25A to the first switching element 61 (see Figure 1). Meanwhile, the second differential amplifier circuit 8 differentially amplifies this pair of input differential voltages 22A and 22B to output a pair of second output differential voltages 24A and 24B, which are at a lower potential than the pair of first output differential voltages 23A and 23B. The second gate drive signal generation circuit 10 generates a second gate drive signal 25B based on a predetermined negative potential reference, using this pair of second output differential voltages 24A and 24B as a reference, and outputs the second gate drive signal 25B to the second switching element 62 (see Figure 1).

[0028] This first configuration example is applicable when it is desirable to protect the computer constituting the control board (control device) 1 from sources of common-mode noise by keeping it as far away as possible.

[0029] Next, a second configuration example will be described. Figure 2B is a block diagram showing a second configuration example of the gate drive circuit 100 in Figure 1. Referring to Figure 2B, the transmission cable 4 and the second pulse transformer 5 are omitted in the second configuration example. Therefore, in the second configuration example, the input side and output side of the gate drive circuit 100 are isolated by the first pulse transformer 3. In addition, the input differential voltage generation circuit 6 generates a pair of input differential voltages 22A and 22B based on the differential signal 21 output to the secondary winding of the first pulse transformer 3. The other configurations are the same as in the first configuration example, so their explanation will be omitted. Such a second configuration example is applicable when it is not necessary to keep the control board 1 away from the source of common-mode noise.

[0030] Next, a third configuration example will be described. In the third configuration example, the gate drive circuit 100 comprises only one set of differential amplifier circuits and gate drive signal generation circuits (for example, a first differential amplifier circuit 7 and a first gate drive signal generation circuit 9 or a second differential amplifier circuit 8 and a second gate drive signal generation circuit 10). The other configurations are the same as in the first or second configuration example, so their description will be omitted. Such a third configuration example is applied when driving a single switching element (for example, the first switching element 61 or the second switching element 62 in Figure 1).

[0031] Next, the detailed configuration and operation of the gate drive circuit 100 in the first configuration example shown in Figure 2A will be described. Note that the second and third configuration examples are simply the first configuration example with some elements omitted, so their detailed configurations and operations will be omitted.

[0032] {Detailed configuration} Figure 3 is a circuit diagram showing a specific example of the circuit configuration of the first configuration example of the gate drive circuit 100 shown in Figure 2A.

[0033] Referring to Figure 3, the circuit shown in Figure 3 includes the gate drive circuit 100 of Figure 2A and the push-pull connected pair of switching elements 60 of Figure 1, and is configured as a push-pull amplifier circuit 500.

[0034] The signal conversion circuit 2 includes a logic circuit 31, a positive signal generation circuit 32, and a negative signal generation circuit 33.

[0035] The logic circuit 31 uses logic circuits to generate an in-phase signal 12A and an out-of-phase signal 12B from the gate control signal 11 from the control board 1.

[0036] The positive signal generation circuit 32 uses a pair of push-pull connected transistors Q1 and Q2, each of which 5 It is configured to be connected to the positive power supply of V and the first ground GND1. The gates of a pair of transistors Q1 and Q2 are connected to a 5V positive power supply and a first ground GND1, respectively, via resistors R3 and R4.Furthermore, diodes pointing in opposite directions are connected in parallel to the pair of transistors Q1 and Q2. Transistors Q1 and Q2 are composed of, for example, a PMOSFET and an NMOSFET, and the in-phase signal 12A from the logic circuit 31 is input to their gates via a resistor R1. As a result, the positive signal generation circuit 32 outputs a positive signal, which is an amplified in-phase signal 12A, from the connection point between transistors Q1 and Q2.

[0037] The negative signal generation circuit 33 uses a pair of push-pull connected transistors Q3 and Q4, each 5 It is configured to be connected to the positive power supply of V and the first ground GND1. The gates of the pair of transistors Q3 and Q4 are connected to a 5V positive power supply and a first ground GND1, respectively, via resistors R5 and R6. A pair of transistors Q3 and Q4 are connected in parallel with diodes pointing in opposite directions. Transistors Q3 and Q4 are composed of, for example, a PMOSFET and an NMOSFET, and the reverse-phase signal 12B from the logic circuit 31 is input to their gates via a resistor R2. As a result, the negative signal generation circuit 33 outputs a negative signal, which is an amplified reverse-phase signal 12B, from the connection point between transistors Q3 and Q4.

[0038] The first pulse transformer 3 has a primary winding and a secondary winding that are electrically isolated from each other and each has a neutral point MP1 and MP2. The neutral point MP1 of the primary winding is connected to the first ground GND1. The first end EP1 of the primary winding is connected to the connection point between transistors Q1 and Q2 of the positive signal generation circuit 32, and a positive signal 21A is input to the first end EP1. The second end EP2 of the primary winding is connected to the connection point between transistors Q3 and Q4 of the negative signal generation circuit 33, and a negative signal 21B is input to the second end EP2.

[0039] The second pulse transformer 5 has a primary winding and a secondary winding that are electrically isolated from each other and each has a neutral point MP3 and MP4. The first end EP5, the second end EP6, and the neutral point MP3 of the primary winding are connected via the transmission cable 4 to the first end EP3, the second end EP4, and the neutral point MP2 of the secondary winding of the first pulse transformer 3, respectively.

[0040] The input differential voltage generation circuit 6 has a pair of resistors R9 and R10 connected in series. The pair of resistors R9 and R10 have equal and appropriate resistance values. It is preferable that the resistance values ​​of the pair of resistors R9 and R10 are equal from the viewpoint of completely canceling out common-mode noise. However, the resistance values ​​of the pair of resistors R9 and R10 do not have to be equal. Even in this case, common-mode noise can be reduced, albeit imperfectly. The high-potential end, the low-potential end, and the connection point N1 of the pair of resistors R9 and R10 are connected to the first end EP7, the second end EP8, and the neutral point MP4 of the secondary winding of the second pulse transformer 5, respectively. This generates a pair of input differential voltages 22A and 22B across the ends of the pair of resistors R9 and R10, with the potential of the connection point N1 as the reference.

[0041] The first differential amplifier circuit 7 includes a pair of transistors Q5 and Q6 as amplifying elements. Transistor Q5 is connected to the positive power supply VCC via transistor Q7 and resistor R19, and to the negative power supply VEE via a common resistor R21. Transistor Q6 is connected to the positive power supply VCC via transistor Q8 and resistor R20, and to the negative power supply VEE via a common resistor R21. The pair of transistors Q5 and Q6 are, for example, npn bipolar transistors. The base of transistor Q5 is connected to the high-potential end of a pair of resistors R9 and R10 via base resistor R17, and an input differential voltage of 22A (high-potential differential voltage) is input to the base of transistor Q5. The base of transistor Q6 is connected to the low-potential end of a pair of resistors R9 and R10 via base resistor R18, and an input differential voltage of 22B (low-potential differential voltage) is input to the base of transistor Q6.

[0042] Furthermore, the gate drive circuit 100 has a circuit that resistively divides the voltage between the positive power supply VCC and the negative power supply VEE. In this circuit, for example, four resistors R11 to R14 are connected in series between the positive power supply VCC and the negative power supply VEE, with resistors R11 and R14 having equal resistance values, and resistors R12 and R13 having equal resistance values. As a result, the connection point N2 between resistors R12 and R13 has a potential midway between the positive power supply VCC and the negative power supply VEE, and this connection point N2 is connected to the connection point N1 of the input differential voltage generation circuit 6. As a result, the potential of the connection point N1 is fixed by the positive power supply VCC and the negative power supply VEE, but this configuration may be omitted.

[0043] The bases of transistors Q7 and Q8 are connected to the connection point between resistors R11 and R12, and the resistance values ​​of these resistors R11 and R12 are appropriately selected so that transistors Q7 and Q8 have a predetermined high resistance value.

[0044] With the above configuration, the first differential amplifier circuit 7 differentially amplifies the pair of input differential voltages 22A and 22B and outputs a pair of first output differential voltages 23A and 23B to connection point N3 and connection point N4, respectively.

[0045] The second differential amplifier circuit 8 includes a pair of transistors Q9 and Q10 as amplifying elements. One transistor Q9 is connected to the positive power supply VCC via a common resistor R22 and to the negative power supply VEE via transistor Q11 and resistor R23. The other transistor Q10 is connected to the positive power supply VCC via a common resistor R22 and to the negative power supply VEE via transistor Q12 and resistor R24. The pair of transistors Q9 and Q10 are, for example, pnp bipolar transistors. The base of transistor Q9 is connected to the high-potential side terminal of the pair of resistors R9 and R10 via a base resistor R16, and an input differential voltage of 22A (high-potential side differential voltage) is input to the base of transistor Q9. The base of transistor Q10 is connected to the low-potential side terminal of the pair of resistors R9 and R10 via a base resistor R15, and the transistor Q10 An input differential voltage of 22B (low-potential differential voltage) is input to the base of the device.

[0046] The bases of transistors Q11 and Q12 are connected to the connection point between resistors R13 and R14, and the resistance values ​​of these resistors R13 and R14 are appropriately selected so that transistors Q11 and Q12 have a predetermined high resistance value.

[0047] With the above configuration, the second differential amplifier circuit 8 differentially amplifies the pair of input differential voltages 22A and 22B and outputs a pair of second output differential voltages 24A and 24B to connection point N5 and connection point N6, respectively.

[0048] The first gate drive signal generation circuit 9 is composed of a square wave waveform shaping circuit. For example, an RS flip-flop, which is a logic circuit, is used as this waveform shaping circuit. This RS flip-flop operates with a predetermined high potential as a reference. In this RS flip-flop, for example, the set input terminal is connected to connection point N3 via a resistor R25, the reset input terminal is connected to connection point N4 via a resistor R26, and the set output terminal is connected to the gate of the first switching element 61. A pair of first output difference voltages 23A and 23B, which consist of single-ended signals with opposite phases to each other, are input to the set input terminal and the reset input terminal, so a single-ended signal in phase with the first output difference voltage 23A is output to the set output terminal. The first gate drive signal generation circuit 9 outputs this single-ended signal as the first gate drive signal 25A to the first switching element 61.

[0049] The second gate drive signal generation circuit 10 is composed of a square wave waveform shaping circuit. For example, an RS flip-flop, which is a logic circuit, is used as this waveform shaping circuit. This RS flip-flop operates with a predetermined low potential as a reference. In this RS flip-flop, for example, the set input terminal is connected to connection point N5 via a resistor R28, the reset input terminal is connected to connection point N6 via a resistor R27, and the set output terminal is connected to the gate of the second switching element 62. A pair of second output differential voltages 24A and 24B, which consist of single-ended signals with opposite phases to each other, are input to the set input terminal and the reset input terminal, so a single-ended signal in phase with the second output differential voltage 24A is output to the set output terminal. The second gate drive signal generation circuit 10 outputs this single-ended signal as the second gate drive signal 25B to the second switching element 62.

[0050] Note that other square wave shaping circuits may be used as the waveform shaping circuit described above.

[0051] [Operation of gate drive circuit 100] Next, the operation of the gate drive circuit 100 configured as described above will be explained with reference to Figures 3 and 4A to 4C. Figure 4A is a waveform diagram showing the waveform of the differential signal 21 superimposed with common-mode noise. The upper waveform diagram of Figure 4A shows the waveform of the positive signal 21A, and the lower waveform diagram of Figure 4A shows the waveform of the negative signal 21B. Figure 4B is a waveform diagram showing the waveform of the differential signal 21 induced in the first pulse transformer 3 by the differential signal 21 in Figure 4A. Figure 4C is a waveform diagram showing the waveforms of the input differential voltages 22A and 22B generated by the input differential voltage generation circuit 6 from the signals originating from the differential signal 21 induced in the first pulse transformer 3 in Figure 4B.

[0052] Referring to Figure 3, the logic circuit 31 generates an in-phase signal 12A and an out-of-phase signal 12B from the gate control signal 11 from the control board 1. The positive signal generation circuit 32 outputs a positive signal 21A, which is an amplified version of the in-phase signal 12A. The negative signal generation circuit 33 outputs a negative signal 21B, which is an amplified version of the out-of-phase signal 12B. The positive signal 21A and the negative signal 21B are input to the first terminal EP1 and the second terminal EP2 of the primary winding of the first pulse transformer 3, respectively.

[0053] Referring to Figure 4A, the positive signal 21A and the negative signal 21B are both single-ended signals that take binary values ​​of a high level of positive voltage (5V) and a low level of zero voltage (potential of the first ground GND1, 0V), and have opposite phases. At time t0, the positive signal 21A and the negative signal 21B are input to the first end EP1 and the second end EP2 of the primary winding, respectively.

[0054] In the first half-cycle of the positive signal 21A and the negative signal 21B, at time t0, the positive voltage of the positive signal 21A is applied to the first terminal EP1 and the zero voltage of the negative signal 21B is applied to the second terminal EP2 in the primary winding of the first pulse transformer, causing an excitation current to flow from the first terminal EP1 toward the neutral point MP1. Referring to Figure 4B, this induces a voltage in the primary winding of the first pulse transformer 3 from the second terminal EP2 toward the first terminal EP1. In this case, since the potential of the neutral point MP1 of the primary winding is 0V, the voltage V1 at the first terminal EP1 is a positive voltage. On the other hand, at time t0, the second terminal EP2 is connected to the first ground GND1 via the resistor R8, so the voltage V2 at the second terminal EP2 is a negative voltage, and current flows from the neutral point MP1 toward the second terminal EP2. Furthermore, at this time, the excitation current induces a voltage in the secondary winding of the first pulse transformer 3 and the primary and secondary windings of the second pulse transformer 5, corresponding to the turns ratio of the first pulse transformer 3 and the second pulse transformer 5.

[0055] In the next half-cycle of the positive signal 21A and the negative signal 21B, at time t1, conversely to the above, the zero voltage of the positive signal 21A is applied to the first terminal EP1 and the positive voltage of the negative signal 21B is applied to the second terminal EP2 in the primary winding of the first pulse transformer 3, so that an excitation current flows from the second terminal EP2 toward the neutral point MP1. This induces a voltage in the primary winding of the first pulse transformer 3 from the first terminal EP1 toward the second terminal EP2. In this case, since the potential of the neutral point MP1 of the primary winding is 0V, the voltage V2 at the second terminal EP2 is a positive voltage. On the other hand, at this time t1, the first terminal EP1 is connected to the first ground GND1 via the resistor R7, so the voltage V1 at the first terminal EP1 is a negative voltage, and current flows from the neutral point MP1 toward the first terminal EP1. Furthermore, at this time, the excitation current induces a voltage in the secondary winding of the first pulse transformer 3 and the primary and secondary windings of the second pulse transformer 5, corresponding to the turns ratio of the first pulse transformer 3 and the second pulse transformer 5. Thereafter (t2, t3, ...), the above cycle is repeated.

[0056] In this way, the positive signal 21A and the negative signal 21B are converted in the first pulse transformer 3 into a pair of single-ended voltage signals, each having voltages V1 and V2 with twice the amplitude and opposite phases (opposite positive and negative), and transmitted via the transmission cable 4 to the secondary winding of the second pulse transformer 5.

[0057] Here, we will explain the common-mode noise rejection function on the input side of the gate drive circuit 100. Referring to Figure 4A, let us assume, for example, that common-mode noise is superimposed on the positive signal 21A and the negative signal 21B between time t0 and time t1. Referring to Figure 3, the common-mode noise superimposed on the positive signal 21A causes an excitation current to flow between the first end EP1 of the primary winding of the first pulse transformer 3 and the neutral point MP1, and the common-mode noise superimposed on the negative signal 21B causes an excitation current to flow between the second end EP2 of the primary winding of the first pulse transformer 3 and the neutral point MP1. However, as shown in Figure 4B, since the two excitation currents are in opposite directions, voltages with opposite positive and negative charges are induced in the primary windings, and they cancel each other out. In this way, common-mode noise superimposed on the positive signal 21A and the negative signal 21B is removed from the pair of single-ended voltage signals converted from the positive signal 21A and the negative signal 21B by the first pulse transformer 3. Furthermore, common-mode noise superimposed on the transmission cable 4 is also removed from the pair of single-ended voltage signals by the second pulse transformer 5 through the same process as described above.

[0058] Referring to Figure 3, in the input differential voltage generation circuit 6, input differential voltages 22A and 22B are generated from a pair of single-ended voltage signals transmitted to the secondary winding of the second pulse transformer 5 as follows. Referring to Figure 4C, a single-ended voltage signal corresponding to voltage V1 in Figure 4B appears at the high-potential end of resistor element R9. When this single-ended voltage signal is referenced to connection point N2, the voltage midway through its amplitude becomes a low-level zero voltage, resulting in a single-ended voltage signal with a waveform as shown in the upper part of Figure 4C. On the other hand, a single-ended voltage signal corresponding to voltage V2 in Figure 4B appears at the low-potential end of resistor element R10. When this single-ended voltage signal is referenced to connection point N2, the voltage midway through its amplitude becomes a low-level zero voltage, resulting in a single-ended voltage signal with a waveform as shown in the lower part of Figure 4C. Therefore, the pair of input differential voltages 22A and 22B have waveforms corresponding to the positive signal 21A and the negative signal 21B in Figure 4A, respectively.

[0059] Furthermore, in the input differential voltage generation circuit 6, the pair of resistors R9 and R10 carry the load current of the second pulse transformer 5, so a corresponding load current also flows through the first pulse transformer 3. Figure 3 shows the current in the transmission path of the differential signal 21 when the positive signal 21A is at a high level. As a result, the impedance of the first pulse transformer 3 and the second pulse transformer 5 is lowered, allowing a large current to flow through the transmission path of the differential signal 21, including the first pulse transformer 3, the transmission cable 4, and the second pulse transformer 5, thereby improving the common-mode noise rejection capability on the input side of the gate drive circuit 100.

[0060] Referring to Figure 3, when common-mode noise is superimposed on a pair of wires from the secondary winding of the second pulse transformer 5 to the first and second differential amplifier circuits 7 and 8, the common-mode noise in this pair of wires will have opposite positive and negative signs in the pair of input differential voltages 22A and 22B generated by the input differential voltage generation circuit 6. The first and second differential amplifier circuits 7 and 8 differentially amplify this pair of input differential voltages 22A and 22B, thereby removing the superimposed common-mode noise.

[0061] Furthermore, due to the wiring configuration from the secondary winding of the second pulse transformer 5 to the first and second differential amplifier circuits 7 and 8, the timing of the input of a pair of input differential voltages 22A and 22B to the first and second differential amplifier circuits 7 and 8 may be slightly out of sync. When the first and second differential amplifier circuits 7 and 8 operate at high speed, this slight timing difference may prevent the common-mode noise from being completely removed. However, since the first and second gate drive signal generation circuits 9 and 10 are composed of waveform shaping circuits, the waveforms of the pair of first output differential voltages 23A and 23B and the pair of second output differential voltages 24A and 24B output from the first and second differential amplifier circuits 7 and 8 are shaped, thereby removing any remaining common-mode noise components from the pair of first output differential voltages 23A and 23B and the pair of second output differential voltages 24A and 24B. In particular, if the waveform shaping circuit is a flip-flop, the noise that has been converted to normal mode in the preceding circuit is suitably removed. In this way, common-mode noise is removed from the output side of the gate drive circuit 100.

[0062] [Mounting onto the circuit board] Referring to Figure 3, in the push-pull amplifier circuit 500, the signal conversion circuit 2 and the first pulse transformer 3 are mounted on the first board 81, while the second pulse transformer 5, input differential voltage generation circuit 6, first differential amplifier circuit 7, second differential amplifier circuit 8, first gate drive signal generation circuit 9, second gate drive signal generation circuit 10, and a pair of switching elements 60 are mounted on the second board 82. The secondary winding of the first pulse transformer 3 on the first board 81 and the primary winding of the second pulse transformer 5 on the second board 82 are connected by a transmission cable 4.

[0063] Therefore, by placing the second substrate 82 near, for example, a switching module 800 (see Figure 5) driven by a pair of switching elements 60, and extending the transmission cable 4 to place the first substrate 81 away from the switching module 800 and near the control substrate 1, the computer constituting the control substrate 1 can be suitably protected from common-mode noise generated by the switching operation of the switching module 800.

[0064] [Application to switching power supplies] Figure 5 is a circuit diagram showing the operation of a switching power supply unit 1000 using the push-pull amplifier circuit 500 of Figure 3. In Figure 3, the reference numerals of detailed elements have been omitted for clarity.

[0065] Referring to Figure 5, the switching power supply unit 1000 includes a switching module 800 and first and second push-pull amplifier circuits 500A and 500B. The switching module 800 includes a high-side switching element SWH and a low-side switching element SWL. The high-side switching element SWH and the low-side switching element SWL are made of, for example, IGBTs. In addition, a reverse diode is connected in parallel to the high-side switching element SWH and the low-side switching element SWL, respectively.

[0066] The first push-pull amplifier circuit 500A includes a first gate drive circuit 100A and a first pair of switching elements 60A. The second push-pull amplifier circuit 500B includes a second gate drive circuit 100B and a second pair of switching elements 60B.

[0067] The high-side switching element SWH is connected to the first pair of switching elements 60A of the first push-pull amplifier circuit 500A, and the output of the first pair of switching elements 60A is input to its gate. The low-side switching element SWL is connected to the second pair of switching elements 60B of the second push-pull amplifier circuit 500B, and the output of the second pair of switching elements 60B is input to its gate. In addition, the control board 1 and the signal conversion circuits 2 of the first and second gate drive circuits 100A and 100B are grounded. Furthermore, the first pair of switching elements 60A is connected to frame ground, and the second pair of switching elements 60B is connected to signal ground.

[0068] In the switching power supply 1000 configured in this way, a high-side gate control signal 11A is input from the control board 1 to the logic circuit 31 of the first gate drive circuit 100A. As a result, the first gate drive circuit 100A generates first and second gate drive signals, and a high-side gate drive signal 26A is output from the first pair of switching elements 60A to the gate of the high-side switching element SWH. Meanwhile, a low-side gate control signal 11B is input from the control board 1 to the logic circuit 31 of the second gate drive circuit 100B. As a result, the second gate drive circuit 100B generates first and second gate drive signals, and a low-side gate drive signal 26B is output from the second pair of switching elements 60B to the gate of the low-side switching element SWL. Here, as shown in Figure 5, the high-side gate control signal 11A and the low-side gate control signal 11B are out of phase with each other.

[0069] As a result, the high-side switching element SWH and the low-side switching element SWL operate on and off at different timings, and the control power of the switching module 800 is output from the connection point Nout between the high-side switching element SWH and the low-side switching element SWL.

[0070] Incidentally, the voltage (potential) Vm at the connection point Nout fluctuates when the high-side switching element SWH and the low-side switching element SWL are switched on and off, respectively. This fluctuation in the voltage Vm at the connection point Nout generates switching noise as shown in Figure 6. Figure 6 is a schematic diagram showing the switching noise generated by the switching module 800 in Figure 5. In Figure 6, Vm1 shows the voltage fluctuation at the connection point Nout when the low-side switching element SWL is turned on while the high-side switching element SWH is off, and Vm2 shows the voltage fluctuation at the connection point Nout when the low-side switching element SWL is turned off while the high-side switching element SWH is on. Voltage fluctuations Vm1 and Vm2 occur at different timings, but for convenience, they are shown as occurring at the same timing in Figure 6. Note that Figure 6 was created by tracing the waveform image of the voltage actually obtained, so the waveform is not accurate.

[0071] When the voltage Vm(Vm1,Vm2) at connection point Nout fluctuates as shown in Figure 6, switching noise is radiated from connection point Nout. This switching noise then superimposes as common-mode noise onto the wiring of the first and second gate drive circuits 100A and 100B. However, as described above, the common-mode noise superimposed on the wiring of the first and second gate drive circuits 100A and 100B is removed.

[0072] As described above, the gate drive circuit 100 of this disclosure can eliminate common-mode noise superimposed on the output and input sides. Furthermore, the computer constituting the control board 1 can be suitably protected from common-mode noise generated by the switching operation of the switching module 800.

[0073] From the above description, many improvements and other embodiments will be apparent to those skilled in the art. Therefore, the above description should be interpreted as illustrative only. [Industrial applicability]

[0074] The gate drive circuit of the present invention is useful as a gate drive circuit capable of removing common-mode noise superimposed on the output and input sides. [Explanation of Symbols]

[0075] 1. Control board 2. Signal conversion circuit 3. First pulse transformer 4. Transmission Cable 5. Second pulse transformer 6. Input Differential Voltage Generation Circuit 7. First differential amplifier circuit 8. Second differential amplifier circuit 9. First gate drive signal generation circuit 10. Second gate drive signal generation circuit 11 Gate control signals 12A in-phase signal 12B Anti-phase signal 21 Differential signals 21A Positive signal 21B Negative signal 22A, 22B Input Differential Voltage 23A, 23B First output differential voltage 24A, 24B Second output differential voltage 25A First gate drive signal 25B Second gate drive signal 26A High-side gate drive signal 26B Low-side gate drive signal 31 Logic Circuits 32 Positive signal generation circuit 33 Negative signal generation circuit 60 pairs of switching elements 61 First switching element 62 Second switching is possible. 81 First board 82 Second board 100 Gate Drive Circuit 500 Push-Pull Amplifier Circuit 800 Switching Modules 1000 Switching Power Supply GND1 First Ground GND2 (2nd Ground)

Claims

1. A signal conversion circuit that operates with the potential of the first ground as the reference potential and converts a gate control signal, which is a single-ended signal, into a differential signal consisting of a positive signal and a negative signal whose signal level difference corresponds to the gate control signal, A first pulse transformer having a primary winding and a secondary winding that are electrically insulated from each other and each having a neutral point, wherein the neutral point of the primary winding is at the potential of the first ground and the positive and negative signals of the differential signal are input to both ends of the primary winding, respectively. An input differential voltage generation circuit having a pair of resistive elements connected in series with respect to each other, wherein both ends and connection points of the pair of resistive elements are connected directly or electrically, or via a transmission cable and a second pulse transformer, to both ends and the neutral point of the secondary winding and the neutral point of the first pulse transformer, respectively, and generates a pair of input differential voltages at both ends of the pair of resistive elements with respect to the potential of the connection points, A differential amplifier circuit is electrically connected to the input differential voltage generation circuit and differentially amplifies the pair of input differential voltages to output a pair of output differential voltages, A gate drive circuit comprising: a gate drive signal generation circuit electrically connected to the differential amplifier circuit, which generates a gate drive signal, which is a single-ended signal with a predetermined potential reference, based on the pair of output differential voltages, and outputs the gate drive signal to a switching element that operates with the potential of a second ground as the reference.

2. The second pulse transformer has a primary winding and a secondary winding that are electrically insulated from each other and each has a neutral point, and both ends and the neutral point of the primary winding are electrically connected to both ends and the neutral point of the secondary winding of the first pulse transformer via the transmission cable, The gate drive circuit according to claim 1, wherein the input differential voltage generation circuit is connected to both ends of the pair of resistive elements and the connection point, respectively, to both ends of the secondary winding of the second pulse transformer and the neutral point.

3. The two switching elements constitute a first switching element and a second switching element that are connected to each other in a push-pull configuration. The differential amplifier circuit comprises a first differential amplifier circuit and a second differential amplifier circuit. The gate drive signal generation circuit comprises a first gate drive signal generation circuit and a second gate drive signal generation circuit. The first differential amplifier circuit is electrically connected to the input differential voltage generation circuit and is a circuit that differentially amplifies the pair of input differential voltages to output a pair of high-potential first output differential voltages. The second differential amplifier circuit is electrically connected to the input differential voltage generation circuit and differentially amplifies the pair of input differential voltages to output a pair of second output differential voltages that are at a lower potential than the pair of first output differential voltages. The first gate drive signal generation circuit is electrically connected to the first differential amplifier circuit and generates a first gate drive signal, which is a gate drive signal referenced to a positive potential, based on the pair of first output differential voltages, and outputs the first gate drive signal to the first switching element. The gate drive circuit according to claim 1 or 2, wherein the second gate drive signal generation circuit is electrically connected to the second differential amplifier circuit and generates a second gate drive signal, which is the gate drive signal referenced to a negative potential, based on the pair of second output differential voltages, and outputs the second gate drive signal to the second switching element.

4. The gate drive circuit according to claim 1 or 2, wherein the gate drive signal generation circuit includes a flip-flop that receives the pair of output differential voltages and outputs a single-ended signal referenced to a predetermined potential, and outputs the single-ended signal as the gate drive signal.

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