Indication device

Abstract

To suppress variations in characteristics of a TFT for connecting selection of a display device and a power line.SOLUTION: In a display device, multiple shift register units successively output selection pulses to multiple selection lines. Respective shift register units of the multiple shift register units output selection pulses to corresponding selection lines of the multiple selection lines. The respective shift register units include multiple parallel-connected first-conductivity-type thin-film transistors for making continuity between the corresponding selection lines and constant potential lines for giving a non-selection level of a selection pulse in an ON state. The multiple thin-film transistors are turned on or off by clock signals of different phases within one frame period. A duty ratio of an ON period of each of multiple thin-film transistors during one frame period is equal to or less than 12.5%.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to a display device. [Background Art]

[0002] As display devices, liquid crystal display devices (LCDs) and OLED (Organic Light-Emitting Diode) display devices are widely used. These display devices include a shift register for driving (selecting) scanning lines for selecting pixel rows to which data signals are written.

[0003] Further, an OLED display device is known which measures the characteristics of elements (driving transistors and OLEDs) of the display device and corrects a data signal based on the measurement result. An OLED display device that performs such external compensation of data signals includes a shift register that outputs a measurement control signal to a measurement control line.

[0004] With the expanding application of display devices, there is an increasing demand for non-rectangular display devices from the viewpoint of design. In order to realize a non-rectangular display device, it is necessary to form a drive circuit including the above-described shift register on an insulating substrate by a thin film process. In addition, since display devices can be used in various environments, requirements for reliability are also increasing. [Prior Art Literature] [Patent Literature]

[0005] [Patent Literature 1] US Patent Application No. 2018 / 0308444 [Patent Literature 2] US Patent Application No. 2012 / 0113088 [Summary of the Invention] [Problem to be Solved by the Invention]

[0006] The drive circuit of the display device sequentially selects selection lines, such as scan lines and light emission control lines. The drive circuit connects the selection lines to wiring that provides either a low or high potential during the selection period, and to wiring that provides either a low or high potential during the non-selection period. The drive circuit makes the selection lines and the potential supply wiring conduct electricity by switching thin film transistors (TFTs) that conduct electricity between the selection lines and the wiring that provides the low or high potential on and off.

[0007] If a TFT is left ON for a long period of time, bias stress can cause characteristic fluctuations and reduce its driving capability. If the driving capability of a TFT that applies low or high potential to a selected line decreases, the display quality of the display device may deteriorate. [Means for solving the problem]

[0008] A display device according to one aspect of the present disclosure includes a plurality of pixel circuit rows, a plurality of selection lines connected to the plurality of circuit rows, and a shift register including a plurality of linked shift register units. The plurality of shift register units sequentially output selection pulses to the plurality of selection lines. Each shift register unit of the plurality of shift register units outputs the selection pulse to the corresponding selection line of the plurality of selection lines. Each shift register unit includes a plurality of thin-film transistors of a first conductivity type connected in parallel, which conduct the corresponding selection line and a constant potential wiring that provides a non-selection level for the selection pulse when in the ON state. Within one frame period, the plurality of thin-film transistors are turned ON / OFF by clock signals of different phases. The duty cycle of the ON period of each of the plurality of thin-film transistors within one frame period is 12.5% ​​or less. [Effects of the Invention]

[0009] According to one aspect of this disclosure, it is possible to suppress characteristic variations of the TFT connecting the display device and the power line. [Brief explanation of the drawing]

[0010] [Figure 1]A schematic example of the configuration of a liquid crystal display device is shown. [Figure 2] A schematic diagram of the cross-sectional structure of a liquid crystal display device is shown. [Figure 3A] An example of a pixel circuit in a liquid crystal display device is shown. [Figure 3B] An example of a pixel circuit in a liquid crystal display device is shown. [Figure 4] This diagram schematically shows the circuit configuration of a single-stage shift register (also called a flip-flop or shift register unit). [Figure 5] This is a sequence diagram showing the time evolution of the input signal, the potential of a specific node, and the output signal for each shift register. [Figure 6A] This shows some of the shift registers that can be implemented in the scan driver. [Figure 6B] This shows some other shift registers that can be implemented in the scan driver. [Figure 7A] Figures 6A and 6B show the signal sequence diagrams for a shift register with the configuration shown. [Figure 7B] Figures 6A and 6B show other signal sequence diagrams for a shift register with the configuration shown. [Figure 8] The relationship between the number of clock signals and the duty cycle is schematically shown. [Figure 9] This shows the measurement results of the relationship between the duty cycle of the gate signal and characteristic variation in an amorphous silicon N-type TFT. [Figure 10] Embodiment 2 shows an example of a configuration where the output signal is output to a single scan line, with each shift register on both sides. [Figure 11A] Embodiment 2 shows a portion of the shift registers that can be implemented in the scanning driver. [Figure 11B] Embodiment 2 shows other parts of the shift registers that can be implemented in the scanning driver. [Figure 12A] Embodiment 2 shows a portion of the shift registers that can be implemented in the scanning driver. [Figure 12B] Embodiment 2 shows other parts of the shift registers that can be implemented in the scanning driver. [Figure 13] A configuration example of a shift register unit according to Embodiment 3 is shown. [Figure 14A] In Embodiment 3, a part of a shift register that can be mounted on a scan driver is shown. [Figure 14B] In Embodiment 3, another part of a shift register that can be mounted on a scan driver is shown. DETAILED DESCRIPTION OF EMBODIMENTS

[0011] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the present embodiment is merely an example for realizing the present invention and does not limit the technical scope of the present invention.

[0012] <Overview> Hereinafter, a circuit configuration applicable to a scanning circuit of a liquid crystal display device (LCD), an OLED (Organic Light-Emitting Diode) display device, or the like will be described. A scanning circuit according to an embodiment of the present specification includes a shift register capable of outputting scanning signals for LCDs and OLED display devices, light emission control signals for OLED display devices, and the like. The shift register includes a plurality of connected shift register units.

[0013] The shift register sequentially selects selection lines such as scanning lines and light emission control lines. The shift register is connected to a wiring that supplies one of a low potential and a high potential during a selection period, and connected to a wiring that supplies the other of the low potential and the high potential during a non-selection period. The drive circuit turns on / off a TFT that electrically connects the selection line and the wiring that supplies the low potential or the high potential, thereby bringing the selection line and the potential supply wiring into conduction.

[0014] If a TFT is kept in an on state for a long period of time, characteristic variation occurs due to bias stress, which may reduce driving capability. When the driving capability of a TFT that supplies a low potential or a high potential to a selection line decreases, the display quality of the display device may decrease.

[0015] A scanning circuit of a display device according to one embodiment of this specification includes a shift register that sequentially outputs selection pulses to selection lines. Each shift register unit of the shift register includes a plurality of thin-film transistors of a first conductivity type connected in parallel, which output selection pulses to the corresponding selection line and, when ON, conduct the corresponding selection line and a wiring that provides a non-selection level for the selection pulse. Within one frame period, the plurality of thin-film transistors are turned ON / OFF by clock signals of different phases. This makes it possible to reduce the duty cycle of the ON period of the thin-film transistors.

[0016] The embodiments will be described in detail below with reference to the drawings. Common components in each drawing are denoted by the same reference numerals. For the sake of clarity, the dimensions and shapes of the illustrated objects may be exaggerated in some cases.

[0017] <Embodiment 1> [Overall structure] Figure 1 schematically shows an example configuration of a liquid crystal display device 10. The features of this disclosure can be applied to other display devices, such as OLED display devices. The liquid crystal display device 10 includes a liquid crystal display panel and a control device. The liquid crystal display panel includes a TFT (Thin Film Transistor) substrate 100 on which electrodes for applying an electric field to the liquid crystal are formed, a counter substrate 200, and a seal portion 150 that joins the TFT substrate 100 and the counter substrate 200. Liquid crystal material is sealed between the TFT substrate 100 and the counter substrate 200.

[0018] The scanning drivers 131, 132 and driver IC 134 are located outside the display area 125 of the TFT substrate 100. Driver IC 134 is connected to an external device via an FPC (Flexible Printed Circuit) 135. The scanning drivers 131, 132 and driver IC 134 are included in the control unit. These are also called the drive circuit.

[0019] The scanning drivers 131 and 132 are arranged opposite each other, with the display area 125 in between. In the example in Figure 1, the scanning drivers 131 and 132 are located on the left and right sides of the display area 125, respectively. The scanning drivers 131 and 132 drive different scan lines of the TFT substrate 100 or drive each scan line simultaneously. One of these may be omitted.

[0020] The driver IC 134 is mounted, for example, using an anisotropic conductive film (ACF). The driver IC 134 supplies power and timing signals (control signals) to the scanning drivers 131 and 132, and also supplies signals corresponding to the video data to the data lines.

[0021] Figure 2 schematically shows the cross-sectional structure of the liquid crystal display device 10. Figure 2 shows a partial configuration of the liquid crystal display device 10, with some components, including the backlight unit, omitted. The liquid crystal display panel includes a TFT 100 and a counter substrate 200 facing the TFT substrate 100. A liquid crystal layer 111 is sandwiched between the TFT substrate 100 and the counter substrate 200. The liquid crystal display device 10 further includes a backlight unit (not shown).

[0022] The TFT substrate 100 includes an insulating substrate 102. The insulating substrate 102 is an insulating transparent substrate made of glass or resin. The insulating substrate 102 is, for example, rectangular, and one of its main surfaces faces one of the main surfaces of the opposing substrate 200. A deflection plate 101 is mounted on the main surface of the insulating substrate 102 opposite to the liquid crystal layer 111.

[0023] On the main surface of the insulating substrate 102 relative to the liquid crystal layer 111, driving electrodes (also called pixel electrodes) 103 and common electrodes (also called counter electrodes) 104 are arranged to apply an electric field to the liquid crystal layer 111. Each pair of driving electrodes 103 and common electrodes 104 applies an electric field to the liquid crystal of one pixel. The amount of light transmitted through the pixel changes depending on the applied electric field. A TFT array (not shown) for selecting the pixel to be controlled is formed on the insulating substrate 102.

[0024] The configuration example shown in Figure 2 is a transverse field controlled liquid crystal display device. A transverse field controlled liquid crystal display device is, for example, an IPS (In-Plane Switching) type or an FFS (Fringe-Field Switching) type liquid crystal display device. In Figure 2, only the driving electrode and common electrode of one of the multiple pixels are indicated by reference numerals 103 and 104, respectively.

[0025] An alignment film 105 is laminated so as to cover the electrode layer, which includes the driving electrode 103 and the common electrode 104. The alignment film 105 is in contact with the liquid crystal layer 111 and defines the arrangement state (initial orientation) of liquid crystal molecules in the absence of an electric field.

[0026] In the configuration example shown in Figure 2, the opposing substrate 200 is a CF substrate including a color filter (CF). The opposing substrate 200 does not necessarily have to include a color filter. The opposing substrate 200 includes an insulating substrate 141 made of glass or resin. The insulating substrate 141 is, for example, rectangular. A deflection plate 142 is mounted on the main surface of the insulating substrate 141 opposite to the liquid crystal layer 111.

[0027] A grid-like black matrix 124 defining pixels is stacked on the main surface of the insulating substrate 141 on the side of the liquid crystal layer 111. The black matrix 124 is, for example, a black resin or a thin metal film using a chromium-based material. A color filter 123 of red, green, or blue is formed in the region of each pixel surrounded by the black matrix 124.

[0028] An insulating overcoat layer 122 is laminated on the color filter 123. The overcoat layer 122 may be omitted. An alignment film 121 is laminated on the overcoat layer 122. The alignment film 121 is in contact with the liquid crystal layer 111 and defines the arrangement state (initial orientation) of the liquid crystal molecules in the absence of an electric field.

[0029] A backlight unit (not shown) is located on the back (rear) side of the liquid crystal display panel. One of the TFT substrate 100 or the opposing substrate 200 is the front side where the user viewing the image is located, and the other is the rear side. In other words, the backlight unit is located on either the TFT substrate 100 side or the opposing substrate 200 side of the liquid crystal display panel shown in Figure 2.

[0030] The liquid crystal layer 111 controls the amount of light transmitted from the backlight unit to each pixel according to the electric field between the drive electrode 103 and the common electrode 104. The driver IC 134 controls the potential of the drive electrode 103 and the common electrode 104 of each pixel. The driver IC 134 controls the amount of light transmitted to each pixel by controlling the potential of the drive electrode 103 and the common electrode 104 of each pixel according to the image data.

[0031] [Pixel circuit configuration] Next, an example of a pixel circuit for a liquid crystal display device will be described. Figures 3A and 3B show examples of pixel circuits for liquid crystal display devices, respectively. The pixel circuit example in Figure 3A includes an N-type switch TFT 202, a retaining capacitance CST, and liquid crystal LC between the common electrode and the pixel electrode. A common potential Vcom is provided to the common electrode. The N-type switch TFT 202 may be, for example, an amorphous silicon TFT, an oxide semiconductor TFT, or a low-temperature polysilicon TFT.

[0032] The scanning drivers 131 and / or 132 output a selection pulse to the scanning line 206, turning on the N-type switch thin-film transistor 202. The selection level (pulse level) of the selection pulse is high, and the non-selection level (reference level) is low.

[0033] The scan line 206 is connected to either one or both of the scan drivers 131 and 132. The data line 205 supplies data signals to the pixel electrodes and holding capacitance CST via the ON-state N-type switch TFT 202. The data signals are supplied from the driver IC 134 to the data line 205.

[0034] The pixel circuit example in Figure 3B includes a P-type switch TFT 212, a retaining capacitor CST, and a liquid crystal LC between the common electrode and the pixel electrode. A common potential Vcom is provided to the common electrode. The P-type switch TFT 212 may be, for example, a low-temperature polysilicon TFT.

[0035] The scanning drivers 131 and / or 132 output a selection pulse to the scanning line 206, turning on the P-type switch TFT 212. The selection level (pulse level) of the selection pulse is low, and the non-selection level (reference level) is high.

[0036] The scan line 206 is connected to either one or both of the scan drivers 131 and 132. The data line 205 supplies data signals to the pixel electrodes and holding capacitance CST via the ON-state P-type switch TFT 212. The data signals are supplied from the driver IC 134 to the data line 205.

[0037] [Scanning driver circuit] The following describes an example of a circuit configuration for a scanning driver that controls a pixel circuit including an N-type switch TFT, as shown in Figure 3A. The scan lines extend in the X-axis direction and are arranged in the Y-axis direction, as shown in Figure 1. The scanning driver sequentially outputs gate signals (selection signals) to the scan lines arranged in the Y-axis direction.

[0038] Figure 4 schematically shows the circuit configuration of a single-stage shift register (also called a flip-flop or shift register unit) 310. Scan drivers 131 and 132 each include a shift register containing multiple shift register units 310 linked in multiple stages. Each shift register unit of scan drivers 131 and 132 can have the configuration shown in Figure 4.

[0039] The output signal OUT of the shift register unit 310 shown in Figure 4 is the gate signal of the N-type TFT 202 of the pixel circuit shown in Figure 3A. The shift register unit supplies a high-potential output signal pulse to the gate of the N-type TFT 202. This turns the N-type TFT 202 ON. In the circuit described below, the N-type TFT 202 of the pixel circuit and the N-type TFT of the shift register unit may be amorphous silicon TFTs. Also, the transistor in the shift register unit is an ON / OFF switch TFT.

[0040] The signals input to the shift register unit 310 include signals IN1, IN2, DIR1, DIR2, and CLK1 to CLK8. Signals DIR1 and DIR2 are control signals for selecting the scan direction (shift direction) of the shift register. CLK1 to CLK8 are clock signals. Signal IN1 is the input signal from one of the preceding shift register units, and signal IN2 is the input signal from the other preceding shift register unit. Depending on the scan direction of the shift register, only one input signal generates a pulse, while the other input signal is maintained at VGL. The first input signal to the shift register unit in the shift register is the start signal.

[0041] Furthermore, a constant low power supply potential VGL is supplied to the shift register unit 310. The signals IN1, IN2, DIR1, DIR2, and CLK1~CLK8 input to the shift register unit change between a constant high power supply potential VGH (high level) and a low power supply potential VGL (low level).

[0042] The shift register unit 310 provides an output signal OUT from the output line OT to the scan line 206. The shift register unit 310 includes 13 transistors T0 to T12, as well as two capacitors C1 and C2.

[0043] One source / drain of transistor T0 is supplied with control signal DIR1, which controls the scan direction of the shift register, and the other is connected to node N1. The gate of transistor T0 is supplied with input signal IN1. One source / drain of transistor T1 is supplied with control signal DIR2, which controls the scan direction of the shift register, and the other is connected to node N1. The gate of transistor T1 is supplied with input signal IN2.

[0044] One source / drain of transistor T2 is supplied with a low power supply potential VGL, and the other is connected to node N1. The gate of transistor T2 is connected to node N2. The gate of transistor T2 is supplied with the clock signal CLK1 via capacitor C2 or the low power supply potential VGL via transistor T3. Transistor T2 is a pull-down TFT that lowers the potential at node N1 to the low power supply potential VGL. Transistor T2 is an example of a third thin-film transistor.

[0045] One of the source / drain terminals of transistor T3 is supplied with a low power supply potential VGL, and the other terminal is connected to node N2. The gate of transistor T3 is connected to node N1. The gate of transistor T3 is supplied with a control signal DIR1 or DIR2 via transistor T0 or T1, or with the low power supply potential VGL via transistor T2.

[0046] One source / drain of transistor T4 is supplied with the clock signal CLK1, and the other is connected to the output line OT. The gate of transistor T4 is connected to node N1. The gate potential of transistor T4 is the same as the gate potential of transistor T3. Transistor T4 is an example of a second thin-film transistor that provides a select level (high level) for the select pulse when it is ON.

[0047] Transistors T5-T12 are pull-down N-type TFTs that reduce the potential of the output line OT to the low power supply potential VGL. Transistors T5-T12 are connected in parallel between the output line OT and the power supply line that provides the low power supply potential VGL. Specifically, one source / drain of transistors T5-T12 is connected to the output line OT, and the other is connected to the wiring that provides the low power supply potential VGL.

[0048] The gate of transistor T5 is connected to node N2. The potential of the gate of transistor T5 is the same as the potential of the gate of transistor T2. Clock signals CLK2 to CLK8 are applied to the gates of transistors T6 to T12, respectively. As will be described later, transistors T6 to T12 and T5 are sequentially turned ON to provide a low power supply potential VGL to the output line OT. In the configuration example in Figure 4, all transistors pulling down the output line are controlled by clock signals of different phases. Transistors T5 to T12, for example, have the same channel width and the same pull-down capability. Transistors T5 to T12 may have the same structure.

[0049] One end of capacitor C1 is connected to node N1, and the other end is connected to the output line OT. One end of capacitor C2 is connected to node N2, and the other end is supplied with the clock signal CLK1. Capacitor C1 is a bootstrap capacitor that provides a bootstrap effect to the potential of node N1. Capacitor C2 enables the appropriate supply of the clock signal CLK1 and the low power supply potential VGL to node N2.

[0050] Figure 5 is a sequence diagram showing the time evolution of the input signal, the potential at node N1, the potential at node N2, and the output signal OUT of the shift register unit 310. Time TM1 is the start time of control of the shift register unit 310 corresponding to one frame of video data (video frame).

[0051] In the example in Figure 5, control signal DIR1 is always high level (VGH), and control signal DIR2 is always low level (VGL). This means that the scan direction of the shift register is maintained in the direction indicated by control signal DIR1.

[0052] At time TM1, input signal IN1 changes from VGL to VGH. Other signals are VGL. Because input signal IN1 is VGH, transistor T0 turns ON. Control signal DIR1 is applied to node N1. Control signal DIR1 is VGH, and the potential of node N1 rises from VGL to V1. The potential V1 of node N1 is effectively VGH, or more precisely, (VGH-Vt) when the threshold of transistor T0 is Vt.

[0053] As the potential of node N1 rises, transistor T3 turns ON. Node N2 and the low power supply line become conductive through transistor T3. The potential of node N2 is VGL. Also, as the potential of node N1 rises, transistor T4 turns ON. The clock signal CLK1 is VGL, and the output signal OUT is also VGL.

[0054] Next, at time TM2, the input signal IN1 becomes VGL, and transistor T0 turns off. Furthermore, the clock signal CLK1 changes from VGL to VGH. Transistor T4 is in the ON state, and the potential of the output signal OUT rises to a high level. The potential of the output signal OUT is effectively VGH, or more precisely, (VGH-Vt) when the threshold of transistor T0 is Vt.

[0055] At this point, node N1 is floating. Therefore, due to the bootstrap effect, the potential of node N1 rises from V1 to V2 via capacitor C1. Potential V2 is (2VGH - VGL - Vt), which is the maximum potential of node N1. Due to the rise in potential of node N1, transistor T4 is kept in the ON state.

[0056] Next, at time TM3, the clock signal CLK1 changes to VGL. As a result, the potential of node N1 becomes VGL, and transistors T3 and T4 turn OFF. Node N2 is in a floating state, and its potential remains VGL. Therefore, transistor T5 is in the OFF state.

[0057] Furthermore, the clock signal CLK2 changes to VGH. This turns on transistor T6. The output line OT and the low power line conduct through transistor T6, and the output signal OUT changes to a low level (VGL). The input signal IN2 changes to VGH according to the output of the next stage shift register, but the signal DIR2 is VGL, and there is no change in the potential of node N1.

[0058] From time TM3 to TM4, the clock signals CLK2 to CLK8 sequentially generate high-level pulses (ON pulses) in this order. This causes transistors T6 to T12 to sequentially turn ON. In the example shown in Figure 5, the falling and rising edges of consecutive ON pulses are simultaneous. There may be an elapsed time between the falling edge of the previous ON pulse and the rising edge of the next ON pulse. Also, there may be some overlap in consecutive ON pulses, that is, the falling edge of the previous ON pulse may occur after the rising edge of the next ON pulse.

[0059] At time TM4, the clock signal CLK1 changes to VGH, causing the potential at node N2 to rise to V3 via capacitance C2. The potential V3 is (VGH-α) using a coefficient α that takes into account the gate capacitances of transistors T2 and T5, and the drain capacitance of transistor T3. Transistors T2 and T5 change to the ON state, and the output signal OUT is maintained at VGL. Transistor T2 switches ON / OFF in the same way as transistor T5.

[0060] From time TM4 onward, ON pulses are repeatedly generated in the order of clock signals CLK1 to CLK8. This causes transistors T5 to T12 to be cyclically turned ON and OFF sequentially. In the example shown in Figure 5, clock signals CLK1 to CLK8 each periodically generate ON pulses. All clock signals CLK1 to CLK8 are synchronized, and in the example in Figure 5, their clock frequencies and clock widths (ON pulse widths) are common. Also, the phases of all clock signals CLK1 to CLK8 are different. The clock period of clock signals CLK1 to CLK8 is 8 times the pulse width.

[0061] In the example shown in Figure 5, consecutive clock signals are simultaneously VGH or VGL. For example, from time TM3 until input signal IN1 rises for data writing in the next frame period (until time TM1 in the next frame period), one of transistors T5 to T12 may be in the ON state, and the output line OT may always be in contact with the low power line. From the time the last pull-down TFT changes from the ON state to the OFF state until time TM1 in the next frame period, the output line may be floating.

[0062] Figure 6A shows a portion of the shift registers that can be implemented in the scan driver 131 or 132. Specifically, Figure 6A shows the uppermost shift register unit 311 and the shift register unit 312 below it (the next or previous stage). Shift register units 311 and 312 have the circuit configurations described with reference to Figures 4 and 5, respectively, and can operate. In this example, the shift register consists of 8N linked shift register units (where N is a positive integer).

[0063] Each shift register unit includes multiple signal terminals. One signal terminal is the output signal terminal for the output signal OUT. The other signal terminals are the input signal terminals for signals IN1, IN2, DIR1, DIR2, CLK1 to CLK8, and the low power supply potential VGL, as described with reference to Figures 4 and 5.

[0064] External signals and the low power supply potential VGL are input to the input signal terminals. Specifically, the control signals DIR1 and DIR2 are input to these signal terminals. The signal terminal IN1 of the uppermost shift register unit 311 receives the start signal ST1. The signal terminal IN1 of the lower shift register unit 312 receives the output signal OUT1 of the upper (previous) shift register unit 311.

[0065] The signal terminal IN2 of shift register unit 312 receives the output signal OUT of the lower (previous) shift register unit (not shown). The signal terminal IN2 of shift register unit 311 receives the output signal OUT2 of the lower (previous) shift register unit 312.

[0066] Each signal terminal of the clock signals CLK1 to CLK8 is input to one of the clock signals CA to CH. In shift register unit 311, the signal terminals of the clock signals CLK1 to CLK8 are input to clock signals CA to CH, respectively. In shift register unit 312, the signal terminals of the clock signals CLK1 to CLK8 are input to clock signals CB to CH and CA, respectively.

[0067] Figure 6B shows other parts of the shift registers that can be implemented in the scan driver 131 or 132. Specifically, Figure 6B shows the bottommost shift register unit 316 and the shift register unit 315 above it (the next or previous stage). Shift register units 315 and 316 are the (8N-1)th and 8Nthth stage shift register units from the top. Shift register units 315 and 316 can operate with the circuit configuration described with reference to Figures 4 and 5, respectively.

[0068] This section primarily explains the differences between shift register units 311 and 312. The signal terminal IN1 of shift register unit 315 receives the output signal OUT of the upper (previous) shift register unit (not shown). The signal terminal IN1 of shift register unit 316 receives the output signal OUT8N-1 of the upper (previous) shift register unit 315.

[0069] The start signal ST2 is input to the IN2 signal terminal of shift register unit 316. The output signal OUT8N of the lower (previous) shift register unit 316 is input to the IN2 signal terminal of shift register unit 315.

[0070] In shift register unit 315, the clock signals CG, CH, and CA-CF are input to the signal terminals of clock signals CLK1-CLK8, respectively. In shift register unit 316, the clock signals CH and CA-CG are input to the signal terminals of clock signals CLK1-CLK8, respectively.

[0071] The shift register units are classified into 8 groups, and the same clock signal is input to each clock signal terminal of a shift register unit within the same group. Different clock signals are input to each clock signal terminal between different groups. Specifically, in the (8k-7)th stage shift register unit, counting from the top, the clock signals CA to CH are input to the signal terminals CLK1 to CLK8, respectively. k is an integer greater than or equal to 1.

[0072] In the (8k-6) stage shift register unit, the signal terminals of the clock signals CLK1 to CLK8 are input to the clock signals CB to CH and CA, respectively. In the (8k-5) stage shift register unit, the signal terminals of the clock signals CLK1 to CLK8 are input to the clock signals CC to CH, CA and CB, respectively. In the (8k-4) stage shift register unit, the signal terminals of the clock signals CLK1 to CLK8 are input to the clock signals CD to CH and CA to CC, respectively.

[0073] In the (8k-3) stage shift register unit, the signal terminals of the clock signals CLK1 to CLK8 are input to the clock signals CE to CH and CA to CD, respectively. In the (8k-2) stage shift register unit, the signal terminals of the clock signals CLK1 to CLK8 are input to the clock signals CF to CH and CA to CE, respectively. In the (8k-1) stage shift register unit, the signal terminals of the clock signals CLK1 to CLK8 are input to the clock signals CG, CH, and CA to CF, respectively. In the 8k stage shift register unit, the signal terminals of the clock signals CLK1 to CLK8 are input to the clock signals CH and CA to CG, respectively.

[0074] Figure 7A shows a signal sequence diagram for a shift register having the configuration shown in Figures 6A and 6B. In the control shown in Figure 7A, the scan direction is from the uppermost shift register unit 311 to the lowermost shift register unit 316. Time TM10 is the start time of each frame period. During one frame period, the control signal DIR1 is at a high level (VGH) and the control signal DIR2 is at a low level (VGL). At time TM10, a pulse for the start signal ST1 is generated. Subsequently, the start signal ST1 remains at a low level (VGL) until the next frame period.

[0075] The pulse of the clock signal CA is generated in conjunction with the end of the pulse of the start signal ST1. The end time of the pulse of the start signal ST1 substantially coincides with the start time of the pulse of the clock signal CA. After the end of the pulse of the start signal ST1, pulses of the clock signals CA to CH are generated sequentially and repeatedly. In the clock signals CA to CH, the next pulse is generated in conjunction with the end of the previous pulse. In the example in Figure 7A, the end times and start times of consecutive pulses substantially coincide. These do not necessarily have to coincide.

[0076] The shift register units sequentially output ON pulses, from the top shift register unit 311 to the bottom shift register unit 316. In Figure 7A, the pulse OUT1 of the output signal of the first shift register unit 311 is generated, followed by the pulse OUT2 of the output signal of the next shift register unit 312. Subsequently, the subsequent shift register units output pulses sequentially, and finally, the ON pulse OUT8N of the output signal of the bottom shift register unit 316 is generated.

[0077] Figure 7B shows another sequence diagram of signals in a shift register having the configuration shown in Figures 6A and 6B. In the control shown in Figure 7B, the scan direction is from the bottom shift register unit 316 to the top shift register unit 311. Time TM10 is the start time of each frame period. During one frame period, the control signal DIR1 is low level (VGL) and the control signal DIR2 is high level (VGH). At time TM10, a pulse of the start signal ST2 is generated. Subsequently, the start signal ST2 remains low level (VGL) until the next frame period.

[0078] The pulse of the clock signal CH is generated in conjunction with the end of the pulse of the start signal ST2. The end time of the pulse of the start signal ST2 substantially coincides with the start time of the pulse of the clock signal CH. After the end of the pulse of the start signal ST2, pulses of the clock signals CH to CA are generated sequentially and repeatedly. In the clock signals CH to CA, the next pulse is generated in conjunction with the end of the previous pulse. In the example in Figure 7B, the end times and start times of consecutive pulses substantially coincide. These do not necessarily have to coincide.

[0079] The shift register units sequentially output ON pulses, from the bottom shift register unit 316 to the top shift register unit 311. In Figure 7B, the pulse OUT8N of the output signal of the first shift register unit 361 is generated, followed by the pulse OUT8N-1 of the output signal of the next shift register unit 315. Subsequently, the subsequent shift register units output pulses sequentially, and finally, the ON pulse OUT1 of the output signal of the top shift register unit 311 is generated.

[0080] In a shift register, the N-type TFT used for pull-down resistors exhibits fluctuations in its Id-Vg characteristics (Vth fluctuations) due to positive bias stress in the ON state. For example, in an n-type TFT, the Vth voltage fluctuates towards the higher voltage side. This reduces the driving capability of the pull-down TFT, making it impossible to accurately control the TFT. This is thought to be caused by charge injection into the gate insulating film or the formation of ranks within the semiconductor film. Characteristic fluctuations are particularly large in amorphous silicon, but can also occur in other semiconductors such as oxide semiconductors and low-temperature polysilicon semiconductors, as well as in P-type TFTs used for pull-up resistors. A pull-up TFT is a TFT used to raise the target node to a high power supply potential VGH. One of the source / drain of the pull-up TFT is connected to the target node, and the other is connected to a power line at a high power supply potential.

[0081] In one embodiment of this specification, as described above, multiple pull-down transistors (TFTs) T5 to T12 are connected in parallel to the output line OT of a shift register unit and are controlled ON / OFF by different clock signals CLK1 to CLK8. The parallel-connected pull-down TFTs are switched ON / OFF sequentially in a cyclical manner.

[0082] This drives each pull-down TFT with a low duty cycle. As a result, the proportion of the ON state is reduced, which suppresses characteristic fluctuations in the pull-down TFTs. Also, the proportion of the OFF state is increased, which promotes characteristic fluctuations that are the opposite of those in the ON state. As a result, the decrease in the driving capability of the pull-down TFTs is effectively suppressed. Furthermore, as explained with reference to Figures 4 and 5, transistor T2 is a pull-down TFT at node N1, and the proportion of its ON state is small, similar to transistor T5. Therefore, the decrease in the driving capability of transistor T2 can be effectively suppressed.

[0083] The duty cycle of the pull-down transistors connected to the output lines depends on the number of clock signals controlling them. The duty cycle of the pull-down transistors matches the duty cycle of the high-level clock signals. Figure 8 schematically shows the relationship between the number of clock signals and the duty cycle. When the number of clock signals is 2, 4, 8, 10, 16, and 20, the duty cycles can be 50%, 25%, 12.5%, 10%, 6.25%, and 5% or less, respectively.

[0084] Figure 9 shows the measurement results of the relationship between the duty cycle of the gate signal and characteristic variation in an amorphous silicon N-type TFT. The measurement involved continuously applying gate signals with different duty cycles to the gate of an amorphous silicon N-type TFT for 500 hours. As shown in Figure 9, the amount of characteristic variation remains virtually unchanged from a duty cycle of 100% to 25%. However, the amount of characteristic variation decreases significantly as the duty cycle decreases from 25% to 12.5%. Thus, the value of the gate signal duty cycle is important for effectively suppressing characteristic variation in pull-down TFTs, and characteristic variation can be greatly reduced by setting the duty cycle to 12.5% ​​or less.

[0085] As mentioned above, the characteristic variations of TFTs are most pronounced in amorphous silicon. Therefore, by setting the duty cycle to 12.5% ​​or less, characteristic variations can be effectively suppressed even in pull-down or pull-up TFTs using oxide semiconductors or low-temperature polysilicon.

[0086] The configuration example described with reference to Figures 4 and 5 controls eight pull-down transistors T5 to T12 with different clock signals CLK1 to CLK8. By providing non-overlapping (separated) ON periods for transistors T5 to T12, the duty cycle of each pull-down transistor can be set to 12.5% ​​or less.

[0087] The number of pull-down transistors connected to the output line is determined by the design and can be more or less than eight. By adjusting the clock signal that controls them, the duty cycle of each pull-down transistor can be set to 12.5% ​​or less. A single clock signal may control multiple pull-down transistors simultaneously.

[0088] <Embodiment 2> Next, we will describe a configuration example in which each scan line 206 is driven by shift register units arranged on both sides of the display area 125. By reducing the width of the left and right bezels of the liquid crystal display device, the display characteristics of the liquid crystal display device can be improved. By arranging shift register units on both sides of the display area 125, the bezel area can be reduced while improving the display characteristics.

[0089] Figure 10 shows an example configuration of two shift register units 320A and 320B that output an output signal to a single scan line 206. The shift register units 320A and 320B simultaneously output selection pulses of the same width to scan line 206. The main explanation will focus on the differences from the configuration example shown in Figure 4. Elements with the same reference numerals as in Figure 4 are the same as those in Figure 4. The signals input to the shift register unit 320A include signals IN1, IN2, DIR1, DIR2, CLK1, CLK2, CLK4, CLK6, and CLK8. Compared to the configuration example in Figure 4, the clock signals CLK3, CLK5, and CLK7 are omitted.

[0090] Shift register unit 320A includes transistors T0A-T6A, T8A, T10A, T12A, and two capacitors C1A and C2A. These correspond to transistors T0-T6, T8, T10, T12, and capacitors C1 and C2 in shift register unit 310 in Figure 4, respectively, and have a similar configuration and operate similarly. Node N1A corresponds to node N1, and their potential changes are identical. Node N2A corresponds to node N2, and their potential changes are identical.

[0091] Shift register unit 320B includes transistors T0B-T5B, T7B, T9B, T11B, and two capacitors C1B and C2B. These correspond to transistors T0-T5, T7, T9, T11, and capacitors C1 and C2 in shift register unit 310 in Figure 4, respectively, and have a similar configuration and operate similarly. Transistors T7B, T9B, and T11B are examples of fourth thin-film transistors. Alternatively, transistors T6A, T8A, T10A, and T12A are examples of fourth thin-film transistors. Node N1B corresponds to node N1, and their potential changes are identical. Node N2B corresponds to node N2, and their potential changes are identical.

[0092] Figure 11A shows a portion of the shift registers that can be implemented in the scan driver 131. Specifically, Figure 11A shows the uppermost shift register unit 331A and the shift register unit 332A below it (the next or previous stage). Shift register units 331A and 332A can each have the circuit configuration of shift register unit 320A, as described with reference to Figure 10. In this example, the shift register is composed of 8N linked shift register units (where N is a positive integer).

[0093] This section primarily explains the differences from the configuration example shown in Figure 6A. Each shift register unit includes multiple signal terminals. One signal terminal is the output signal terminal for the output signal OUT. The other signal terminals are the input signal terminals for signals IN1, IN2, DIR1, DIR2, CLK1, CLK2, CLK4, CLK6, CLK8, and the low power supply potential VGL. Compared to shift register units 311 and 312 in Figure 6A, the input terminals for clock signals CLK3, CLK5, and CLK7 are omitted.

[0094] The signal terminal IN1 of the top shift register unit 331A receives the start signal ST1. The signal terminal IN1 of the lower shift register unit 332A receives the output signal OUT1 of the upper (previous) shift register unit 331A.

[0095] The signal terminal IN2 of shift register unit 332A receives the output signal OUT of the lower (previous) shift register unit (not shown). The signal terminal IN2 of shift register unit 331A receives the output signal OUT2 of the lower (previous) shift register unit 332A.

[0096] In shift register unit 331A, the signal terminals for clock signals CLK1, CLK2, CLK4, CLK6, and CLK8 receive the clock signals CA, CB, CD, CF, and CH respectively. In shift register unit 332A, the signal terminals for clock signals CLK1, CLK2, CLK4, CLK6, and CLK8 receive the clock signals CB, CC, CE, CG, and CA respectively.

[0097] Figure 11B shows other parts of the shift registers that can be implemented in the scan driver 131. Specifically, Figure 11B shows the bottommost shift register unit 336A and the shift register unit 335A above it (the next or previous stage). Shift register units 335A and 336A are the (8N-1)th and 8Nthth stage shift register units from the top. Shift register units 335A and 336A can each have the circuit configuration of shift register unit 320A, as described with reference to Figure 10.

[0098] This section primarily explains the differences between shift register units 331A and 332A. The signal IN1 terminal of shift register unit 335A receives the output signal OUT of the upper (previous) shift register unit (not shown). The signal IN1 terminal of shift register unit 336A receives the output signal OUT8N-1 of the upper (previous) shift register unit 335A.

[0099] The start signal ST2 is input to the IN2 signal terminal of shift register unit 336A. The output signal OUT8N of the lower (previous) shift register unit 336A is input to the IN2 signal terminal of shift register unit 335A.

[0100] In shift register unit 335A, the signal terminals for clock signals CLK1, CLK2, CLK4, CLK6, and CLK8 receive the clock signals CG, CH, CB, CD, and CF, respectively. In shift register unit 336A, the signal terminals for clock signals CLK1, CLK2, CLK4, CLK6, and CLK8 receive the clock signals CH, CA, CC, CE, and CG, respectively.

[0101] Each clock signal terminal of each shift register unit in each stage of the shift registers shown in Figures 11A and 11B receives the same clock signal as the same clock signal terminal of the same stage of shift register unit in the configuration example shown in Figures 6A and 6B.

[0102] Figure 12A shows a portion of the shift registers that can be implemented in the scan driver 132. Specifically, Figure 12A shows the uppermost shift register unit 331B and the lower (next or previous) shift register unit 332B. Shift register units 331B and 332B can each have the circuit configuration of shift register unit 320B, as described with reference to Figure 10. In this example, the shift register is composed of 8N linked shift register units (where N is a positive integer).

[0103] This section primarily explains the differences from the configuration example shown in Figure 6A. Each shift register unit includes multiple signal terminals. One signal terminal is the output signal terminal for the output signal OUT. The other signal terminals are the input signal terminals for signals IN1, IN2, DIR1, DIR2, CLK1, CLK3, CLK5, CLK7, and the low power supply potential VGL. Compared to shift register units 311 and 312 in Figure 6A, the input terminals for clock signals CLK2, CLK4, CLK6, and CLK8 are omitted.

[0104] The signal terminal IN1 of the uppermost shift register unit 331B receives the start signal ST1. The signal terminal IN1 of the lower shift register unit 332B receives the output signal OUT1 of the upper (previous) shift register unit 331B.

[0105] The signal terminal IN2 of shift register unit 332B receives the output signal OUT of the lower (previous) shift register unit (not shown). The signal terminal IN2 of shift register unit 331B receives the output signal OUT2 of the lower (previous) shift register unit 332B.

[0106] In shift register unit 331B, the signal terminals for clock signals CLK1, CLK3, CLK5, and CLK7 receive the clock signals CA, CC, CE, and CG, respectively. In shift register unit 332B, the signal terminals for clock signals CLK1, CLK3, CLK5, and CLK7 receive the clock signals CB, CD, CF, and CH, respectively.

[0107] Figure 12B shows other parts of the shift registers that can be implemented in the scan driver 132. Specifically, Figure 12B shows the bottommost shift register unit 336B and the shift register unit 335B above it (the next or previous stage). Shift register units 335B and 336B are the (8N-1)th and 8Nthth stage shift register units from the top. Shift register units 335B and 336B can each have the circuit configuration of shift register unit 320B, as described with reference to Figure 10.

[0108] This section primarily explains the differences between shift register units 331B and 332B. The signal terminal IN1 of shift register unit 335B receives the output signal OUT of the upper (previous) shift register unit (not shown). The signal terminal IN1 of shift register unit 336B receives the output signal OUT8N-1 of the upper (previous) shift register unit 335B.

[0109] The start signal ST2 is input to the IN2 signal terminal of shift register unit 336B. The output signal OUT8N of the lower (previous) shift register unit 336B is input to the IN2 signal terminal of shift register unit 335B.

[0110] In shift register unit 335B, the clock signals CG, CA, CC, and CE are input to the signal terminals CLK1, CLK3, CLK5, and CLK7, respectively. In shift register unit 336B, the clock signals CH, CB, CD, and CF are input to the signal terminals CLK1, CLK3, CLK5, and CLK7, respectively.

[0111] Each clock signal terminal of the shift register unit in each stage of the shift register shown in Figures 12A and 12B receives the same clock signal as the same clock signal terminal of the same stage of the shift register unit in the configuration example shown in Figures 6A and 6B. Furthermore, the time variation of the input and output signals of the two shift registers and the operation of the shift registers, as explained with reference to Figures 10 to 12B, are as explained with reference to Figures 7A and 7B.

[0112] In the above example, the rising and falling edges of the selection pulses output by the shift register units on both sides of each scan line 206 are simultaneous. The number of pull-down TFTs for scan line 206 in shift register unit 320A is 5, and the number of pull-down TFTs for shift register unit 320B is 4. In this way, by keeping the difference in the number of pull-down TFTs between the shift register units on both sides of the scan line to 1 or less, the bezel area can be effectively reduced.

[0113] Transistors T5A and T5B are switched ON / OFF simultaneously. The other pull-down TFTs for scan line 206 are switched ON alternately between the left and right shift register units 320A and 320B. That is, transistors 6A, 7B, 8A, 9B, 10A, 11B, and 12A are switched ON in that order. In this way, by selecting transistors to be switched ON alternately in the shift register units on both sides, the impact on display quality can be reduced in a configuration that controls the scan line potential with two shift register units.

[0114] <Embodiment 3> One embodiment of this specification, described below, intermittently turns on the pull-down TFTs of the output lines (scan lines) of each shift register. After the output line conducts to the low-power line via the pull-down TFT, the output line remains in a floating state until the pull-down TFT is turned off and the next pull-down TFT is turned on. The potential of the output line in the floating state remains at VGL. The number of pull-down TFTs can be reduced by inserting a floating period in which all pull-down TFTs are in the OFF state during a pull-down period in which one or more pull-down TFTs are in the ON state.

[0115] Figure 13 shows an example configuration of a shift register unit 350 according to one embodiment of this specification. Compared to the shift register unit 310 shown in Figure 4, transistors T7, T9, and T11 are omitted. The other components are the same as those of the shift register unit 310. In addition, the clock signals CLK3, CLK5, and CLK7 that control transistors T7, T9, and T11, respectively, are omitted in the input signals to the shift register unit 310. The other signals are the same as the input signals to the shift register unit 310.

[0116] Because clock signals CLK3, CLK5, and CLK7 are omitted, the output lines are pulled down every other CLK. A floating period exists between the ON pulses of clock signals CLK2, CLK4, CLK6, and CLK8.

[0117] Figure 14A shows a portion of the shift registers that can be implemented in the scan driver 131 or 132. Specifically, Figure 14A shows the uppermost shift register unit 351 and the shift register unit 352 below it (the next or previous stage). Shift register units 351 and 352 each have the circuit configuration described with reference to Figure 13 and can operate. In this example, the shift register is composed of linked 8N stages (N is a positive integer) of shift register units.

[0118] Compared to the configuration example shown in Figure 6A, the input terminals for clock signals CLK3, CLK5, and CLK7 are omitted in shift register units 351 and 352. The other parts are the same as the configuration example shown in Figure 6A.

[0119] Figure 14B shows other parts of the shift registers that can be implemented in the scan driver 131 or 132. Specifically, Figure 14B shows the bottommost shift register unit 356 and the shift register unit 355 above it (the next or previous stage). Shift register units 355 and 356 are the (8N-1)th and 8Nthth stage shift register units from the top. Shift register units 355 and 356 can operate with the circuit configuration described with reference to Figure 13.

[0120] The signal terminal IN1 of shift register unit 355 receives the output signal OUT of the upper (previous) shift register unit (not shown). The signal terminal IN1 of shift register unit 356 receives the output signal OUT8N-1 of the upper (previous) shift register unit 355.

[0121] The start signal ST2 is input to the IN2 signal terminal of shift register unit 316. The output signal OUT8N of the lower (previous) shift register unit 356 is input to the IN2 signal terminal of shift register unit 355.

[0122] In shift register unit 355, the signal terminals for clock signals CLK1, CLK2, CLK4, CLK6, and CLK8 receive the clock signals CG, CH, CB, CD, and CF, respectively. In shift register unit 356, the signal terminals for clock signals CLK1, CLK2, CLK4, CLK6, and CLK8 receive the clock signals CH, CA, CC, CE, and CG, respectively.

[0123] The time variations of the input and output signals of the shift register are as described with reference to Figures 7A and 7B. The shift register of this embodiment is the same as the configuration described with reference to Figures 4 to 7B, except that the input of the clock signal at the shift register level is omitted.

[0124] In the above example, the floating period and the ON periods of each pull-down TFT are of the same length. The floating period may be longer than the ON periods. For example, in the configuration example shown in Figure 13, transistors T8 and T12 may be omitted.

[0125] While embodiments of the present disclosure have been described above, the present disclosure is not limited to the embodiments described above. Those skilled in the art can easily modify, add to, and transform each element of the above embodiments within the scope of the present disclosure. It is possible to replace parts of the configuration of one embodiment with the configuration of another embodiment, and to add the configuration of another embodiment to the configuration of one embodiment. [Explanation of Symbols]

[0126] 10 OLED display device, 105 data lines, 106 scan lines, 125 display area, 131, 132 scan driver, 134 driver IC, 310, 311, 312, 315, 316, 320, 331, 332, 335, 336, 350, 352, 352, 355, 356 shift register unit, T1~T12 thin-film transistor, C1, C2 capacitance

Claims

1. A display device, Multiple pixel circuit rows, Multiple selection lines connected to the aforementioned multiple pixel circuit rows, A shift register containing multiple linked shift register units, Includes, The aforementioned multiple shift register unit outputs selection pulses sequentially to the aforementioned multiple selection lines, Each of the multiple shift register units outputs the selection pulse to the corresponding selection line of the multiple selection lines. Each shift register unit includes a plurality of thin-film transistors of a first conductivity type connected in parallel, which conduct the corresponding selection line and a constant potential wiring for providing a non-selection level for the selection pulse when in the ON state. Within one frame period, the multiple thin-film transistors are turned ON / OFF by clock signals of different phases. The duty cycle of the ON period of each of the multiple thin-film transistors in the aforementioned one frame period is 12.5% ​​or less. The aforementioned shift register is the first shift register, The system further includes a second shift register located on the opposite side of the first shift register, separated by the multiple selection lines, The second shift register is, The aforementioned multiple selection lines include a plurality of connected second shift register units that sequentially output the selection pulses together with the first shift register, Each of the plurality of second shift register units includes, in the ON state, a plurality of fourth thin-film transistors of the first conductivity type connected in parallel, which conduct a corresponding selection line and a constant potential wiring that provides a non-selection level for the selection pulse. Within the aforementioned one frame period, the plurality of fourth thin-film transistors are turned ON / OFF by clock signals with different phases. The duty cycle of the ON period of each of the multiple fourth thin-film transistors in the aforementioned one frame period is 12.5% ​​or less. The difference between the number of thin-film transistors conducting each selected line and the wiring that provides the deselection level in the first shift register and the number of thin-film transistors conducting each selected line and the constant potential wiring that provides the deselection level in the second shift register is 1 or less. A thin-film transistor selected from the plurality of thin-film transistors of the first shift register and a fourth thin-film transistor selected from the plurality of fourth thin-film transistors are alternately turned ON. Display device.

2. A display device according to claim 1, Each of the multiple thin-film transistors in the first shift register is an N-type amorphous silicon thin-film transistor. The aforementioned non-selection level is a low level. Display device.

3. A display device according to claim 1, Each shift register unit of the first shift register is: In the ON state, the second thin-film transistor of the first conductivity type provides the selection level of the selection pulse to the corresponding selection line, In the ON state, the constant potential wiring and the third thin-film transistor of the first conductivity type conduct to the gate of the second thin-film transistor, It further includes, The third thin-film transistor is controlled by the same clock signal as one of the thin-film transistors among the plurality of thin-film transistors. Display device.

4. A display device according to claim 1, In the aforementioned frame period, the plurality of thin-film transistors of the first shift register are cyclically selected and turned ON / OFF. In the aforementioned plurality of thin-film transistors, during the ON period of consecutively selected thin-film transistors, there exists a floating period in which all of the plurality of thin-film transistors are in the OFF state. During the floating period, the corresponding selection line is in a floating state. Display device.

5. A display device according to claim 4, The ON period of each of the consecutively selected thin-film transistors is less than or equal to the floating period. Display device.

6. A display device according to claim 1, In the aforementioned frame period, the multiple thin-film transistors are cyclically turned ON / OFF in sequence. The end and start of the consecutive ON periods of the aforementioned multiple thin-film transistors coincide. Display device.

7. A display device according to claim 1, In the first shift register, all thin-film transistors that conduct to each selection line and the constant potential wiring are controlled by clock signals of different phases. Display device.

8. A display device, Multiple pixel circuit rows, Multiple selection lines connected to the aforementioned multiple pixel circuit rows, A shift register containing multiple linked shift register units, Includes, The aforementioned multiple shift register unit outputs selection pulses sequentially to the aforementioned multiple selection lines, Each of the multiple shift register units outputs the selection pulse to the corresponding selection line of the multiple selection lines. Each shift register unit includes a plurality of thin-film transistors of a first conductivity type connected in parallel, which conduct the corresponding selection line and a constant potential wiring for providing a non-selection level for the selection pulse when in the ON state. Within one frame period, the multiple thin-film transistors are turned ON / OFF by clock signals of different phases. The duty cycle of the ON period of each of the multiple thin-film transistors in the aforementioned one frame period is 12.5% ​​or less. In the aforementioned frame period, the multiple thin-film transistors are cyclically selected and turned ON / OFF in sequence. In the aforementioned plurality of thin-film transistors, during the ON period of consecutively selected thin-film transistors, there exists a floating period in which all of the plurality of thin-film transistors are in the OFF state. During the floating period, the corresponding selection line is in a floating state. The ON period of each of the consecutively selected thin-film transistors is less than or equal to the floating period. Display device.

9. A display device, Multiple pixel circuit rows, Multiple selection lines connected to the aforementioned multiple pixel circuit rows, A shift register containing multiple linked shift register units, Includes, The aforementioned multiple shift register unit outputs selection pulses sequentially to the aforementioned multiple selection lines, Each of the multiple shift register units outputs the selection pulse to the corresponding selection line of the multiple selection lines. Each shift register unit includes a plurality of thin-film transistors of a first conductivity type connected in parallel, which conduct the corresponding selection line and a constant potential wiring for providing a non-selection level for the selection pulse when in the ON state. Within one frame period, the multiple thin-film transistors are turned ON / OFF by clock signals of different phases. The duty cycle of the ON period of each of the multiple thin-film transistors in the aforementioned one frame period is 12.5% ​​or less. In the aforementioned frame period, the multiple thin-film transistors are cyclically turned ON / OFF in sequence. The end and start of the consecutive ON periods of the aforementioned multiple thin-film transistors coincide. Display device.

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