Thin-film transistor substrate and display device including the same

Abstract

SOLUTION: A thin film transistor substrate 100 including a thin film transistor on a substrate, includes an active layer 130, a conductive material layer on the active layer, and a gate electrode 150 spaced apart and partially overlapping the active layer. The active layer includes a channel area 130n partially overlapping the gate electrode in the plane, and a source area 160 and a drain area 170 connected to one side and the other side of the channel area in the plane. The conductive material layer includes a first conductive material layer 165 on the source area and a second conductive material layer 175 on the drain area. The second conductive material layer overlaps at least a portion of the channel area, and an active hole 135 in which the active layer is absent is arranged within an area defined by the active layer. The active hole protrudes in the direction of the drain area from the gate electrode in the plane.EFFECT: Exposure to hydrogen and light for a channel is prevented or suppressed.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a thin film transistor substrate and a display device including the same.

Background Art

[0002] Transistors are widely used as switching devices and driving devices in the field of electronic equipment. In particular, thin film transistors can be manufactured on a glass substrate or a plastic substrate, so they are widely used as switching elements for display devices such as liquid crystal display devices or organic light emitting devices.

[0003] Thin film transistors can be classified based on the material constituting the active layer into: amorphous silicon thin film transistors in which amorphous silicon is used as the active layer; polycrystalline silicon thin film transistors in which polycrystalline silicon is used as the active layer; and oxide semiconductor thin film transistors in which an oxide semiconductor is used as the active layer.

[0004] Amorphous silicon thin film transistors (a-SiTFT) allow amorphous silicon to be deposited to form an active layer within a short time, so they have the advantages of short manufacturing process time and low production cost. On the other hand, they have low mobility, poor current driving capability, and threshold voltage variation, so they have the disadvantage that their use is limited in applications such as active matrix organic light emitting diodes (AMOLED).

[0005] Polycrystalline silicon thin-film transistors (poly-SiTFTs) are manufactured by depositing amorphous silicon and then allowing the amorphous silicon to crystallize. Because the manufacturing process requires a crystallization step, the number of steps increases, raising manufacturing costs. Furthermore, the crystallization process requires high temperatures, making it difficult to apply polycrystalline silicon thin-film transistors to large-area devices. Additionally, the polycrystalline properties make it difficult to ensure uniformity in polycrystalline silicon thin-film transistors.

[0006] Oxide semiconductor thin-film transistors (TFTs) allow for the deposition of the active layer oxide at relatively low temperatures, possess high mobility, and exhibit large resistance changes depending on the oxygen content, making it easy to obtain desired physical properties. Furthermore, due to the properties of oxides, oxide semiconductors are transparent, which is advantageous for realizing transparent displays.

[0007] In the case of oxide semiconductor thin-film transistors, they can be susceptible to exposure to light or hydrogen. In this case, structural modifications are necessary to control exposure to light or hydrogen. Therefore, techniques for controlling exposure to light or hydrogen are being researched. [Overview of the project] [Problems that the invention aims to solve]

[0008] One embodiment of the present invention aims to provide a thin-film transistor substrate that prevents or suppresses exposure to hydrogen and light by including active holes.

[0009] One embodiment of the present invention aims to provide a thin-film transistor substrate that, by including active holes, prevents or suppresses a shift in the threshold voltage (Vth) towards the negative direction, even when the channel region has a large width.

[0010] One embodiment of the present invention aims to provide a thin-film transistor substrate that prevents or suppresses exposure to hydrogen and light by including a conductive material layer superimposed on the channel region.

[0011] One embodiment of the present invention aims to provide a thin-film transistor substrate with improved reliability, wherein the active layer includes a pattern and includes a conductive material layer superimposed on the channel region.

[0012] One embodiment of the present invention aims to provide a thin-film transistor substrate that includes active holes and a conductive material layer superimposed on the channel region, thereby ensuring optimization of the capacitor area.

[0013] Another embodiment of the present invention aims to provide a display device including such a thin-film transistor substrate. [Means for solving the problem]

[0014] One embodiment of the present invention for achieving the aforementioned technical problems provides a thin-film transistor substrate comprising a substrate and a thin-film transistor on the substrate, wherein the thin-film transistor comprises an active layer, a conductive material layer on the active layer, and a gate electrode separated from the active layer and partially overlapping with the active layer, the active layer comprises a channel region partially overlapping with the gate electrode in a plane, a source region connected to one side of the channel region in a plane, and a drain region connected to the other side of the channel region in a plane, the conductive material layer comprises a first conductive material layer on the source region and a second conductive material layer on the drain region, the first conductive material layer overlapping with at least a portion of the channel region, and the active layer includes active holes in a region defined by the active layer where the active layer is not located, and the active holes extend in a plane from the channel region to the drain region.

[0015] A portion of the active hole can be superimposed on the gate electrode in the plane.

[0016] The active holes can be separated from the first conductive material layer in a plane.

[0017] The second conductive material layer can be separated from the channel region in a plane.

[0018] The source region and the drain region are each positioned between the base substrate and the first conductive material layer and the second conductive material layer, and the first conductive material layer and the second conductive material layer can each contact the active layer.

[0019] The gate electrode, source electrode, and drain electrode are arranged on the same layer, and include a source electrode and a drain electrode that are spaced apart from each other and in contact with the source region and the drain region, respectively.

[0020] The active hole may have a plurality of subactive holes, the plurality of subactive holes being spaced apart from each other, and each of the plurality of subactive holes may have an elongated shape extending from the channel region to the drain region.

[0021] The conductive material layer may include at least one selected from titanium (Ti), molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), chromium (Cr), tantalum (Ta), neodymium (Nd), calcium (Ca), barium (Ba), and transparent conductive oxide (TCO).

[0022] The shortest distance from the drain region to the first conductive material layer is the first length, and the shortest length over which the first conductive material layer overlaps with the gate electrode in the plane in the longitudinal direction of the channel of the active layer is the second length, and the first length may be longer than the second length.

[0023] A part of said active hole overlaps with said gate electrode. In the length direction of the channel of said active layer, the shortest length at which said active hole overlaps with said gate electrode is a third length, and in the length direction of the channel of said active layer, the shortest distance from said active hole to said first conductive material layer is a fourth length, and said fourth length may be longer than said third length.

[0024] It comprises a light blocking layer on said substrate, and may further comprise a storage capacitor in an overlapping region between said light blocking layer and said thin film transistor.

[0025] Said storage capacitor comprises a first storage capacitor, said first storage capacitor comprises a first capacitor electrode connected to said light blocking layer and a second capacitor electrode connected to said active layer, said first capacitor electrode and said second capacitor electrode are spaced apart from each other and can overlap each other to form a first capacitor.

[0026] Said first storage capacitor comprises a third capacitor electrode connected to said gate electrode, said second capacitor electrode and said third capacitor electrode are spaced apart from each other and can overlap each other to form a second capacitor.

[0027] Said second capacitor electrode can comprise a first layer integrated with any one of said source region and said drain region, and a second layer integrated with any one of said first conductive material layer and said second conductive material layer.

[0028] Said second capacitor electrode is located between said first capacitor electrode and said third capacitor electrode, and said third capacitor electrode can be connected to said first capacitor electrode.

[0029] Said storage capacitor can comprise a second storage capacitor formed by said gate electrode and said first conductive material layer being spaced apart from each other and overlapping each other.

[0030] The storage capacitor may include a third storage capacitor formed by superimposing the gate electrode and the light-blocking layer while being spaced apart from each other.

[0031] The third storage capacitor may be formed in a region that overlaps with the active hole.

[0032] The active layer comprises an oxide semiconductor material, and the oxide semiconductor material may include at least one of the following oxide semiconductor materials: IZO (InZnO) system, IGO (InGaO) system, ITO (InSnO) system, IGZO (InGaZnO) system, IGZTO (InGaZnSnO) system, GZTO (GaZnSnO) system, GZO (GaZnO) system, ITZO (InSnZnO) system, and FIZO (FeInZnO) system.

[0033] Another embodiment of the present invention provides a display device including the thin-film transistor substrate. [Effects of the Invention]

[0034] A thin-film transistor substrate according to one embodiment of the present invention can prevent or suppress exposure of the channel to hydrogen and light by including active holes.

[0035] A thin-film transistor substrate according to one embodiment of the present invention can prevent or suppress the shift of the threshold voltage (Vth) in the negative direction by including active holes.

[0036] A thin-film transistor substrate according to one embodiment of the present invention can prevent or suppress exposure of the channel to hydrogen and light by including a conductive material layer superimposed on the channel region.

[0037] A thin-film transistor substrate according to one embodiment of the present invention can have safety and excellent reliability by including active holes and a conductive material layer superimposed on the channel region.

[0038] A thin-film transistor substrate according to one embodiment of the present invention includes active holes and a conductive material layer superimposed on the channel region, thereby ensuring optimization of the capacitor area.

[0039] In addition to the effects described above, other features and advantages of the present invention can be described below, and such descriptions and explanations will be clearly understandable to a person with ordinary skill in the art to which the present invention pertains. [Brief explanation of the drawing]

[0040] [Figure 1] This is a plan view of a thin-film transistor substrate according to one embodiment of the present invention. [Figure 2] This is a cross-sectional view taken along the line I-I' in Figure 1. [Figure 3] This is a cross-sectional view taken along the line II-II' in Figure 1. [Figure 4] This is a plan view of a thin-film transistor substrate according to another embodiment of the present invention. [Figure 5] This is a cross-sectional view taken along the line I-I' in Figure 4. [Figure 6] This is a cross-sectional view taken along the line II-II' in Figure 4. [Figure 7] This is a cross-sectional view of a thin-film transistor substrate according to yet another embodiment of the present invention. [Figure 8] This is a plan view of a thin-film transistor substrate according to yet another embodiment of the present invention. [Figure 9] This is a schematic diagram illustrating the transistor of the present invention. [Figure 10] This is a cross-sectional view of a thin-film transistor substrate according to an embodiment illustrating the capacitor of the present invention. [Figure 11] This is a cross-sectional view of a thin-film transistor substrate as an example illustrating the capacitor of the present invention. [Figure 12A] This is a plan view of a thin-film transistor substrate according to yet another embodiment of the present invention. [Figure 12B] This is a cross-sectional view taken along the line I-I' in Figure 12A. [Figure 13] This is a schematic diagram of a display device according to one embodiment of the present invention. [Figure 14] This is a schematic diagram of the shift resist. [Figure 15] This is a circuit diagram of one pixel in Figure 13. [Figure 16] This is a plan view of the pixels in Figure 15. [Figure 17] This is a cross-sectional view taken along the line III-III' in Figure 16. [Figure 18] This is a circuit diagram of any one pixel of a display device according to another embodiment of the present invention. [Figure 19] This is a circuit diagram of any single pixel of a display device according to yet another embodiment of the present invention. [Modes for carrying out the invention]

[0041] The advantages and features of the present invention, as well as methods for achieving them, will become clear upon detailed reference to the various examples described below with reference to the accompanying drawings. However, the present invention is not limited to the examples disclosed below and can be embodied in a variety of different forms, and the examples provided are merely to complete the disclosure of the present invention and to inform those with ordinary skill in the art to which the technical idea of ​​the present invention pertains.

[0042] The shapes, sizes, ratios, angles, and quantities disclosed in the drawings illustrating embodiments of the present invention are illustrative only, and the present invention is not limited to what is shown in the drawings. The same components throughout the specification may be indicated by the same reference numerals in the drawings. Furthermore, in describing the present invention, if it is determined that a specific description of related known technology may unnecessarily obscure the gist of the present invention, such detailed description will be omitted.

[0043] When using terms like "includes," "possesses," or "becomes" in a specification, other parts can be added unless the expression "only" is used. When expressing a component singularly, it includes multiple components unless otherwise explicitly stated.

[0044] In interpreting the constituent elements, even if there is no separate explicit description, it should be interpreted as including a margin of error.

[0045] For example, when describing the relative positions of two parts, such as "on top of," "above," "below," or "next to," one or more other parts can be located between the two parts, unless expressions like "immediately" or "directly" are used.

[0046] Spatially relative terms such as "below" or "beneath," "lower," "above," and "upper" can be used to easily describe the correlation between one element or component and another, as shown in the drawing. Spatially relative terms should be understood to include different directions of the element during use or operation, in addition to the directions shown in the drawing. For example, when overturning an element shown in the drawing, an element described as "below" or "beneath" another element may be placed "above" the other element. Therefore, the exemplary term "below" can include both downward and upward directions. Similarly, the exemplary terms "up" or "upper side" can include both upward and downward directions.

[0047] When describing temporal relationships, for example, when describing sequential relationships using phrases like "after," "following," "next," or "before," it can include non-continuous events unless expressions like "immediately" or "directly" are used.

[0048] The terms "first," "second," etc., are used to describe various components, but these components are not limited to these terms. These terms are used simply to distinguish one component from others. Therefore, the first component mentioned below may also be the second component within the technical concept of the present invention.

[0049] The term "at least one" should be understood to include all possible combinations of one or more related items. For example, "at least one of items 1, 2, and 3" can mean not just each of items 1, 2, or 3 individually, but all possible combinations of two or more items from items 1, 2, and 3.

[0050] The features of many embodiments of the present invention can be partially or entirely combined or combined with one another, enabling a variety of technically diverse interlocking and driving mechanisms. Each embodiment can be implemented independently of the others or together in a related manner.

[0051] When assigning reference numerals to the components in each figure illustrating an embodiment of the present invention, the same reference numerals can be used for the same component as much as possible, even if they are shown in other figures.

[0052] In the embodiments of the present invention, the source electrode and drain electrode are distinguished only for the sake of explanation, and the source electrode and drain electrode can be interchanged with each other. The source electrode can become the drain electrode, and the drain electrode can become the source electrode. Furthermore, the source electrode of one embodiment can become the drain electrode in another embodiment, and the drain electrode of one embodiment can become the source electrode in another embodiment.

[0053] In one embodiment of the present invention, for the sake of explanation, the source region and source electrode may be distinguished, and the drain region and drain electrode may be distinguished, but the embodiments of the present invention are not limited thereto. The source region can be the source electrode, and the drain region can be the drain electrode. Furthermore, the source region can be the drain electrode, and the drain region can be the source electrode.

[0054] Figure 1 is a plan view of a thin-film transistor substrate 100 according to one embodiment of the present invention. Figure 2 is a cross-sectional view taken along the line I-I' in Figure 1. Figure 3 is a cross-sectional view taken along the line II-II' in Figure 1.

[0055] Referring to Figures 1, 2, and 3, a thin-film transistor substrate 100 according to one embodiment of the present invention includes a thin-film transistor TFT on a substrate 110, and the thin-film transistor TFT may include an active layer 130, a gate electrode 150, and conductive material layers 165, 175.

[0056] Specifically, referring to Figures 1, 2, and 3, the system may include an active layer 130 on a substrate 110, a gate electrode 150 spaced apart from the active layer 130 and overlapping at least a portion of the active layer 130, and conductive material layers 165 and 175 on the active layer 130.

[0057] A thin-film transistor substrate 100 according to one embodiment of the present invention may further include a substrate 110. Referring to Figures 2 and 3, the active layer 130 is disposed on the substrate 110.

[0058] A thin-film transistor substrate 100 according to one embodiment of the present invention may further include a buffer layer 120. Referring to Figures 2 and 3, the active layer 130 is disposed on the buffer layer 120. Specifically, the buffer layer 120 is disposed between the substrate 110 and the active layer 130.

[0059] A thin-film transistor substrate 100 according to one embodiment of the present invention may further include a gate insulating film 140. Referring to Figures 2 and 3, the gate insulating film 140 is disposed on the active layer 130. Specifically, the gate insulating film 140 is disposed between the active layer 130 and the gate electrode 150.

[0060] In one embodiment of the present invention, the thin-film transistor substrate 100 may have further layers disposed on the gate electrode 150. Specifically, the thin-film transistor substrate 100 may further include an interlayer insulating film 180. Referring to Figure 17, the interlayer insulating film 180 is disposed on the gate electrode 150. Specifically, the gate electrode 150 is disposed between the gate insulating film 140 and the interlayer insulating film 180.

[0061] A thin-film transistor substrate 100 according to one embodiment of the present invention may further include a source electrode 160 and a drain electrode 170. Referring to Figures 1, 2, and 3, the source electrode 160 and the drain electrode 170 are arranged on the gate insulating film 140.

[0062] The components of the thin-film transistor substrate 100 according to one embodiment of the present invention will be described in more detail below.

[0063] The substrate 110 can be made of glass or plastic. As the plastic, a transparent plastic with flexible properties, such as polyimide, can be used.

[0064] When polyimide is used as the substrate 110, considering that a high-temperature deposition process is performed on the substrate 110, a heat-resistant polyimide that can withstand high temperatures can be used. In this case, for thin-film transistor formation, processes such as deposition and etching can be carried out with the polyimide substrate placed on a carrier substrate made of a highly durable material such as glass.

[0065] Referring to Figures 2 and 3, a buffer layer 120 can be placed on the substrate 110.

[0066] The buffer layer 120 is formed on the substrate 110 and can be made of an inorganic or organic material. For example, it can include insulating oxides such as silicon oxide (SiOx) and aluminum oxide (Al2O3).

[0067] The buffer layer 120 protects the active layer 130 by blocking impurities such as moisture and oxygen flowing in from the substrate 110, and plays a role in flattening the top of the substrate 110. It can be formed as a single layer or multiple layers.

[0068] Referring to Figures 2 and 3, the active layer 130 can be placed on the buffer layer 120.

[0069] The active layer 130 may include a channel region 130n, a source region 130a, and a drain region 130b.

[0070] Specifically, the active layer 130 may include a channel region 130n that overlaps with the gate electrode 150 in a plane, a source region 130a that does not overlap with the gate electrode 150 in a plane and is connected to one side of the channel region 130n, and a drain region 130b that does not overlap with the gate electrode 150 in a plane and is connected to the other side of the channel region 130n.

[0071] According to one embodiment of the present invention, the source region 130a and the drain region 130b are separated from each other with the channel region 130n in between.

[0072] According to one embodiment of the present invention, the active layer 130 can be formed from a semiconductor material. The active layer 130 may include an oxide semiconductor material.

[0073] The oxide semiconductor material may include, for example, at least one of the following: IZO (InZnO)-based oxide semiconductor material, IGO (InGaO)-based oxide semiconductor material, ITO (InSnO)-based oxide semiconductor material, IGZO (InGaZnO)-based oxide semiconductor material, IGZTO (InGaZnSnO)-based oxide semiconductor material, GZTO (GaZnSnO)-based oxide semiconductor material, GZO (GaZnO)-based oxide semiconductor material, ITZO (InSnZnO)-based oxide semiconductor material, and FIZO (FeInZnO)-based oxide semiconductor material. However, the embodiment of the present invention is not limited thereto, and the active layer 130 can also be formed with other oxide semiconductor materials known in the art.

[0074] The source region 130a and the drain region 130b can be formed by selective conductor formation of the active layer 130, which is made of a semiconductor material. According to one embodiment of the present invention, selective conductor formation refers to imparting conductivity to a specific part of the active layer 130 so that it functions like a conductor.

[0075] For example, the active layer 130 can be selectively made conductive by ion doping. As a result, a source region 130a and a drain region 130b can be formed. However, the embodiment of the present invention is not limited thereto, and the active layer 130 can also be selectively made conductive by other methods known in the art.

[0076] The source region 130a and the drain region 130b do not overlap with the gate electrode 150. The source region 130a and the drain region 130b have superior electrical conductivity and high mobility compared to the channel region 130n. Therefore, each of the source region 130a and the drain region 130b can function as wiring.

[0077] Referring to Figures 1 and 3, an active hole 135, where the active layer 130 is not present, is located within a region whose edge is defined by the active layer 130. According to one embodiment of the present invention, the active hole 135 is located on a plane within a region defined by the active layer 130. Specifically, the active hole 135 can be described as a region formed by the removal of a portion of the active layer 130.

[0078] Referring to Figures 1 and 3, the active hole 135 can be described as a hole formed in the active layer 130 by the removal of a portion of the active layer 130. Therefore, according to one embodiment of the present invention, the said hole is called an "active hole".

[0079] Specifically, according to one embodiment of the present invention, the active hole 135 can protrude on a plane from the gate electrode 150 in the direction of the drain region 130b.

[0080] More specifically, the active layer 130 does not need to be located in a portion of the drain region 130b.

[0081] Figures 1 and 3 show a configuration in which the active hole 135 protrudes in the direction of the drain region 130b from the gate electrode 150 on a plane.

[0082] According to one embodiment of the present invention, a portion of the active hole 135 can be superimposed on the gate electrode 150. Figures 1 and 3 show a configuration in which a portion of the active hole 135 is superimposed on the gate electrode 150.

[0083] More specifically, the active layer 130 does not need to be placed in a portion of the channel region 130n.

[0084] According to one embodiment of the present invention, the active hole 135 can be formed by patterning the active layer 130. Specifically, the active hole 135 can be described as a region surrounded by the active layer 130. For example, the active hole 135 can be described as a portion of the active layer 130 that has been partially patterned and removed.

[0085] Generally, when the channel region 130n of the active layer 130 has a large channel width, the conduction can diffuse significantly in the boundary region between the channel region 130n and the drain region 130b. When conduction diffuses, the threshold voltage (Vth) of the thin-film transistor may shift in the negative (-) direction, which can reduce the driving safety of the thin-film transistor.

[0086] When the channel region 130n of the active layer 130 has a small channel width, conduction diffusion may decrease in the boundary region between the channel region 130n, the source region 130a, and the drain region 130b. On the other hand, when the channel region 130n of the active layer 130 has a small channel width, the total amount of carriers passing through the channel region 130n of the thin-film transistor decreases, which may degrade the ON current characteristics. As a result, if a large current flows through a thin-film transistor with a small channel width in the channel region 130n, the thin-film transistor may be damaged, reducing its drive safety. Therefore, it is necessary to control conduction diffusion while the active layer 130 has a large channel width.

[0087] According to one embodiment of the present invention, when the active hole 135 is formed to overlap with the gate electrode 150, the boundary between the channel region 130n and the drain region 130b of the active layer 130 is patterned, thereby making the region of the channel region 130n of the active layer 130 conductive, excluding the active hole. As a result, even when the channel region 130n of the active layer 130 has a large channel width, the width of the conductive region is narrowed, which prevents or controls the penetration of conductivity into the channel region 130n, and suppresses or prevents the penetration of light or hydrogen into the channel region 130n of the active layer 130.

[0088] According to one embodiment of the present invention, the active hole 135 may have a plurality of subactive holes. Figure 1 shows a configuration in which the active hole 135 has a plurality of subactive holes. When the active hole 135 has a plurality of subactive holes, each subactive hole overlaps with at least a portion of the gate electrode 150. Also, when the active hole 135 has a plurality of subactive holes, each subactive hole is separated from each other. However, this embodiment of the present invention is not limited thereto, and the active hole 135 may also have a single subactive hole.

[0089] According to one embodiment of the present invention, the active hole 135 may have a rectangular shape. However, the embodiment of the present invention is not limited thereto, and the active hole 135 according to one embodiment of the present invention can have a variety of shapes.

[0090] According to one embodiment of the present invention, the thin-film transistor substrate 100 may include conductive material layers 165 and 175 on the active layer 130.

[0091] Specifically, referring to Figures 1, 2, and 3, the conductive material layers 165 and 175 may include a first conductive material layer 165 on the source region 130a and a second conductive material layer 175 on the drain region 130b.

[0092] More specifically, referring to Figures 1, 2, and 3, the first conductive material layer 165 and the second conductive material layer 175 are arranged apart from each other, with a portion of the channel region 130n in between.

[0093] Referring to Figures 1, 2, and 3, the source region 130a and the drain region 130b can be positioned between the substrate 110 and the first conductive material layer 165 and the second conductive material layer 175, respectively.

[0094] More specifically, referring to Figures 1, 2, and 3, the first conductive material layer 165 and the second conductive material layer 175 can each contact the active layer 130 via the source region 130a and the drain region 130b.

[0095] According to one embodiment of the present invention, the first conductive material layer 165 can be superimposed on at least a portion of the channel region 130n. Figures 1, 2, and 3 show a configuration in which the first conductive material layer 165 is superimposed on the channel region 130n. More specifically, the first conductive material layer 165 can also be superimposed on at least a portion of the gate electrode 150.

[0096] According to one embodiment of the present invention, when the first conductive material layer 165 is superimposed on the channel region 130n, the first conductive material layer 165 can protect the boundary region between the source region 130a and the channel region 130n from external light or hydrogen. Therefore, the channel region 130n of the active layer 130 can be protected from external light or hydrogen.

[0097] According to one embodiment of the present invention, the second conductive material layer 175 does not have to be placed on the active hole 135. Specifically, Figures 1 and 3 show a configuration in which the second conductive material layer 175 is not placed on the active hole 135.

[0098] According to one embodiment of the present invention, the active hole 135 may be arranged at a distance from the first conductive material layer 165. Specifically, the active hole 135 does not have to overlap with at least a portion of the gate electrode 150. Figure 1 shows a configuration in which the active hole 135 is arranged at a distance from the first conductive material layer 165 on a plane.

[0099] According to one embodiment of the present invention, the first conductive material layer 165 may be superimposed on the channel region 130n, while the second conductive material layer 175 may be arranged separately from the channel region 130n.

[0100] Specifically, in the case of the source region 130a of the active layer 130, the first conductive material layer 165 can superimpose on the channel region 130n to protect the channel region 130n from external light or hydrogen, and in the case of the drain region 130b of the active layer 130, the active hole 135 can superimpose on the gate electrode 150 to protect the channel region 130n from external light or hydrogen.

[0101] According to one embodiment of the present invention, the conductive material layers 165 and 175 may include at least one selected from titanium (Ti), molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), chromium (Cr), tantalum (Ta), neodymium (Nd), calcium (Ca), barium (Ba), and transparent conductive oxide (TCO). The conductive material layers 165 and 175 may be reducing. According to one embodiment of the present invention, the transparent conductive oxide (TCO) may include ITO (InSnO), IZO (InZnO), IO (InO), TO (SnO), and ZO (ZnO).

[0102] The conductive material layers 165 and 175 allow the active layer 130 to be selectively made conductive. According to one embodiment of the present invention, the source region 130a and the drain region 130b are in contact with the first conductive material layer 165 and the second conductive material layer 175, respectively. The regions of the active layer 130 that are in contact with the first conductive material layer 165 and the second conductive material layer 175 become conductive, forming the source region 130a and the drain region 130b, respectively.

[0103] Specifically, according to one embodiment of the present invention, the source region 130a and the drain region 130b can be formed by reducing the portions of the active layer 130 that are in contact with the conductive material layers 165 and 175, respectively.

[0104] For example, when a portion of the active layer 130 that is in contact with and superimposed on the conductive material layers 165 and 175 is reduced, oxygen vacancies are generated in the active layer 130, and thus the active layer 130 can be selectively made conductive. By such selective reduction of the active layer 130, a source region 130a and a drain region 130b can be formed.

[0105] According to one embodiment of the present invention, the active layer 130 can be selectively made conductive by the conductive material layers 165 and 175 without the need for separate conductive processing steps such as plasma treatment, ion doping, or ultraviolet treatment.

[0106] Referring to Figure 1, if we define the shortest distance from the drain region 130b to the first conductive material layer 165 as the first length L1, and define the shortest length of the region in the channel length direction of the active layer 130 where the first conductive material layer 165 overlaps with the gate electrode 150 as the second length L2, then the first length L1 may be longer than the second length L2. Therefore, light and hydrogen incident from the outside can be efficiently blocked in the source region 130a of the active layer 130, and as a result, the reliability of the thin-film transistor can be improved.

[0107] On the other hand, if the second length L2 is longer than the first length L1, the first conductive material layer 165 may excessively overlap with the gate electrode 150, causing the channel region 130n of the active layer 130 to become excessively conductive. As a result, the threshold voltage (Vth) of the thin-film transistor may shift in the negative direction, reducing the driving safety of the thin-film transistor.

[0108] Referring to Figure 1, if we define the shortest length of the region in the channel length direction of the active layer 130 where the active hole 135 overlaps with the gate electrode 150 as the third length L3, and define the shortest distance from the active hole 135 to the first conductive material layer 165 in the channel length direction of the active layer 130 as the fourth length L4, then the fourth length L4 may be longer than the third length L3. Therefore, light and hydrogen incident from the outside can be efficiently blocked in the drain region 130b of the active layer 130, and as a result, the reliability of the thin-film transistor can be improved.

[0109] On the other hand, if the third length L3 is longer than the fourth length L4, the active holes 135 may penetrate excessively into the channel region 130n, reducing the total amount of carriers passing through the channel region 130n of the thin-film transistor and potentially degrading the ON current characteristics. As a result, if a large current flows through the thin-film transistor, the thin-film transistor may be damaged, reducing its drive safety.

[0110] According to one embodiment of the present invention, the thin-film transistor substrate 100 may further include a source electrode 160 and a drain electrode 170.

[0111] The source electrode 160 and drain electrode 170 are arranged on the gate insulating film 140 and may be placed on the same layer as the gate electrode 150. The source electrode 160 and drain electrode 170 can be formed from the same material and using the same process as the gate electrode 150.

[0112] Each of the source electrode 160, drain electrode 170, and gate electrode 150 may include at least one of the following: aluminum-based metals such as aluminum (Al) or aluminum alloys; silver-based metals such as silver (Ag) or silver alloys; copper-based metals such as copper (Cu) or copper alloys; molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys; chromium (Cr); tantalum (Ta); neodymium (Nd); and titanium (Ti). Each of the source electrode 160, drain electrode 170, and gate electrode 150 may also have a multilayer structure comprising at least two conductive films with different physical properties.

[0113] Referring to Figures 2 and 3, the source electrode 160 and the drain electrode 170 are connected to the active layer 130 via contact holes. Specifically, the source electrode 160 and the drain electrode 170 are connected to the active layer 130 by contacting the first conductive material layer 165 and the second conductive material layer 175, respectively.

[0114] Referring to Figures 1, 2, and 3, a light-blocking layer 111 may be placed on the substrate 110. Specifically, the light-blocking layer 111 may be placed between the substrate 110 and the active layer 130. The light-blocking layer 111 overlaps with the channel region 130n. The light-blocking layer 111 blocks light incident from the outside and protects the channel region 130n.

[0115] The light-blocking layer 111 can be formed from a material having light-blocking properties. The light-blocking layer 111 may include at least one of the following: aluminum (Al) or aluminum alloys (aluminum-based metals), molybdenum (Mo) or molybdenum alloys (molybdenum-based metals), chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), and iron (Fe). According to one embodiment of the present invention, the light-blocking layer 111 may be electrically conductive.

[0116] The light-blocking layer 111 may be omitted. Although not shown in Figures 1, 2, and 3, a buffer layer may be further placed between the substrate 110 and the light-blocking layer 111. Although not shown, the light-blocking layer 111 may be electrically connected to either the source electrode 160 or the drain electrode 170. The light-blocking layer 111 may also be electrically connected to the gate electrode 150.

[0117] According to one embodiment of the present invention, the light-blocking layer 111 can be arranged to overlap the front surface of the active layer 130. However, the embodiment of the present invention is not limited thereto, and the light-blocking layer 111 can also be arranged so as not to overlap with a portion of the active layer 130 excluding the channel region 130n.

[0118] Figure 4 is a plan view of a thin-film transistor substrate 200 according to another embodiment of the present invention. Figure 5 is a cross-sectional view taken along the line I-I' in Figure 4. Figure 6 is a cross-sectional view taken along the line II-II' in Figure 4.

[0119] According to one embodiment of the present invention, the thin-film transistor substrate 200 may further include a gate insulating film 140 between the active layer 130 and the gate electrode 150. The source region 130a and drain region 130b of the active layer 130 may be exposed from the gate insulating film 140. Figures 5 and 6 show a configuration in which the source region 130a and drain region 130b of the active layer 130 are exposed from the gate insulating film 140.

[0120] However, the present invention is not limited to this embodiment, and the gate insulating film 140 can cover the entire upper surface of the active layer 130. Figures 2 and 3 show a configuration in which the gate insulating film 140 covers the entire upper surface of the active layer 130.

[0121] The gate insulating film 140 may include at least one of silicon oxide, silicon nitride, and metal oxide. The gate insulating film 140 may have a single-film structure or a multilayer structure. The gate insulating film 140 protects the channel region 130n.

[0122] Figure 7 is a cross-sectional view of a thin-film transistor substrate 300 according to yet another embodiment of the present invention, and Figure 8 is a plan view of a thin-film transistor substrate 400 according to yet another embodiment of the present invention.

[0123] According to one embodiment of the present invention, the active layer 130 of the thin-film transistor substrates 300, 400 can have a multilayer structure. For example, the active layer 130 may include a first active layer 131 and a second active layer 132.

[0124] Specifically, referring to Figure 7, the active layer 130 may include a first active layer 131 and a second active layer 132 on the first active layer 131.

[0125] The first active layer 131 and the second active layer 132 may contain the same semiconductor material, or they may contain different semiconductor materials.

[0126] The first active layer 131 supports the second active layer 132. Therefore, the first active layer 131 is also called the "supporting layer". A structure in which the active layer 130 consists of the first active layer 131 and the second active layer 132 is also called a bi-layer structure.

[0127] According to one embodiment of the present invention, the active layer 130 may further include a third active layer 133 on the second active layer 132.

[0128] The thin-film transistor substrate 400 in Figure 8, compared to the thin-film transistor substrate 300 in Figure 7, further includes a third active layer 133 on the second active layer 132 in the active layer 130. However, this embodiment of the present invention is not limited thereto, and the active layer 130 may further include other semiconductor layers.

[0129] Figure 9 is a schematic diagram illustrating the capacitor of the present invention. Figure 10 is a cross-sectional view of a thin-film transistor substrate according to an embodiment illustrating the capacitor of the present invention. Figure 11 is a cross-sectional view of a thin-film transistor substrate according to a comparative example illustrating the capacitor of the present invention.

[0130] Specifically, Figure 9 is a circuit diagram of one of the pixels P in Figure 13, and more specifically, it is an equivalent circuit diagram of a pixel P in a display device 1000 that includes an organic light-emitting diode (OLED) as the display element 710.

[0131] Referring to Figure 9, a pixel P includes a display element 710 and a pixel driving circuit PDC that drives the display element 710. The pixel driving circuit PDC in Figure 9 includes a first thin-film transistor TR1, which is a switching transistor, and a second thin-film transistor TR2, which is a driving transistor.

[0132] The first thin-film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off by the scan signal SS supplied via the gate line GL.

[0133] The data line DL provides the data voltage Vdata to the pixel drive circuit PDC, and the first thin-film transistor TR1 controls the application of the data voltage Vdata.

[0134] The drive power line PL provides a drive voltage Vdd to the display element 710, and the first thin-film transistor TR1 controls the drive voltage Vdd. The drive voltage Vdd is the pixel drive voltage for driving the organic light-emitting diode (OLED), which is the display element 710.

[0135] When the first thin-film transistor TR1 is turned on by a scan signal SS applied from the gate driver 320 via the gate line GL, a data voltage Vdata supplied via the data line DL is supplied to the gate electrode of the second thin-film transistor TR2, which is connected to the display element 710. The data voltage Vdata charges the first storage capacitor C1 formed between the gate electrode and source electrode of the second thin-film transistor TR2.

[0136] Figure 9 shows a thin-film transistor according to one embodiment of the present invention with a gate voltage V GS The following schematically shows the capacitors that may be generated when a certain voltage is applied.

[0137] As shown in Figures 9 and 10, a gate voltage V is applied to the thin-film transistor. GS When a voltage is applied, a first parasitic capacitor Cp1 is formed between the source region 130a of the active layer 130 and the gate electrode 150, and a second parasitic capacitor Cp2 is formed between the drain region 130b of the active layer 130 and the gate electrode 150.

[0138] Figure 10 shows a configuration in which a first conductive material layer 165 on the source region 130a is superimposed on the gate electrode 150 at a distance from each other to form a first parasitic capacitor Cp1, and a second conductive material layer 175 is separated from the gate electrode 150 to form a second parasitic capacitor Cp2.

[0139] On the other hand, Figure 11 shows a configuration in which the first conductive material layer 165 on the source region 130a forms a first parasitic capacitor Cp1 without overlapping with the gate electrode 150, and the second conductive material layer 175 forms a second parasitic capacitor Cp2 away from the gate electrode 150.

[0140] In the thin-film transistor substrate of Figure 10, compared to the thin-film transistor substrate of Figure 11, the first conductive material layer 165 on the source region 130a is superimposed with the gate electrode 150 to form a first parasitic capacitor Cp1. Therefore, the first parasitic capacitor Cp1 formed on the thin-film transistor substrate of Figure 10 can be larger than the first parasitic capacitor Cp1 formed on the thin-film transistor substrate of Figure 11.

[0141] Furthermore, the thin-film transistor substrate in Figure 10 includes an active hole 135 that protrudes in the direction from the gate electrode 150 towards the drain region 130b on a planar surface and overlaps with the gate electrode 150, compared to the thin-film transistor substrate in Figure 11. Therefore, the second parasitic capacitor Cp2 formed in the thin-film transistor substrate of Figure 10 can be minimized and become smaller than the second parasitic capacitor Cp2 formed in the thin-film transistor substrate of Figure 11.

[0142] According to one embodiment of the present invention, the thin-film transistor substrate in Figure 10 has a first conductive material layer 165 on the source region 130a superimposed on the gate electrode 150 to form a first parasitic capacitor Cp1, and includes an active hole 135 that protrudes in the direction from the gate electrode 150 towards the drain region 130b on a plane and superimposed on the gate electrode 150. As a result, the first parasitic capacitor Cp1 is maximized and the second parasitic capacitor Cp2 is minimized. That is, the first parasitic capacitor Cp1 can be larger than the second parasitic capacitor Cp2. Therefore, the first parasitic capacitor Cp1 can act as a second storage capacitor C2.

[0143] As a result, referring to Figures 10, 12A, and 12B, when a second storage capacitor C2 is further formed on a thin-film transistor substrate according to one embodiment of the present invention, the second storage capacitor C2 is formed in parallel with the first storage capacitor C1, thereby easily securing the area of ​​the capacitor and improving space efficiency.

[0144] On the other hand, referring to Figure 11, in the comparative example, the thin-film transistor substrate does not have the first conductive material layer 165 superimposed on the gate electrode 150, so it is not possible to secure a sufficient first parasitic capacitor Cp1, and therefore it is not possible to easily secure the area of ​​the capacitor.

[0145] Furthermore, the thin-film transistor substrate in the comparative example does not include the active hole 135 in the drain region 130b, so the second parasitic capacitor Cp2 is not minimized. Therefore, an RC delay caused by the second parasitic capacitor Cp2 may occur, making voltage charging difficult. In addition, the second parasitic capacitor Cp2 causes increased heat generation and current consumption of the transistor.

[0146] According to one embodiment of the present invention, the thin-film transistor substrate may include a third storage capacitor. Specifically, the thin-film transistor substrate of Figure 10, compared to the thin-film transistor substrate of Figure 11, includes an active hole 135 that protrudes in the direction from the gate electrode 150 towards the drain region 130b on a planar surface and overlaps with the gate electrode 150. Therefore, it may include a third storage capacitor C3 formed such that the gate electrode 150 and the light-blocking layer 111 are superimposed on each other at a distance from each other.

[0147] According to one embodiment of the present invention, the third storage capacitor C3 is formed in a region where the gate electrode 150 and the light-blocking layer 111 overlap with the active hole 135.

[0148] As a result, referring to Figures 10, 12A, and 12B, when a third storage capacitor C3 is further formed on a thin-film transistor substrate according to one embodiment of the present invention, the third storage capacitor C3 is formed in parallel with the first storage capacitor C1 and the second storage capacitor C2, thereby easily securing the area of ​​the capacitor and improving space efficiency.

[0149] On the other hand, referring to Figure 11, the thin-film transistor substrate in the comparative example does not contain active holes 135, so it is not possible to secure the third storage capacitor C3, and therefore it is not easy to secure the area of ​​the capacitor.

[0150] Figure 12A is a plan view of a thin-film transistor substrate according to yet another embodiment of the present invention. Figure 12B is a cross-sectional view taken along the line I-I' in Figure 12A.

[0151] According to one embodiment of the present invention, the thin-film transistor substrate 500 includes a storage capacitor Cst. Specifically, the storage capacitor Cst may be provided in the superposition region between the light-blocking layer 111 and the thin-film transistor TFT.

[0152] According to one embodiment of the present invention, the storage capacitor Cst includes a first storage capacitor C1, and the first storage capacitor C1 may include a first capacitor electrode CE1 and a second capacitor electrode CE2. The first capacitor electrode CE1 and the second capacitor electrode CE2 can be superimposed on each other to form a first capacitor C11.

[0153] According to one embodiment of the present invention, the first capacitor electrode CE1 can be connected to the light-blocking layer 111. Figure 12B shows a configuration in which the first capacitor electrode CE1 is connected to the light-blocking layer 111.

[0154] According to one embodiment of the present invention, the second capacitor electrode CE2 can be connected to the active layer 130. Specifically, the second capacitor electrode CE2 can be connected to either the source region 130a or the drain region 130b. As shown in Figure 12A, the second capacitor electrode CE2 can be connected to the source region 130a.

[0155] According to yet another embodiment of the present invention, the second capacitor electrode CE2 may include a first layer CE21 and a second layer CE22 on the first layer CE21. The second capacitor electrode CE2 may include a first layer CE21 integrated with either a source region 130a or a drain region 130b, and a second layer CE22 integrated with either a first conductive material layer 165 or a second conductive material layer 175.

[0156] Figure 12A shows a configuration in which the second capacitor electrode CE2 is integrated with the source region 130a in a first layer CE21 and with the first conductive material layer 165 in a second layer CE22.

[0157] According to one embodiment of the present invention, the second capacitor electrode CE2 can be formed by the active layer 130 and the conductive material layers 165 and 175, so no separate process is required for forming the second capacitor electrode CE2, and as a result, space efficiency is improved and the area of ​​the second capacitor electrode CE2 can be increased.

[0158] Referring to Figures 12A and 12B, a thin-film transistor substrate 500 according to one embodiment of the present invention may further include a third capacitor electrode CE3 connected to the gate electrode 150. The third capacitor electrode CE3 can be formed from the same material and in the same process as the gate electrode 150, source electrode 160, and drain electrode 170.

[0159] According to one embodiment of the present invention, the second capacitor electrode CE2 and the third capacitor electrode CE3 can be superimposed on each other to form a second capacitor C12.

[0160] By connecting the gate electrode 150 and the third capacitor electrode CE3 to each other, the first capacitor electrode CE1 and the third capacitor electrode CE3 can be connected to each other, and the same voltage can be applied to the first capacitor electrode CE1 and the third capacitor electrode CE3.

[0161] Referring to Figures 12A and 12B, the second capacitor electrode CE2 is positioned between the first capacitor electrode CE1 and the third capacitor electrode CE3. As a result, the same effect as if two capacitors C11 and C12 were formed with the second capacitor electrode CE2 in between can be achieved.

[0162] Figure 13 is a schematic diagram of a display device 1000 according to yet another embodiment of the present invention.

[0163] A display device 1000 according to yet another embodiment of the present invention may include a display panel 310, a gate driver 320, a data driver 330, and a control unit 340, as shown in Figure 13.

[0164] The display panel 310 includes a gate line GL and a data line DL, and pixels P are positioned in the intersection region of the gate line GL and the data line DL. An image is displayed by driving the pixels P. The gate line GL, data line DL, and pixels P can be arranged on a substrate 110.

[0165] The control unit 340 controls the gate driver 320 and the data driver 330.

[0166] The control unit 340 uses signals supplied from an external system (not shown) to output a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330. The control unit 340 also samples the input video data received from the external system, rearranges it, and supplies the rearranged digital video data RGB to the data driver 330.

[0167] The gate control signal GCS includes the gate start pulse GSP, gate shift clock GSC, gate output enable signal GOE, start signal Vst, and gate clock GCLK. The gate control signal GCS may also include control signals for controlling the shift register.

[0168] The data control signal DCS includes the source start pulse SSP, source shift clock signal SSC, source output enable signal SOE, polarity control signal POL, etc.

[0169] The data driver 330 supplies data voltage to the data line DL of the display panel 310. Specifically, the data driver 330 converts the digital video data RGB input from the control unit 340 into analog data voltage and supplies the data voltage to the data line DL.

[0170] According to one embodiment of the present invention, the gate driver 320 can be mounted on the display panel 310. This structure, in which the gate driver 320 is directly mounted on the display panel 310, is called a Gate In Panel (GIP) structure. Specifically, in a Gate In Panel (GIP) structure, the gate driver 320 can be arranged on a substrate 110.

[0171] A display device 1000 according to one embodiment of the present invention may include the thin-film transistor substrates 100, 200, 300, 400, and 500 described above. According to one embodiment of the present invention, a gate driver 320 may include the thin-film transistor substrates 100, 200, 300, 400, and 500 described above.

[0172] The gate driver 320 may include a shift register 350.

[0173] The shift register 350 sequentially supplies gate pulses to the gate line GL during one frame using the start signal and gate clock transmitted from the control unit 340. Here, one frame refers to the period during which one image is output via the display panel 310. The gate pulse has a turn-on voltage that can turn on the switching element (thin-film transistor) placed on the pixel P.

[0174] Furthermore, the shift register 350 supplies a gate-off signal to the gate line GL during the remaining period of a frame when no gate pulse is supplied, which can turn off the switching element. Hereinafter, the gate pulse and the gate-off signal are collectively referred to as the scan signal SS or Scan.

[0175] The shift register 350 may include the thin-film transistor substrates 100, 200, 300, 400, and 500 mentioned above.

[0176] Figure 14 is a schematic diagram of the shift register 350.

[0177] Referring to Figure 14, the shift register 350 can contain g stages 351ST1~STg.

[0178] The shift register 350 transmits one scan signal SS to a pixel P connected to one gate line GL via one gate line GL. Each of the stages 351 can be connected to one gate line GL. If g gate lines GL are formed on the display panel 310, the shift register 350 can include g stages 351ST1~STg and generate g scan signals SS1~SSg.

[0179] Generally, each stage 351 outputs a gate pulse GP once per frame, and the gate pulse GPs are output sequentially from each stage 351.

[0180] Figure 15 is a circuit diagram of any single pixel P in Figure 13.

[0181] Figure 15 shows the equivalent circuit diagram of a pixel P of a display device 1000, which includes an organic light-emitting diode (OLED) as the display element 710.

[0182] Referring to Figure 15, a pixel P includes a display element 710 and a pixel driving circuit PDC that drives the display element 710. Specifically, a display device 1000 according to one embodiment of the present invention may include a pixel driving circuit PDC on a substrate 110.

[0183] The pixel driving circuit PDC in Figure 15 includes a first thin-film transistor TR1, which is a switching transistor, and a second thin-film transistor TR2, which is a driving transistor. A display device 1000 according to yet another embodiment of the present invention may include at least one of the thin-film transistor substrates 100, 200, 300, 400, and 500.

[0184] The first thin-film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off by the scan signal SS supplied via the gate line GL.

[0185] The data line DL provides the data voltage Vdata to the pixel drive circuit PDC, and the first thin-film transistor TR1 controls the application of the data voltage Vdata.

[0186] The drive power line PL provides a drive voltage Vdd to the display element 710, and the first thin-film transistor TR1 controls the drive voltage Vdd. The drive voltage Vdd is the pixel drive voltage for driving the organic light-emitting diode (OLED), which is the display element 710.

[0187] When the first thin-film transistor TR1 is turned on by a scan signal SS applied from the gate driver 320 via the gate line GL, a data voltage Vdata supplied via the data line DL is supplied to the gate electrode of the second thin-film transistor TR2, which is connected to the display element 710. The data voltage Vdata charges the storage capacitor C1 formed between the gate electrode and source electrode of the second thin-film transistor TR2.

[0188] The data voltage Vdata controls the amount of current supplied to the organic light-emitting diode (OLED), which is the display element 710, via the second thin-film transistor TR2, thereby controlling the gradation of the light output from the display element 710.

[0189] Figure 16 is a plan view of the pixels in Figure 15, and Figure 17 is a cross-sectional view taken along the line III-III' in Figure 16.

[0190] Referring to Figures 15 and 16, the first thin-film transistor TR1 and the second thin-film transistor TR2 are arranged on the substrate 110. The first thin-film transistor TR1 and the second thin-film transistor TR2 include conductive material layers 165 and 175.

[0191] The substrate 110 can be made of glass or plastic. A flexible plastic, such as polyimide (PI), can be used as the substrate 110.

[0192] A light-blocking layer 111 is placed on the substrate 110. The light-blocking layer 111 can have light-blocking properties. The light-blocking layer 111 can block light incident from the outside and protect the active layers A1 and A2.

[0193] A buffer layer 120 is placed on the light-blocking layer 111. The buffer layer 120 is made of an insulating material and protects the active layers A1 and A2 from moisture and oxygen that flow in from the outside.

[0194] The first active layer A1 of the first thin-film transistor TR1 and the second active layer A2 of the second thin-film transistor TR2 are placed on the buffer layer 120.

[0195] The first active layer A1 and the second active layer A2 may include, for example, an oxide semiconductor material. The first active layer A1 and the second active layer A2 may consist of oxide semiconductor layers made of an oxide semiconductor material.

[0196] In the first thin-film transistor TR1, the first active layer A1 may include a channel region, a source region, and a drain region. The channel region of the first active layer A1 is superimposed on the gate electrode G1. According to another embodiment of the present invention, the source region may be called the source electrode S1, and the drain region may be called the drain electrode D1.

[0197] In the second thin-film transistor TR2, the second active layer A2 may include a channel region, a source region, and a drain region. The channel region of the second active layer A2 is superimposed on the gate electrode G2. According to another embodiment of the present invention, the source region can be called the source electrode S2, and the drain region can be called the drain electrode D2.

[0198] In the first thin-film transistor TR1, the first conductive material layer 165 is located on the source region of the first active layer A1 and superimposed on the gate electrode G1. In the second thin-film transistor TR2, the first conductive material layer 165 is located on the source region of the second active layer A2 and superimposed on the gate electrode G2.

[0199] Referring to Figures 16 and 17, a portion of the light-blocking layer 111 can become the first capacitor electrode CE1 of the first capacitor C11.

[0200] Furthermore, a portion of the second active layer A2 can become the second capacitor electrode CE2 of the first capacitor C11, or it can become the second capacitor electrode CE2 of the second capacitor C12.

[0201] A gate insulating film 140 is placed on the first active layer A1 and the second active layer A2. The gate insulating film 140 can cover the entire upper surface of the first active layer A1 and the second active layer A2, or it can cover only a portion of the first active layer A1 and the second active layer A2.

[0202] The gate electrode G1 of the first thin-film transistor TR1 and the gate electrode G2 of the second thin-film transistor TR2 are positioned on the gate insulating film 140.

[0203] The gate electrode G1 of the first thin-film transistor TR1 overlaps, at least partially, with the first active layer A1 of the first thin-film transistor TR1. The gate electrode G2 of the second thin-film transistor TR2 overlaps, at least partially, with the second active layer A2 of the second thin-film transistor TR2.

[0204] The source electrode S1 and drain electrode D1 of the first thin-film transistor TR1 are placed on the gate insulating film 140. The source electrode S2 and drain electrode D2 of the second thin-film transistor TR2 are also placed on the gate insulating film 140.

[0205] The source electrode S1 and drain electrode D1 of the first thin-film transistor TR1 are located on the same layer as the source electrode S2 and drain electrode D2 of the second thin-film transistor TR2. Specifically, the gate electrode G1, source electrode S1 and drain electrode D1 of the first thin-film transistor TR1, and the gate electrode G2, source electrode S2 and drain electrode D2 of the second thin-film transistor TR2 are located on the same layer.

[0206] An interlayer insulating film 180 is placed on gate electrodes G1 and G2, source electrodes S1 and S2, and drain electrodes D1 and D2.

[0207] Data lines DL and drive power lines PL are arranged on the interlayer insulating film 180.

[0208] The data line DL contacts the first source electrode S1 formed in the first active layer A1 via the first contact hole H1. According to yet another embodiment of the present invention, the portion of the data line DL superimposed on the first active layer A1 can also be referred to as the first source electrode S1.

[0209] The drive power line PL contacts the second drain electrode D2 formed in the second active layer A2 via the eleventh contact hole H11. According to yet another embodiment of the present invention, the portion of the drive power line PL superimposed on the second active layer A2 can also be referred to as the second drain electrode D2.

[0210] Referring to Figures 16 and 17, a portion of the gate electrode G2 of the second thin-film transistor TR2 can become the third capacitor electrode CE3 of the second capacitor C12.

[0211] Referring to Figures 16 and 17, the first capacitor electrode CE1 is superimposed with the second capacitor electrode CE2 to form the first capacitor C11. The second capacitor electrode CE2 is superimposed with the third capacitor electrode CE3 to form the second capacitor C12.

[0212] Referring to Figures 16 and 17, the first bridge BR1 is positioned on the interlayer insulating film 180. The first bridge BR1 is connected to the first drain electrode D1 via the fourth contact hole H4 and to the third capacitor electrode CE3 of the second capacitor C12 via the fifth contact hole.

[0213] Referring to Figures 16 and 17, the third capacitor electrode CE3 is connected to the light-blocking layer 111 via the sixth contact hole H6.

[0214] A planarization layer 190 is placed on the data line DL, the first bridge BR1, and the drive power line PL. The planarization layer 190 planarizes the top of the first thin-film transistor TR1 and the second thin-film transistor TR2, protecting the first thin-film transistor TR1 and the second thin-film transistor TR2.

[0215] The first electrode 711 of the display element 710 is placed on the planarization layer 190. The first electrode 711 of the display element 710 contacts the second source electrode S2 of the second thin-film transistor TR2 via a ninth contact hole H9 formed in the planarization layer 190 and an eighth contact hole H8 formed in the interlayer insulating film 180. As a result, the first electrode 711 can be connected to the second source electrode S2 of the second thin-film transistor TR2. It is also connected to the second active layer A2 via a seventh contact hole H7 formed in the gate insulating film 140.

[0216] A bank layer 750 is placed on the edge of the first electrode 711. The bank layer 750 defines the light-emitting region of the display element 710.

[0217] An organic light-emitting layer 712 is placed on the first electrode 711, and a second electrode 713 is placed on the organic light-emitting layer 712. Thus, a display element 710 is completed. The display element 710 shown in Figure 17 is an organic light-emitting diode (OLED). Therefore, the display device 1000 according to one embodiment of the present invention is an organic light-emitting display device.

[0218] Figure 18 is a circuit diagram of any one pixel of the display device 1100 according to another embodiment of the present invention.

[0219] Figure 18 is an equivalent circuit diagram of a pixel P in an organic light-emitting display device.

[0220] The pixels P of the display device 1100 shown in Figure 18 include an organic light-emitting diode (OLED), which is a display element 710, and a pixel driving circuit PDC that drives the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0221] Pixel P is equipped with signal lines DL, GL, PL, RL, and SCL, which supply signals to the pixel drive circuit PDC.

[0222] The data voltage Vdata is supplied to the data line DL, the scan signal SS is supplied to the gate line GL, the drive voltage Vdd for driving pixels is supplied to the drive power line PL, the reference voltage Vref is supplied to the reference line RL, and the sensing control signal SCS is supplied to the sensing control line SCL.

[0223] The pixel driving circuit PDC includes, for example, a first thin-film transistor TR1 (switching transistor) connected to the gate line GL and the data line DL, a second thin-film transistor TR2 (driving transistor) that controls the magnitude of the current output to the display element 710 by the data voltage Vdata transmitted through the first thin-film transistor TR1, and a third thin-film transistor TR3 (sensing transistor) for sensing the characteristics of the second thin-film transistor TR2.

[0224] The first thin-film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL, thereby transmitting the data voltage Vdata supplied to the data line DL to the gate electrode of the second thin-film transistor TR2.

[0225] The third thin-film transistor TR3 is connected to the first node n1 and the reference line RL between the second thin-film transistor TR2 and the display element 710, and is turned on or off by the sensing control signal SCS, sensing the characteristics of the second thin-film transistor TR2, which is the driving transistor, during the sensing period.

[0226] The second node n2, which is connected to the gate electrode of the second thin-film transistor TR2, is connected to the first thin-film transistor TR1. A storage capacitor Cst is formed between the second node n2 and the first node n1.

[0227] When the first thin-film transistor TR1 is turned on, the data voltage Vdata supplied via the data line DL is supplied to the gate electrode of the second thin-film transistor TR2. The data voltage Vdata charges the storage capacitor Cst formed between the gate electrode and source electrode of the second thin-film transistor TR2.

[0228] When the second thin-film transistor TR2 is turned on, a current is supplied to the display element 710 via the second thin-film transistor TR2 by the drive voltage Vdd that drives the pixels, causing light to be output from the display element 710.

[0229] A display device 1100 according to yet another embodiment of the present invention may include at least one of the thin-film transistor substrates 100, 200, 300, 400, and 500.

[0230] Figure 19 is a circuit diagram of any one pixel P of a display device 1200 according to yet another embodiment of the present invention.

[0231] The pixels P of the display device 1200 shown in Figure 19 include an organic light-emitting diode (OLED), which is a display element 710, and a pixel driving circuit PDC that drives the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0232] The pixel drive circuit PDC includes thin-film transistors TR1, TR2, TR3, and TR4.

[0233] Pixel P is equipped with signal lines DL, EL, GL, PL, SCL, and RL, which supply drive signals to the pixel drive circuit PDC.

[0234] The pixel P in Figure 19 further includes a light emission control line EL, compared to the pixel P in Figure 18. A light emission control signal EM is supplied to the light emission control line EL. Furthermore, the pixel driving circuit PDC in Figure 19 further includes a fourth thin-film transistor TR4, which is a light emission control transistor for controlling the light emission timing of the second thin-film transistor TR2, compared to the pixel driving circuit PDC in Figure 18.

[0235] The first thin-film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL, thereby transmitting the data voltage Vdata supplied to the data line DL to the gate electrode of the second thin-film transistor TR2.

[0236] A storage capacitor Cst is located between the gate electrode of the second thin-film transistor TR2 and the display element 710.

[0237] The third thin-film transistor TR3 is connected to the reference line RL and is turned on or off by the sensing control signal SCS, sensing the characteristics of the third thin-film transistor TR3, which is the driving transistor, during the sensing period.

[0238] The fourth thin-film transistor TR4 either transmits the drive voltage Vdd to the second thin-film transistor TR2 or cuts off the drive voltage Vdd based on the light emission control signal EM. When the fourth thin-film transistor TR4 is turned on, current is supplied to the second thin-film transistor TR2, causing light to be output from the display element 710.

[0239] Pixel driving circuits PDCs according to yet another embodiment of the present invention can be formed into a variety of structures other than those described above. For example, a pixel driving circuit PDC may include five or more thin-film transistors.

[0240] The present invention described above is not limited by the embodiments and accompanying drawings, and it will be apparent to those with ordinary skill in the art to which the present invention pertains that various substitutions, modifications, and alterations are possible without departing from the technical matters of the present invention. Accordingly, the scope of the present invention is determined by the claims described below, and all forms of modification or alteration derived from the meaning, scope, and equivalent concepts of the claims should be interpreted as being included within the scope of the present invention. [Explanation of Symbols]

[0241] 110 circuit boards 120 buffer layers 130 active users 130n channel region 130a Source area 130b Drain area 131 First Active Layer 132 Second Active Layer 133 Third Active Layer 111 Light-blocking layer 135 Active Holes 140 Gate Insulator 150 Guard signals 160 source electrodes 170 Drain electrode 180 Interlayer insulating film 165 First conductive layer 175 Second conductive layer

Claims

1. A substrate and a thin-film transistor on the substrate, The thin-film transistor is Active users and The conductive material layer on the active layer, A gate electrode separated from the active layer and partially overlapping with the active layer, Source electrode and, Includes a drain electrode, The aforementioned active layer is In a plan view, the channel region overlaps with a portion of the gate electrode, In the plan view, a source region connected to one side of the channel region, The plan view includes a drain region connected to the other side of the channel region, The conductive material layer is A first conductive material layer on the source region that is in contact with the source electrode, The drain electrode is in contact with a second conductive material layer on the drain region, The first conductive material layer overlaps with at least a portion of the channel region, The active layer includes an active hole within the region defined by the active layer in which the active layer does not exist. The active hole extends from the channel region to the drain region in the plan view, The active holes are separated from the first conductive material layer in the plan view, and the substrate is a thin-film transistor substrate.

2. The thin-film transistor substrate according to claim 1, wherein a portion of the active holes overlaps with the gate electrode in the plan view.

3. The thin-film transistor substrate according to claim 1, wherein the second conductive material layer is separated from the channel region in the plan view.

4. The source region and the drain region are respectively arranged between the base substrate and the first conductive material layer, and between the base substrate and the second conductive material layer. The thin-film transistor substrate according to claim 1, wherein each of the first conductive material layer and the second conductive material layer is in contact with the active layer.

5. The thin-film transistor substrate according to claim 1, wherein the gate electrode, the source electrode, and the drain electrode are arranged on the same layer.

6. The aforementioned active hole has a plurality of sub-active holes, The plurality of subactive holes are spaced apart from each other. The thin-film transistor substrate according to claim 1, wherein each of the plurality of subactive holes has an elongated shape extending from the channel region to the drain region.

7. The thin-film transistor substrate according to claim 1, wherein the conductive material layer comprises at least one selected from titanium (Ti), molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), chromium (Cr), tantalum (Ta), neodymium (Nd), calcium (Ca), barium (Ba), and transparent conductive oxide (TCO).

8. The shortest distance from the drain region to the first conductive material layer is the first length. In the longitudinal direction of the channel of the active layer, the shortest length over which the first conductive material layer overlaps with the gate electrode in the plan view is the second length. The thin-film transistor substrate according to claim 1, wherein the first length is longer than the second length.

9. A portion of the active hole is superimposed on the gate electrode, In the longitudinal direction of the channel of the active layer, the shortest length over which the active hole overlaps with the gate electrode is the third length. In the longitudinal direction of the channel of the active layer, the shortest distance from the active hole to the first conductive material layer is the fourth length. The thin-film transistor substrate according to claim 1, wherein the fourth length is longer than the third length.

10. The substrate includes a light-blocking layer, The thin-film transistor substrate according to claim 1, further comprising a storage capacitor in the superimposed region between the light-blocking layer and the thin-film transistor.

11. The storage capacitor includes a first storage capacitor, The first storage capacitor is A first capacitor electrode connected to the light-blocking layer, The active layer includes a second capacitor electrode connected to the active layer, The thin-film transistor substrate according to claim 10, wherein the first capacitor electrode and the second capacitor electrode are separated from each other and superimposed on each other to form the first capacitor.

12. The first storage capacitor includes a third capacitor electrode connected to the gate electrode, The thin-film transistor substrate according to claim 11, wherein the second capacitor electrode and the third capacitor electrode are separated from each other and superimposed on each other to form a second capacitor.

13. The second capacitor electrode is A first layer which is integrated with either the source region or the drain region, The thin-film transistor substrate according to claim 11, comprising a second layer which is integrated with either the first conductive material layer or the second conductive material layer.

14. The second capacitor electrode is located between the first capacitor electrode and the third capacitor electrode. The thin-film transistor substrate according to claim 12, wherein the third capacitor electrode is connected to the first capacitor electrode.

15. The thin-film transistor substrate according to claim 10, wherein the storage capacitor includes a second storage capacitor formed by separating and superimposing the gate electrode and the first conductive material layer.

16. The thin-film transistor substrate according to claim 10, wherein the storage capacitor includes a third storage capacitor formed by the gate electrode and the light-blocking layer being separated from and superimposed on each other.

17. The thin-film transistor substrate according to claim 16, wherein the third storage capacitor is located in a region that overlaps with the active hole.

18. The active layer comprises an oxide semiconductor material. The thin-film transistor substrate according to claim 1, wherein the oxide semiconductor material comprises at least one of the following oxide semiconductor materials: IZO (InZnO) system, IGO (InGaO) system, ITO (InSnO) system, IGZO (InGaZnO) system, IGZTO (InGaZnSnO) system, GZTO (GaZnSnO) system, GZO (GaZnO) system, ITZO (InSnZnO) system, and FIZO (FeInZnO) system.

19. A display device comprising a thin-film transistor substrate according to any one of claims 1 to 18.

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