Semiconductor equipment

Abstract

The present invention comprises: a step for forming, on a semiconductor substrate (12), a first insulating film (20) having a first opening (20a); a step for forming, on the first insulating film (20), a first resist (24) having a second opening (24a) larger than the first opening (20a) above the first opening (20a); a step for forming a gate electrode (18) in the first opening (20a), in the second opening (24a), above the second opening (24a), and on the first resist (24); and a step for forming, on the gate electrode (18), a second resist (26) that covers at least vertically above the second opening (24a) and that has a wider width than the second opening (24a); and a step for etching the gate electrode (18) and the first resist (24) partway by using the second resist (26) as a mask.

Description

[[Technical Field]]

[0001] The present disclosure relates to a semiconductor device, and particularly to a semiconductor device with improved electrostatic discharge (ESD) breakdown resistance. [[Background Art]]

[0002] Semiconductor devices may be damaged by ESD. For integrated circuits, a protection circuit can be incorporated to increase ESD breakdown resistance; however, in the case of discrete devices such as semiconductor laser elements, it is unavoidable to rely on the ESD breakdown resistance of the element itself.

[0003] Patent Document 1 discloses a semiconductor laser element in which, separately from a resonator section, a p-type / i-type / p-type structure is formed for a p-type substrate, and an n-type / i-type / n-type structure is formed for an n-type substrate, and ESD breakdown resistance is improved using these structures. [[Prior Art Literature]] [[Patent Literature]]

[0004] [[Patent Document 1]] Japanese Unexamined Patent Application Publication No. 2010-287604 [[Summary of the Invention]] [[Problem to be Solved by the Invention]]

[0005] However, in the above-described semiconductor laser element, it is necessary to separately form a semiconductor layer to produce the aforementioned structure, which inevitably leads to an increase in man-hours.

[0006] The present disclosure has been made to solve the above problem, and an object thereof is to obtain a semiconductor device with improved ESD breakdown resistance without increasing man-hours. [[Means for Solving the Problem]]

[0007] The semiconductor device according to this disclosure comprises a semiconductor substrate of a first conductivity type having a back electrode formed on its back surface, a ridge portion formed on the surface of the semiconductor substrate and having a lower cladding layer of the first conductivity type, an MQW portion formed on the lower cladding layer, an upper cladding layer of the second conductivity type formed on the MQW portion, block layers embedded on the semiconductor substrate on both sides of the ridge portion, and a contact layer formed on the upper cladding layer further formed on the ridge portion and the block layer. The semiconductor layer, consisting of the semiconductor substrate, block layer and contact layer, is stacked with at least layers of the first conductivity type, second conductivity type, first conductivity type and second conductivity type from the bottom, and a composite layer consisting of layers from the block layer to the contact layer has two first grooves formed thereon, and the contact layer on the ridge portion and the contact layer sandwiched between the two first grooves are connected by a first electrode.

[0008] Another semiconductor device according to the present disclosure comprises a semiconductor substrate of a first conductivity type having a back electrode formed on its back surface, a ridge portion formed on the surface of the semiconductor substrate and having a lower cladding layer of the first conductivity type, an MQW portion formed on the lower cladding layer, an upper cladding layer of the second conductivity type formed on the MQW portion, block layers embedded on the semiconductor substrate on both sides of the ridge portion, and a contact layer formed on the upper cladding layer further formed on the ridge portion and the block layer, wherein the semiconductor layer consisting of the semiconductor substrate, block layer and contact layer is stacked with at least layers of the first conductivity type, second conductivity type, first conductivity type and second conductivity type from the bottom, a composite layer consisting of layers from the block layer to the contact layer has two first grooves formed in it, and a composite layer has two second grooves formed in it, the contact layer on the ridge portion and a first region of the contact layer sandwiched between the second two grooves are connected by a first electrode, and the second region of the contact layer sandwiched between the second two grooves and the contact layer sandwiched between the first two grooves are connected by a second electrode. [Effects of the Invention]

[0009] According to this disclosure, a semiconductor device with improved ESD resistance can be obtained without increasing the number of man-hours. [Brief explanation of the drawing]

[0010] [Figure 1] This is a perspective view of a semiconductor device according to Embodiment 1. [Figure 2] This is a cross-sectional view of a semiconductor device according to Embodiment 1. [Figure 3] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1. [Figure 4] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1. [Figure 5] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1. [Figure 6] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1. [Figure 7] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1. [Figure 8] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1. [Figure 9] This is a perspective view of a semiconductor device according to Embodiment 2. [Figure 10] This is a cross-sectional view of a semiconductor device according to Embodiment 2. [Figure 11] This is a cross-sectional view of a semiconductor device according to Embodiment 3. [Figure 12] This is a cross-sectional view of a semiconductor device according to Embodiment 4. [Modes for carrying out the invention]

[0011] Embodiment 1. The semiconductor device 10 according to Embodiment 1 is a distributed feedback (DFB) semiconductor laser element. A perspective view of the semiconductor device 10 is shown in Figure 1. A cross-sectional view of point AA in Figure 1 is shown in Figure 2. Note that the dimensions and scale of each part in the drawings, including these, may differ from drawing to drawing.

[0012] The semiconductor device 10 comprises a semiconductor substrate 12. The semiconductor substrate 12 is made of p-type InP. A back electrode 14 is formed on the back surface of the semiconductor substrate 12.

[0013] A ridge portion 22 is formed on the surface of the semiconductor substrate 12. The ridge portion 22 includes a lower clad layer 16, an MQW portion 18 formed on the lower clad layer 16, and an upper clad layer 20 formed on the MQW portion 18. The lower clad layer 16 is made of p-type InP. The MQW portion 18 is made of InP and includes Multiple Quantum Well (MQW). The upper clad layer 20 is made of n-type InP. The ridge portion 22 is a resonator in which laser light resonates.

[0014] Block layers 36 are embedded on both sides of the ridge portion 22. The block layers 36 are embedded on the semiconductor substrate 12 on both sides of the ridge portion 22, and a first semiconductor layer 28 of a first conductivity type, a second semiconductor layer 30 of a second conductivity type, an i-type i-type semiconductor layer 32, and a third semiconductor layer 34 of the first conductivity type are stacked from the bottom up. Here, the i-type semiconductor layer refers to a semiconductor layer into which no carriers are injected. All of these layers are made of InP. The block layer 36 is a current confinement layer for allowing current to flow only through the ridge portion 22. Note that the i-type semiconductor layer 32 may be omitted. Further, an i-type semiconductor layer may be inserted between any layers constituting the block layer 36. The inserted layer may be an Fe-doped i-type semiconductor layer.

[0015] A contact layer 38 in which n-type InP and n-type InGaAs are stacked is formed on the upper clad layer 20 further formed on the ridge portion 22 and the block layers 36.

[0016] Two grooves 26 are formed in the block layers 36 on the left and right of the ridge portion 22 so as to sandwich the ridge portion 22. By these grooves 26, the ridge portion 22 is electrically isolated from other portions.

[0017] The composite layer 40, consisting of layers from the block layer 36 to the contact layer 38, has two first grooves 42 formed therein. The semiconductor layer from the contact layer 38 to the semiconductor substrate 12 in the region sandwiched between the two first grooves 42 is a voltage clamping section 46 that clamps the voltage. This semiconductor layer only needs to consist of layers of at least p-type, n-type, p-type, and n-type stacked from the bottom. In this embodiment, the first semiconductor layer 28 is p-type, the second semiconductor layer 30 is n-type, the third semiconductor layer 34 is p-type, and the contact layer 38 is n-type. Note that one of the two grooves 26 and one of the two first grooves 42 may be the same groove.

[0018] An insulating film 48 is formed on the contact layer 38 and the groove. The insulating film 48 has openings on the ridge portion 22 and the voltage clamp portion 46.

[0019] The contact layer 38 sandwiched between the first two grooves 42 and the contact layer 38 on the ridge portion 22 are connected by the first electrode 50. The lower part of the voltage clamp portion 46 sandwiched between the first two grooves 42 and the lower part of the ridge portion 22 are electrically connected via the back electrode 14. Therefore, the voltage clamp portion 46 and the ridge portion 22 are electrically connected in parallel. The first electrode 50 is connected to the pad electrode 52.

[0020] Since the voltage clamp section 46 and the ridge section 22 are electrically connected in parallel, even if ESD is applied to the ridge section 22, any excess charge above a certain level will mainly flow through the voltage clamp section 46, which has a voltage clamping function.

[0021] The manufacturing method for the semiconductor device 10 will now be explained. First, as shown in Figure 3, a lower cladding layer 16, an MQW portion 18, and an upper cladding layer 20 are sequentially formed on a semiconductor substrate 12 on which a back surface electrode 14 is formed on the back surface.

[0022] Next, as shown in Figure 4, the upper cladding layer 20 is etched from the lower cladding layer 16, leaving the ridge portion 22 intact.

[0023] Next, as shown in Figure 5, block layers 36 are embedded on both sides of the ridge portion 22.

[0024] Next, as shown in Figure 6, the upper cladding layer 20 and the contact layer 38 are formed on the ridge portion 22 and the block layer 36.

[0025] Next, as shown in Figure 7, grooves are formed on both sides of the ridge portion 22 and the voltage clamp portion 46 by etching. The first two grooves 42 are formed in this step.

[0026] Next, as shown in Figure 8, an insulating film 48 is formed on the contact layer 38 and the groove.

[0027] Next, the first electrode 50 is formed. After this step is completed, the semiconductor device 10 shown in Figure 1 is formed.

[0028] Based on the above, according to this embodiment, since the voltage clamp portion and the ridge portion 22 are electrically connected in parallel, the ridge portion 22 can be protected from ESD, and the ESD breakdown resistance of the semiconductor device can be improved.

[0029] Furthermore, the voltage clamping section is formed using a contact layer, a block layer as a current-constricting layer, and a semiconductor substrate, and the first two grooves are formed simultaneously with the grooves on the left and right sides of the ridge section. Therefore, there is no increase in the number of steps required.

[0030] Embodiment 2. Unlike Embodiment 1, the semiconductor device 210 according to Embodiment 2 has a resistor 262 connected between the ridge portion 222 and the voltage clamp portion 46. Figure 9 shows a perspective view of the semiconductor device 210. Figure 10 shows a cross-sectional view of BB in Figure 9.

[0031] The composite layer 40 has two second grooves 244 formed therein. The composite layer 40 sandwiched between these two second grooves is the resistive portion 262. The end of the resistive portion 262 is the first region 254 and the second region 256 of the contact layer 38 sandwiched between the two second grooves 244. Note that one of the two first grooves 42 and one of the two second grooves 244 may be the same groove.

[0032] The contact layer 38 on the ridge portion 222 and the first region 254 are connected by the first electrode 50, and the second region 256 and the contact layer 38 sandwiched between the first two grooves 42 are connected by the second electrode 258. In other words, the resistor 262 is connected between the ridge portion 222 and the voltage clamp portion 46.

[0033] Based on the above, according to this embodiment, since the resistor is connected between the ridge and the voltage clamp, the ESD breakdown resistance of the semiconductor device can be further improved.

[0034] Furthermore, the resistive section is formed using a block layer that acts as a current-constricting layer, and the two second grooves are formed simultaneously with the grooves on the left and right sides of the ridge section. Therefore, there is no increase in the number of steps required.

[0035] Embodiment 3. Unlike Embodiment 1, the semiconductor device 310 according to Embodiment 3 has the i-type semiconductor layer constituting the block layer 336 removed and the second semiconductor layer replaced with an Fe-doped i-type semiconductor layer 360. A cross-sectional view of the semiconductor device 310 is shown in Figure 11.

[0036] Even with this structure, the voltage clamping section 346 still has the effect of clamping the voltage, and has the same effect as in Embodiment 1. Furthermore, doping the i-type semiconductor layer 360 with Fe enhances the current narrowing effect.

[0037] Embodiment 4. Unlike Embodiment 1, the semiconductor device according to Embodiment 4 has an electro-absorption (EA) modulator unit (EA unit 464) connected to the DFB unit. The basic configuration of the EA unit 464 is the same as that of the DFB unit, and the laser light generated in the DFB unit is modulated by the voltage applied to the EA electrode 466. Specifically, the laser light generated in the ridge unit of the DFB unit is modulated by the ridge unit 422 of the EA unit 464.

[0038] A cross-sectional view of the EA section 464 is shown in Figure 12. Unlike the DFB section, the sides of the ridge section 422 in the EA section 464 are covered with an insulating film 448.

[0039] In the EA section 464, the voltage clamp section 446 also has the function of clamping the voltage, and has the same effect as in Embodiment 1.

[0040] For example, in Embodiment 1, the semiconductor substrate was p-type and the contact layer was n-type, but the semiconductor substrate could be n-type and the contact layer p-type. The same applies to other semiconductor layers. In order to demonstrate that pn reversal is possible, for example, the semiconductor substrate can be described as a first conductivity type and the contact layer as a second conductivity type. Either the first conductivity type is p-type and the second conductivity type is n-type, or the first conductivity type is n-type and the second conductivity type is p-type. The fact that pn reversal is possible and that the types can be described as first conductivity type and second conductivity type applies to all embodiments.

[0041] Furthermore, the features of each embodiment may be used in combination. [Explanation of Symbols]

[0042] 10,210,310 Semiconductor device, 12 Semiconductor substrate, 14 Backside electrode, 16,416 Lower cladding layer, 18,418 MQW section, 20,420 Upper cladding layer, 22,222,422 Ridge section, 26,426 Groove, 28 First semiconductor layer, 30 Second semiconductor layer, 32,360 i-type semiconductor layer, 34 Third semiconductor layer, 36,336 Block layer, 38 Contact layer, 40 Composite layer, 42 First two grooves, 244 Second two grooves, 46,346,446 Voltage clamp section, 48,448 Insulating film, 50 First electrode, 52,452 Pad electrode, 254 First region, 256 Second region, 258 Second electrode, 262 Resistor section, 464 EA section, 466 EA electrode

Claims

1. A first-conductivity semiconductor substrate having a back electrode formed on its back surface, A ridge portion formed on the surface of the semiconductor substrate, comprising a lower cladding layer of the first conductivity type, an MQW portion formed on the lower cladding layer, and an upper cladding layer of the second conductivity type formed on the MQW portion, Block layers embedded on the semiconductor substrate on both sides of the ridge portion, A contact layer formed on the upper cladding layer further formed on the ridge portion and the block layer, Equipped with, The semiconductor layer, comprising the semiconductor substrate, the block layer, and the contact layer, is constructed by stacking at least the first conductivity type, the second conductivity type, the first conductivity type, and the second conductivity type layers from the bottom up. The composite layer, consisting of the layers from the block layer to the contact layer, has two first grooves formed in it. The contact layer on the ridge portion and the contact layer sandwiched between the two first grooves are connected by the first electrode. Semiconductor equipment.

2. A first-conductivity semiconductor substrate having a back electrode formed on its back surface, A ridge portion formed on the surface of the semiconductor substrate, comprising a lower cladding layer of the first conductivity type, an MQW portion formed on the lower cladding layer, and an upper cladding layer of the second conductivity type formed on the MQW portion, Block layers embedded on the semiconductor substrate on both sides of the ridge portion, A contact layer formed on the upper cladding layer further formed on the ridge portion and the block layer, Equipped with, The semiconductor layer, comprising the semiconductor substrate, the block layer, and the contact layer, is constructed by stacking at least the first conductivity type, the second conductivity type, the first conductivity type, and the second conductivity type layers from the bottom up. The composite layer, consisting of the layers from the block layer to the contact layer, has two first grooves formed in it. The composite layer has two second grooves formed in it. The contact layer on the ridge portion and the first region of the contact layer sandwiched between the two second grooves are connected by the first electrode. The second region of the contact layer sandwiched between the two second grooves and the contact layer sandwiched between the two first grooves are connected by a second electrode. Semiconductor equipment.

3. The semiconductor device according to claim 1 or 2, wherein the first conductivity type or second conductivity type layer constituting the block layer is replaced with an Fe-doped i-type semiconductor layer.

4. The semiconductor device according to claim 1 or 2, wherein an i-type semiconductor layer is inserted in the block layer.

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