Thin-film transistors and display devices containing them

Abstract

To provide a thin film transistor in which the conduction penetration depth can be controlled.SOLUTION: A thin film transistor (100) comprises an active layer (130) and a gate electrode (150) spaced apart from the active layer to at least partially overlap the active layer. The active layer includes a channel area (130a) that is overlapped by the gate electrode in the plan view, a source area (130b) connected to one side of the channel area without being overlapped by the gate electrode in the plan view and a drain area (130c) connected to the other side of the channel area without being overlapped by the gate electrode in the plan view. The source area and the drain area are spaced apart from each other with the channel area interposed therebetween. The active layer includes a first source conductive control area (135a) and a first drain conductive control area (136a), which are spaced apart from each other. At least a portion of the first source conductive control area overlaps at least a portion of the gate electrode, and at least a portion of the first drain conductive control area overlaps at least a portion of the gate electrode.SELECTED DRAWING: Figure 1

Description

TECHNICAL FIELD

[0001] The present specification relates to a transistor and a display device including the transistor. BACKGROUND ART

[0002] Transistors are widely used as switching devices and driving devices in the field of electronic equipment. In particular, thin film transistors can be manufactured on glass substrates or plastic substrates, and thus are widely used as switching elements for display devices such as liquid crystal display devices and organic light emitting devices.

[0003] Thin film transistors are classified based on the material constituting the active layer into amorphous silicon thin film transistors in which amorphous silicon is used as the active layer, polycrystalline silicon thin film transistors in which polycrystalline silicon is used as the active layer, and oxide semiconductor thin film transistors in which an oxide semiconductor is used as the active layer.

[0004] Amorphous silicon thin film transistors (a-Si TFT) can form an active layer by depositing amorphous silicon within a short time, and thus have the advantages of short manufacturing process time and low production cost. In contrast, they have low mobility, poor current driving capability, and experience threshold voltage shifts, so they have the disadvantage that their use is limited in applications such as active matrix organic light emitting diodes (AMOLED).

[0005] Polycrystalline silicon thin-film transistors (poly-Si TFTs) are manufactured by depositing amorphous silicon and then crystallizing it. Because the manufacturing process requires a crystallization step, the number of steps increases, raising manufacturing costs. Furthermore, the crystallization process requires high temperatures, making polycrystalline silicon thin-film transistors difficult to apply to large-area devices. Additionally, due to their polycrystalline properties, ensuring uniformity in polycrystalline silicon thin-film transistors is challenging.

[0006] Oxide semiconductor thin-film transistors (TFTs) allow for the deposition of the oxide that constitutes the active layer at relatively low temperatures, possess high mobility, and exhibit large resistance changes depending on the oxygen content, making it easy to obtain desired physical properties. Furthermore, due to the properties of oxides, oxide semiconductors are transparent, which is advantageous for realizing transparent displays.

[0007] In the case of oxide semiconductor thin-film transistors, selective conduction of the oxide semiconductor layer is sometimes required, and in this case, control over the conduction region and the conduction penetration depth formed in the oxide semiconductor layer is extremely important. Therefore, techniques for controlling the conduction region and conduction penetration depth are being studied. [Overview of the project] [Problems that the invention aims to solve]

[0008] One embodiment of the present invention provides a thin-film transistor that can control the conduction penetration depth even when the active layer includes a pattern and the channel region has a large width.

[0009] One embodiment of the present invention provides a thin-film transistor that prevents or suppresses a shift in the threshold voltage (Vth) toward the negative direction, even when the active layer includes a pattern and the channel region has a large width.

[0010] One embodiment of the present invention provides a thin-film transistor in which the active layer includes a pattern, thereby improving reliability.

[0011] Another embodiment of the present invention provides a display device including the transistor described above. [Means for solving the problem]

[0012] One embodiment of the present invention for achieving the aforementioned technical problems provides a thin-film transistor comprising an active layer and a gate electrode separated from the active layer and at least partially superimposed on the active layer, wherein the active layer comprises, in a plan view, a channel region superimposed on the gate electrode, a source region not superimposed on the gate electrode in a plan view and connected to one side of the channel region, and a drain region not superimposed on the gate electrode in a plan view and connected to the other side of the channel region, wherein the source region and the drain region are separated from each other with the channel region in between, and the active layer comprises a first source conductor adjustment region and a first drain conductor adjustment region separated from each other, wherein at least a portion of the first source conductor adjustment region superimposed on at least a portion of the gate electrode, and at least a portion of the first drain conductor adjustment region superimposed on at least a portion of the gate electrode. [Effects of the Invention]

[0013] A thin-film transistor according to one embodiment of the present invention can control the conduction penetration depth even when the active layer includes a pattern and the channel region has a large width.

[0014] A thin-film transistor according to one embodiment of the present invention can control the shift of the threshold voltage (Vth) in the negative direction, even if the active layer includes a pattern and the channel region has a large width.

[0015] According to one embodiment of the present invention, the thin-film transistor can have stability and excellent reliability because the active layer includes a pattern.

[0016] In addition to the effects described above, other features and advantages of the present invention will be described below, or can be clearly understood by those having ordinary knowledge in the technical field to which the present invention pertains from such techniques and description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] [Figure 1] It is a plan view of a thin film transistor according to an embodiment of the present invention. [Figure 2A] It is a cross-sectional view taken along line I-I' in FIG. 1. [Figure 2B] It is a cross-sectional view taken along line II-II' in FIG. 1. [Figure 3] It is a cross-sectional view of a thin film transistor according to another embodiment of the present invention. [Figure 4A] It is a plan view of a thin film transistor according to still another embodiment of the present invention and a cross-sectional view taken along line III-III' of the plan view. [Figure 4B] It is a plan view of a thin film transistor according to still another embodiment of the present invention and a cross-sectional view taken along line III-III' of the plan view. [Figure 5] It is a plan view of a thin film transistor according to still another embodiment of the present invention and a cross-sectional view taken along line IV-IV' of the plan view. [Figure 6] It is a plan view of a thin film transistor according to still another embodiment of the present invention and a cross-sectional view taken along line V-V' of the plan view. [Figure 7] It is a cross-sectional view of a thin film transistor according to still another embodiment of the present invention. [Figure 8] It is a plan view of a thin film transistor according to still another embodiment of the present invention. [Figure 9] It is a plan view of a thin film transistor according to still another embodiment of the present invention. [Figure 10] It is a plan view of a thin film transistor according to still another embodiment of the present invention. [Figure 11A] It is a plan view of a thin film transistor according to still another embodiment of the present invention. [Figure 11B]It is a cross-sectional view taken along VI-VI' of FIG. 11A. [Figure 11C] It is a cross-sectional view taken along VII-VII' of FIG. 11A. [Figure 12A] It is a cross-sectional view taken along VI-VI' of a thin film transistor according to another embodiment of FIG. 11A. [Figure 12B] It is a cross-sectional view taken along VII-VII' of a thin film transistor according to another embodiment of FIG. 11A. [Figure 13] It is a plan view of a thin film transistor according to still another embodiment of the present invention. [Figure 14] It is a plan view of a thin film transistor according to still another embodiment of the present invention. [Figure 15] It is a plan view of a thin film transistor according to still another embodiment of the present invention. [Figure 16A] It is a graph of threshold voltage (Vth) measurement for thin film transistors according to Examples and Comparative Examples. [Figure 16B] It is a plan view of a thin film transistor according to the comparative example of FIG. 16A. [Figure 17] It is a graph of carrier concentration for each region of an active layer. [Figure 18] It is a graph of carrier concentration for each region of an active layer. [Figure 19] It is a schematic diagram of a display device according to an embodiment of the present invention. [Figure 20] It is a schematic diagram of a shift register. [Figure 21] It is a circuit diagram of any one pixel in FIG. 19. [Figure 22] It is a circuit diagram of any one pixel in a display device according to another embodiment of the present invention. [Figure 23] It is a circuit diagram of any one pixel in a display device according to still another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0018] The advantages and features of the present invention, as well as methods for achieving them, will become apparent by referring to the embodiments described below in detail with accompanying figures. However, the present invention is not limited to the embodiments disclosed below and can consist of various different forms, and these embodiments are provided merely to complete the disclosure of the present invention and to fully inform those who are ordinary skill in the art to which the invention pertains of the invention of the scope of the invention.

[0019] The shapes, sizes, proportions, angles, numbers, etc., disclosed in the figures illustrating embodiments of the present invention are illustrative, and the present invention is not limited to those shown in the figures. Throughout the specification, the same reference numeral can refer to the same component. In addition, in the description of the present invention, if it is determined that a specific description of related prior art would unnecessarily obscure the gist of the present invention, such detailed description will be omitted.

[0020] Wherever "includes," "has," "consists of," etc., are used in this invention, other parts may be added unless "only" is used. When a component is expressed singly, it includes multiple components unless otherwise explicitly stated.

[0021] In interpreting the constituent elements, even without further explicit mention, they shall be interpreted as including a margin of error.

[0022] For example, when the positional relationship between two parts is described using phrases such as "on top," "above," "below," or "next to," one or more other parts can be located between the two parts unless the expressions "immediately" or "directly" are used.

[0023] Spatially relative terms such as "below," "beneath," "lower," "above," and "upper" can be used to easily describe the correlation between one element or component and another, as shown in the diagram. Spatially relative terms should be understood as terms that include the different directions of elements in use or operation, in addition to the directions shown in the diagram. For example, if the elements shown in the diagram are reversed, an element described as "below" or "beneath" another element can be placed "above" the other element. Therefore, the exemplary term "below" can include both downward and upward directions. Similarly, the exemplary terms "up" or "upper" can include both upward and downward directions.

[0024] When describing temporal relationships, for example, when a temporal sequence is described using phrases like "after," "following," "next," or "before," it can include non-continuous events unless expressions like "immediately" or "directly" are used.

[0025] The terms "first," "second," etc., are used to describe various components, but these components are not limited by these terms. These terms are simply used to distinguish one component from another. Therefore, the first component referred to below may also be the second component within the technical concept of the present invention.

[0026] The term "at least one" should be understood to include all possible combinations of one or more related items. For example, "at least one of item 1, item 2, and item 3" could mean not just each of item 1, item 2, or item 3 individually, but all possible combinations of items that can be presented from two or more of items 1, item 2, and item 3.

[0027] The features of each of the various embodiments of the present invention can be combined or linked together, either partially or as a whole, and are technically capable of various interlocking and driving mechanisms. Each embodiment can be implemented independently of the others or together in a related manner.

[0028] When adding reference numerals to the components of each figure illustrating an embodiment of the present invention, identical components may, to the greatest extent possible, have the same reference numeral, even if they are shown in different figures.

[0029] In the embodiments of the present invention, the source electrode and the drain electrode are distinguished only for the sake of explanation, and the source electrode and the drain electrode can be interchangeable. The source electrode can become the drain electrode, and the drain electrode can become the source electrode. Furthermore, the source electrode in one embodiment can become the drain electrode in another embodiment, and the drain electrode in one embodiment can become the source electrode in another embodiment.

[0030] In some embodiments of the present invention, for the sake of explanation, the source region and source electrode may be distinguished, and the drain region and drain electrode may be distinguished, but the embodiments of the present invention are not limited thereto. The source region can be the source electrode, and the drain region can be the drain electrode. Furthermore, the source region can also be the drain electrode, and the drain region can also be the source electrode.

[0031] Figure 1 is a plan view of a thin-film transistor 100 according to one embodiment of the present invention. Figure 2A is a cross-sectional view taken along line I-I' in Figure 1. Figure 2B is a cross-sectional view taken along line II-II' in Figure 1.

[0032] Referring to Figures 1, 2A, and 2B, a transistor 100 according to one embodiment of the present invention may include an active layer 130 and a gate electrode 150.

[0033] Referring in detail to Figures 1, 2A and 2B, the device may include an active layer 130 and a gate electrode 150 that is separated from the active layer 130 and at least partially overlaps it.

[0034] According to one embodiment of the present invention, the thin-film transistor 100 may further include a base substrate 110. Referring to Figures 2A and 2B, the active layer 130 is disposed on the base substrate 110.

[0035] According to one embodiment of the present invention, the thin-film transistor 100 may further include a buffer layer 120. Referring to Figures 2A and 2B, the active layer 130 is located on the buffer layer 120. More specifically, the buffer layer 120 is located between the base substrate 110 and the active layer 130.

[0036] According to one embodiment of the present invention, the thin-film transistor 100 may further include a gate insulating film 140. Referring to Figures 2A and 2B, the gate insulating film 140 is located on the active layer 130. More specifically, the gate insulating film 140 is located between the active layer 130 and the gate electrode 150.

[0037] According to one embodiment of the present invention, the thin-film transistor 100 may further include an interlayer insulating film 160. Referring to Figure 2A, the interlayer insulating film 160 is located on the gate electrode 150. More specifically, the gate electrode 150 is located between the gate insulating film 140 and the interlayer insulating film 160.

[0038] According to one embodiment of the present invention, the thin-film transistor 100 may further include a source electrode 171 and a drain electrode 172. Referring to Figure 2A, the source electrode 171 and the drain electrode 172 are arranged on an interlayer insulating film 160. More specifically, the interlayer insulating film 160 is arranged between the gate electrode 150 and the source electrode 171 and the drain electrode 172.

[0039] The components of the thin-film transistor 100 according to one embodiment of the present invention will be described in more detail below.

[0040] The base substrate 110 can be made of glass or plastic. As the plastic, a transparent plastic with flexible properties, such as polyimide, can be used.

[0041] When using polyimide as the base substrate 110, considering that a high-temperature deposition process is performed on the base substrate 110, a heat-resistant polyimide that can withstand high temperatures can be used. In this case, for thin-film transistor formation, the polyimide substrate can be placed on a carrier substrate made of a highly durable material such as glass, and processes such as deposition and etching can be carried out.

[0042] Referring to Figures 2A and 2B, the buffer layer 120 can be placed on the base substrate 110.

[0043] The buffer layer 120 is formed on the base substrate 110 and can be made of an inorganic or organic material. For example, it can include insulating oxides such as silicon oxide (SiOx) and aluminum oxide (Al2O3).

[0044] The buffer layer 120 protects the active layer 130 by blocking impurities such as moisture and oxygen flowing in from the base substrate 110, and also plays a role in flattening the top of the base substrate 110. It can be formed as a single layer or in multiple layers.

[0045] Referring to Figures 2A and 2B, the active layer 130 can be placed on top of the buffer layer 120.

[0046] The active layer 130 may include a channel region 130a, a source region 130b, and a drain region 130c.

[0047] More specifically, the active layer 130 may include a channel region 130a that overlaps with the gate electrode 150 in a plan view, a source region 130b that does not overlap with the gate electrode 150 in a plan view and is connected to one side of the channel region 130a, and a drain region 130c that does not overlap with the gate electrode 150 in a plan view and is connected to the other side of the channel region 130a.

[0048] According to one embodiment of the present invention, the source region 130b and the drain region 130c are separated from each other with the channel region 130a in between.

[0049] According to one embodiment of the present invention, the active layer 130 can be formed from a semiconductor material. The active layer 130 may include an oxide semiconductor material.

[0050] The oxide semiconductor material may include, for example, at least one of the following: IZO(InZnO)-based oxide semiconductor material, IGO(InGaO)-based oxide semiconductor material, ITO(InSnO)-based oxide semiconductor material, IGZO(InGaZnO)-based oxide semiconductor material, IGZTO(InGaZnSnO)-based oxide semiconductor material, GZTO(GaZnSnO)-based oxide semiconductor material, GZO(GaZnO)-based oxide semiconductor material, ITZO(InSnZnO)-based oxide semiconductor material, and FIZO(FeInZnO)-based oxide semiconductor material. However, the embodiment of the present invention is not limited thereto, and the active layer 130 can also be made from other oxide semiconductor materials known in the art.

[0051] The source region 130b and the drain region 130c can be formed by selective conductor formation of the active layer 130, which is made of a semiconductor material. According to one embodiment of the present invention, selective conductor formation refers to imparting conductivity to a specific part of the active layer 130 so that it can function like a conductor.

[0052] For example, the active layer 130 can be selectively made conductive by ion doping. As a result, a source region 130b and a drain region 130c can be formed. However, the embodiment of the present invention is not limited thereto, and the active layer 130 can also be selectively made conductive by other methods known in the art.

[0053] The source region 130b and drain region 130c do not overlap with the gate electrode 150. The source region 130b and drain region 130c have superior conductivity and high mobility compared to the channel region 130a. Therefore, the source region 130b and drain region 130c can each serve as wiring.

[0054] Referring to Figure 1, the channel region 130a has a channel length (L) and a channel width (W). Here, the channel length (L) of the channel region 130a refers to the length in the direction of the source region 130b and the drain region 130c. The channel width (W) of the channel region 130a refers to the length perpendicular to the length of the channel region 130a.

[0055] According to one embodiment of the present invention, the active layer 130 may include a first source conductor adjustment region 135a and a first drain conductor adjustment region 136a. Furthermore, the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a are separated from each other. More specifically, they are separated from each other with at least a portion of the channel region 130a in between.

[0056] Referring to Figures 1 and 2B, the first source conductor adjustment region 135a can overlap with at least a portion of the channel region 130a. Figure 1 shows a configuration in which the first source conductor adjustment region 135a overlaps with at least a portion of the channel region 130a. More specifically, at least a portion of the first source conductor adjustment region 135a can overlap with at least a portion of the gate electrode 150. Figure 1 shows a configuration in which at least a portion of the first source conductor adjustment region 135a overlaps with at least a portion of the gate electrode 150. However, an embodiment of the present invention is not limited thereto, and the first source conductor adjustment region 135a can overlap with the channel region 130a and simultaneously with the source region 130b. More specifically, at least a portion of the first source conductor adjustment region 135a may overlap with the gate electrode 150, while another portion of the first source conductor adjustment region 135a does not overlap with the gate electrode 150. Here, the superposition of the first source conductor adjustment region 135a with at least a portion of the channel region 130a can be seen as structurally equivalent to the superposition of the first source conductor adjustment region 135a with at least a portion of the gate electrode 150. The same applies to the case of the first source conductor adjustment region 136a.

[0057] Furthermore, the first drain conductor adjustment region 136a can overlap with at least a portion of the channel region 130a. Figure 1 shows a configuration in which the first drain conductor adjustment region 136a overlaps with at least a portion of the channel region 130a. More specifically, at least a portion of the first drain conductor adjustment region 136a can overlap with at least a portion of the gate electrode 150. Figure 1 shows a configuration in which at least a portion of the first drain conductor adjustment region 136a overlaps with at least a portion of the gate electrode 150. However, one embodiment of the present invention is not limited thereto, and referring to Figure 1, the first drain conductor adjustment region 136a can overlap with the channel region 130a and at the same time with the drain region 130c. More specifically, it is possible that at least a portion of the first drain conductor adjustment region 136a overlaps with the gate electrode 150 while another portion of the first drain conductor adjustment region 136a does not overlap with the gate electrode 150.

[0058] According to one embodiment of the present invention, the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a can be formed by patterning the active layer 130. More specifically, the first source conductor adjustment region 135a can be described as a region that overlaps with at least a part of the channel region 130a and is surrounded by the active layer 130. More specifically, the first source conductor adjustment region 135a can be described as a region that overlaps with at least a part of the gate electrode 150 and is surrounded by the active layer 130. For example, the first source conductor adjustment region 135a can be described as a portion of the active layer 130 that has been partially patterned and removed.

[0059] Furthermore, the first drain conductor modification region 136a can be described as a region that overlaps with at least a part of the channel region 130a and is surrounded by the active layer 130. More specifically, the first drain conductor modification region 136a can be described as a region that overlaps with at least a part of the gate electrode 150 and is surrounded by the active layer 130. For example, the first drain conductor modification region 136a can be described as a portion of the active layer 130 that has been partially patterned and removed.

[0060] Referring to Figure 1, according to one embodiment of the present invention, the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a have a width (D) and a length (S), where the width (D) may be in the range of 0.5 to 5 μm.

[0061] Referring to Figure 1, according to one embodiment of the present invention, if S1 is the length of the region where the first source conductor adjustment region 135a and the gate electrode 150 overlap, then S1 may be in the range of 0.5 to 1.5 μm. The same applies to the first drain conductor adjustment region 136a, where S2 is the length of the region where the first drain conductor adjustment region 136a and the gate electrode 150 overlap, then S2 may be in the range of 0.5 to 1.5 μm.

[0062] According to one embodiment of the present invention, the first source conductor adjustment region 135a can overlap with the source region 130b. More specifically, the first source conductor adjustment region 135a can protrude from the gate electrode 150 toward the source region 130b in a plan view. If S3 is the length of the region where the first source conductor adjustment region 135a and the source region 130b overlap, then S3 may be in the range of 0.5 to 5 μm. More specifically, if S3 is the length of the region where the first source conductor adjustment region 135a protrudes from the gate electrode 150 in a plan view, then S3 may be in the range of 0.5 to 5 μm. The same applies to the first drain conductor adjustment region 136a, and if S4 is the length of the region where the first drain conductor adjustment region 136a and the drain region 130c overlap, then S4 may be in the range of 0.5 to 5 μm. In detail, if S4 is the length of the region in which the first drain conductor adjustment region 136a protrudes from the gate electrode 150 in a plan view, then S4 may be in the range of 0.5 to 5 μm.

[0063] Referring to Figure 13, according to one embodiment of the present invention, the first source conductor adjustment region 135a may not overlap with the boundary between the channel region 130a and the source region 130b. More specifically, the first source conductor adjustment region 135a can be positioned at a distance from the boundary between the gate electrode 150 and the source region 130b. More specifically, the first source conductor adjustment region 135a can be positioned within the gate electrode 150 at a distance from the boundary between the gate electrode 150 and the source region 130b. If the shortest distance between the first source conductor adjustment region 135a and the boundary between the channel region 130a and the source region 130b is S5, then S5 may be in the range of 0.5 to 1.5 μm. This is also true for the first drain conductor adjustment region 136a, and if S6 is the shortest distance between the first drain conductor adjustment region 136a and the boundary between the channel region 130a and the drain region 130c, then S6 can be in the range of 0.5 to 1.5 μm.

[0064] According to one embodiment of the present invention, the channel region 130a can be partially made conductive. Specifically, since the channel region 130a is superimposed on the gate electrode 150, it is not directly targeted for conductivity in the conductivity process. However, the boundaries between the channel region 130a and the source region 130b, and the boundaries between the channel region 130a and the drain region 130c, can be partially made conductive during the conductivity process by diffusion of dopants such as metal ions, diffusion of hydrogen, and indirect influence of the plasma. As a result, the boundaries between the channel region 130a and the source region 130b, and the boundaries between the channel region 130a and the drain region 130c, can each have a carrier concentration gradient. The carrier concentration gradient will be explained in detail in Figures 17 and 18.

[0065] Generally, when the channel region 130a of the active layer 130 has a large channel width (W), conduction diffusion can progress significantly at the boundary regions between the channel region 130a and the source region, drain region 130b, and 130c. As conduction diffusion progresses, the threshold voltage (Vth) of the thin-film transistor 100 shifts to the negative (-) direction, which can reduce the driving stability of the thin-film transistor 100.

[0066] If the channel region 130a of the active layer 130 has a small channel width (W), conduction diffusion may decrease in the boundary regions between the channel region 130a and the source region, drain region 130b, and 130c. On the other hand, if the channel region 130a of the active layer 130 has a small channel width (W), the total amount of carriers passing through the channel region 130a of the thin-film transistor 100 decreases, and the ON current characteristics may deteriorate. As a result, if a large current flows through the thin-film transistor 100 with a small channel width (W) in the channel region 130a, the thin-film transistor 100 may be damaged, and the driving stability may decrease. Therefore, it is necessary to control conduction diffusion while the active layer 130 has a large channel width (W).

[0067] Referring to Figures 3, 4A, and 4B, in one embodiment of the present invention, the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a are formed by patterning the first active layer 131, and the first active layer 131 may not be laminated in the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a, or the thickness of the first active layer 130 may be reduced. As a result, the dopant concentration in the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a may be low or almost nonexistent, and the diffusion of the dopant can be prevented or suppressed around the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a. Therefore, the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a can perform the same role as if multiple channel regions 130a with small channel widths (W) were formed in the active layer 130, and conductor penetration can be controlled even if the channel regions 130a have a large width.

[0068] Referring to Figure 1, if the active layer 130 includes a first source conductor adjustment region 135a and a first drain conductor adjustment region 136a, conductor formation can be suppressed on the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a. Therefore, conductor formation progresses in the channel region 130a of the active layer 130, excluding the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a. As a result, even if the channel region 130a of the active layer 130 has a large channel width (W), the width of the region where conductor formation progresses becomes narrower, and the penetration of conductor formation into the channel region 130a can be prevented or controlled.

[0069] According to one embodiment of the present invention, the first drain conductor adjustment region 136a can be positioned on a first line (LN), which is the shortest line connecting the source region 130b and the drain region 130c, crossing the first source conductor adjustment region 135a. In detail, referring to Figure 1, the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a can be positioned on the first line (LN). However, one embodiment of the present invention is not limited thereto, and the first drain conductor adjustment region 136a and the first source conductor adjustment region 135a can also be positioned on a first line (LN), which is the shortest line connecting the source region 130b and the drain region 130c, crossing the first drain conductor adjustment region 136a and the first source conductor adjustment region 135a.

[0070] According to one embodiment of the present invention, the active layer 130 may include a first active layer 131. More specifically, the first active layer 131 may be located in at least a portion of the channel region 130a, at least a portion of the source region 130b, and at least a portion of the drain region 130c. Alternatively, the first active layer 131 may not be located in at least a portion of the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a.

[0071] When the first active layer 131 is located in the first source conductor adjustment region 135a, the thickness of the first active layer 131 located in the first source conductor adjustment region 135a may be thinner than the thickness of the first active layer 131 located in the channel region 130a excluding the first source conductor adjustment region 135a (see Figure 4B).

[0072] Furthermore, when the first active layer 131 is located in the first drain conductor adjustment region 136a, the thickness of the first active layer 131 located in the first drain conductor adjustment region 136a may be thinner than the thickness of the first active layer 131 located in the channel region 130a excluding the first drain conductor adjustment region 136a (see Figure 4B).

[0073] According to one embodiment of the present invention, the first source conductor adjustment region 135a can overlap with the boundary between the channel region 130a and the source region 130b, and can overlap with at least a portion of the source region 130b. More specifically, the first source conductor adjustment region 135a can protrude from the gate electrode 150 toward the source region 130b in a plan view. Figure 1 shows a configuration in which the first source conductor adjustment region 135a overlaps with the boundary between the channel region 130a and the source region 130b, and overlaps with the source region 130b. Figure 1 also shows a configuration in which the first source conductor adjustment region 135a protrudes from the gate electrode 150 toward the source region 130b in a plan view. However, one embodiment of the present invention is not limited thereto, and the first source conductor adjustment region 135a may overlap with the boundary between the channel region 130a and the source region 130b, but not with the source region 130b. In detail, at least a portion of the end of the first source conductor adjustment region 135a may be located at the boundary between the gate electrode 150 and the source region 130b in a plan view, and the first source conductor adjustment region 135a may not protrude from the gate electrode 150 toward the source region 130b in a plan view (see Figure 9). Also, the first source conductor adjustment region 135a may not overlap with the boundary between the channel region 130a and the source region 130b. In detail, the first source conductor adjustment region 135a can be positioned at a distance from the boundary between the gate electrode 150 and the source region 130b in a plan view (see Figure 13).

[0074] Furthermore, according to one embodiment of the present invention, the first drain conductor adjustment region 136a can overlap with the boundary between the channel region 130a and the drain region 130c, and can overlap with at least a portion of the drain region 130c. In detail, the first drain conductor adjustment region 136a can protrude from the gate electrode 150 toward the drain region 130c in a plan view. Figure 1 shows a configuration in which the first drain conductor adjustment region 136a overlaps with the boundary between the channel region 130a and the drain region 130c, and overlaps with the drain region 130c. Also, Figure 1 shows a configuration in which the first drain conductor adjustment region 136a protrudes from the gate electrode 150 toward the drain region 130c in a plan view. However, one embodiment of the present invention is not limited thereto, and the first drain conductor adjustment region 136a may overlap with the boundary between the channel region 130a and the drain region 130c, but not with the drain region 130c. In detail, at least a portion of the edge of the first drain conductor adjustment region 136a may be located at the boundary between the gate electrode 150 and the drain region 130c in a plan view, and the first drain conductor adjustment region 136a may not protrude from the gate electrode 150 toward the drain region 130c in a plan view (see Figure 9). Also, the first drain conductor adjustment region 136a may not overlap with the boundary between the channel region 130a and the drain region 130c. In detail, the first drain conductor adjustment region 136a may be located at a distance from the boundary between the gate electrode 150 and the drain region 130c in a plan view (see Figure 13).

[0075] Referring to Figure 1 or Figure 9, the channel region 130a may have a first diffusion region (A1) and a second diffusion region (A2). More specifically, according to one embodiment of the present invention, the first diffusion region (A1) and the second diffusion region (A2) are arranged spaced apart from each other.

[0076] According to one embodiment of the present invention, a first diffusion region (A1) is located on the channel region 130a and can come into contact with the source region 130b. A second diffusion region (A2) is located on the channel region 130a and can come into contact with the drain region 130c.

[0077] More specifically, the first diffusion region (A1) and the second diffusion region (A2) do not overlap with the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a.

[0078] The first diffusion region (A1) and the second diffusion region (A2) are partially conductive regions, meaning that the first diffusion region (A1) and the second diffusion region (A2) are partially conductive regions in the channel region 130a. In detail, the first diffusion region (A1) and the second diffusion region (A2) are superimposed on the gate electrode 150 and are therefore not directly targeted for conductivity in the conductivity process. However, the first diffusion region (A1) and the second diffusion region (A2) can be partially conductive during the conductivity process through dopant diffusion, hydrogen diffusion, and the indirect influence of the plasma. Therefore, the first diffusion region (A1) and the second diffusion region (A2) each have a carrier concentration gradient. The carrier concentration gradient will be explained in detail in Figures 17 and 18.

[0079] Referring to Figure 1, the first diffusion region (A1) and the second diffusion region (A2) are regions in which the channel region 130a is partially conducted, and the length of the conducted region of the channel region 130a, or the distance of conduction, is called the conduction penetration depth (ΔL).

[0080] According to one embodiment of the present invention, if the length of the first diffusion region (A1) and the second diffusion region (A2) is defined as the conduction penetration depth (ΔL), then the conduction penetration depth (ΔL) can be in the range of 0 to 1 μm.

[0081] In detail, during the selective conduction process of the active layer 130, a portion of the channel region 130a becomes conductive, and this conductive region cannot function as a channel. In Figure 1, the conduction penetration depth, which is the length of the first diffusion region (A1) and the second diffusion region (A2) within the channel region 130a, is shown as "ΔL". The region within the channel region 130a that is not conductive and can effectively function as a channel is called the effective channel. As the conduction penetration depth (ΔL) increases, the length of the effective channel decreases.

[0082] For a thin-film transistor to perform a switching function, it is preferable to maintain the effective channel length above a predetermined value, and it is preferable to adjust the conduction penetration depth (ΔL) to ensure the predetermined effective channel length. Therefore, the conduction penetration depth (ΔL) is preferably in the range of 0 to 1 μm.

[0083] A gate insulating film 140 can be placed on the active layer 130. Specifically, referring to Figure 2A, the gate insulating film 140 is placed between the active layer 130 and the gate electrode 150.

[0084] The gate insulating film 140 may include at least one of silicon oxide, silicon nitride, and metal oxide. The gate insulating film 140 may have a single film structure or a multilayer film structure.

[0085] A gate electrode 150 can be placed on the gate insulating film 140. The gate electrode 150 may include at least one of the following: aluminum-based metals such as aluminum (Al) or aluminum alloys; silver-based metals such as silver (Ag) or silver alloys; copper-based metals such as copper (Cu) or copper alloys; molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys; chromium (Cr); tantalum (Ta); neodymium (Nd); and titanium (Ti). Although not shown in the figure, the gate electrode 150 may also have a multilayer structure including two conductive films with different physical properties.

[0086] The gate electrode 150 acts as a hydrogen barrier membrane, preventing hydrogen from flowing in from the top of the gate electrode 150.

[0087] A thin-film transistor 100 according to one embodiment of the present invention may further include an interlayer insulating film 160. The interlayer insulating film 160 is disposed on the gate electrode 150. The interlayer insulating film 160 is an insulating layer made of an insulating material. The interlayer insulating film 160 may be made of an organic material, an inorganic material, or a laminate of an organic layer and an inorganic layer.

[0088] According to one embodiment of the present invention, the thin-film transistor 100 may include a source electrode 171 and a drain electrode 172. The source electrode 171 and the drain electrode 172 can be arranged on an interlayer insulating film 160, for example, as shown in Figure 2A.

[0089] The source electrode 171 and the drain electrode 172 can be connected to the active layer 130 while separated from each other. Referring to Figure 2A, the source electrode 171 and the drain electrode 172 can each be connected to the active layer 130 via contact holes. More specifically, the source electrode 171 and the drain electrode 172 can each be connected to the source region 130b and the drain region 130c of the active layer 130 via contact holes.

[0090] The source electrode 171 and the drain electrode 172 may each include at least one of the following: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0091] In one embodiment and in the figures of the present invention, the source electrode 171 and the drain electrode 172 are distinguished only for the sake of explanation, and the source electrode 171 and the drain electrode 172 are not limited by the figures and the above description. The source electrode 171 and the drain electrode 172 are interchangeable. Similarly, the source region 130b and the drain region 130c are distinguished only for the sake of explanation, and the source region 130b and the drain region 130c are interchangeable.

[0092] Figure 3 is a cross-sectional view of a thin-film transistor 200 according to another embodiment of the present invention.

[0093] According to one embodiment of the present invention, the first active layer 131 may further include a first oxide semiconductor layer 131a and a second oxide semiconductor layer 131b. Referring to Figure 3, the second oxide semiconductor layer 131b may be placed on the first oxide semiconductor layer 131a.

[0094] Figure 4A is a plan view and a cross-sectional view taken along line III-III' of the plan view of a thin-film transistor 300 according to another embodiment of the present invention, and Figure 4B is a plan view and a cross-sectional view taken along line III-III' of the plan view of a thin-film transistor according to another embodiment of the present invention.

[0095] According to Figure 4A, in comparison with Figure 1, according to one embodiment of the present invention, the active layer 130 may further include a first active layer 131 and a second active layer 132 on the first active layer 131.

[0096] According to one embodiment of the present invention, the second active layer 132 can be formed from a semiconductor material. The second active layer 132 may include an oxide semiconductor material.

[0097] The second active layer 132 can be made from the same oxide semiconductor material as the first active layer 131, or it can be made from a different oxide semiconductor material than the first active layer 131.

[0098] According to one embodiment of the present invention, the second active layer 132 can be arranged throughout the entire channel region 130a, the entire source region 130b, and the entire drain region 130c. More specifically, the second active layer 132 can be arranged in the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a. Figure 4 shows a configuration in which the second active layer 132 is arranged in the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a. More specifically, at least a portion of the second active layer 132 can be in contact with the side surface of the first active layer 131 within the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a.

[0099] More specifically, Figure 4A shows a configuration in which the first active layer 131 is not located in at least a portion of the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a, while the second active layer 132 is located in the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a. Also, referring to Figure 4A, the second active layer 132 can also be in contact with the buffer layer 120 within the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a.

[0100] On the other hand, Figure 4B shows a configuration in which the first active layer 131 is placed in the first source conductor adjustment region 135a, compared to Figure 4A. More specifically, when the first active layer 131 is placed in the first source conductor adjustment region 135a, the thickness of the first active layer 131 placed in the first source conductor adjustment region 135a may be thinner than the thickness of the first active layer 131 placed in the channel region 130a excluding the first source conductor adjustment region 135a. Here, the second active layer 132 does not come into contact with the buffer layer 120 within the first source conductor adjustment region 135a.

[0101] Alternatively, the first active layer 131 can be placed in the first drain conductor adjustment region 136a. More specifically, when the first active layer 131 is placed in the first drain conductor adjustment region 136a, the thickness of the first active layer 131 placed in the first drain conductor adjustment region 136a may be thinner than the thickness of the first active layer 131 placed in the channel region 130a excluding the first drain conductor adjustment region 136a. In this case, the second active layer 132 does not come into contact with the buffer layer 120 within the first drain conductor adjustment region 136a.

[0102] According to one embodiment of the present invention, even when the active layer 130 has a multilayer structure, the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a are thinner than the region of the active layer 130 excluding the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a, and the conductor penetration depth (ΔL) into the channel region 130a can be controlled.

[0103] Figure 5 is a plan view and a cross-sectional view of a thin-film transistor 400 according to the present invention and other embodiments thereof, cut along line IV-IV' in the plan view.

[0104] As shown in Figure 5, compared to Figure 4, the first active layer 131 can include a first oxide semiconductor layer 131a and a second oxide semiconductor layer 131b. Referring to Figure 5, the first active layer 131 can include a first oxide semiconductor layer 131a and a second oxide semiconductor layer 131b on the first oxide semiconductor layer 131a. More specifically, the first active layer 131 can be patterned to form a first source conductor adjustment region 135a and a first drain conductor adjustment region 136a, and the second active layer 132 can be placed over the entire channel region 130a, the entire source region 130b, and the entire drain region 130c. More specifically, the second active layer 132 can be placed over the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a. At least a portion of the second active layer 132 can come into contact with either the first oxide semiconductor layer 131a or the second oxide semiconductor layer 131b within the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a.

[0105] Figure 6 is a plan view and a cross-sectional view of a thin-film transistor 500 according to another embodiment of the present invention, cut along line V-V' in the plan view.

[0106] In comparison with Figure 4, Figure 6 shows that the second active layer 132 can include a tertiary oxide semiconductor layer 132a and a quaternary oxide semiconductor layer 132b. Referring to Figure 6, the second active layer 132 can include a tertiary oxide semiconductor layer 132a and a quaternary oxide semiconductor layer 132b on the tertiary oxide semiconductor layer 132a. More specifically, the first active layer 131 can be patterned to form a first source conductor adjustment region 135a and a first drain conductor adjustment region 136a, and the second active layer 132 can be placed over the entire channel region 130a, the entire source region 130b, and the entire drain region 130c. More specifically, at least a portion of the second active layer 132 can be in contact with at least a portion of the tertiary oxide semiconductor layer 132a within the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a.

[0107] Figure 7 is a cross-sectional view of a thin-film transistor 600 according to the present invention and other embodiments.

[0108] Referring to Figure 7, according to one embodiment of the present invention, the gate insulating film 140 can be patterned in various ways that cover the upper surface of the channel region 130a of the active layer 130 and expose the upper surfaces of the source region 130b and the drain region 130b.

[0109] Figure 7 shows a configuration in which the gate insulating film 140 covers the entire upper surface of the active layer 130. However, the embodiment of the present invention is not limited to this, and the gate insulating film 140 can also expose the upper surfaces of the source region 130b and the drain region 130b (see Figure 2A).

[0110] Figure 8 is a plan view of a thin-film transistor 700 according to the present invention and other embodiments.

[0111] According to Figure 8, compared to Figure 1, the second source conductor adjustment region 135b and the second drain conductor adjustment region 136b can be further included.

[0112] According to one embodiment of the present invention, the active layer 130 includes a second source conductor adjustment region 135b and a second drain conductor adjustment region 136b that are spaced apart from each other, and the second source conductor adjustment region 135b can be superimposed on at least a portion of the channel region 130a. More specifically, at least a portion of the second source conductor adjustment region 135b can be superimposed on at least a portion of the gate electrode 150.

[0113] The second drain conductor adjustment region 136b can overlap with at least a portion of the channel region 130a. More specifically, at least a portion of the second drain conductor adjustment region 136b can overlap with at least a portion of the gate electrode 150.

[0114] As shown in Figure 8, the first source conductor adjustment region 135a, the second source conductor adjustment region 135b, the first drain conductor adjustment region 136a, and the second drain conductor adjustment region 136b are shown as being of the same size in the figure. However, one embodiment of the present invention is not limited to this, and the first source conductor adjustment region 135a, the second source conductor adjustment region 135b, the first drain conductor adjustment region 136a, and the second drain conductor adjustment region 136b may not be of the same size.

[0115] Figure 8 shows the first source conductor adjustment region 135a positioned above the second source conductor adjustment region 135b in a plan view. However, the embodiment of the present invention is not limited to this, and the positions of the first source conductor adjustment region 135a and the second source conductor adjustment region 135b can be changed. This also applies to the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b.

[0116] The second source conductor adjustment region 135b can overlap with the boundary between the channel region 130a and the source region 130b, and can overlap with at least a portion of the source region 130b. More specifically, the second source conductor adjustment region 135b can protrude from the gate electrode 150 toward the source region 130b in a plan view. Figure 8 shows a configuration in which the second source conductor adjustment region 135b overlaps with the boundary between the channel region 130a and the source region 130b, and overlaps with at least a portion of the source region 130b. Figure 8 also shows a configuration in which the second source conductor adjustment region 135b protrudes from the gate electrode 150 toward the source region 130b in a plan view. However, the embodiment of the present invention is not limited thereto, and the second source conductor adjustment region 135b may not overlap with the source region 130b, nor may it overlap with the boundary between the channel region 130a and the source region 130b. In detail, at least a portion of the end of the second source conductor adjustment region 135b may be located at the boundary between the gate electrode 150 and the source region 130b in a plan view, and the second source conductor adjustment region 135b may not protrude from the gate electrode 150 toward the source region 130b in a plan view, and the second source conductor adjustment region 135b may be positioned at a distance from the boundary between the gate electrode 150 and the source region 130b in a plan view.

[0117] The second drain conductor adjustment region 136b can overlap with the boundary between the channel region 130a and the drain region 130c, and can overlap with at least a portion of the drain region 130c. More specifically, the second drain conductor adjustment region 136b can protrude from the gate electrode 150 toward the drain region 130c in a plan view. Figure 8 shows a configuration in which the second drain conductor adjustment region 136b overlaps with the boundary between the channel region 130a and the drain region 130c, and overlaps with at least a portion of the drain region 130c. Figure 8 also shows a configuration in which the second drain conductor adjustment region 136b protrudes from the gate electrode 150 toward the drain region 130c in a plan view. However, the embodiment of the present invention is not limited to this, and the second drain conductor adjustment region 136b may not overlap with the drain region 130b, and may not overlap with the boundary between the channel region 130a and the drain region 130c. In detail, at least a portion of the end of the second drain conductor adjustment region 136b may be located at the boundary between the gate electrode 150 and the drain region 130c in a plan view, and the second drain conductor adjustment region 136b may not protrude from the gate electrode 150 toward the drain region 130c in a plan view, and the second drain conductor adjustment region 136b may be positioned at a distance from the boundary between the gate electrode 150 and the drain region 130c in a plan view.

[0118] Referring to Figure 8, the first diffusion region (A1) can also be positioned between the first source conductor adjustment region 135a and the second source conductor adjustment region 135b. In this case, the first diffusion region (A1) does not overlap with the first source conductor adjustment region 135a and the second source conductor adjustment region 135b.

[0119] Referring to Figure 8, the second diffusion region (A2) can also be positioned between the first drain conduction adjustment region 136a and the second drain conduction adjustment region 136b. In this case, the second diffusion region (A2) does not overlap with the first drain conduction adjustment region 136a and the second drain conduction adjustment region 136b.

[0120] According to one embodiment of the present invention, when the active layer 130 includes a second source conductor adjustment region 135b, the first source conductor adjustment region 135a and the second source conductor adjustment region 135b are separated from each other. When the first source conductor adjustment region 135a and the second source conductor adjustment region 135b are separated, the first diffusion region (A1) can be placed between the first source conductor adjustment region 135a and the second source conductor adjustment region 135b.

[0121] When the active layer 130 includes a first drain conductor adjustment region 136a and a second drain conductor adjustment region 136b, the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b are separated from each other. When the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b are separated, the second diffusion region (A2) can be placed between the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b.

[0122] According to one embodiment of the present invention, the first source conductor adjustment region 135a and the second source conductor adjustment region 135b can be arranged at intervals of 0.5 to 20 μm.

[0123] Furthermore, the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b can be arranged at intervals of 0.5 to 20 μm. Here, the interval between the first source conductor adjustment region 135a and the second source conductor adjustment region 135b and the interval between the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b may be the same or different.

[0124] If the distance between the first source conductor adjustment region 135a and the second source conductor adjustment region 135b exceeds 20 μm, the width of the region where conductor formation progresses in the channel region 130a increases, and it may become impossible to prevent or control conductor formation in the channel region 130a. As a result, the conductor penetration depth (ΔL) of the diffusion regions (A1, A2) increases, resulting in a relatively short effective channel length. Furthermore, the threshold voltage (Vth) of the thin-film transistor may shift to the negative (-) direction, reducing the driving stability of the thin-film transistor. The same applies when the distance between the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b exceeds 20 μm.

[0125] When the distance between the first source conductor adjustment region 135a and the second source conductor adjustment region 135b is in the range of 0.5 to 20 μm, the width of the region where conductor formation progresses in the channel region 130a becomes narrower, making it possible to prevent or control conductor formation in the channel region 130a. On the other hand, when the distance between the first source conductor adjustment region 135a and the second source conductor adjustment region 135b is less than 0.5 μm, the width of the region where conductor formation progresses becomes too narrow, reducing the total amount of carriers passing through the channel region 130a of the thin-film transistor 100, and potentially suppressing the ON current. As a result, if a large current flows through the thin-film transistor 100 with a narrow width of the region where conductor formation progresses, the thin-film transistor 100 may be damaged, and the driving stability may decrease. The same applies when the distance between the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b is less than 0.5 μm.

[0126] According to one embodiment of the present invention, the active layer 130 may further include a third source conductor adjustment region and a third drain conductor adjustment region. Figure 8 shows only the first source conductor adjustment region 135a, the second source conductor adjustment region 135b, the first drain conductor adjustment region 136a, and the second drain conductor adjustment region 136b, but one embodiment of the present invention is not limited thereto, and although not shown in the figure, there may be three or more source homes and drain homes each.

[0127] Figure 9 is a plan view of a thin-film transistor 800 according to the present invention and other embodiments.

[0128] According to Figure 9, compared to Figure 8, the first source conductor adjustment region 135a and the second source conductor adjustment region 135b may overlap with the boundary between the channel region 130a and the source region 130b, but not with the source region 130b. Also, the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b may overlap with the boundary between the channel region 130a and the drain region 130c, but not with the drain region 130c. In detail, at least a portion of the ends of the first source conductor adjustment region 135a and the second source conductor adjustment region 135b may be located at the boundary between the gate electrode 150 and the source region 130b in a plan view, and the first source conductor adjustment region 135a and the second source conductor adjustment region 135b may not protrude from the gate electrode 150 toward the source region 130b in a plan view. The same applies to the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b.

[0129] According to one embodiment of the present invention, even when the first source conductor adjustment region 135a, the second source conductor adjustment region 135b, the first drain conductor adjustment region 136a, and the second drain conductor adjustment region 136b do not overlap with the source region 130b and the drain region 130c, respectively, conductor diffusion into the channel region 130a can be prevented or controlled. More specifically, even when the first source conductor adjustment region 135a and the second source conductor adjustment region 135b do not protrude from the gate electrode 150 toward the source region 130b in a plan view, and the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b do not protrude from the gate electrode 150 toward the drain region 130c in a plan view, conductor diffusion into the channel region 130a can be prevented or controlled.

[0130] Figure 10 is a plan view of a thin-film transistor 900 according to the present invention and other embodiments.

[0131] According to Figure 10, compared to Figure 9, at least one of the first source conductor adjustment region 135a and the second source conductor adjustment region 135b can overlap with the source region 130b. More specifically, at least one of the first source conductor adjustment region 135a and the second source conductor adjustment region 135b can protrude from the gate electrode 150 toward the source region 130b in a plan view.

[0132] Figure 10 shows a configuration in which the first source conductor adjustment region 135a overlaps with the source region 130b, and the second source conductor adjustment region 135b does not overlap with the source region 130b. More specifically, Figure 10 shows a configuration in which the first source conductor adjustment region 135a protrudes from the gate electrode 150 toward the source region 130b in a plan view, and the second source conductor adjustment region 135b does not protrude toward the source region 130b. However, one embodiment of the present invention is not limited to this, and the first source conductor adjustment region 135a may not overlap with the source region 130b, while the second source conductor adjustment region 135b may overlap with the source region 130b.

[0133] According to one embodiment of the present invention, at least one of the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b can overlap with the drain region 130c. More specifically, at least one of the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b can protrude from the gate electrode 150 toward the drain region 130c in a plan view. Figure 10 shows a configuration in which the first drain conductor adjustment region 136a overlaps with the drain region 130c, and the second drain conductor adjustment region 136b does not overlap with the drain region 130c. More specifically, Figure 10 shows a configuration in which the first drain conductor adjustment region 136a protrudes from the gate electrode 150 toward the drain region 130c in a plan view, and the second drain conductor adjustment region 136b does not protrude toward the drain region 130c. However, the present invention is not limited to this embodiment, and the first drain conductor adjustment region 136a may not overlap with the drain region 130c, while the second drain conductor adjustment region 136b may overlap with the drain region 130c.

[0134] Figure 11A is a plan view of a thin-film transistor according to the present invention and other embodiments.

[0135] Figure 11B is a cross-sectional view taken along the line VI-VI' in Figure 11A.

[0136] Figure 11C is a cross-sectional view taken along line VII-VII' of Figure 11A.

[0137] According to one embodiment of the present invention, the first source conductor adjustment region 135a overlaps with the longitudinal edge (R) of the channel region 130a, and more specifically, the first source conductor adjustment region 135a can be positioned on the longitudinal edge (R) of the channel region 130a in a plan view. Here, the longitudinal direction of the channel region 130a is the direction connecting the source region 130b and the drain region 130c.

[0138] Referring to Figures 11A, 11B, and 11C, the active layer 130 of the thin-film transistor 1000 according to one embodiment of the present invention includes a first active layer 131 and a second active layer 132.

[0139] More specifically, the active layer 130 includes a first source conductor adjustment region 135a and a second source conductor adjustment region 135b, the first source conductor adjustment region 135a and the second source conductor adjustment region 135b overlap with the longitudinal edge (R) of the channel region 130a. More specifically, referring to Figure 8, a configuration is shown in which the first source conductor adjustment region 135a and the second source conductor adjustment region 135b do not overlap with the longitudinal edge (R) of the channel region 130a. For example, in Figure 8, the first source conductor adjustment region 135a and the second source conductor adjustment region 135b are arranged at a distance from the longitudinal edge (R) of the channel region 130a.

[0140] According to one embodiment of the present invention, the first drain conductor adjustment region 136a can overlap with the longitudinal edge (R) of the channel region 130a. More specifically, the first drain conductor adjustment region 136a can be positioned on the longitudinal edge (R) of the channel region 130a in a plan view.

[0141] Referring to Figures 11A, 11B, and 11C, the active layer 130 includes a first drain conductor adjustment region 136a and a second drain conductor adjustment region 136b, and the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b overlap with the longitudinal edge (R) of the channel region 130a. Content that overlaps with the first source conductor adjustment region 135a and the second source conductor adjustment region 135b is omitted.

[0142] Figures 11B and 11C show a configuration including a first active layer 131 and a second active layer 132. However, one embodiment of the present invention is not limited to this, and the second active layer 132 may be omitted.

[0143] Figure 12A is a cross-sectional view taken along VI-VI' of a thin-film transistor according to another embodiment of Figure 11A.

[0144] Figure 12B is a cross-sectional view taken along line VII-VII' of a thin-film transistor according to another embodiment of Figure 11A.

[0145] Figures 12A and 12B show a configuration that does not include the second active layer 132, compared to Figures 11B and 11C.

[0146] Figure 13 is a plan view of a thin-film transistor 1100 according to the present invention and other embodiments.

[0147] According to one embodiment of the present invention, the first source conductor adjustment region 135a may not overlap with the boundary between the channel region 130a and the source region 130b. Similarly, the first drain conductor adjustment region 136a may not overlap with the boundary between the channel region 130a and the drain region 130c. More specifically, the first source conductor adjustment region 135a can be positioned at a distance from the boundary between the gate electrode 150 and the source region 130b in a plan view, and the first drain conductor adjustment region 136a can be positioned at a distance from the boundary between the gate electrode 150 and the drain region 130c in a plan view.

[0148] According to Figure 13, compared to Figure 8, the first source conductor adjustment region 135a and the second source conductor adjustment region 135b may not overlap with the source region 130b, nor may they overlap with the boundary between the source region 130b and the channel region 130a.

[0149] According to one embodiment of the present invention, even when the first source conductor adjustment region 135a and the second source conductor adjustment region 135b do not overlap with the boundary between the source region 130b and the channel region 130a, conductor diffusion into the channel region 130a can be prevented or controlled. More specifically, even when the first source conductor adjustment region 135a and the second source conductor adjustment region 135b are positioned at a distance from the boundary between the gate electrode 150 and the source region 130b in a plan view, conductor diffusion into the channel region 130a can be prevented or controlled. Similarly, in the case of the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b, even when they do not overlap with the boundary between the drain region 130c and the channel region 130a, conductor diffusion into the channel region 130a can be prevented or controlled. In detail, even when the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b are positioned at a distance from the boundary between the gate electrode 150 and the drain region 130c in a plan view, conductor diffusion into the channel region 130a can be prevented or controlled.

[0150] Figure 14 is a plan view of a thin-film transistor 1200 according to the present invention and other embodiments.

[0151] Figure 14 shows a configuration in which the first source conductor adjustment region 135a and the second source conductor adjustment region 135b overlap with the boundary between the source region 130b and the channel region 130a, but do not overlap with the source region 130b, compared to Figure 13. More specifically, Figure 14 shows a configuration in which at least a portion of the ends of the first source conductor adjustment region 135a and the second source conductor adjustment region 135b are located at the boundary between the gate electrode 150 and the source region 130b in a plan view, and the first source conductor adjustment region 135a and the second source conductor adjustment region 135b do not protrude from the gate electrode 150 toward the source region 130b in a plan view. On the other hand, the embodiment of the present invention is not limited thereto, and it is possible that only the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b overlap with the boundary between the drain region 130c and the channel region 130a, but do not overlap with the drain region 130c. In this case as well, the conduction diffusion into the channel region 130a can be controlled or prevented.

[0152] Figure 15 is a plan view of a thin-film transistor 1300 according to the present invention and other embodiments.

[0153] Figure 15 shows a configuration in which the first source conductor adjustment region 135a and the second source conductor adjustment region 135b overlap with the source region 130b, compared to Figure 13. More specifically, Figure 15 shows a configuration in which the first source conductor adjustment region 135a and the second source conductor adjustment region 135b protrude from the gate electrode 150 toward the source region 130b in a plan view. On the other hand, one embodiment of the present invention is not limited to this, and it is also possible for only the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b to overlap with the drain region 130c. In either case, it is possible to control or prevent conduction diffusion into the channel region 130a.

[0154] Figure 16A shows the threshold voltage (Vth) measurement graphs of thin-film transistors for the examples and comparative examples.

[0155] Figure 16B is a plan view of a thin-film transistor according to the comparative example in Figure 16A.

[0156] Referring to Figure 16A, graph a shows the measurement results of the threshold voltage (Vth) of the thin-film transistor according to the example, and graph b shows the measurement results of the threshold voltage (Vth) of the thin-film transistor according to the comparative example.

[0157] In the graph in Figure 16A, the horizontal axis represents the gate voltage (V). G ) means that the vertical axis is drain-source current (I DS This refers to the logarithmic (log) value of ).

[0158] The thin-film transistor according to one embodiment includes a first source conductor adjustment region 135a and a first drain conductor adjustment region 136a. On the other hand, the thin-film transistor according to the comparative example does not include the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a (see Figure 16B). The thin-film transistor according to the embodiment may further include a second source conductor adjustment region 135b and a second drain conductor adjustment region 136b.

[0159] In the embodiment including the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a, conductor penetration can be prevented or controlled at the boundary between the channel region 130a and the source region 130b, and at the boundary between the channel region 130a and the drain region 130c. As a result, even when the channel region 130a of the active layer 130 has a large channel width (W), the channel width (W) of the region where conductor formation progresses becomes narrower, and conductor formation into the channel region 130a can be suppressed or controlled.

[0160] Therefore, when conduction into the channel region 130a is suppressed or controlled, the conduction penetration depth (ΔL) becomes shorter, resulting in a relatively larger effective channel length. Furthermore, when conduction into the channel region 130a is suppressed or controlled, the threshold voltage (Vth) of the thin-film transistor can be controlled to shift in the negative direction, thereby improving the driving stability of the thin-film transistor.

[0161] Referring to Figure 16B, in the comparative example that does not include the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a, conductor formation can progress at the boundary between the channel region 130a and the source region 130b, and at the boundary between the channel region 130a and the drain region 130c.

[0162] Therefore, as conduction progresses into the channel region 130a, the conduction penetration depth (ΔL) increases, resulting in a relatively shorter effective channel length. Furthermore, as conduction progresses into the channel region 130a, the threshold voltage (Vth) of the thin-film transistor shifts to the negative (-) direction, potentially reducing the driving stability of the thin-film transistor.

[0163] When comparing a thin-film transistor according to an embodiment of the present invention having an active layer 130 including a first source conductor adjustment region 135a and a first drain conductor adjustment region 136a with a thin-film transistor according to a comparative example of the present invention having an active layer 130 that does not include the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a, it can be confirmed that, at the same ON current, the threshold voltage (Vth) of the thin-film transistor according to the comparative example of the present invention shifts in the negative direction.

[0164] Figure 17 is a graph of the carrier concentration in each region of the active layer 130. More specifically, Figure 17 is a graph of the carrier concentration in the active layer 130 from VII to VII'. Here, the active layer 130 can be made of an oxide semiconductor material.

[0165] The horizontal axis of the graph in Figure 17 represents the source region 130b, the channel region 130a, and the drain region 130c, respectively. The first source conductor adjustment region 135a overlaps with the source region 130b and the channel region 130a, and the first drain conductor adjustment region 136a overlaps with the channel region 130a and the drain region 130c. The horizontal axis of Figure 17 can correspond to the distance measured from the left edge of the active layer 130 shown in Figure 17.

[0166] The vertical axis of the graph in Figure 17 represents carrier concentration (au).

[0167] Referring to Figure 17, the first active layer 131 may not be laminated in the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a, or the thickness of the first active layer 130 may be thin. As a result, the dopant concentration in the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a may be low or almost nonexistent. Therefore, the carrier concentration in the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a may be absent or very low. On the other hand, the thickness of the first active layer 131 located in the channel region 130a, excluding the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a, is greater than the thickness of the first active layer 131 located in the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a. Therefore, the carrier concentration in the channel region 130a, excluding the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a, is greater than the carrier concentration in the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a. The source region 130b and the drain region 130c are regions formed by conductor formation and have high carrier concentrations.

[0168] Figure 18 is a graph of the carrier concentration in each region of the active layer 130. More specifically, Figure 18 is a graph of the carrier concentration in the IX-IX' region of the active layer 130. Here, the active layer 130 can be made of an oxide semiconductor material.

[0169] The vertical axis of the graph in Figure 18 is the same as that of Figure 17 and is therefore omitted.

[0170] The horizontal axis of the graph in Figure 18 represents the source region 130b, the channel region 130a, and the drain region 130c, respectively, with the channel region 130a including the first diffusion region (A1) and the second diffusion region (A2). The horizontal axis of Figure 18 can correspond to the distance measured from the left edge of the active layer 130 shown in Figure 18.

[0171] Referring to Figure 18, the channel region 130a, excluding the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a, has a high carrier concentration, while the source region 130b and drain region 130c, which are formed by conductor formation, also have high carrier concentrations. Furthermore, a carrier concentration gradient is formed in the first diffusion region (A1) and the second diffusion region (A2).

[0172] According to one embodiment of the present invention, the first diffusion region (A1) has a carrier concentration gradient that decreases along the direction away from the source region 130b. Specifically, referring to the graph in Figure 18, the carrier concentration is highest in the source region 130b, the carrier concentration in the first diffusion region (A1) decreases gradually as it moves away from the source region 130b, and the carrier concentration is lowest in the region of the channel region 130a that is not the first diffusion region (A1) or the second diffusion region (A2).

[0173] According to one embodiment of the present invention, the second diffusion region (A2) has a carrier concentration gradient that decreases along the direction away from the drain region 130c. Specifically, referring to the graph in Figure 18, the carrier concentration is highest in the drain region 130c, the carrier concentration in the second diffusion region (A2) decreases gradually as it moves away from the drain region 130c, and the carrier concentration is lowest in the region of the channel region 130a that is not the first diffusion region (A1) or the second diffusion region (A2).

[0174] Figure 19 is a schematic diagram of a display device 1500 according to the present invention or another embodiment.

[0175] Another embodiment of the present invention, the display device 1500, may include a display panel 310, a gate driver 320, a data driver 330, and a control unit 340, as shown in Figure 19.

[0176] The display panel 310 includes gate lines (GL) and data lines (DL), and pixels (P) are arranged in the intersection region of the gate lines (GL) and data lines (DL). An image is displayed by driving the pixels (P). The gate lines (GL), data lines (DL), and pixels (P) can be arranged on the base substrate 110.

[0177] The control unit 340 controls the gate driver 320 and the data driver 330.

[0178] The control unit 340 outputs a gate control signal (GCS) for controlling the gate driver 320 and a data control signal (DCS) for controlling the data driver 330, using signals supplied from an external system (not shown). The control unit 340 also samples the input video data received from the external system, rearranges it, and supplies the rearranged digital video data (RGB) to the data driver 330.

[0179] The gate control signal (GCS) includes the gate start pulse (GSP), gate shift clock (GSC), gate output enable signal (GOE), start signal (Vst), and gate clock (GCLK). The gate control signal (GCS) may also include control signals for controlling the shift register.

[0180] Data control signals (DCS) include source start pulse (SSP), source shift clock signal (SSC), source output enable signal (SOE), polarity control signal (POL), etc.

[0181] The data driver 330 supplies data voltage to the data lines (DL) of the display panel 310. More specifically, the data driver 330 converts the video data (RGB) input from the control unit 340 into analog data voltage and supplies the data voltage to the data lines (DL).

[0182] According to one embodiment of the present invention, the gate driver 320 can be mounted on the display panel 310. This structure, in which the gate driver 320 is directly mounted on the display panel 310, is called a Gate In Panel (GIP) structure. More specifically, in a Gate In Panel (GIP) structure, the gate driver 320 can be placed on a base substrate 110.

[0183] A display device 1500 according to one embodiment of the present invention may include the thin-film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, and 1300 described above. According to one embodiment of the present invention, a gate driver 320 may include the thin-film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, and 1300 described above.

[0184] The gate driver 320 may include a shift register 350.

[0185] The shift register 350 sequentially supplies gate pulses to the gate line (GL) for one frame using a start signal and gate clock transmitted from the control unit 340. Here, one frame refers to the period during which one image is output via the display panel 310. The gate pulse has a turn-on voltage that can turn on the switching element (thin-film transistor) placed in the pixel (P).

[0186] Furthermore, the shift register 350 supplies a gate-off signal to the gate line (GL) during the remaining period in a frame when no gate pulse is supplied, which can turn off the switching element. Hereinafter, the gate pulse and the gate-off signal will be collectively referred to as the scan signal (SS or Scan).

[0187] The shift register 350 may include the thin-film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, and 1300 mentioned above.

[0188] Figure 20 is a schematic diagram of the shift register 350.

[0189] Referring to Figure 20, the shift register 350 can contain g stages 351 (ST1 to STg).

[0190] The shift register 350 transmits one scan signal (SS) to a pixel (P) connected to one gate line (GL) via one gate line (GL). Each of the stages 351 can be connected to one gate line (GL). If g gate lines (GL) are formed on the display panel 110, the shift register 350 can contain g stages 351 (ST1 to STg) and generate g scan signals (SS1 to SSg).

[0191] Generally, each stage 351 outputs a gate pulse (GP) once per frame, and the gate pulses (GP) are output sequentially by each stage 351.

[0192] Figure 21 is the circuit diagram of one of the pixels (P) in Figure 19.

[0193] Figure 21 is an equivalent circuit diagram for a pixel (P) of a display device 1500 that includes an organic light-emitting diode (OLED) as the display element 710.

[0194] Referring to Figure 21, a pixel (P) includes a display element 710 and a pixel driver circuit (PDC) that drives the display element 710. More specifically, a display device 1500 according to one embodiment of the present invention may include a pixel driver circuit (PDC) on a base substrate 110.

[0195] The pixel driver circuit (PDC) in Figure 21 includes a first thin-film transistor (TR1) which is a switching transistor and a second thin-film transistor (TR2) which is a driving transistor. Another embodiment of the present invention, the display device 1500, may include at least one of the thin-film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, and 1300.

[0196] The first thin-film transistor (TR1) is connected to a gate line (GL) and a data line (DL), and is turned on or off by a scan signal (SS) supplied via the gate line (GL).

[0197] The data line (DL) provides the data voltage (Vdata) to the pixel drive circuit (PDC), and the first thin-film transistor (TR1) controls the application of the data voltage (Vdata).

[0198] The drive power line (PL) provides a drive voltage (Vdd) to the display element 710, and the first thin-film transistor (TR1) controls the drive voltage (Vdd). The drive voltage (Vdd) is the pixel drive voltage for driving the organic light-emitting diode (OLED), which is the display element 710.

[0199] When the first thin-film transistor (TR1) is turned on by a scan signal (SS) applied from the gate driver 320 via the gate line (GL), a data voltage (Vdata) supplied via the data line (DL) is supplied to the gate electrode of the second thin-film transistor (TR2) connected to the display element 710. The data voltage (Vdata) charges the storage capacitor (Cst) formed between the gate electrode and source electrode of the second thin-film transistor (TR2).

[0200] The amount of current supplied to the organic light-emitting diode (OLED), which is the display element 710, via the second thin-film transistor (TR2) is controlled by the data voltage (Vdata), thereby controlling the gradation of the light output from the display element 710.

[0201] Figure 22 is a circuit diagram of any one pixel (P) of the display device 1600 according to the present invention or other embodiments.

[0202] Figure 22 is an equivalent circuit diagram for a pixel (P) of an organic light-emitting display device.

[0203] The pixels (P) of the display device 1600 shown in Figure 22 include an organic light-emitting diode (OLED), which is a display element 710, and a pixel driver circuit (PDC) that drives the display element 710. The display element 710 is connected to the pixel driver circuit (PDC).

[0204] Each pixel (P) has signal lines (DL, GL, PL, RL, SCL) that supply signals to the pixel drive circuit (PDC).

[0205] The data line (DL) is supplied with a data voltage (Vdata), the gate line (GL) is supplied with a scan signal (SS), the drive power line (PL) is supplied with a drive voltage (Vdd) to drive the pixels, the reference line (RL) is supplied with a reference voltage (Vref), and the sensing control line (SCL) is supplied with a sensing control signal (SCS).

[0206] The pixel drive circuit (PDC) includes, for example, a first thin-film transistor (TR1) (switching transistor) connected to the gate line (GL) and the data line (DL), a second thin-film transistor (TR2) (drive transistor) that controls the magnitude of the current output to the display element 710 by the data voltage (Vdata) transmitted through the first thin-film transistor (TR1), and a third thin-film transistor (TR3) (sensing transistor) for sensing the characteristics of the second thin-film transistor (TR2).

[0207] The first thin-film transistor (TR1) is turned on by a scan signal (SS) supplied to the gate line (GL), and transmits the data voltage (Vdata) supplied to the data line (DL) to the gate electrode of the second thin-film transistor (TR2).

[0208] The third thin-film transistor (TR3) is connected to the first node (n1) and reference line (RL) between the second thin-film transistor (TR2) and the display element 710, and is turned on or off by a sensing control signal (SCS) to sense the characteristics of the second thin-film transistor (TR2), which is the driving transistor, during the sensing period.

[0209] A second node (n2) connected to the gate electrode of the second thin-film transistor (TR2) can be connected to the first thin-film transistor (TR1). A storage capacitor (Cst) is formed between the second node (n2) and the first node (n1).

[0210] When the first thin-film transistor (TR1) is turned on, the data voltage (Vdata) supplied via the data line (DL) is supplied to the gate electrode of the second thin-film transistor (TR2). The data voltage (Vdata) charges the storage capacitor (Cst) formed between the gate electrode and source electrode of the second thin-film transistor (TR2).

[0211] When the second thin-film transistor (TR2) is turned on, a current is supplied to the display element 710 via the second thin-film transistor (TR2) by the drive voltage (Vdd) that drives the pixels, and light is output from the display element 710.

[0212] A display device 1600 according to yet another embodiment of the present invention may include at least one of the thin-film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, and 1300.

[0213] Figure 23 is a circuit diagram of any one pixel (P) of the display device 1700 according to the present invention or another embodiment.

[0214] The pixels (P) of the display device 1700 shown in Figure 23 include an organic light-emitting diode (OLED), which is a display element 710, and a pixel driver circuit (PDC) that drives the display element 710. The display element 710 is connected to the pixel driver circuit (PDC).

[0215] The pixel drive circuit (PDC) includes thin-film transistors (TR1, TR2, TR3, TR4).

[0216] Each pixel (P) has signal lines (DL, EL, GL, PL, SCL, RL) that supply drive signals to the pixel drive circuit (PDC).

[0217] The pixel (P) in Figure 23 further includes an emission control line (EL) compared to the pixel (P) in Figure 22. An emission control signal (EM) is supplied to the emission control line (EL). Furthermore, the pixel driver circuit (PDC) in Figure 23 further includes a fourth thin-film transistor (TR4), which is an emission control transistor for controlling the emission timing of the second thin-film transistor (TR2), compared to the pixel driver circuit (PDC) in Figure 22.

[0218] The first thin-film transistor (TR1) is turned on by a scan signal (SS) supplied to the gate line (GL), and transmits the data voltage (Vdata) supplied to the data line (DL) to the gate electrode of the second thin-film transistor (TR2).

[0219] A storage capacitor (Cst) is located between the gate electrode of the second thin-film transistor (TR2) and the display element 710.

[0220] The third thin-film transistor (TR3) is connected to the reference line (RL) and is turned on or off by the sensing control signal (SCS), sensing the characteristics of the second thin-film transistor (TR2), which is the driving transistor, during the sensing period.

[0221] The fourth thin-film transistor (TR4) either transmits a drive voltage (Vdd) to the second thin-film transistor (TR2) or cuts off the drive voltage (Vdd) in response to the light emission control signal (EM). When the fourth thin-film transistor (TR4) is turned on, current is supplied to the second thin-film transistor (TR2), and light is output from the display element 710.

[0222] Pixel driving circuits (PDCs) according to other embodiments of the present invention can be formed with various structures other than those described above. For example, a pixel driving circuit (PDC) may include five or more thin-film transistors.

[0223] The present invention, as described above, is not limited by the embodiments and accompanying figures, and it will be apparent to those with ordinary skill in the art to which the invention pertains that various substitutions, modifications, and alterations are possible without departing from the technical matters of the invention. Accordingly, the scope of the invention is indicated by the claims described below, and all modified or altered forms derived from the meaning, scope, and equivalent concepts of the claims should be interpreted as being included within the scope of the invention. [Explanation of Symbols]

[0224] 110: Base board 120: Buffer layer 130: Active layer 130a: Channel area 130b: Source area 130c: Drain area 131: First Active Tier 132: Second Active Layer 131a: First oxide semiconductor layer 131b: Second oxide semiconductor layer 132a: Third oxide semiconductor layer 132b: Quaternary oxide semiconductor layer 135a: First source conductor adjustment region 135b: Second source conductor adjustment region 136a: First drain conductor adjustment region 136b: Second drain conductor adjustment region 140: Gate Insulator 150: Gate Shutdown 160: Interlayer insulating film 171: Source electrode 172: Drain electrode

Claims

1. Active users and It includes a gate electrode that is separated from the active layer and superimposed on the active layer in at least a portion thereof, The aforementioned active layer, In a planar view, the channel region superimposed on the gate electrode, In a plan view, the source region is not superimposed on the gate electrode and is connected to one side of the channel region, In a plan view, it includes a drain region that does not overlap the gate electrode and is connected to the other side of the channel region, The source region and the drain region are separated from each other with the channel region in between. The active layer includes a first source conductor adjustment region and a first drain conductor adjustment region that are separated from each other. At least a portion of the first source conductor adjustment region is superimposed on at least a portion of the gate electrode, At least a portion of the first drain conductor adjustment region is superimposed on at least a portion of the gate electrode, The channel region includes an area extending from the first source conductor adjustment region to the first drain conductor adjustment region, based on the longitudinal direction of the channel region. The thickness of the said region is the same as the thickness of the source region and the drain region. The channel region has a first diffusion region and a second diffusion region that are separated from each other. The first diffusion region is positioned on the channel region and in contact with the source region. The second diffusion region is located on the channel region and is in contact with the drain region. The first diffusion region and the second diffusion region do not overlap the first source conductor adjustment region and the first drain conductor adjustment region. The first diffusion region has a carrier concentration gradient that decreases along the direction away from the source region, A thin-film transistor in which the second diffusion region has a carrier concentration gradient that decreases along the direction away from the drain region.

2. The thin-film transistor according to claim 1, wherein the first drain conductor adjustment region is arranged on a first line which is the shortest line connecting the source region and the drain region, crossing the first source conductor adjustment region.

3. The thin-film transistor according to claim 1, wherein the active layer is not present in at least a portion of the first source conductor adjustment region and the first drain conductor adjustment region.

4. The active layer includes a first active layer and a second active layer on the first active layer. The thin-film transistor according to claim 1, wherein the first active layer is disposed in at least a portion of the channel region, at least a portion of the source region, and at least a portion of the drain region.

5. The thickness of the first active layer located in the first source conductor adjustment region is thinner than the thickness of the first active layer located in the channel region excluding the first source conductor adjustment region. The thin-film transistor according to claim 4, wherein the thickness of the first active layer disposed in the first drain conductor adjustment region is thinner than the thickness of the first active layer disposed in the channel region excluding the first drain conductor adjustment region.

6. The first active layer is not located in at least a portion of the first source conductor adjustment region and the first drain conductor adjustment region. The thin-film transistor according to claim 4, wherein the second active layer is arranged across the entire channel region, the entire source region, and the entire drain region.

7. The second active layer is arranged in the first source conductor adjustment region and the first drain conductor adjustment region. The thin-film transistor according to claim 4, wherein at least a portion of the second active layer is in contact with the side surface of the first active layer within the first source conductor adjustment region and the first drain conductor adjustment region.

8. The thin-film transistor according to claim 4, wherein the first active layer includes a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer.

9. The thin-film transistor according to claim 4, wherein the second active layer includes a tertiary oxide semiconductor layer and a quaternary oxide semiconductor layer on the tertiary oxide semiconductor layer.

10. The active layer further includes a second active layer on the first active layer, The thin-film transistor according to claim 8, wherein at least a portion of the second active layer is in contact with one of the first oxide semiconductor layer and the second oxide semiconductor layer within the first source conductor adjustment region and the first drain conductor adjustment region.

11. The thin-film transistor according to claim 9, wherein at least a portion of the first active layer is in contact with at least a portion of the third oxide semiconductor layer within the first source conductor adjustment region and the first drain conductor adjustment region.

12. At least a portion of the end of the first source conductor adjustment region is positioned at the boundary between the gate electrode and the source region in a plan view, The thin-film transistor according to claim 1, wherein the first source conductor adjustment region does not protrude from the gate electrode toward the source region in a plan view.

13. At least a portion of the end of the first drain conductor adjustment region is positioned at the boundary between the gate electrode and the drain region in a plan view. The thin-film transistor according to claim 1, wherein the first drain conductor adjustment region does not protrude from the gate electrode toward the drain region in a plan view.

14. The thin-film transistor according to claim 1, wherein the first source conductor adjustment region protrudes from the gate electrode toward the source region in a plan view.

15. The thin-film transistor according to claim 1, wherein the first drain conductor adjustment region protrudes from the gate electrode toward the drain region in a plan view.

16. The thin-film transistor according to claim 1, wherein the first source conductor adjustment region is arranged in a plan view at a distance from the boundary between the gate electrode and the source region.

17. The thin-film transistor according to claim 1, wherein the first drain conductor adjustment region is arranged in a plan view at a distance from the boundary between the gate electrode and the drain region.

18. The active layer includes a second source conductor adjustment region and a second drain conductor adjustment region that are separated from each other. At least a portion of the second source conductor adjustment region is superimposed on at least a portion of the gate electrode, At least a portion of the second drain conductor adjustment region is superimposed on at least a portion of the gate electrode, The first source conductor adjustment region and the second source conductor adjustment region are separated from each other. The thin-film transistor according to claim 1, wherein the first drain conductor adjustment region and the second drain conductor adjustment region are separated from each other.

19. The first source conductor adjustment region and the second source conductor adjustment region are arranged at intervals of 0.5 to 20 μm. The thin-film transistor according to claim 18, wherein the first drain conductor adjustment region and the second drain conductor adjustment region are arranged at intervals of 0.5 to 20 μm.

20. The thin-film transistor according to claim 18, wherein at least one of the first source conductor adjustment region and the second source conductor adjustment region protrudes from the gate electrode toward the source region in a plan view.

21. The thin-film transistor according to claim 18, wherein at least one of the first drain conductor adjustment region and the second drain conductor adjustment region protrudes from the gate electrode toward the drain region in a plan view.

22. The first source conductor adjustment region is located at the longitudinal edge (R) of the channel region in a plan view, The thin-film transistor according to claim 1, wherein the longitudinal direction of the channel region is the direction connecting the source region and the drain region.

23. The first drain conductor adjustment region is located at the longitudinal edge (R) of the channel region in a plan view. The thin-film transistor according to claim 1, wherein the longitudinal direction of the channel region is the direction connecting the source region and the drain region.

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