Silicon-based Josephson junction for qubit devices

Abstract

To provide a qubit device which includes a Josephson junction including superconducting silicon material implemented in a vertical structure orientation, and a method for manufacturing the same.SOLUTION: A qubit device 100 includes a Josephson junction that includes a tunnel barrier 106 disposed between two vertically stacked superconducting silicon electrodes 102, 104.SELECTED DRAWING: Figure 1A

Description

Technical Field

[0001] The present disclosure relates to one or more silicon-based Josephson junctions that can be incorporated into qubit devices, and more particularly to Josephson junctions comprising superconducting silicon materials that can be implemented in vertical structure orientation.

Summary of the Invention

[0002] The following presents a summary to provide a basic understanding of one or more embodiments of the present invention. This summary is not intended to identify key or critical elements, nor to delineate any scope of particular embodiments or any scope of the claims. Its sole purpose is to present concepts in a summary form as a preface to the more detailed description presented later. In one or more embodiments described herein, an apparatus and / or method relating to a silicon-based Josephson junction for one or more qubit devices is described.

[0003] According to one embodiment, an apparatus is provided. The apparatus may comprise a Josephson junction including a tunnel barrier disposed between two vertically stacked superconducting silicon electrodes.

[0004] According to another embodiment, an apparatus is provided. The apparatus may comprise a Josephson junction including a dielectric tunnel barrier disposed between two superconducting silicon electrodes.

[0005] According to one embodiment, a method is provided. The method may include doping a portion of a silicon substrate to form a first superconducting electrode. The method may also include depositing a silicon layer on the first superconducting electrode via an epitaxial growth process to form a tunnel barrier. Further, the method may include doping a portion of the tunnel barrier to form a second superconducting electrode, thereby forming a Josephson junction.

Brief Description of the Drawings

[0006] [Figure 1A] This is an exemplary and non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction that can be oriented in a vertical stack, according to one or more embodiments described herein. [Figure 1B] This is an exemplary and non-limiting top view of a device comprising a silicon-based Josephson junction that can be oriented in a vertical stack, according to one or more embodiments described herein. [Figure 2] This is an exemplary and non-limiting cross-sectional view of an apparatus comprising a silicon-based Josephson junction during a first step of manufacturing, according to one or more embodiments described herein. [Figure 3] This is an exemplary and non-limiting cross-sectional view of an apparatus comprising a silicon-based Josephson junction during a second step of manufacturing, according to one or more embodiments described herein. [Figure 4] This is an exemplary and non-limiting cross-sectional view of an apparatus comprising a silicon-based Josephson junction during a third step of manufacturing, according to one or more embodiments described herein. [Figure 5A] This is an exemplary and non-limiting cross-sectional view of an apparatus comprising a silicon-based Josephson junction during a fourth step of manufacturing, according to one or more embodiments described herein. [Figure 5B] This is an exemplary and non-limiting top view of an apparatus comprising a silicon-based Josephson junction during a fourth step of manufacturing, according to one or more embodiments described herein. [Figure 6A] This is an exemplary and non-limiting cross-sectional view of an apparatus having a silicon-based Josephson junction during a fifth step of manufacturing, according to one or more embodiments described herein. [Figure 6B] This is an exemplary and non-limiting top view of an apparatus comprising a silicon-based Josephson junction during a fifth step of manufacturing, according to one or more embodiments described herein. [Figure 7A]This is an exemplary and non-limiting cross-sectional view of an apparatus having a silicon-based Josephson junction during a sixth step of manufacturing, according to one or more embodiments described herein. [Figure 7B] This is an exemplary and non-limiting top view of an apparatus comprising a silicon-based Josephson junction during a sixth step of manufacturing, according to one or more embodiments described herein. [Figure 8A] This is an exemplary and non-limiting cross-sectional view of an apparatus comprising a silicon-based Josephson junction during a seventh step of manufacturing, according to one or more embodiments described herein. [Figure 8B] This is an exemplary and non-limiting top view of an apparatus comprising a silicon-based Josephson junction during a seventh step of manufacturing, according to one or more embodiments described herein. [Figure 9A] This is an exemplary and non-limiting cross-sectional view of an apparatus comprising a silicon-based Josephson junction during an eighth step of manufacturing, according to one or more embodiments described herein. [Figure 9B] This is an exemplary and non-limiting top view of an apparatus comprising a silicon-based Josephson junction during an eighth step of manufacturing, according to one or more embodiments described herein. [Figure 10A] This is an exemplary and non-limiting cross-sectional view of an apparatus comprising a silicon-based Josephson junction during the ninth step of manufacturing, according to one or more embodiments described herein. [Figure 10B] This is an exemplary and non-limiting top view of an apparatus comprising a silicon-based Josephson junction during the ninth step of manufacturing, according to one or more embodiments described herein. [Figure 11A] This is an exemplary and non-limiting cross-sectional view of an apparatus having a silicon-based Josephson junction during a tenth step of manufacturing, according to one or more embodiments described herein. [Figure 11B]This is an exemplary and non-limiting top view of an apparatus comprising a silicon-based Josephson junction during a tenth step of manufacturing, according to one or more embodiments described herein. [Figure 12A] This is an exemplary and non-limiting cross-sectional view of a device comprising a silicon-based Josephson joint having one or more isolation implants, according to one or more embodiments described herein. [Figure 12B] This is an exemplary and non-limiting top view of a device comprising a silicon-based Josephson joint having one or more isolation implants, according to one or more embodiments described herein. [Figure 13] This is an exemplary and non-limiting cross-sectional view of an apparatus comprising a silicon-based Josephson junction during a first step of manufacturing, according to one or more embodiments described herein. [Figure 14A] This is an exemplary and non-limiting cross-sectional view of an apparatus comprising a silicon-based Josephson junction during a second step of manufacturing, according to one or more embodiments described herein. [Figure 14B] This is an exemplary and non-limiting top view of an apparatus comprising a silicon-based Josephson junction during a second stage of manufacturing, according to one or more embodiments described herein. [Figure 15A] This is an exemplary and non-limiting cross-sectional view of an apparatus comprising a silicon-based Josephson junction during a third step of manufacturing, according to one or more embodiments described herein. [Figure 15B] This is an exemplary and non-limiting top view of an apparatus comprising a silicon-based Josephson junction during a third stage of manufacturing, according to one or more embodiments described herein. [Figure 16A] This is an exemplary and non-limiting cross-sectional view of an apparatus comprising a silicon-based Josephson junction during a fourth step of manufacturing, according to one or more embodiments described herein. [Figure 16B]It is an exemplary, non-limiting top view of a device comprising a silicon-based Josephson junction during a fourth manufacturing stage, according to one or more embodiments described in this specification. [Figure 17A] It is an exemplary, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during a fifth manufacturing stage, according to one or more embodiments described in this specification. [Figure 17B] It is an exemplary, non-limiting top view of a device comprising a silicon-based Josephson junction during a fifth manufacturing stage, according to one or more embodiments described in this specification. [Figure 18A] It is an exemplary, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during a sixth manufacturing stage, according to one or more embodiments described in this specification. [Figure 18B] It is an exemplary, non-limiting top view of a device comprising a silicon-based Josephson junction during a sixth manufacturing stage, according to one or more embodiments described in this specification. [Figure 19A] It is an exemplary, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during a seventh manufacturing stage, according to one or more embodiments described in this specification. [Figure 19B] It is an exemplary, non-limiting top view of a device comprising a silicon-based Josephson junction during a seventh manufacturing stage, according to one or more embodiments described in this specification. [Figure 20A] It is an exemplary, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during an eighth manufacturing stage, according to one or more embodiments described in this specification. [Figure 20B] It is an exemplary, non-limiting top view of a device comprising a silicon-based Josephson junction during an eighth manufacturing stage, according to one or more embodiments described in this specification. [Figure 21A]It is an exemplary, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during the ninth manufacturing step, in accordance with one or more embodiments described herein. [Figure 21B] It is an exemplary, non-limiting top view of a device comprising a silicon-based Josephson junction during the ninth manufacturing step, in accordance with one or more embodiments described herein. [Figure 22A] It is an exemplary, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during the tenth manufacturing step, in accordance with one or more embodiments described herein. [Figure 22B] It is an exemplary, non-limiting top view of a device comprising a silicon-based Josephson junction during the tenth manufacturing step, in accordance with one or more embodiments described herein. [Figure 23A] It is an exemplary, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during the eleventh manufacturing step, in accordance with one or more embodiments described herein. [Figure 23B] It is an exemplary, non-limiting top view of a device comprising a silicon-based Josephson junction during the eleventh manufacturing step, in accordance with one or more embodiments described herein. [Figure 24A] It is an exemplary, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during the twelfth manufacturing step, in accordance with one or more embodiments described herein. [Figure 24B] It is an exemplary, non-limiting top view of a device comprising a silicon-based Josephson junction during the twelfth manufacturing step, in accordance with one or more embodiments described herein. [Figure 25A] It is an exemplary, non-limiting cross-sectional view of a device comprising a silicon-based Josephson junction during the thirteenth manufacturing step, in accordance with one or more embodiments described herein. [Figure 25B]This is an exemplary and non-limiting top view of an apparatus comprising a silicon-based Josephson junction during a thirteenth step of manufacturing, according to one or more embodiments described herein. [Figure 26A] This is an exemplary and non-limiting cross-sectional view of an apparatus having a silicon-based Josephson junction during a 14th step of manufacturing, according to one or more embodiments described herein. [Figure 26B] This is an exemplary and non-limiting top view of an apparatus comprising a silicon-based Josephson junction during a 14th step of manufacturing, according to one or more embodiments described herein. [Figure 27A] This is an exemplary and non-limiting cross-sectional view of an apparatus having a silicon-based Josephson junction during a 15th step of manufacturing, according to one or more embodiments described herein. [Figure 27B] This is an exemplary and non-limiting top view of an apparatus comprising a silicon-based Josephson junction during a 15th step of manufacturing, according to one or more embodiments described herein. [Figure 28] This is an exemplary, non-limiting flowchart of a method that can facilitate the manufacture of one or more silicon-based Josephson junctions according to one or more embodiments described herein. [Figure 29] This is an exemplary, non-limiting flowchart of a method that can facilitate the manufacture of one or more silicon-based Josephson junctions according to one or more embodiments described herein. [Modes for carrying out the invention]

[0007] The following detailed description is illustrative only and is not intended to limit the embodiments, uses, or both of the embodiments. Furthermore, it is not intended to be bound by any representations or implied information presented in the prior art or summary section or the section on embodiments for carrying out the invention.

[0008] Hereafter, one or more embodiments will be described with reference to the drawings, in which similar reference numerals will be used throughout to refer to similar elements. In the following description, for illustrative purposes, a number of specific details will be mentioned for the purpose of giving a more complete understanding of one or more embodiments. However, it will be clear that in various cases one or more embodiments may be carried out without such specific details. Furthermore, features shown in the drawings, along with similar shading, cross-hatching, or color coding, or combinations thereof, may include common compositions or materials, or both.

[0009] Josephson junctions have been used to fabricate qubits (e.g., superconducting qubits) with the aim of increasing the coherence time exhibited by quantum computing devices. However, the theoretical coherence time associated with Josephson junctions is often shorter than that actually exhibited by qubits. The material composition of the Josephson junction can affect the coherence time. For example, the type of superconducting material used, impurities in the superconducting material, or defects introduced by the manufacturing process of the superconducting material, or a combination thereof, can adversely affect the coherence time exhibited by Josephson junction qubits. For example, an aluminum-based Josephson junction may exhibit a longer coherence time than a niobium-based Josephson junction, but it can still be subject to decoherence caused by defects (e.g., aluminum oxide defects) commonly introduced during the manufacturing or deposition of aluminum or aluminum derivatives or both.

[0010] Various embodiments described herein may relate to apparatus or methods, or both, for manufacturing silicon-based Josephson junctions for incorporation into one or more qubit devices. For example, one or more embodiments may relate to a Josephson junction comprising a crystalline silicon material, such as a doped superconducting silicon electrode, where single-crystal undoped silicon acts as the junction. By using silicon materials, chemical purification, crystal growth, or defect control, or a combination thereof, can be achieved in various embodiments described herein while implementing complementary metal-oxide-semiconductor ("CMOS") technology. In one or more embodiments, the silicon-based Josephson junction may include a silicon dielectric material as a tunnel barrier to the two superconducting silicon electrodes. Furthermore, one or more embodiments may include oriented the silicon-based Josephson junction structure in a vertical orientation. Furthermore, in various embodiments, electrical isolation of the Josephson junction can be achieved via intrinsic silicon, or the incorporation of one or more isolation implants into the silicon, or both.

[0011] As described herein, the term “superconducting” may characterize a material that exhibits superconducting properties below its superconducting critical temperature. Furthermore, as described herein, the term “deposition process” may refer to any process of growing, coating, depositing, or transferring one or more first materials onto one or more second materials, or a combination thereof. Exemplary deposition processes include, but are not limited to, physical vapor deposition ("PVD"), chemical vapor deposition ("CVD"), electrochemical deposition ("ECD"), atomic layer deposition ("ALD"), low-pressure chemical vapor deposition ("LPCVD"), plasma-enhanced chemical vapor deposition ("PECVD"), high-density plasma chemical vapor deposition ("HDPCVD"), near-atmospheric pressure chemical vapor deposition ("SACVD"), rapid thermochemical vapor deposition ("RTCVD"), and in-situ radical-assisted deposition. This may include deposition, high-temperature oxide deposition ("HTO"), low-temperature oxide deposition ("LTO"), limited-reaction chemical vapor deposition ("LRPCVD"), ultra-high vacuum chemical vapor deposition ("UHVCVD"), metal-organic chemical vapor deposition ("MOCVD"), physical vapor deposition ("PVD"), chemical oxidation, sputtering, plating, vapor deposition, spin-on coating, ion beam deposition, electron beam deposition, laser-assisted deposition, or chemical solution deposition, or combinations thereof.

[0012] As described herein, the terms “epitaxial growth process” or “epitaxial growth process” or both may refer to any process for growing an epitaxial material (e.g., a crystalline semiconductor material) on a deposited surface of another semiconductor material, and the grown epitaxial material has substantially the same crystalline properties as the semiconductor material on the deposited surface. In an epitaxial deposition process, the chemical reactants supplied by a source gas (e.g., a gas containing silicon or germanium or both) or a source liquid or both may be controlled, system parameters may be set, and as a result, the deposited atoms arrive at the deposition surface with sufficient energy to move around on the surface and orient themselves relative to the crystalline structure of the atoms on the deposition surface. Thus, the grown epitaxial material has substantially the same crystalline properties as the deposited surface on which the epitaxial material is formed. For example, <100> Epitaxially grown semiconductor material deposited on a crystal surface oriented in a certain direction is <100> It may have an orientation. Exemplary epitaxial growth processes may include, but are not limited to, gas-phase epitaxy ("VPE"), molecular beam epitaxy ("MBE"), or liquid-phase epitaxy ("LPE"), or a combination thereof.

[0013] As described herein, the terms “etching process” or “removal process” or both may refer to any process for removing one or more first materials from one or more second materials. Exemplary etching processes or removal processes or both may include, but are not limited to, wet etching, dry etching (e.g., reactive ion etching ("RIE")), or chemical mechanical planarization ("CMP"), or a combination thereof.

[0014] As described herein, the term “laser doping process” may refer to one or more gas immersion laser doping techniques capable of achieving a homogeneous doped layer of silicon with varying active concentration, thickness, or both. The laser doping process may be carried out in an ultra-high vacuum ("UHV") chamber, and a precursor gas (e.g., boron trichloride) may be injected into the chamber and onto the surface of the silicon material (e.g., thereby saturating one or more chemiadsorption sites in the silicon material). Subsequently, the silicon material may be melted using a pulsed laser (e.g., a pulsed excimer XeCl laser) to heat the silicon material for a defined duration. One or more dopants (e.g., boron, gallium, or germanium, or a combination thereof) from the precursor gas may diffuse into the silicon material and be incorporated substitutionally. This allows silicon dopant crystals (e.g., silicon-boron (Si:B), silicon-germanium (Si:Ge), or silicon-gallium (Si:Ga)) to grow on the underlying silicon via one or more epitaxial growth processes.

[0015] Figure 1A or Figure 1B, or both, shows an exemplary and non-limiting qubit device 100 that may include a silicon-based Josephson junction comprising a first superconducting silicon electrode 102, a second superconducting silicon electrode 104, or a tunnel barrier 106, or a combination thereof, according to one or more embodiments described herein. Figure 1A shows a cross-sectional view of the qubit device 100, and Figure 1B shows a top view of the qubit device 100. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted.

[0016] As shown in Figure 1A, a silicon-based Josephson junction may be located on a semiconductor substrate 108. Furthermore, a first superconducting silicon electrode 102, a second superconducting silicon electrode 104, or a dielectric tunnel barrier 106, or a combination thereof, may be stacked on the semiconductor substrate 108 in a vertical orientation (for example, along the "Y" axis). Furthermore, at least a portion of the semiconductor substrate 108 and one or more isolation layers 110 may form an isolation region 112 adjacent to the silicon-based Josephson junction (for example, shown by a bold dashed line). Furthermore, the silicon-based Josephson junction may include a first metal contact 114 operably coupled to the first superconducting silicon electrode 102, or a second metal contact 116 operably coupled to the second superconducting silicon electrode 104, or both.

[0017] The semiconductor substrate 108 may be crystalline, quasicrystalline, microcrystalline, or amorphous. The semiconductor substrate 108 may essentially consist of a single element (e.g., silicon or germanium) or a compound (e.g., aluminum oxide, silicon dioxide, gallium arsenide, silicon carbide, or silicon-germanium, or a combination thereof) (e.g., aluminum oxide, silicon dioxide, gallium arsenide, silicon carbide, or silicon-germanium, or a combination thereof). The semiconductor substrate 110 may also have multiple material layers, including, but are not limited to, a semiconductor-on-insulator substrate ("SeOI"), a silicon-on-insulator substrate ("SOI"), a germanium-on-insulator substrate ("GeOI"), or a silicon-germanium-on-insulator substrate ("SGOI"), or a combination thereof. Furthermore, the semiconductor substrate 110 may also have other layers, such as a high-dielectric constant oxide ("high-K oxide") or nitride, or both. In one or more embodiments, the semiconductor substrate 110 may be a silicon wafer. In various embodiments, the semiconductor substrate 110 may include single-crystal silicon (Si), silicon-germanium (for example, characterized by the chemical formula SiGe), or a III-V semiconductor wafer or surface / active layer, or a combination thereof.

[0018] In one or more embodiments, at least the upper portion of the semiconductor substrate 108 may provide structural support for a silicon-based Josephson junction or qubit device 100 or both (for example, as shown in Figure 1A or Figure 1B or both). In various embodiments, at least the upper portion of the semiconductor substrate 108 may contain intrinsic silicon. In some embodiments, at least the upper portion of the semiconductor substrate 108 may contain silicon-germanium (SiGe).

[0019] The first superconducting silicon electrode 102 may comprise a laser-doped crystalline silicon material. For example, one or more dopants may be incorporated into a portion of the silicon material via one or more laser doping processes to enhance superconductivity. Exemplary dopants that may be included in the first superconducting silicon electrode 102 may include, but are not limited to, boron, gallium, or germanium, or combinations thereof. In one or more embodiments, the first superconducting silicon electrode 102 may have an active dopant concentration ranging from, for example, 4 atomic percentages (At%) to 40 At% (for example, if the first superconducting electrode 102 comprises a boron dopant, at least 4 At% to 11 At%; or if the first superconducting electrode 102 comprises a gallium dopant, at least 10 At% to 40 At%; or both). In various embodiments, the critical temperature of the first superconducting electrode 102 can range, for example, from 500 millikelvin (mK) or higher to 6K or lower (for example, 500 mK to 600 mK if the first superconducting electrode 102 contains a boron dopant, or 5K to 6K or both if the first superconducting electrode 102 contains a gallium dopant).

[0020] Those skilled in the art will understand that the length (for example, along the "X" axis) of the first superconducting silicon electrode 102 may vary depending on the function of the silicon-based Josephson junction, the structure of the qubit device 100, or both. For example, the length (for example, along the "X" axis) of the first superconducting silicon electrode 102 may be between 100 nanometers (nm) and several hundred microns (for example, 500 nm to 1,000 nm). Similarly, the thickness (for example, along the "Y" axis) of the first superconducting silicon electrode 102 may vary depending on the function of the silicon-based Josephson junction, the structure of the qubit device 100, or both. For example, the thickness (for example, along the "Y" axis) of the first superconducting silicon electrode 102 may be between 5 nm and 500 nm (for example, 10 nm to 50 nm). Furthermore, in one or more embodiments, the first superconducting silicon electrode 102 may be embedded in a semiconductor substrate 108 (for example, as shown in Figure 1A).

[0021] In one or more embodiments, a tunnel barrier 106, one or more isolation layers 110, or a first metal contact, or a combination thereof, may be located on (for example, immediately above) the first superconducting silicon electrode 102. The tunnel barrier 106 is shown as a dashed line in Figure 1A. In various embodiments, the tunnel barrier 106 may include a dielectric material to make the silicon-based Josephson junction a superconductor-insulator-superconductor ("SIS") Josephson junction. For example, the tunnel barrier 106 may include an intrinsic silicon material. In one or more embodiments, the tunnel barrier 106 may include doped silicon to make the silicon-based Josephson junction a superconductor-normal-superconductor ("SNS") Josephson junction. For example, one or more dopants that may be included in the tunnel barrier 106 may include, but are not limited to, phosphorus (P) or arsenic (As) or both. Those skilled in the art will understand that the length of the tunnel barrier 106 (for example, along the "X" axis) may vary depending on the function of the silicon-based Josephson junction or the qubit device 100 or both. For example, the length of the tunnel barrier 106 (for example, along the "X" axis) may be between 30 nm and 1,000 nm (for example, between 100 nm and 300 nm). Similarly, the thickness of the tunnel barrier 106 (for example, along the "Y" axis) may vary depending on the function of the silicon-based Josephson junction or the qubit device 100 or both. For example, the thickness of the tunnel barrier 106 (for example, along the "Y" axis) may be between 0.5 nm and 300 nm.

[0022] The second superconducting silicon electrode 104 may be positioned on the tunnel barrier 106 such that the tunnel barrier 106 is located between the first superconducting silicon electrode 102 and the second superconducting silicon electrode 104. In one or more embodiments, the second superconducting silicon electrode 104 may have the same or substantially the same composition as the first superconducting silicon electrode 102. Alternatively, in one or more embodiments, the second superconducting silicon electrode 104 may have a different composition from the first superconducting silicon electrode 102.

[0023] For example, the second superconducting silicon electrode 104 may include a laser-doped crystalline silicon material. For example, one or more dopants may be incorporated into a portion of the silicon material via one or more laser doping processes to enhance superconductivity. Exemplary dopants that may be included in the second superconducting silicon electrode 104 may include, but are not limited to, boron or gallium or a combination thereof. In one or more embodiments, the second superconducting silicon electrode 104 may have an active dopant concentration in the range of, for example, 4 At% to 40 At% (for example, if the first superconducting electrode 102 includes a boron dopant, at least 4 At% to 11 At% or if the first superconducting electrode 102 includes a gallium dopant, at least 10 At% to 40 At% or both). In various embodiments, the critical temperature of the second superconducting silicon electrode 104 can range, for example, from 500 mK to 6 K (for example, 500 mK to 600 mK if the second superconducting electrode 104 contains a boron dopant, or 5 K to 6 K if the second superconducting electrode 104 contains a gallium dopant, or both).

[0024] Those skilled in the art will understand that the length of the second superconducting silicon electrode 104 (for example, along the "X" axis) may vary depending on the function of the silicon-based Josephson junction or the qubit device 100 or both. For example, the length of the second superconducting silicon electrode 104 (for example, along the "X" axis) may be between 10 nm and several hundred microns (for example, 500 nm to 1,000 nm). Similarly, the thickness of the second superconducting silicon electrode 104 (for example, along the "Y" axis) may vary depending on the function of the silicon-based Josephson junction or the qubit device 100 or both. For example, the thickness of the second superconducting silicon electrode 104 (for example, along the "Y" axis) may be between 5 nm and 500 nm (for example, 10 nm to 50 nm).

[0025] In one or more embodiments, one or more isolation layers 110 may be adjacent to a first superconducting silicon electrode 102, a tunnel barrier 106, or a second superconducting silicon electrode 104, or a combination thereof. One or more isolation layers 110 may comprise one or more insulating materials and / or may electrically isolate the silicon-based Josephson junction from adjacent hardware and / or devices (e.g., adjacent qubit devices 100). In various embodiments, one or more isolation layers 110 may comprise intrinsic silicon, or may be deposited in the same manufacturing step as the tunnel barrier 106, or both. One or more isolation layers 110 or at least a portion or both of the semiconductor substrate 108 may define an isolation region 112 (e.g., shown by a bold dashed line in Figure 1A). As shown in Figure 1A, in one or more embodiments, the semiconductor substrate 108, the tunnel barrier 106, or the isolation layers 110, or a combination thereof, may comprise the same or substantially the same material (e.g., intrinsic silicon).

[0026] As shown in Figure 1A, the first metal contact 114 or the second metal contact 116, or both, may be positioned adjacent to the isolation region 112 (for example, at the top of the isolation region 112 if the first superconducting silicon electrode 102, the tunnel barrier 106, or the second superconducting silicon electrode 104 or a combination thereof are arranged in a stacked vertical orientation). The second metal contact 116 may be operably coupled to (e.g., directly in contact with) the second superconducting silicon electrode 104. Furthermore, the first metal contact 114 may extend through what would normally be part of the isolation region 112 operably coupled to the first superconducting silicon electrode 102. The first metal contact 114 or the second metal contact 116 or both may include, but are not limited to, conductive superconductors such as aluminum (Al), niobium (Nb), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), vanadium (V), tin (Sb), or lead (Pb), or combinations thereof.

[0027] Figure 1B shows a top view of the qubit device 100 shown in Figure 1A and / or an exemplary arrangement and / or structural configuration of the features of the qubit device 100 along the "Z" axis. Figure 1A or Figure 1B or both show a qubit device comprising a single Josephson junction disposed on a semiconductor substrate 108, but the architecture of the qubit device 100 is not limited in this way. For example, a qubit device 100 comprising multiple Josephson junctions (e.g., multiple first superconducting silicon electrodes 102, tunnel barriers 106, or second superconducting silicon electrodes 104, or a combination thereof) is also conceivable. For example, one or more qubit devices 100 may comprise multiple Josephson junctions arranged adjacent to each other on the semiconductor substrate 108, including the features described herein (e.g., shown in Figure 1A or Figure 1B).

[0028] Figure 2 shows an exemplary and non-limiting qubit device 100 during a first stage of manufacturing according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. During the first stage of manufacturing, one or more resist masks 202 may be deposited on the semiconductor substrate 108 via one or more deposition processes. The thickness of the resist mask 202 (e.g., along the "Y" axis) may vary, for example, in the range of 100 or more to 1,000 nm or less (e.g., 100 nm to 300 nm). Exposed areas of the semiconductor substrate 108 (e.g., not covered by the resist mask 202) may define one or more boundaries of a silicon-based Josephson junction.

[0029] Figure 3 shows an exemplary and non-limiting qubit device 100 during the second stage of fabrication according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. During the second stage of fabrication, the first superconducting silicon electrode 102 may be formed, or the resist mask 202 may be removed, or both.

[0030] In one or more embodiments, one or more laser doping processes may be applied to exposed areas of the semiconductor substrate 108 (e.g., areas not covered by the resist mask 202) to form the first superconducting silicon electrode 102. For example, one or more laser doping processes may be applied to the exposed areas to implant boron dopants and form the first superconducting silicon electrode 102. In one or more embodiments, the first superconducting silicon electrode 102 may be formed by etching trenches into the exposed areas of the semiconductor substrate 108 (e.g., via one or more etching processes). Subsequently, an epitaxial silicon material, such as an epitaxial silicon dopant material (e.g., Si:Ga, Si:Ge, or Ge, or a combination thereof), may be selectively deposited into the trenches via one or more epitaxial growth processes. If the first superconducting silicon electrode 102 is grown via one or more epitaxial growth processes, the thickness of the first superconducting silicon electrode 102 (for example, along the "Y" axis) can be defined via one or more CMP processes. The resist mask 202 can be removed via one or more etching processes.

[0031] Figure 4 shows an exemplary and non-limiting diagram of a qubit device 100 during the third stage of manufacturing according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. During the third stage of manufacturing, one or more silicon layers 402 may be deposited on the first superconducting electrode 102 or the semiconductor substrate 108 or both via one or more deposition processes or epitaxial growth processes or both. In one or more embodiments, one or more silicon layers 402 may be deposited at low temperatures (e.g., by molecular beam epitaxy ("MBE"), for example, at temperatures below 500 degrees Celsius (°C)) via one or more epitaxial growth processes.

[0032] In one or more embodiments, one or more silicon layers 402 may subsequently form a tunnel barrier 106 or one or more isolation layers 110 or both. Thereafter, the thickness of one or more silicon layers 402 (for example, along the "Y" axis) may vary depending on the desired thickness of the tunnel barrier 106, one or more isolation layers 110, or a second superconducting silicon electrode 104, or a combination thereof. For example, the thickness of one or more silicon layers 402 (for example, along the "Y" axis) may range from 5 nm to 500 nm (for example, from 20 nm to 50 nm).

[0033] Figure 5A or Figure 5B or both show an exemplary and non-limiting diagram of a qubit device 100 during the fourth stage of fabrication according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 5A shows a cross-sectional view of the qubit device 100 during the fourth stage of fabrication, or Figure 5B shows a top view of the qubit device 100 during the fourth stage of fabrication, or both. During the fourth stage of fabrication, one or more resist masks 202 may be deposited on one or more silicon layers 402 via one or more deposition processes. Exposed regions of one or more silicon layers 402 (e.g., not covered by the resist masks 202) may define one or more boundaries of the second superconducting silicon electrode 104.

[0034] Figure 6A or Figure 6B or both show an exemplary and non-limiting diagram of a qubit device 100 during the fifth stage of fabrication according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 6A shows a cross-sectional view of the qubit device 100 during the fifth stage of fabrication, or Figure 6B shows a top view of the qubit device 100 during the fifth stage of fabrication, or both. During the fifth stage of fabrication, a second superconducting silicon electrode 104 may be formed.

[0035] In one or more embodiments, one or more laser doping processes may be applied to exposed regions (e.g., regions not covered by the resist mask 202) of one or more silicon layers 402 to form a second superconducting silicon electrode 104. For example, one or more laser doping processes may be applied to exposed regions to inject a dopant (e.g., boron) to form a second superconducting silicon electrode 104. In one or more embodiments, a second superconducting silicon electrode 104 may be formed by etching trenches into exposed regions of one or more silicon layers 402 (e.g., via one or more etching processes). Subsequently, an epitaxial silicon material, such as an epitaxial silicon dopant material (e.g., Si:Ga, Si:Ge, or Ge, or a combination thereof), may be selectively deposited into the trenches via one or more epitaxial growth processes. If the second superconducting silicon electrode 104 is grown via one or more epitaxial growth processes, the thickness of the second superconducting silicon electrode 104 (for example, along the "Y" axis) can be defined via one or more CMP processes.

[0036] This allows the formation of the second superconducting silicon electrode 104 to define a tunnel barrier 106 or one or more isolation layers 110, or both, from the remaining portion of one or more silicon layers 402. For example, the portion of one or more silicon layers 402 remaining between the first superconducting silicon electrode 102 and the second superconducting silicon electrode 104 may be the tunnel barrier 106. For example, the tunnel barrier 106 may contain intrinsic silicon (which can act as a dielectric at a critical temperature of, for example, about 20 mK). Furthermore, the portion of one or more silicon layers 402 remaining adjacent to the second superconducting silicon electrode 104 and the tunnel barrier 106 may be one or more isolation layers 110.

[0037] In one or more embodiments, the remaining portion of the silicon layer 402 that can form a tunnel barrier 106 may be doped (for example, with P or As or both) to form a conventional metal tunnel barrier 106. For example, the remaining portion of the silicon layer 402 that can form a tunnel barrier 106 may be doped before an epitaxial growth process that can form a second superconducting silicon electrode 104.

[0038] Figure 7A or Figure 7B or both show an exemplary and non-limiting diagram of a qubit device 100 during the sixth stage of manufacturing according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 7A shows a cross-sectional view of the qubit device 100 during the sixth stage of manufacturing, or Figure 7B shows a top view of the qubit device 100 during the sixth stage of manufacturing, or both. During the sixth stage of manufacturing, one or more resist masks 202 may be removed from one or more isolation layers 110 via one or more etching processes.

[0039] Figure 8A or Figure 8B or both show an exemplary and non-limiting diagram of a qubit device 100 during the seventh stage of manufacturing according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 8A shows a cross-sectional view of the qubit device 100 during the seventh stage of manufacturing, or Figure 8B shows a top view of the qubit device 100 during the seventh stage of manufacturing, or both.

[0040] During the seventh stage of manufacturing, one or more resist masks 202 may be deposited on one or more isolation layers 110 or the second superconducting silicon electrode 104 or both via one or more deposition processes. As shown in Figure 8A or Figure 8B or both, the resist masks 202 may be deposited in such a way that a portion of one or more isolation layers 110 is exposed. Furthermore, the exposed portion of one or more isolation layers 110 (e.g., a portion not covered by the resist mask 202) may be aligned with a portion of the first superconducting silicon electrode 102 along the "Y" axis (e.g., as shown in Figure 8A).

[0041] Figure 9A or Figure 9B or both show an exemplary and non-limiting diagram of a qubit device 100 during the eighth stage of manufacturing according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 9A shows a cross-sectional view of the qubit device 100 during the eighth stage of manufacturing, or Figure 9B shows a top view of the qubit device 100 during the eighth stage of manufacturing, or both.

[0042] During the eighth stage of manufacturing, one or more exposed portions of the isolation layer 110 may be etched away (e.g., via one or more etching processes such as RIE) to form contact holes 902 within the isolation layer 110 that may extend to the first superconducting silicon electrode 102. By etching the contact holes 902, as shown in Figure 9A or Figure 9B or both, a portion of the first superconducting silicon electrode 102 may be exposed (e.g., by removing at least a portion of the isolation layer 110 that previously covered the first superconducting silicon electrode 102). After etching the contact holes 902, one or more resist masks 202 may be removed (e.g., via one or more etching processes), or the exposed surface of the qubit device 100 may be cleaned (e.g., using DHF), or both.

[0043] Figure 10A or Figure 10B or both show an exemplary and non-limiting diagram of a qubit device 100 during the ninth stage of manufacturing according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 10A shows a cross-sectional view of the qubit device 100 during the ninth stage of manufacturing, or Figure 10B shows a top view of the qubit device 100 during the ninth stage of manufacturing, or both.

[0044] During the ninth step of the manufacturing process, one or more resist masks 202 may be patterned (e.g., via one or more lift-off processes) onto the second superconducting silicon electrode 104 or the isolation layer 110 or both, to facilitate the formation of one or more metal contacts for the qubit device 100, and / or the incorporation of one or more capacitors and / or resonators. As shown in Figure 10A or Figure 10B or both, at least a portion of the first superconducting silicon electrode 102 or the second superconducting silicon electrode or both may remain exposed (e.g., uncovered) by one or more resist masks 202 deposited during the ninth step of the manufacturing process.

[0045] Figure 11A or Figure 11B or both show an exemplary and non-limiting diagram of a qubit device 100 during a tenth manufacturing step according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 11A shows a cross-sectional view of the qubit device 100 during a tenth manufacturing step, or Figure 11B shows a top view of the qubit device 100 during a tenth manufacturing step, or both.

[0046] During the tenth stage of manufacturing, the conductive metallic material 1102 may be deposited on the exposed surface of the qubit device 100 or one or more resist masks 202 or both (for example, via one or more deposition processes). After the conductive metallic material 1102 has been deposited, the resist mask 202 and the portion of the conductive metallic material 1102 placed on the resist mask 202 may be removed (for example, via one or more etching processes) to form a first metal contact 114 or a second metal contact 116 or both (for example, as shown in Figure 1A or Figure 1B or both). Thereafter, the conductive metallic material 1102 may be the same metal contained in the first metal contact 114 or the second metal contact 116 or both. The conductive metallic material may be deposited in the contact hole 902, so as shown in Figure 11A, the conductive metallic material is deposited on the first superconducting silicon electrode 102. Those skilled in the art will understand that the thickness of the conductive metal material 1102 (for example, along the "Y" axis) may vary depending on the functionality of the qubit device 100, and / or the structural characteristics of the first metal contact 114 and / or the second metal contact 116.

[0047] Figure 12A or Figure 12B or both show an exemplary and non-limiting qubit device 100 having a separation layer 110, which may include one or more separation implants, according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 12A shows a cross-sectional view of the qubit device 100 with separation implants, or Figure 12B shows a top view of the qubit device 100 with separation implants, or both.

[0048] In one or more embodiments, one or more isolation implants may be incorporated into one or more portions of one or more silicon layers 402 or semiconductor substrate 108 or both, thereby forming one or more isolation layers 110. Exemplary isolation implants may include, but are not limited to, carbon, oxygen, nitrogen, or combinations thereof. For example, one or more isolation implants may be incorporated into one or more portions of one or more silicon layers 402 or semiconductor substrate 108 or both using one or more plasma immersion processes. In one or more embodiments, one or more isolation implants may be carbon implants, and acetylene or benzene or combinations thereof may be used as carbon sources in one or more plasma immersion processes. One or more isolation implants may suppress the electrical conductivity of one or more isolation layers 110, thereby defining isolation regions 112. According to various embodiments described herein, a qubit device 100 comprising isolation implants may comprise one or more silicon-based Josephson junctions arranged in a stacked vertical orientation. Furthermore, the tunnel barrier 106 of the qubit device 100 with the isolation implant may include a dielectric material or a conventional metallic material according to the various embodiments described herein.

[0049] Figure 13 shows an exemplary and non-limiting qubit device 100 comprising one or more isolation implants during a first step of manufacturing, according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. During the first step of manufacturing, the cap layer 1302 may be deposited (e.g., via one or more deposition processes) on a multilayer structure comprising a semiconductor substrate 108, one or more superconducting silicon layers 1304, or silicon barrier layers 1306, or a combination thereof. Exemplary materials that may be contained within the cap layer 1302 may include, but are not limited to, silicon oxide, silicon nitride, silicon, or CVD carbon, or a combination thereof. Those skilled in the art will understand that the thickness of the cap layer 1302 (e.g., along the "Y" axis) may vary. For example, the thickness of the cap layer 1302 (e.g., along the "Y" axis) may be between 5 nm and 500 nm (e.g., 30 nm to 100 nm).

[0050] As shown in Figure 13, a silicon barrier layer 1306 may be positioned between one superconducting silicon layer 1304 (for example, positioned on a semiconductor substrate 108) and another superconducting silicon layer 1304 (for example, positioned adjacent to a cap layer 1302). In one or more embodiments, the superconducting silicon layer 1304 may proceed to constitute a first superconducting silicon electrode 102 or a second superconducting silicon electrode 104 or both in a subsequent manufacturing step. Thus, the superconducting silicon layer 1304 may contain the same material as the first superconducting silicon electrode 102 or the second superconducting silicon electrode 104 or both in the various embodiments described herein. Furthermore, in one or more embodiments, the multilayer structure may be formed via one or more laser doping processes, epitaxial growth processes, or etching processes according to one or more embodiments described herein (for example, according to the features shown in Figures 2 to 7B).

[0051] Figure 14A or Figure 14B or both illustrate an exemplary and non-limiting qubit device 100 having one or more isolation implants during a second stage of manufacturing, according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 14A shows a cross-sectional view of the qubit device 100 having one or more isolation implants during a second stage of manufacturing, or Figure 14B shows a top view of the qubit device 100 having one or more isolation implants during a second stage of manufacturing, or both. During the second stage of manufacturing the qubit device 100 having one or more isolation implants, one or more resist layers 202 may be deposited on the cap layer 1302 (for example, via one or more deposition processes). In one or more embodiments, one or more resist layers 202 may cover a portion of the cap layer 1302 that is aligned with the boundary to be defined of the silicon-based Josephson junction.

[0052] Figure 15A or Figure 15B or both illustrate an exemplary and non-limiting qubit device 100 having one or more isolation implants during a third stage of manufacturing, according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 15A shows a cross-sectional view of the qubit device 100 having one or more isolation implants during a third stage of manufacturing, or Figure 15B shows a top view of the qubit device 100 having one or more isolation implants during a third stage of manufacturing, or both. During the third stage of manufacturing the qubit device 100 having one or more isolation implants, one or more exposed portions of the cap layer 1302 (e.g., portions not covered by one or more resist masks 202) may be removed via one or more etching processes (e.g., using diluted hydrofluoric acid ("DHF") or oxygen plasma or both).

[0053] Figure 16A or Figure 16B or both illustrate an exemplary and non-limiting qubit device 100 having one or more isolation implants during a fourth stage of manufacturing, according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 16A shows a cross-sectional view of the qubit device 100 having one or more isolation implants during a fourth stage of manufacturing, or Figure 16B shows a top view of the qubit device 100 having one or more isolation implants during a fourth stage of manufacturing, or both. During the fourth stage of manufacturing the qubit device 100 having one or more isolation implants, one or more resist layers 202 may be removed via one or more etching processes, exposing the remainder of the cap layer 1302.

[0054] Figure 17A or Figure 17B or both show an exemplary and non-limiting qubit device 100 having one or more isolation implants during the fifth stage of manufacturing, according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 17A shows a cross-sectional view of the qubit device 100 having one or more isolation implants during the fifth stage of manufacturing, or Figure 17B shows a top view of the qubit device 100 having one or more isolation implants during the fifth stage of manufacturing, or both.

[0055] During a fifth step in the fabrication of a qubit device 100 comprising one or more isolation implants, one or more portions or both of the cap layer 1302 or the multilayer stack (e.g., comprising one or more superconducting silicon layers 1304 or silicon barrier layers 1306 or both) may be subjected to a first plasma immersion 1702 with one or more isolation implant sources. For example, if one or more isolation implants are carbon, the first plasma immersion 1702 may be subjected to one or more carbon sources such as acetylene or benzene or both of them. As shown in Figure 17A or Figure 17B or both, one or more portions or both of the cap layer 1302 or the multilayer stack may be saturated with the isolation implant source (e.g., a carbon source such as acetylene or benzene or both).

[0056] In various embodiments, one or more portions of a multilayer stack subjected to the first plasma immersion 1702 may be isolation regions 112 of the qubit device 100. Thereafter, the first plasma immersion 1702 may define one or more boundaries of one or more Josephson junctions contained within the qubit device 100. For example, the first plasma immersion 1702 may define structural boundaries of the first superconducting silicon electrode 102 or the tunnel barrier 106 or both (as shown, for example, in Figure 17A).

[0057] Figure 18A or Figure 18B or both illustrate an exemplary and non-limiting qubit device 100 having one or more isolation implants during the sixth stage of manufacturing, according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 18A shows a cross-sectional view of the qubit device 100 having one or more isolation implants during the sixth stage of manufacturing, or Figure 18B shows a top view of the qubit device 100 having one or more isolation implants during the sixth stage of manufacturing, or both.

[0058] During the sixth step of manufacturing the qubit device 100 comprising one or more isolation implants, a portion of the qubit device 100 saturated with the isolation implant source may be annealed (e.g., laser annealing) to implant the isolation implants (e.g., and / or reduce lattice damage). For example, laser annealing may melt silicon in the irradiated area, and a pulsing time may be established based on how much silicon is to be melted. For example, in one or more embodiments, the isolation region 112 may be annealed (e.g., laser annealing) to form one or more isolation layers 110 that can suppress electrical conductivity within the isolation region 112. For example, in various embodiments, the isolation region 112 may be saturated with a carbon source in the fifth step and laser annealed in the sixth step to implant one or more carbon isolation implants into the isolation region 112 and form one or more isolation layers 110. As shown in Figure 18A or Figure 18B or both, the cap layer 1302 can protect the superconducting silicon layer 1304, the tunnel barrier 106, or the first superconducting silicon electrode 102, or a combination thereof, from being implanted with a separation implant during the sixth step.

[0059] Figure 19A or Figure 19B or both show an exemplary and non-limiting qubit device 100 having one or more isolation implants during the seventh stage of manufacturing, according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 19A shows a cross-sectional view of the qubit device 100 having one or more isolation implants during the seventh stage of manufacturing, or Figure 19B shows a top view of the qubit device 100 having one or more isolation implants during the seventh stage of manufacturing, or both.

[0060] During the seventh step of manufacturing the qubit device 100 comprising one or more isolation implants, one or more resist layers 202 may be deposited on the cap layer 1302 (for example, via one or more deposition processes). In one or more embodiments, one or more resist layers 202 may cover a portion of the cap layer 1302 that is aligned with the boundary to be defined for the second superconducting silicon electrode 104.

[0061] Figure 20A or Figure 20B, or both, shows an exemplary and non-limiting qubit device 100 having one or more isolation implants during the eighth stage of manufacturing, according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 20A shows a cross-sectional view of the qubit device 100 having one or more isolation implants during the eighth stage of manufacturing, or Figure 20B shows a top view of the qubit device 100 having one or more isolation implants during the eighth stage of manufacturing. During the eighth stage of manufacturing the qubit device 100 having one or more isolation implants, one or more exposed portions of the cap layer 1302 (e.g., portions not covered by one or more resist masks 202) may be removed via one or more etching processes (e.g., using DHF). The remaining portions of one or more resist masks 202 may then be removed. This allows the remaining portion of the cap layer 1302 to be positioned above the location where the second superconducting silicon electrode 104 is to be defined (for example, along the "Y" axis).

[0062] Figure 21A or Figure 21B, or both, shows an exemplary and non-limiting qubit device 100 having one or more isolation implants during the ninth stage of manufacturing, according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 21A shows a cross-sectional view of the qubit device 100 having one or more isolation implants during the ninth stage of manufacturing, or Figure 21B shows a top view of the qubit device 100 having one or more isolation implants during the ninth stage of manufacturing.

[0063] During the ninth step of manufacturing the qubit device 100 having one or more isolation implants, one or more portions or both of the cap layer 1302 or the remaining superconducting silicon layer 1304 may be subjected to a second plasma immersion 2102 with one or more isolation implant sources. For example, if one or more isolation implants are carbon, one or more portions or both of the cap layer 1302 or the superconducting silicon layer 1304 may be subjected to a second plasma immersion 2102 with one or more carbon sources such as acetylene or benzene or both. As shown in Figure 21A or Figure 21B or both, one or more portions or both of the cap layer 1302 or the superconducting silicon layer 1304 may be saturated with the isolation implant source (e.g., a carbon source such as acetylene or benzene or both). In various embodiments, one or more portions of the superconducting silicon layer 1304 subjected to the second plasma immersion 2102 may extend the isolation region 112 of the qubit device 100 (for example, shown by the bold dashed line in Figure 21A). Thereafter, the second plasma immersion 2102 may define one or more boundaries of the second superconducting silicon electrode 104 (for example, as shown in Figure 21A or Figure 21B or both).

[0064] Figure 22A or Figure 22B or both illustrate an exemplary and non-limiting qubit device 100 having one or more isolation implants during a tenth step of manufacturing, according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 22A may show a cross-sectional view of the qubit device 100 having one or more isolation implants during a tenth step of manufacturing, or Figure 22B may show a top view of the qubit device 100 having one or more isolation implants during a tenth step of manufacturing, or both.

[0065] During the tenth step of manufacturing the qubit device 100 having one or more isolation implants, a portion of the qubit device 100 saturated with the isolation implant source may be annealed (e.g., laser annealing) to implant the isolation implants. For example, in one or more embodiments, the isolation region 112 may be annealed (e.g., laser annealing) to form one or more isolation layers 110 that can suppress the electrical conductivity within the isolation region 112. For example, in various embodiments, the isolation region 112 may be saturated with a carbon source in the ninth step and laser annealed in the tenth step to implant one or more carbon isolation implants into the isolation region 112 and extend one or more isolation layers 110. As shown in Figure 22A or Figure 22B or both, the cap layer 1302 may protect the second superconducting silicon electrode 104 from being implanted with the isolation implants during the tenth step. Furthermore, in one or more embodiments, the tunnel barrier 106 or the first superconducting silicon electrode 102 or both may remain unimpeded with the isolation implant during the 10th step, controlling the depth of saturation (e.g., along the "Y" axis) of the isolation implant source during the 9th step of manufacturing, and thereby the depth of isolation implant integration (e.g., along the "Y" axis) during the 10th step of manufacturing.

[0066] Figure 23A or Figure 23B, or both, shows an exemplary and non-limiting diagram of a qubit device 100 during the eleventh step of manufacturing according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 23A may show a cross-sectional view of the qubit device 100 during the eleventh step of manufacturing, or Figure 23B may show a top view of the qubit device 100 during the eleventh step of manufacturing, or both.

[0067] During the eleventh step of manufacturing, one or more resist masks 202 may be deposited on one or more isolation layers 110 or capping layers 1302 or both via one or more deposition processes. As shown in Figure 23A or Figure 23B or both, the resist masks 202 may be deposited such that a portion of one or more isolation layers 110 is exposed. Furthermore, the exposed portion of one or more isolation layers 110 (e.g., a portion not covered by the resist mask 202) may be aligned with a portion of the first superconducting silicon electrode 102 along the "Y" axis (e.g., as shown in Figure 23A).

[0068] Figure 24A or Figure 24B or both show an exemplary and non-limiting diagram of a qubit device 100 during a twelfth step of manufacturing according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 24A shows a cross-sectional view of the qubit device 100 during a twelfth step of manufacturing, or Figure 24B shows a top view of the qubit device 100 during a twelfth step of manufacturing, or both.

[0069] During the twelfth step of the manufacturing process, one or more exposed portions of the isolation layer 110 may be etched away (for example, via one or more etching processes such as RIE) to form contact holes 902 within the isolation layer 110 that may extend to the first superconducting silicon electrode 102. By etching the contact holes 902, as shown in Figure 9A or Figure 9B or both, a portion of the first superconducting silicon electrode 102 may be exposed (for example, by removing at least a portion of the isolation layer 110 or tunnel barrier 106 or both that previously covered the first superconducting silicon electrode 102). After etching the contact holes 902, one or more resist masks 202 may be removed (for example, via one or more etching processes), or the exposed surface of the qubit device 100 may be cleaned (for example, using DHF), or both.

[0070] Figure 25A or Figure 25B or both show an exemplary and non-limiting diagram of a qubit device 100 during a thirteenth step of manufacturing according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 25A shows a cross-sectional view of the qubit device 100 during a thirteenth step of manufacturing, or Figure 25B shows a top view of the qubit device 100 during a thirteenth step of manufacturing, or both. During a thirteenth step of manufacturing, the cap layer 1302 may be etched off (e.g., via one or more etching processes such as RIE) to expose the second superconducting silicon electrode 104. Furthermore, the exposed surface of the qubit device 100 may be cleaned (e.g., using DHF).

[0071] Figure 26A or Figure 26B or both show an exemplary and non-limiting diagram of a qubit device 100 during a 14th step of manufacturing according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 26A shows a cross-sectional view of the qubit device 100 during a 14th step of manufacturing, or Figure 26B shows a top view of the qubit device 100 during a 14th step of manufacturing, or both.

[0072] During the 14th step of the manufacturing process, one or more resist masks 202 may be patterned (e.g., via one or more lift-off processes) onto the second superconducting silicon electrode 104 or the isolation layer 110 or both, to facilitate the formation of one or more metal contacts for the qubit device 100, and / or the incorporation of one or more capacitors and / or resonators. As shown in Figure 26A or Figure 26B or both, at least a portion of the first superconducting silicon electrode 102 or the second superconducting silicon electrode or both may remain exposed (e.g., uncovered) by one or more resist masks 202.

[0073] Figure 27A or Figure 27B or both show an exemplary and non-limiting diagram of a qubit device 100 during a 15th step of manufacturing according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. Figure 27A shows a cross-sectional view of the qubit device 100 during a 15th step of manufacturing, or Figure 27B shows a top view of the qubit device 100 during a 15th step of manufacturing, or both.

[0074] During the 15th stage of manufacturing, the conductive metallic material 1102 may be deposited on the exposed surface of the qubit device 100 or one or more resist masks 202 or both (for example, via one or more deposition processes). After the conductive metallic material 1102 has been deposited, the resist mask 202 and the portion of the conductive metallic material 1102 placed on the resist mask 202 may be removed (for example, via one or more etching processes) to form a first metal contact 114 or a second metal contact 116 or both (for example, as shown in Figure 12A or Figure 12B or both). Thereafter, the conductive metallic material 1102 may be the same metal contained in the first metal contact 114 or the second metal contact 116 or both. As shown in Figure 27A, the conductive metallic material may be deposited in the contact hole 902, so as the conductive metallic material is deposited on the first superconducting silicon electrode 102. Those skilled in the art will understand that the thickness of the conductive metal material 1102 (for example, along the "Y" axis) may vary depending on the functionality of the qubit device 100, and / or the structural characteristics of the first metal contact 114 and / or the second metal contact 116.

[0075] Figure 28 shows a flowchart of an exemplary and non-limiting method 2800 that can facilitate the fabrication of one or more qubit devices 100 comprising one or more silicon-based Josephson junctions, according to one or more embodiments described herein. For the sake of brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted.

[0076] In 2802, method 2800 may include doping a portion of the semiconductor substrate 108 to form a first superconducting electrode (e.g., a first superconducting silicon electrode 102). For example, doping in 2802 may be carried out according to at least the second step of the manufacturing shown in Figure 3. For example, the first superconducting electrode may be a first superconducting silicon electrode 102, or doping may include one or more laser doping processes according to one or more embodiments described herein, or both.

[0077] In 2804, method 2800 may include depositing a silicon layer on a first superconducting electrode via an epitaxial growth process to form a tunnel barrier 106. For example, the deposition in 2804 may be carried out according to at least a third step of the fabrication shown in Figure 4. For example, in one or more embodiments, the deposition in 2804 may grow a layer of intrinsic silicon that can act as a dielectric tunnel barrier 106 of a silicon-based Josephson junction during operation of the qubit device 100 at near-zero temperatures. In another example, the deposition in 2804 may further include doping one or more portions of the deposited silicon layer to form a conventional metallic tunnel barrier 106 according to one or more embodiments described herein.

[0078] In 2806, method 2800 may include doping one or more portions of the tunnel barrier 106 to form a second superconducting electrode (e.g., a second superconducting silicon electrode 104) and a Josephson junction. For example, doping in 2806 may be carried out according to at least a fifth step of the fabrication shown in Figure 6A or Figure 6B or both. For example, the second superconducting electrode may be a second superconducting silicon electrode 104, or doping may include one or more laser doping processes according to one or more embodiments described herein, or both. In various embodiments, the Josephson junction formed by method 2800 may be a silicon-based Josephson junction comprising a superconducting silicon electrode. Furthermore, the superconducting silicon electrodes may be stacked in a vertical orientation. Furthermore, in one or more embodiments, the tunnel barrier 106 may be a dielectric tunnel barrier containing intrinsic silicon.

[0079] Figure 29 shows an exemplary and non-limiting method 2900 that can facilitate the fabrication of one or more qubit devices 100 comprising one or more silicon-based Josephson junctions electrically isolated via one or more isolation layers 110, which may include one or more isolation implants, according to one or more embodiments described herein. For brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted.

[0080] In 2902, method 2900 may include doping a portion of the semiconductor substrate 108 to form a first superconducting electrode (e.g., a first superconducting silicon electrode 102). For example, doping in 2902 may be carried out according to at least the second step of the manufacturing shown in Figure 3. For example, the first superconducting electrode may be a first superconducting silicon electrode 102, or doping may include one or more laser doping processes according to one or more embodiments described herein, or both.

[0081] In 2904, method 2900 may include depositing a silicon layer on a first superconducting electrode via an epitaxial growth process to form a tunnel barrier 106. For example, the deposition in 2904 may be carried out according to at least a third step of the fabrication shown in Figure 4. For example, in one or more embodiments, the deposition in 2904 may grow a layer of intrinsic silicon that can act as a dielectric tunnel barrier 106 of a silicon-based Josephson junction during operation of the qubit device 100 at near-zero temperatures. In another example, the deposition in 2904 may further include doping one or more portions of the deposited silicon layer to form a conventional metallic tunnel barrier 106 according to one or more embodiments described herein.

[0082] In 2906, method 2900 may include doping one or more portions of the tunnel barrier 106 to form a second superconducting electrode (e.g., a second superconducting silicon electrode 104) and a Josephson junction. For example, doping in 2806 may be carried out according to at least a fifth step of the fabrication shown in Figure 6A or Figure 6B or both. For example, the second superconducting electrode may be a second superconducting silicon electrode 104, or doping may include one or more laser doping processes according to one or more embodiments described herein, or both. In various embodiments, the Josephson junction formed in method 2906 may be a multilayer stack structure such as the multilayer stack shown in Figure 13, and one or more subsequent fabrication steps may further define one or more structural features of the Josephson junction, or may electrically isolate the Josephson junction via the incorporation of isolation implants, or both.

[0083] In 2908, method 2900 may include forming a separation region 112 from the Josephson junction by plasma immersion of one or more separation implants into portions of the first superconducting electrode (e.g., the first superconducting silicon electrode 102), the tunnel barrier 106, and the second superconducting electrode (e.g., the second superconducting silicon electrode 104). For example, the formation of the separation region in 2908 may be carried out according to the fifth to tenth steps of the fabrication shown in Figures 17A to 22B. For example, the formation of the separation region in 2908 may include one or more plasma immersion processes or annealing processes or both, according to one or more embodiments described herein.

[0084] In 2910, method 2900 may include forming a contact hole 902 within the isolation region 112 that may extend to a first superconducting electrode (e.g., a first superconducting silicon electrode 102). For example, forming the contact hole 902 may be carried out according to the 11th to 12th steps of the manufacturing shown in Figures 23A to 24B.

[0085] In 2912, method 2900 may include depositing a first metal layer (e.g., a conductive metallic material 1102) within a contact hole 902 to form a first metal contact 114 operably coupled to a first superconducting electrode (e.g., a first superconducting silicon electrode 102). For example, the formation of the first metal contact 114 in 2912 may be carried out according to a 14th or 15th step of the manufacturing process, or both, as shown in Figures 26A–27B or Figures 12A–12B or both.

[0086] In 2914, method 2900 may include depositing a second metal layer (e.g., a conductive metallic material 1102) onto a second superconducting electrode (e.g., a second superconducting silicon electrode 104) to form a second metal contact 116 operably coupled to the second superconducting electrode (e.g., a second superconducting silicon electrode 104). For example, the formation of the first metal contact 114 in 2914 may be carried out according to the 14th or 15th step of the manufacturing process shown in Figures 26A–27B or Figures 12A–12B or both.

[0087] Furthermore, the term “or” shall mean inclusive “or” rather than exclusive “or.” That is, unless otherwise specified or it is clear from the context, “X utilizes A or B” shall mean either of the natural inclusive permutations. That is, if X utilizes A, X utilizes B, or X utilizes both A and B, “X utilizes A or B” is satisfied under any of the above examples. Furthermore, the articles “a” and “an” used herein and in the accompanying drawings should generally be interpreted as meaning “one or plural” unless otherwise specified or it is clear from the context that they refer to a singular form. In this specification, the terms “example” or “exemplary” or both are used to mean that they serve as examples, cases, or illustrations. To avoid doubt, the subject matter disclosed herein is not limited by such examples. Furthermore, any embodiment or design described herein as “example” or “exemplary” or both shall not necessarily be construed as being preferable or advantageous to other embodiments or designs, nor shall it preclude equivalent exemplary structures and techniques known to those skilled in the art.

[0088] Of course, it is not impossible to describe every conceivable combination of components, products, or methods in order to explain this disclosure, but those skilled in the art will understand that many other combinations and permutations of this disclosure are possible. Furthermore, to the extent that terms such as “including,” “having,” and “owning” are used in the detailed description, claims, appendices, and drawings, such terms shall be as inclusive as “including,” so that when used as a transition word in a claim, “comprising” is interpreted as such. Although descriptions of various embodiments have been presented for illustrative purposes, the descriptions are not exhaustive and are not limited to the embodiments disclosed. Many changes and modifications will be apparent to those skilled in the art without departing from the scope and idea of ​​the embodiments described. The terms used herein have been chosen to best describe the principles of the embodiments, the practical applications or technical improvements that surpass the art found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein. This disclosure also discloses the following inventions: <Note 1> A Josephson junction including a tunnel barrier positioned between two vertically stacked superconducting silicon electrodes. A device equipped with the following features. <Note 2> The apparatus according to Appendix 1, wherein the two vertically stacked superconducting silicon electrodes include silicon doped with at least one dopant selected from the group consisting of boron, gallium, and germanium. <Note 3> The apparatus according to Appendix 2, wherein at least one dopant is boron, and each of the two vertically stacked superconducting silicon electrodes contains boron at a concentration of more than 4 atoms and less than or equal to 11 atoms. <Note 4> A first metal contact operably coupled to a first superconducting silicon electrode from the two vertically stacked superconducting silicon electrodes, A second metal contact operably coupled to a second superconducting silicon electrode from the two vertically stacked superconducting silicon electrodes, A separation layer, wherein the separation layer is positioned on the tunnel barrier such that it electrically separates the first metal contact from the second metal contact, and the separation layer includes carbon implantation in silicon. The apparatus further comprising any one of the appendices 1 to 3. <Note 5> A first metal contact operably coupled to a first superconducting silicon electrode from the two vertically stacked superconducting silicon electrodes, A second metal contact operably coupled to a second superconducting silicon electrode from the two vertically stacked superconducting silicon electrodes, A separation layer is disposed on the tunnel barrier such that the separation layer electrically separates the first metal contact from the second metal contact, and the separation layer comprises intrinsic silicon. The apparatus further comprising any one of the appendices 1 to 4. <Note 6> The apparatus according to any one of appendices 1 to 5, wherein the tunnel barrier is doped with at least one dopant selected from the group consisting of phosphorus and arsenic. <Note 7> The apparatus according to any one of appendices 1 to 6, wherein the tunnel barrier contains intrinsic crystalline silicon. <Note 8> Josephson junction including a dielectric tunnel barrier placed between two superconducting silicon electrodes A device equipped with the following features. <Note 9> The apparatus according to Appendix 8, wherein the two superconducting silicon electrodes include silicon doped with at least one dopant selected from the group consisting of boron, germanium, and gallium. <Note 10> The apparatus according to Appendix 9, wherein at least one dopant is boron, and each of the two superconducting silicon electrodes contains boron in a concentration of more than 4 atoms and boron in a concentration of 11 atoms or less. <Note 11> A first metal contact operably coupled to the first superconducting silicon electrode from the two superconducting silicon electrodes, A second metal contact operably coupled to a second superconducting silicon electrode from the two superconducting silicon electrodes, An isolation layer, wherein the isolation layer is disposed on the dielectric tunnel barrier such that it electrically isolates the first metal contact from the second metal contact, and the isolation layer includes carbon implantation in silicon. The apparatus further comprising any one of the appendices 8 to 10. <Note 12> A first metal contact operably coupled to the first superconducting silicon electrode from the two superconducting silicon electrodes, A second metal contact operably coupled to a second superconducting silicon electrode from the two superconducting silicon electrodes, An isolation layer, wherein the isolation layer is disposed on the dielectric tunnel barrier such that it electrically isolates the first metal contact from the second metal contact, and the isolation layer comprises intrinsic silicon. The apparatus further comprising any one of the appendices 8 to 11. <Note 13> The apparatus according to any one of appendices 8 to 12, wherein the dielectric tunnel barrier contains intrinsic crystalline silicon. <Note 14> The apparatus according to any one of appendices 8 to 13, wherein the two superconducting silicon electrodes and the dielectric tunnel barrier are stacked vertically on a dielectric substrate. <Note 15> The process involves doping a portion of the silicon substrate to form a first superconducting electrode, A silicon layer is deposited on the first superconducting electrode via an epitaxial growth process to form a tunnel barrier. A portion of the tunnel barrier is doped to form a second superconducting electrode, and a Josephson junction is formed. A method that includes this. <Note 16> The method according to Appendix 15, wherein the first dopant added by doping the portion of the silicon substrate and the second dopant added by doping the portion of the silicon layer are at least one member selected from the group consisting of boron, gallium, and germanium. <Note 17> A separation region from the Josephson junction is formed by plasma immersion of the separation implant into the first superconducting electrode, the tunnel barrier, and the second superconducting electrode. The method described in Appendix 15 or 16, further including the method described in Appendix 15 or 16. <Note 18> A contact hole extending to the first superconducting electrode is formed within the separation region, A first metal layer is deposited in the contact hole to form a first metal contact operably coupled to the first superconducting electrode, A second metal layer is deposited on the second superconducting electrode to form a second metal contact operably coupled to the second superconducting electrode. The method described in Appendix 17, further including the method described in Appendix 17. <Note 19> The method according to any one of appendices 15 to 18, wherein the undoped portion of the silicon substrate and the undoped portion of the silicon layer define an isolation region adjacent to the Josephson junction. <Note 20> A contact hole extending to the first superconducting electrode is formed within the separation region, A first metal layer is deposited in the contact hole to form a first metal contact operably coupled to the first superconducting electrode, A second metal layer is deposited on the second superconducting electrode to form a second metal contact operably coupled to the second superconducting electrode. The method described in Appendix 19, further including the method described in Appendix 19.

Claims

1. Doping a portion of the silicon substrate to form a first superconducting electrode, A silicon layer is deposited on the first superconducting electrode via an epitaxial growth process to form a tunnel barrier. A portion of the tunnel barrier is doped using a laser doping process to form a second superconducting electrode and a Josephson junction. By plasma immersion of the separation implant into the portion of the first superconducting electrode, the tunnel barrier, and the second superconducting electrode, a separation region is formed from the Josephson junction. A method that includes this.

2. The method according to claim 1, wherein the first dopant added by doping the portion of the silicon substrate and the second dopant added by doping the portion of the silicon layer are at least one member selected from the group consisting of boron, gallium, and germanium.

3. Forming the aforementioned separation region means A cap layer is formed on the stack of the first superconducting electrode, the tunnel barrier, and the second superconducting electrode, Inserting a separation implant into the portion of the first superconducting electrode, the tunnel barrier, and the second superconducting electrode that is exposed from the cap layer, Etching and removing the cap layer while leaving a portion of the cap layer that is aligned with the boundary to be defined of the second superconducting electrode, Inserting a separation implant into the portion of the second superconducting electrode exposed from the aforementioned cap layer, Etching off the remaining portion of the cap layer The method according to claim 1 or 2, including the method described in claim 1 or 2.

4. A contact hole extending to the first superconducting electrode is formed within the separation region, A first metal layer is deposited in the contact hole to form a first metal contact that is operably coupled to the first superconducting electrode, A second metal layer is deposited on the second superconducting electrode to form a second metal contact operably coupled to the second superconducting electrode. The method according to claim 1 or 2, further comprising:

5. The method according to any one of claims 1 to 4, wherein the undoped portion of the silicon substrate and the undoped portion of the silicon layer define an isolation region adjacent to the Josephson junction.

6. A contact hole extending to the first superconducting electrode is formed within the separation region, A first metal layer is deposited in the contact hole to form a first metal contact that is operably coupled to the first superconducting electrode, A second metal layer is deposited on the second superconducting electrode to form a second metal contact operably coupled to the second superconducting electrode. The method according to claim 5, further comprising:

7. The method according to any one of claims 1 to 6, wherein the first dopant added by doping the portion of the silicon substrate and the second dopant added by doping the portion of the silicon layer each contain boron in a concentration of more than 4 atoms and less than or equal to 11 atoms.

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