Drive circuit

Abstract

Provided is a drive circuit (1), wherein a common substrate (10) generates a common drive signal (DRS) for on / off control of a plurality of power semiconductor elements (61p-63p) connected in parallel. Each of a plurality of individual substrates (30a, 31, 30c) is individually provided to a corresponding power semiconductor element, and supplies the drive signal to the corresponding power semiconductor element. Among the plurality of individual substrates, one individual substrate or some of the individual substrates (31) include(s) a detection circuit (41). The detection circuit (41) changes the drive signal (DRS) by transmitting an abnormality detection signal (DTS) to the plurality of individual substrates and the common substrate when an abnormality in the electrical characteristics of the corresponding power semiconductor element (62p) is detected.

Description

[[Technical Field]]

[0001] The present disclosure relates to a drive circuit, and more specifically to a drive circuit for driving a plurality of power semiconductor elements connected in parallel. [[Background Art]]

[0002] In a power converter using power semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), large-capacity models are configured by connecting a plurality of power semiconductor elements in parallel to secure a desired power capacity.

[0003] However, in the above configuration, when an overcurrent state or a short-circuit state occurs, current concentrates on one of the plurality of power semiconductor elements connected in parallel, which may lead to thermal destruction of that element. Therefore, a drive circuit that drives a plurality of parallel-connected power semiconductor elements is required to have a function of detecting an overcurrent state or a short-circuit state of the power semiconductor elements and protecting the power semiconductor elements from thermal destruction.

[0004] As drive circuits provided with such a short-circuit protection function, for example, the drive circuits disclosed in Japanese Patent Laying-Open No. 2021-044963 (Patent Document 1) and Japanese Patent Laying-Open No. 2000-217337 (Patent Document 2) are known.

[0005] For example, the "gate driving device for driving a plurality of insulated-gate semiconductor elements connected in parallel" disclosed in Japanese Patent Application Publication No. 2021-044963 (Patent Document 1) " comprises a gate driving circuit that drives the gates of the plurality of insulated-gate semiconductor elements in response to an externally provided control signal, an abnormality detection circuit that has a plurality of abnormality detection terminals corresponding to each of the plurality of insulated-gate semiconductor elements and detects an abnormal state of the plurality of insulated-gate semiconductor elements and outputs an abnormality detection signal, and an output circuit that is connected to at least one of the plurality of abnormality detection terminals and outputs the abnormality detection signal to the outside" (see Claim 1 of Patent Document 1).

[0006] Furthermore, the semiconductor device disclosed in Japanese Patent Application Publication No. 2000-217337 (Patent Document 2) is configured such that "a plurality of voltage-driven elements are divided into a plurality of groups, each consisting of a parallel connection of a plurality of voltage-driven elements, including a voltage-driven element having an auxiliary emitter for current detection, and each of these groups is protected from overcurrent by a single overcurrent protection circuit." And, "within each group, the auxiliary emitter, main emitter, and gate of the voltage-driven element with the largest collector current at the same gate-emitter voltage are connected to the overcurrent protection circuit" (see claims 1 and 2 of Patent Document 2). [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2021-044963 [Patent Document 2] Japanese Patent Publication No. 2000-217337 [Overview of the project] [Problems that the invention aims to solve]

[0008] In the drive circuit disclosed in Japanese Patent Publication No. 2021-044963 (Patent Document 1) mentioned above, an abnormality detection terminal is provided for each of the multiple semiconductor elements connected in parallel, and the current flowing through the detection resistor connected to the sense emitter of each semiconductor element is detected. However, in a configuration that detects abnormalities in all semiconductor elements in this way, there is a problem that the abnormality detection circuit tends to become large and complex.

[0009] Furthermore, in the semiconductor device disclosed in Japanese Patent Publication No. 2000-217337 (Patent Document 2), the current flowing through a detection resistor connected to the auxiliary emitter of the semiconductor element that has the largest collector current at the same gate-emitter voltage within each group is detected. However, since collector currents are usually designed to be uniform, it is impractical to identify the semiconductor element with the largest collector current at the design stage and connect its auxiliary emitter, main emitter, and gate to an overcurrent protection circuit.

[0010] This disclosure has been made in consideration of the above-mentioned background art, and its purpose is to provide a drive circuit equipped with a short-circuit protection function that can detect a short-circuit condition occurring in any of a plurality of parallel-connected power semiconductor elements with a simple configuration and protect these power semiconductor elements. [Means for solving the problem]

[0011] In one embodiment, a drive circuit for driving a plurality of power semiconductor elements connected in parallel comprises a common board and a plurality of individual boards. The common board generates a common drive signal for controlling the on and off states of all power semiconductor elements connected in parallel. Each of the plurality of individual boards is individually provided for a corresponding power semiconductor element among the plurality of power semiconductor elements and supplies the drive signal to the corresponding power semiconductor element. Each of the plurality of individual boards, one or some of the individual boards, includes a detection circuit. The detection circuit causes the drive signal to be modified by transmitting an abnormality detection signal to the plurality of individual boards and the common board, or by transmitting an abnormality detection signal to the common board without transmitting an abnormality detection signal to the plurality of individual boards, when it detects an abnormality in the electrical characteristics of the corresponding power semiconductor element. [Effects of the Invention]

[0012] According to the above embodiment, by providing an abnormality detection circuit on one or some of the individual substrates among the multiple individual substrates, a short-circuit condition occurring in any of the multiple power semiconductor elements connected in parallel can be detected with a simple configuration, thereby protecting these power semiconductor elements. [Brief explanation of the drawing]

[0013] [Figure 1] This figure shows an example of the configuration of the drive circuit according to Embodiment 1. [Figure 2A] Figure 1 is a circuit diagram showing an example of the logic operation circuit 14, detection circuit 41, and switching circuit 11. [Figure 2B] This figure shows the truth table for the SRFF circuit 18 in Figure 2A. [Figure 3] This figure shows another example of the configuration of the drive circuit according to Embodiment 1. [Figure 4] Figure 1 is a circuit diagram showing an example configuration of the soft cutoff circuit 15. [Figure 5] This figure shows an example of the configuration of a drive circuit according to a modified example of Embodiment 1. [Figure 6] This figure shows an example of the configuration of the drive circuit according to Embodiment 2. [Figure 7] It is a diagram showing an example of gate charge characteristics of an IGBT. [Figure 8] It is a diagram showing a configuration example of a drive circuit according to a modification of the second embodiment. [Figure 9] It is a diagram showing a configuration example of a drive circuit according to the third embodiment. [Figure 10] It is a diagram showing a configuration example of a drive circuit according to a modification of the third embodiment. [Figure 11A] It is a diagram for explaining the reason why variations occur in the current and voltage of each IGBT among a plurality of IGBTs connected in parallel. [Figure 11B] It is a diagram for explaining the reason why variations occur in the on-resistance of each IGBT among a plurality of IGBTs connected in parallel. [Figure 12] It is a diagram showing a configuration example of a main circuit for one phase of a power conversion device. [Figure 13] It is a diagram showing another configuration example of a main circuit for one phase of a power conversion device. [Figure 14A] It is a diagram showing an example of a drive circuit that drives the upper arm of the main circuit shown in Fig. 13. [Figure 14B] It is a diagram showing another example of a drive circuit that drives the upper arm of the main circuit shown in Fig. 13. [Figure 14C] It is a diagram showing an example of a drive circuit that drives the upper arm of the main circuit of another configuration example. [Figure 14D] It is a diagram showing another example of a drive circuit that drives the upper arm of the main circuit shown in Fig. 14C. [Figure 15] It is a diagram showing a configuration example of a drive circuit according to the fifth embodiment. [Figure 16] It is a diagram showing a configuration example of a drive circuit according to a modification of the fifth embodiment. MODE FOR CARRYING OUT THE INVENTION

[0014] Hereinafter, each embodiment will be described in detail with reference to the accompanying drawings. The same or corresponding parts are denoted by the same reference signs, and repeated description thereof will be omitted.

[0015] Embodiment 1. [Overall configuration of the main circuit and drive circuit] Figure 1 shows an example configuration of a drive circuit according to Embodiment 1. The drive circuit 1 in Figure 1 drives a plurality of power semiconductor elements connected in parallel. Furthermore, the drive circuit 1 is equipped with a function to detect abnormal conditions (i.e., overcurrent conditions or short-circuit conditions) of the power semiconductor elements, thereby protecting the plurality of power semiconductor elements from abnormal conditions.

[0016] Figure 1 shows, as an example, the U-phase that constitutes the main circuit 101 of the power converter. The drive circuit 1 drives a plurality of parallel-connected power semiconductor elements that constitute the upper arm of the U-phase. The power converter may be an inverse converter that converts DC power to AC power, or a forward converter that converts AC power to DC power.

[0017] Furthermore, Figure 1 illustrates three IGBTs (61p, 62p, and 63p) as multiple power semiconductor elements. The number and type of power semiconductor elements are not limited to these. For example, the number of power semiconductor elements may be two or four or more, and the type of power semiconductor element may be a power MOSFET or a bipolar power transistor.

[0018] Furthermore, multiple power semiconductor elements connected in parallel may be provided on a single main circuit board or on multiple main circuit boards. Also, multiple power semiconductor elements may be arranged in a single row on each main circuit board or in multiple rows.

[0019] The drive circuit 1 comprises a common board 10 and individual boards 30a, 31, and 30c. The common board 10 generates a common drive signal DRS for controlling the on and off states of the parallel-connected IGBTs 61p, 62p, and 63p. The individual boards 30a, 31, and 30c correspond individually to IGBTs 61p, 62p, and 63p, respectively, and supply the generated drive signal DRS to the corresponding IGBT.

[0020] More specifically, the common board 10 includes a control signal input terminal S1, a drive signal output terminal A1, a detection signal input terminal D1, a switching circuit 11, and a logic operation circuit 14. The switching circuit 11 includes an internal turn-on circuit 12 and a turn-off circuit 13.

[0021] Individual circuit board 30a is equipped with a detection signal input terminal D2a and a soft cutoff circuit 21a. Similarly, individual circuit board 30c is equipped with a detection signal input terminal D2c and a soft cutoff circuit 21c. Individual circuit board 31 is equipped with a detection signal output terminal F1, a soft cutoff circuit 21b, and a detection circuit 41. The connections and functions of each component of the common circuit board 10 and individual circuit boards 30a, 31, and 30c will be explained together when describing the operation of the drive circuit 1.

[0022] The main circuit 101 includes U-phase, V-phase, and W-phase connected in parallel to each other between the positive terminal P and the negative terminal N. Although only the configuration of the U-phase is shown in Figure 1, the configurations of the V-phase and W-phase are similar.

[0023] The U-phase of the main circuit 101 includes an upper arm composed of parallel-connected IGBTs 61p, 62p, and 63p, and a lower arm composed of parallel-connected IGBTs 61n, 62n, and 63n.

[0024] IGBT61p and IGBT61n are connected in series between the positive node P1 and the negative node N1 via connecting node U1. IGBT62p and IGBT62n are connected in series between the positive node P2 and the negative node N2 via connecting node U2. IGBT63p and IGBT63n are connected in series between the positive node P3 and the negative node N3 via connecting node U3. Positive node P2 is connected to each of positive nodes P1 and P3, and further connected to the positive terminal P. Negative node N2 is connected to each of negative nodes N1 and N3, and further connected to the negative terminal N. Connecting node U2 is connected to each of connecting nodes U1 and U3, and further connected to the U-phase load terminal U.

[0025] Therefore, the collector terminals 61p_c, 62p_c, and 63p of the IGBT61p, 62p, and 63p constituting the upper arm are connected to the positive terminal P via a common positive node P2. The emitter terminals 61n_e, 62n_e, and 63n_e of the IGBT61n, 62n_e, and 63n_e constituting the lower arm are connected to the negative terminal N via a common negative node N2. The emitter terminal 61p_e of IGBT61p and the collector terminal 61n_c of IGBT61n are connected via connection node U1. The emitter terminal 62p_e of IGBT62p and the collector terminal 62n_c of IGBT62n are connected via connection node U2. The emitter terminal 63p_e of IGBT63p and the collector terminal 63n_c of IGBT63n are connected via connection node U3.

[0026] The gate terminal 61p_g of IGBT61p, which constitutes the upper arm, is connected to the drive signal output terminal A1 of the common board 10 via the corresponding individual board 30a. Similarly, the gate terminal 62p_g of IGBT62p, which constitutes the upper arm, is connected to the drive signal output terminal A1 of the common board 10 via the corresponding individual board 31. Similarly, the gate terminal 63p_g of IGBT63p, which constitutes the upper arm, is connected to the drive signal output terminal A1 of the common board 10 via the corresponding individual board 30c.

[0027] Furthermore, the collector terminal 62p_c of the IGBT62p constituting the upper arm is connected to a detection circuit 41 provided on the corresponding individual circuit board 31 in order to acquire the collector potential. Although not shown in Figure 1, the emitter terminal 62p_e of the IGBT62p constituting the upper arm is also connected to a detection circuit 41 provided on the individual circuit board 31 in order to acquire the emitter potential.

[0028] The gate terminals 61n_g, 62n_g, and 63n_g of the IGBTs 61n, 62n, and 63n that make up the lower arm are connected to a drive circuit for the lower arm (not shown).

[0029] [Operation of the drive circuit] Next, the operation of the drive circuit 1 in Figure 1 will be described. As shown in Figure 1, a control signal CS is input to the control signal input terminal S1 of the common board 10 from outside the drive circuit 1. Furthermore, a detection signal DTS generated by the detection circuit 41 of the individual board 31 is input to the detection signal input terminal D1 of the common board 10. Based on these control signals CS and detection signals DTS, the common board 10 generates a drive signal DRS for driving IGBTs 61p, 62p, and 63p and outputs it from the drive signal output terminal A1.

[0030] More specifically, the logic circuit 14 provided on the common board 10 generates a drive command DRC by performing a logic operation using the control signal CS input to the control signal input terminal S1 and the detection signal DTS input to the detection signal input terminal D1. The logic circuit 14 outputs the drive command DRC to the switching circuit 11 provided on the common board 10.

[0031] For example, when the control signal CS input to the control signal input terminal S1 is at a high level (H) and the detection signal DTS input to the detection signal input terminal D1 is at a low level (L), the logic circuit 14 outputs a drive command DRC at a high level (H) to the switching circuit 11. When the control signal CS input to the control signal input terminal S1 is at a high level and the detection signal DTS input to the detection signal input terminal D1 is at a high level, the logic circuit 14 outputs a drive command DRC at a low level (L) to the switching circuit 11. In other words, when the detection signal DTS is at a low level (L), indicating a normal state, the logic circuit 14 outputs a drive command DRC with a logic level corresponding to the logic level of the control signal CS. When the detection signal DTS is at a high level (H), indicating an abnormal state, the logic circuit 14 outputs a drive command DRC at a low level regardless of the logic level of the control signal CS. In the following explanation, the high level (H) will also be referred to as Hi, and the low level (L) will also be referred to as Lo.

[0032] The switching circuit 11 generates a drive signal DRS by operating the turn-on circuit 12 and the turn-off circuit 13 complementaryly according to the logic level of the drive command DRC input from the logic operation circuit 14. Specifically, in Figure 1, when the drive command DRC is at the H level, the switching element 19a of the turn-on circuit 12 turns on, causing the switching circuit 11 to output a drive signal DRS at the H level. When the drive command DRC is at the L level, the switching element 19b of the turn-off circuit 13 turns on, causing the switching circuit 11 to output a drive signal DRS at the L level.

[0033] The drive signal DRS output from the switching circuit 11 is input to the gate terminals 61p_g, 62p_g, and 63p_g of IGBTs 61p, 62p, and 63p, respectively, via individual boards 30a, 31, and 30c corresponding to IGBTs 61p, 62p, and 63p. When the drive signal DRS is at a high level, IGBTs 61p, 62p, and 63p are turned on, and when the drive signal DRS is at a low level, IGBTs 61p, 62p, and 63p are turned off.

[0034] The detection circuit 41 provided on the individual board 31 detects an abnormal state of IGBT62p based on physical quantities (i.e., electrical characteristics) acquired for IGBT62p, one of the three IGBTs 61p, 62p, and 63p. When the detection circuit 41 detects an abnormal state of IGBT62p, it outputs a detection signal DTS (hereinafter referred to as the abnormality detection signal) indicating the abnormal state to the soft cutoff circuit 21b provided on the individual board 31, and also outputs the detection signal DTS indicating the abnormal state to the outside of the individual board 31 via the detection signal output terminal F1. The detection signal DTS output via the detection signal output terminal F1 is input to the logic circuit 14 via the detection signal input terminal D1 of the common board 10. Furthermore, the detection signal DTS is input to the soft cutoff circuit 21a via the detection signal input terminal D2a of the individual board 30a, and to the soft cutoff circuit 21c via the detection signal input terminal D2c of the individual board 30c. The detailed operation of the detection circuit 41 will be described later.

[0035] The soft cutoff circuit 21a provided on the individual board 30a is connected to the drive signal wiring (more specifically, node E2a on the individual board 30a) that connects the drive signal output terminal A1 of the common board 10 and the gate terminal 61p_g of the IGBT 61p. When the abnormality detection signal DTS is input from the detection circuit 41, the soft cutoff circuit 21a lowers the potential of node E2a on the wiring and clamps the gate-emitter voltage to a predetermined voltage. This temporarily reduces the short-circuit current, making it possible to reduce the rate of current change when the turn-off circuit 13 performs the turn-off operation. This makes it possible to suppress the surge voltage generated when the turn-off circuit 13 performs the turn-off operation.

[0036] Similarly, the soft cutoff circuit 21b provided on the individual board 31 is connected to the wiring of the drive signal DRS connecting the drive signal output terminal A1 of the common board 10 and the gate terminal 62p_g of the IGBT 62p (more specifically, to node E2b on the individual board 31). When the abnormality detection signal DTS is input from the detection circuit 41, the soft cutoff circuit 21b lowers the potential of node E2b on the wiring and clamps the gate-emitter voltage to a predetermined voltage. This temporarily reduces the short-circuit current, making it possible to reduce the rate of current change when the turn-off circuit 13 performs the turn-off operation. This makes it possible to suppress the surge voltage generated when the turn-off circuit 13 performs the turn-off operation.

[0037] Similarly, the soft cutoff circuit 21c provided on the individual board 30c is connected to the drive signal wiring (more specifically, node E2c on the individual board 30c) that connects the drive signal output terminal A1 of the common board 10 and the gate terminal 63p_g of the IGBT 63p. When the abnormality detection signal DTS is input from the detection circuit 41, the soft cutoff circuit 21c lowers the potential of node E2c on the wiring and clamps the gate-emitter voltage to a predetermined voltage. This temporarily reduces the short-circuit current, making it possible to reduce the rate of current change when the turn-off circuit 13 performs the turn-off operation. This makes it possible to suppress the surge voltage generated when the turn-off circuit 13 performs the turn-off operation. Specific circuit configuration examples of the soft cutoff circuits 21a, 21b, and 21c will be described later with reference to Figure 4.

[0038] [Detailed operation of the detection circuit] The operation of the detection circuit 41 in Figure 1 will be described in more detail below. In Embodiment 1, the detection circuit 41 determines an abnormality based on the collector-emitter voltage of the corresponding IGBT62p.

[0039] Three IGBTs 61p, 62p, and 63p connected in parallel, with a common collector-emitter connection, will have equal voltages across each of the parallel-connected IGBTs 61p, 62p, and 63p, assuming individual IGBT variations and parasitic impedance of the wiring are negligible. Furthermore, the currents flowing through each of the IGBTs 61p, 62p, and 63p will also be equal.

[0040] The detection circuit 41 provided on the individual circuit board 31 performs abnormality detection based on the collector-emitter voltage of the corresponding IGBT62p. When the IGBT62p turns on, it enters a short-circuit state and a large short-circuit current flows through the IGBT62p, causing the collector-emitter voltage of the IGBT62p to become higher than the on-voltage during normal operation. Therefore, abnormalities can be detected by appropriately setting a threshold for the collector-emitter voltage.

[0041] If the upper and lower arms of the same phase that constitute the main circuit 101 are turned on simultaneously, the main circuit 101 will short-circuit. Therefore, in the normal operation of the main circuit 101, the upper and lower arms of the same phase are turned on alternately. However, due to IGBT failures or misfires, the upper and lower arms of the same phase may be turned on simultaneously. This is called an arm short circuit.

[0042] When one of the IGBTs constituting the lower arm is in a conductive state due to a short-circuit failure or an incorrect ON signal, an ON command is input to the IGBT connected in parallel to the upper arm, resulting in an arm short circuit. In the drive circuit 1 of Embodiment 1 shown in Figure 1, when an arm short circuit occurs, a detection circuit 41 provided on the individual circuit board 31 corresponding to the IGBT 62p of the upper arm detects the arm short circuit.

[0043] Specifically, suppose that IGBT61n, one of the IGBTs in the lower arm, is in a conductive state, and an ON command is input to all IGBTs in the upper arm. In this case, there are three possible paths for the short-circuit current to flow: one through IGBT61p and IGBT61n, one through IGBT62p and IGBT61n, and one through IGBT63p and IGBT61n.

[0044] In other words, the short-circuit current flowing from the positive terminal P to the negative terminal N is divided at the positive node P2 of the upper arm and flows through all IGBTs 61p, 62p, and 63p of the upper arm. If individual differences in the IGBTs and parasitic impedance of the wiring are negligible, the short-circuit current flows equally through the three IGBTs 61p, 62p, and 63p. At this time, the collector-emitter voltages of IGBTs 61p, 62p, and 63p of the upper arm are the same magnitude and higher than the on-voltage during normal operation. Therefore, the same number of detection circuits 41 as the number of parallel-connected IGBTs are not required to detect an arm short circuit, and an arm short circuit can be detected with one detection circuit 41, which is fewer than the number of parallel IGBTs.

[0045] The above explanation described the case where IGBT61n is short-circuited, but the same applies when IGBT62n or IGBT63n is short-circuited. That is, regardless of which IGBT on the lower arm is short-circuited, if individual differences in the IGBTs and parasitic impedance of the wiring can be ignored, the short-circuit current will flow equally through the three IGBTs on the upper arm. In either case, an arm short circuit can be detected with one detection circuit 41, which is fewer than the number of IGBTs in parallel.

[0046] In addition to arm short circuits, there are also load short circuits, which occur due to loads such as motors. There are two types of load short circuits: one where the load shorts when the upper arm is ON, and another where the load shorts when the lower arm is ON. The detection circuit 41 provided in the drive circuit 1 in Figure 1 is connected to the upper arm, so it can detect load short circuits when the upper arm is ON.

[0047] Specifically, when a load short circuit occurs while the upper arm is ON, a short-circuit current flows from the positive terminal P to the U-phase load terminal U. The short-circuit current is divided at the positive node P2 of the upper arm and flows through all IGBTs 61p, 62p, and 63p of the upper arm. Assuming that individual differences in IGBTs and parasitic impedance of the wiring are negligible, the short-circuit current flows equally through the three IGBTs 61p, 62p, and 63p. At this time, the collector-emitter voltages of IGBTs 61p, 62p, and 63p of the upper arm are the same magnitude and higher than the ON voltage during normal operation. Therefore, it is not necessary to have the same number of detection circuits 41 as the number of parallel-connected IGBTs to detect a load short circuit; a load short circuit can be detected with just one detection circuit 41, which is fewer than the number of parallel IGBTs.

[0048] [Example configuration and operation of detection circuit 41, logic operation circuit, and switching circuit] The following describes the configuration and operation of the detection circuit 41, the logic operation circuit 14, and the switching circuit 11 with reference to Figures 2A and 2B.

[0049] Figure 2A is a circuit diagram showing an example of the detection circuit 41, logic operation circuit 14, and switching circuit 11 of Figure 1. The detection circuit 41 comprises a detection unit 41A and a signal holding unit 41B.

[0050] The signal holding unit 41B in Figure 2A includes a NOT circuit 16a and a set-reset flip-flop (SRFF) circuit 18. The SRFF circuit 18 includes an inverting set terminal ( / S terminal), an inverting reset terminal ( / R terminal), and an output terminal (Q terminal). In this specification, the symbol " / " means inverted. The logic operation circuit 14 also includes a NOT circuit 16b and an AND circuit 17.

[0051] The control signal input terminal S1 is connected to the / R terminal of the SRFF circuit 18 and also to the first input node of the AND circuit 17. Input terminal D1 is connected to the / S terminal of the SRFF circuit 18 via the NOT circuit 16a. The Q terminal of the SRFF circuit 18 is connected to the second input node of the AND circuit 17 via the NOT circuit 16b. The drive command DRC is output from the output node of the AND circuit 17 to the switching circuit 11.

[0052] The switching circuit 11 includes a turn-on circuit 12 and a turn-off circuit 13. The turn-on circuit 12 includes a switching element 19a and a common gate resistor 20a connected in series between the high-potential power supply node VDD and the output node 20c. The turn-off circuit 13 includes a switching element 19b and a common gate resistor 20b connected in series between the low-potential ground GND and the output node 20c. The output node 20c corresponds to the connection point of the common gate resistors 20a and 20b. The switching elements 19a and 19b are, for example, MOSFETs and bipolar transistors. The switching elements 19a and 19b are switched on and off complementaryly in accordance with the drive command DRC.

[0053] Next, the operation of the logic circuit 14 will be explained. The logic circuit 14 receives a control signal CS via the control signal input terminal S1 and a detection signal DTS via the detection signal input terminal D1. In this embodiment, the control signal CS is at a high level (Hi) when the IGBT is turned on and at a low level (Lo) when the IGBT is turned off. In this embodiment, the detection signal DTS is at a low level (Lo) when the main circuit 101 is functioning normally and at a high level (Hi) when an abnormality in the main circuit 101, such as overcurrent or short-circuit current, is detected.

[0054] Figure 2B is a truth table for the SRFF circuit 18 shown in Figure 2A. Before operation starts, an L-level signal is output as the control signal CS to turn off all IGBTs, so an L-level signal is input to the / R terminal. Subsequently, an H-level signal is input to the / R terminal as the control signal CS. In this state, if an L-level signal is input to the / S terminal, the output signal output from the Q terminal becomes H-level. On the other hand, if an H-level signal is input to the / S terminal, the output signal output from the Q terminal becomes L-level. Note that when an L-level signal is input to the / S terminal, the output signal output from the Q terminal becomes H-level regardless of the input signal to the / R terminal. In other words, when the detection unit 41A detects an abnormality, the signal output from / Q remains at H-level (abnormal state) until the detection unit 41A detects normality and the control signal outputs an L-level signal.

[0055] Returning to Figure 2A, we will first explain the operation of the signal holding unit 41B and the logic operation circuit 14 when the main circuit 101 is functioning normally. Before operation begins, a normal signal at an L level is input to the detection signal input terminal D1, so an inverted signal at an H level is input to the / S terminal of the SRFF circuit 18 via the NOT circuit 16a. Also, in order to turn off all IGBTs, an L level signal is output as the control signal CS, and an L level signal is input to the / R terminal. Therefore, an L level signal is output from the Q terminal of the SRFF circuit 18. The L level signal output from the Q terminal of the SRFF circuit 18 is inverted by the NOT circuit 16b and input to the AND circuit 17 as an H level signal. The AND circuit 17 outputs the logical AND of this H level signal and the control signal CS as a drive command DRC to the switching circuit 11. Therefore, an L level signal is output as the drive command DRC output from the AND circuit 17. Next, a turn-on command is output. In other words, when an H-level signal is input to the / R terminal, the output signal output from the Q terminal becomes L-level because an H-level signal is also input to the / S terminal, and the drive command DRC output from the AND circuit 17 becomes H-level.

[0056] Next, the operation of the signal holding unit 41B and the logic operation circuit 14 when the main circuit 101 is abnormal will be explained. In this case, an H-level signal is input to the detection signal input terminal D1, starting from a state where an H-level signal is input to the / R terminal and an H-level signal is input to the / S terminal. Therefore, an inverted signal, an L-level signal, is input to the / S terminal of the SRFF circuit 18 via the NOT circuit 16a. This causes an H-level signal to be output from the Q terminal. The H-level signal output from the Q terminal is inverted by the NOT circuit 16b and input to the AND circuit 17 as an L-level signal. The AND circuit 17 outputs a logical AND of this L-level signal and the control signal CS. Therefore, the drive command DRC output from the AND circuit 17 becomes L-level, and this L-level drive command DRC is input to the switching circuit 11.

[0057] In this manner, when the detection circuit 41 detects an abnormality in the main circuit 101, a detection signal DTS at the H level is input to the detection signal input terminal D1, and the drive command DRC input to the switching circuit 11 becomes L level. As a result, the switching circuit 11 performs a turn-off operation.

[0058] Next, the operation of the switching circuit 11 will be explained. The switching circuit 11 receives a drive command DRC output from the logic circuit 14. Based on the drive command DRC input to the switching circuit 11, the turn-on circuit 12 and the turn-off circuit 13 operate complementaryly, and a drive signal DRS is output to IGBTs 61p, 62p, and 63p. When an ON command (high-level drive command DRC) is input, the switching element 19a of the turn-on circuit 12 turns ON, turning IGBTs 61p, 62p, and 63p to the ON state. When an OFF command (low-level drive command DRC) is input, the switching element 19b of the turn-off circuit 13 turns ON, turning IGBTs 61p, 62p, and 63p to the OFF state.

[0059] The operation of the logic circuit 14 and the switching circuit 11 described above can be summarized as follows: When the logic circuit 14 receives an abnormality detection signal DTS via the detection signal input terminal D1 of the common board 10, it sets the drive command DRC input to the switching circuit 11 to an OFF command (L level in this embodiment) and maintains that state. When the switching circuit 11 receives an OFF command, if IGBTs 61p, 62p, and 63p are ON, it turns OFF and maintains that OFF state thereafter. Also, when the switching circuit 11 receives an OFF command, if IGBTs 61p, 62p, and 63p are OFF, it maintains that OFF state.

[0060] On the other hand, if the detection signal DTS input via the detection signal input terminal D1 of the common board 10 indicates a normal state, the logic operation circuit 14 switches the drive command DRC to an ON command and an OFF command according to the logic level of the control signal CS. As a result, the switching circuit 11 switches IGBTs 61p, 62p, and 63p to the ON state and the OFF state, respectively, according to the ON and OFF commands of the drive command DRC.

[0061] Figure 3 shows another example of the configuration of the drive circuit according to Embodiment 1. In Figure 1, the individual board 30a had a soft cutoff circuit 21a, the individual board 30c had a soft cutoff circuit 21c, and the individual board 31 had a soft cutoff circuit 21b and a detection circuit 41. In Figure 3, however, the common board 10 has a soft cutoff circuit 15 instead.

[0062] The soft cutoff circuit 15 provided on the common board 10 is connected to the wiring for the drive signal (more specifically, node E1 of the wiring) that connects the switching circuit 11 of the common board 10 to the drive signal output terminal A1. When the soft cutoff circuit 15 receives an abnormality detection signal DTS from the detection circuit 41 indicating that the main circuit 101 is in an abnormal state, it lowers the potential of node E1 of the wiring and clamps the gate-emitter voltage to a predetermined voltage. This temporarily reduces the short-circuit current, making it possible to reduce the rate of current change when the turn-off circuit 13 performs the turn-off operation. This makes it possible to suppress the surge voltage generated when the turn-off circuit 13 performs the turn-off operation.

[0063] [Example configuration and operation of a soft-cut circuit] Figure 4 is a circuit diagram showing an example configuration of the soft-cut circuit 21b in Figure 1. The configuration example and operation of the soft-cut circuit 21b will be explained below with reference to Figure 4. The configuration and operation of soft-cut circuits 15, 21a, and 21c are similar.

[0064] The soft-cut circuit 21b in Figure 4 comprises an N-channel MOSFET 23, resistors 24 and 26, and a diode 25. The drain of the MOSFET 23 is connected to connection node E2b via the series-connected diode 25 and the soft-cut resistor 26. The direction of the drain of the MOSFET 23 from connection node E2b is the forward direction of the diode 25. The source of the MOSFET 23 is connected to the ground GND of the drive circuit 1. The gate of the MOSFET 23 is connected to the detection signal input terminal D1 via the resistor 24 for driving the MOSFET.

[0065] Next, the operation of the soft cutoff circuit 21b will be described with reference to Figures 2A and 4. When the detection circuit 41 has not detected any abnormality in the main circuit 101, an L-level detection signal DTS is input to the gate of MOSFET 23 via the detection signal input terminal D1. Therefore, MOSFET 23 is in the off state. In this case, when IGBTs 61p, 62p, and 63p are turned off, the charge on the gates of IGBTs 61p, 62p, and 63p is drawn out via the common gate resistor 20b of the turnoff circuit 13, causing IGBTs 61p, 62p, and 63p to turn off.

[0066] On the other hand, when IGBTs 61p, 62p, and 63p are ON, if an H-level abnormality detection signal DTS is input to the gate of MOSFET 23 from the detection circuit 41, MOSFET 23 turns ON. As a result, the output node 20c of the switching circuit 11 is connected to the power node VDD via the common gate resistor 20a of the turn-on circuit 12, and also to ground GND via the resistor element 26 of the soft-cut circuit. Consequently, the voltage between the power node VDD and ground GND is divided by the common gate resistor 20a and the soft-cut resistor element 26, and the divided voltage is applied between the gates and emitters of IGBTs 61p, 62p, and 63p, causing the gate-emitter voltages of IGBTs 61p, 62p, and 63p to decrease. This decrease in gate-emitter voltage reduces the short-circuit current flowing through IGBTs 61p, 62p, and 63p. The abnormality detection signal DTS is also input to the logic circuit 14, but due to the time delay in the logic circuit 14, the drive command DRC does not immediately switch from an on command to an off command. Therefore, after the short-circuit current decreases due to the drop in the gate-emitter voltage, the drive command DRC switches to an off command, which causes the charge on the gates of IGBTs 61p, 62p, and 63p to be withdrawn via the common gate resistor 20b of the turn-off circuit 13. As a result, the current peak value and current change rate di / dt when IGBTs 61p, 62p, and 63p are turned off by the turn-off circuit 13 can be reduced, thereby suppressing surge voltage. In other words, soft interruption of IGBTs 61p, 62p, and 63p is achieved.

[0067] [Effects of Embodiment 1] As described above, according to the drive circuit 1 of Embodiment 1, a detection circuit 41 is provided on one of the individual substrates (individual substrates 30a, 31, 30c) corresponding to each of the multiple power semiconductor switching elements (IGBTs 61p, 62p, 63p) connected in parallel. This detection circuit 41 can detect abnormalities in the multiple power semiconductor switching elements connected in parallel. When an abnormality in these power semiconductor switching elements is detected, the drive command DRC input from the logic operation circuit 14 to the switching circuit 11 is held as an off command. This ensures that the multiple power semiconductor switching elements connected in parallel are reliably turned off, protecting them.

[0068] Furthermore, when an anomaly occurs, a large current flows through multiple power semiconductor switching elements connected in parallel. If such a large current is interrupted at the normal operating cutoff speed, a large surge voltage may be generated, potentially destroying these power semiconductor switching elements. (Off-operation speed during an anomaly) Regarding By clamping the gate-emitter voltage to a predetermined voltage using the resistance value of the soft-cutting resistor element 26 provided in the soft-cutting circuit 15 or 21a, 21b, and 21c, the short-circuit current can be temporarily reduced, thereby reducing the rate of current change during the turn-off operation by the turn-off circuit 13. In this way, damage to the power semiconductor switching element due to the off operation when an abnormality is detected can be prevented.

[0069] Therefore, it is possible to detect abnormalities in multiple power semiconductor switching elements connected in parallel and protect these power semiconductor switching elements with a low-cost and simple configuration.

[0070] [Modified example of Embodiment 1] In Embodiment 1, IGBTs 61p, 62p, and 63p were used as examples of multiple power semiconductor switching elements connected in parallel, but the power semiconductor switching elements are not necessarily limited to IGBTs. For example, MOSFETs can be used as power semiconductor switching elements, and other types of semiconductor switching elements can also be used. Furthermore, the material of the power semiconductor switching element is not limited to silicon, but may be a wide-bandgap semiconductor (for example, silicon carbide, gallium nitride, gallium oxide, diamond, etc.).

[0071] Furthermore, the above-mentioned power semiconductor switching elements may be in either discrete or power module form. Types of power modules include 1-in-1 modules (1-pack modules) that constitute one arm of the power converter, 2-in-1 modules (2-pack modules) that constitute one phase of the power converter, i.e., two arms connected in series, and 6-in-1 modules (6-pack modules) that constitute the three phase upper and lower arms of the power converter. If the IGBTs connected in parallel are in power module form, any module with any circuit configuration may be used, or modules with other configurations may be used.

[0072] The drive circuit 1 in Figure 1 may be configured to drive the lower arm of the main circuit 101. Alternatively, a drive circuit for driving the upper arm of the main circuit 101 and a drive circuit for driving the lower arm of the main circuit 101 may be provided separately. The case in which the drive circuit 1 drives the lower arm of the main circuit 101 will be described below with reference to Figure 5.

[0073] Figure 5 shows an example of the configuration of a drive circuit according to a modification of Embodiment 1. The drive circuit 1 in Figure 5 differs from the drive circuit 1 in Figure 1 in that it drives IGBTs 61n, 62n, and 63n which constitute the lower arm of the main circuit 101, instead of IGBTs 61p, 62p, and 63p which constitute the upper arm of the main circuit 101. The drive circuit 1 in Figure 5 protects multiple power semiconductor elements from abnormal conditions by having a function to detect abnormal conditions of the parallel-connected IGBTs 61n, 62n, and 63n.

[0074] More specifically, the configuration of the drive circuit 1 in Figure 5 and the configuration of the main circuit 101 in Figure 5 are the same as in Figure 1, but the connection between them differs from that in Figure 1. Below, we will mainly explain the differences from that in Figure 1, and parts that are the same as or equivalent to those in Figure 1 will be given the same reference numerals and will not be repeated in the explanation.

[0075] As shown in Figure 5, the common board 10 constituting the drive circuit 1 generates a common drive signal DRS for controlling the on and off states of the IGBTs 61n, 62n, and 63n that constitute the parallel-connected lower arm. The individual boards 30a, 31, and 30c constituting the drive circuit 1 each correspond individually to IGBTs 61n, 62n, and 63n, respectively, and supply the generated drive signal DRS to the corresponding IGBT.

[0076] Specifically, the gate terminal 61n_g of IGBT61n, which constitutes the lower arm, is connected to the drive signal output terminal A1 of the common board 10 via the corresponding individual board 30a. Similarly, the gate terminal 62n_g of IGBT62n, which constitutes the lower arm, is connected to the drive signal output terminal A1 of the common board 10 via the corresponding individual board 31. Similarly, the gate terminal 63n_g of IGBT63n, which constitutes the lower arm, is connected to the drive signal output terminal A1 of the common board 10 via the corresponding individual board 30c.

[0077] Furthermore, the collector terminal 62n_c of the IGBT62n constituting the lower arm is connected to a detection circuit 41 provided on the corresponding individual circuit board 31 in order to acquire the collector potential. Although not shown in Figure 5, the emitter terminal 62n_e of the IGBT62n constituting the lower arm is also connected to a detection circuit 41 provided on the individual circuit board 31 in order to acquire the emitter potential.

[0078] The soft cutoff circuit 21a on individual board 30a is connected to the drive signal wiring (more specifically, node E2a on individual board 30a) that connects the drive signal output terminal A1 on the common board 10 to the gate terminal 61n_g of IGBT61n. The soft cutoff circuit 21b on individual board 31 is connected to the drive signal DRS wiring (more specifically, node E2b on individual board 31) that connects the drive signal output terminal A1 on the common board 10 to the gate terminal 62n_g of IGBT62n. The soft cutoff circuit 21c on individual board 30c is connected to the drive signal wiring (more specifically, node E2c on individual board 30c) that connects the drive signal output terminal A1 on the common board 10 to the gate terminal 63n_g of IGBT63n.

[0079] Similar to the case in Figure 1, when the abnormality detection signal DTS is input from the detection circuit 41, the soft interruption circuits 21a to 21c lower the potential of nodes E2a to E2c, respectively, and clamp the gate-emitter voltage to a predetermined voltage. This temporarily reduces the short-circuit current, thereby reducing the rate of current change when the turn-off circuit 13 performs the turn-off operation. This suppresses the surge voltage generated when the turn-off circuit 13 performs the turn-off operation.

[0080] The gate terminals 61p_g, 62p_g, and 63p_g of the IGBTs 61p, 62p, and 63p that make up the upper arm are connected to a drive circuit for the upper arm, which is not shown in the diagram.

[0081] The operation of the detection circuit 41 in the drive circuit 1 shown in Figure 5 will be described below. The detection circuit 41 determines an abnormality in the main circuit 101 based on the collector-emitter voltage of the IGBT62n.

[0082] Three IGBTs 61n, 62n, and 63n connected in parallel, with a common collector-emitter connection, will have equal voltages across each of the parallel-connected IGBTs 61n, 62n, and 63n, provided that individual IGBT variations and parasitic impedances in the wiring are negligible. Similarly, the currents flowing through each of the IGBTs 61n, 62n, and 63n will also be equal.

[0083] The detection circuit 41 provided on the individual circuit board 31 performs abnormality detection based on the collector-emitter voltage of the corresponding IGBT62n. When a short circuit occurs and a large short-circuit current flows through the IGBT62n, the collector-emitter voltage of the IGBT62n becomes higher than the on-voltage during normal operation. Therefore, abnormalities can be detected by appropriately setting a threshold for the collector-emitter voltage.

[0084] The operation of the detection circuit 41 in the drive circuit 1 shown in Figure 5 will be specifically explained below in the case of arm short circuit and load short circuit.

[0085] When one of the IGBTs constituting the upper arm is in a conductive state due to a short-circuit failure or an incorrect ON signal, an ON command is input to the parallel-connected IGBT of the lower arm, resulting in an arm short circuit. In the drive circuit 1 of Figure 5, when an arm short circuit occurs, a detection circuit 41 provided on the individual circuit board 31 corresponding to the IGBT 62n of the lower arm detects the arm short circuit.

[0086] Specifically, suppose that when IGBT61p on the upper arm is conducting, an ON command is input to all IGBTs on the lower arm. In this case, there are three possible paths for the short-circuit current to flow: one through IGBT61p and IGBT61n, one through IGBT61p and IGBT62n, and one through IGBT61p and IGBT63n.

[0087] In other words, the short-circuit current flowing from the positive terminal P to the negative terminal N flows through the conducting upper arm IGBT 61p, is divided at the connection node U1, and flows through all the lower arm IGBTs 61n, 62n, and 63n. If individual differences in the IGBTs and parasitic impedance of the wiring are negligible, the short-circuit current flows equally through the three IGBTs 61n, 62n, and 63n. At this time, the collector-emitter voltages of the lower arm IGBTs 61n, 62n, and 63n are the same magnitude and higher than the on-voltage during normal operation. Therefore, it is not necessary to have the same number of detection circuits 41 as the number of parallel-connected IGBTs to detect an arm short circuit; an arm short circuit can be detected with just one detection circuit 41, which is fewer than the number of parallel IGBTs.

[0088] The above explanation described the case where IGBT61p is short-circuited, but the same applies if IGBT62p or IGBT63p is short-circuited. In other words, regardless of which IGBT on the upper arm is short-circuited, if individual differences in IGBTs and parasitic impedance of the wiring can be ignored, the short-circuit current will flow equally through the three IGBTs on the lower arm. In either case, an arm short-circuit can be detected with one detection circuit 41, which is fewer than the number of IGBTs in parallel.

[0089] Next, we will explain load short circuits. As mentioned above, there are two cases in which a load short circuit occurs: when the upper arm is ON, and when the lower arm is ON. Since the drive circuit 1 in Figure 5 is connected to the lower arm, it can detect load short circuits when the lower arm is ON.

[0090] Specifically, when a load short circuit occurs while the lower arm is ON, a short-circuit current flows from the U-phase load terminal U to the negative terminal N. The short-circuit current is divided at the connection node U2 connected to the U-phase load terminal U and flows through all IGBTs 61n, 62n, and 63n of the lower arm. Assuming individual differences in the elements and parasitic impedance of the wiring can be ignored, the short-circuit current flows equally through the three IGBTs 61n, 62n, and 63n. The collector-emitter voltages of the IGBTs 61n, 62n, and 63n of the lower arm become the same magnitude and higher than the ON voltage during normal operation. Therefore, it is not necessary to have the same number of detection circuits 41 as the number of parallel-connected IGBTs to detect a load short circuit; a load short circuit can be detected with just one detection circuit 41, which is fewer than the number of parallel IGBTs.

[0091] As described above, according to the drive circuit 1 shown in Figure 5, which is a modified example of Embodiment 1, a detection circuit 41 is provided on one of the individual substrates 30a, 31, or 30c, which correspond to each of the multiple IGBTs 61n, 62n, and 63n connected in parallel on the lower arm. This detection circuit 41 can detect abnormalities in the multiple IGBTs 61n, 62n, and 63n connected in parallel.

[0092] Embodiment 2. In the drive circuit 2 of Embodiment 2, the method by which the detection circuit 42 detects an abnormal state of the IGBT 62p differs from that of the detection circuit 41 of Embodiment 1. This will be explained below with reference to Figures 6 to 8.

[0093] [Overall configuration of the main circuit and drive circuit] Figure 6 shows an example of the configuration of a drive circuit according to Embodiment 2. In Figure 6, the main circuit 101 for one phase of the power converter and the drive circuit 2 that drives the IGBTs 61p, 62p, and 63p of the upper arm of the main circuit 101 are shown. The configuration of the main circuit 101 in Figure 6 is the same as in Embodiment 1 shown in Figure 1, so the same or corresponding parts are denoted by the same reference numerals and the description will not be repeated.

[0094] The drive circuit 2 comprises a common board 10 and individual boards 30a, 32, and 30c. The common board 10 generates a common drive signal DRS for controlling the on and off states of the parallel-connected IGBTs 61p, 62p, and 63p. The individual boards 30a, 32, and 30c correspond individually to IGBTs 61p, 62p, and 63p, respectively, and supply the generated drive signal DRS to the corresponding IGBT. The configurations of the common board 10 and the individual boards 30a and 30c are the same as in Embodiment 1 described in Figure 1, so the same or corresponding parts are denoted by the same reference numerals and the description will not be repeated. Also, the connection relationships between the common board 10 and the individual boards 30a and 30c and the main circuit 101 are the same as in Embodiment 1, so the description will not be repeated.

[0095] The individual circuit board 32 includes a detection signal output terminal F1, a soft cutoff circuit 21b, a detection circuit 42, and individual gate resistors 52. The connections and functions of these components will be explained together when describing the operation of the drive circuit 2.

[0096] Furthermore, the individual circuit boards 30a and 30c are equipped with individual gate resistors (not shown). [Operation of the drive circuit] Next, the operation of the drive circuit 2 in Figure 6 will be described. Below, we will mainly describe the operation of the individual circuit board 32, which differs from the case of Embodiment 1. The operation of the common circuit board 10 and the individual circuit boards 30a and 30c is the same as in Embodiment 1, except that the detection circuit 42 is used instead of the detection circuit 41, so we will not repeat the detailed explanation.

[0097] On the individual circuit board 32, the individual gate resistor 52 is connected between the drive signal output terminal A1 of the common circuit board 10 and the gate terminal 62p_g of the IGBT 62p corresponding to the individual circuit board 32. In other words, the individual gate resistor 52 is provided on the wiring of the drive signal DRS.

[0098] The detection circuit 42 detects an abnormal state of the IGBT62p based on a physical quantity obtained from the corresponding IGBT62p. When the detection circuit 42 detects an abnormal state of the IGBT62p, it outputs a detection signal DTS to the soft cutoff circuit 21b provided on the individual board 32, and also outputs the detection signal DTS to the outside of the individual board 32 via the detection signal output terminal F1. The detection signal DTS output via the detection signal output terminal F1 is input to the logic circuit 14 via the detection signal input terminal D1 of the common board 10. Furthermore, the detection signal DTS is input to the soft cutoff circuit 21a via the detection signal input terminal D2a of the individual board 30a, and to the soft cutoff circuit 21c via the detection signal input terminal D2c of the individual board 30c.

[0099] The connection and operation of the soft cutoff circuit 21b are the same as in the first embodiment. That is, it is connected to the wiring of the drive signal DRS that connects the drive signal output terminal A1 of the common board 10 and the gate terminal 62p_g of the IGBT 62p (more specifically, to node E2b of the individual board 31). When the abnormality detection signal DTS is input to the soft cutoff circuit 21b, it lowers the potential of node E2b on the wiring and clamps the gate-emitter voltage to a predetermined voltage. This temporarily reduces the short-circuit current, making it possible to reduce the rate of current change when the turn-off circuit 13 performs a turn-off operation. This makes it possible to suppress the surge voltage generated when the turn-off circuit 13 performs a turn-off operation.

[0100] The operation of the detection circuit 42 provided on the individual circuit board 32 will be explained in more detail below. As shown in Figure 6, the detection circuit 42 detects the potential across the individual gate resistor 52. Furthermore, although not shown in Figure 6, the detection circuit 42 is connected to the emitter terminal 62p_e of the corresponding IGBT 62p to detect the emitter potential of the IGBT 62p.

[0101] The detection circuit 42 detects abnormalities in the IGBT62p based on the gate charge characteristics of the IGBT62p. Specifically, the detection circuit 42 detects a voltage equivalent to the gate charge by integrating the voltage across the individual gate resistors 52, and also detects the gate-emitter voltage. The relationship between the gate-emitter voltage and the gate charge is called the gate charge characteristic. Since the gate charge characteristics of the IGBT62p normally differ between switching and short-circuit conditions, abnormalities can be detected by setting an appropriate threshold.

[0102] Figure 7 shows an example of the gate charge characteristics of an IGBT. The vertical axis in Figure 7 represents the gate-emitter voltage Vge, and the horizontal axis represents the gate charge Qg. The gate charge characteristics under normal conditions are shown by a solid line, and the gate charge characteristics under arm short circuit conditions are shown by a dashed line. The behavior of the IGBT under normal conditions and under arm short circuit conditions will be explained below with reference to Figure 7, and further, a method for detecting arm short circuit conditions based on the behavior of the IGBT will be explained.

[0103] Under normal conditions, when a turn-on signal is input to the gate of the IGBT from the switching circuit 11, the gate-emitter voltage rises and the gate-emitter capacitance is charged. When the gate-emitter voltage exceeds the threshold voltage of the IGBT, collector current begins to flow.

[0104] Once the gate-emitter capacitance is fully charged, the collector-emitter voltage begins to decrease, and the collector-gate capacitance begins to charge. During this time, the gate-emitter voltage remains constant (hereinafter referred to as the Miller voltage). This period during which the gate-emitter voltage remains constant is called the Miller period. When the collector-emitter voltage drops to the IGBT's ON voltage, the gate-emitter voltage begins to rise again, eventually reaching the power supply voltage of the gate drive circuit.

[0105] Therefore, under normal conditions, as shown by the solid line in Figure 7, the amount of charge Qg supplied to the gate of the IGBT increases as the gate-emitter voltage Vge rises based on the turn-on command. When the gate-emitter voltage Vge rises to the Miller voltage Vm, the gate-emitter voltage Vge remains constant at the Miller voltage Vm, but the amount of charge Qg supplied to the gate of the IGBT continues to increase. When the amount of charge Qg supplied to the gate of the IGBT reaches Q1, the Miller period ends, and the gate-emitter voltage Vge increases again. Subsequently, the gate-emitter voltage Vge reaches the power supply voltage Vd of the gate drive circuit. At that time, the amount of charge Qg is Qd.

[0106] On the other hand, when the arm is short-circuited, the collector-emitter voltage Vce remains at a high voltage and hardly changes. Therefore, the collector-gate capacitance remains almost constant. As a result, the gate current supplied from the switching circuit 11 only charges the gate-emitter capacitance. Consequently, as shown by the dashed line in Figure 7, there is no Miller period in which the gate-emitter voltage Vge remains constant, and the gate-emitter voltage Vge rises rapidly to the power supply voltage Vd of the gate drive circuit.

[0107] Thus, a significant difference is observed in the gate charge characteristics, specifically the relationship between the gate-emitter voltage Vge and the gate charge Qg, between the normal operation of the IGBT and the arm short-circuit operation.

[0108] Based on the above, we will refer again to Figure 6 and describe the method for detecting abnormalities when an arm short circuit or load short circuit occurs in the main circuit 101. First, we will explain the case when an arm short circuit occurs.

[0109] When one of the IGBTs constituting the lower arm is in a conductive state due to a short-circuit failure or a false ON signal, an ON command is input to the IGBT connected in parallel to the upper arm, causing an arm short circuit. In the drive circuit 2 of Embodiment 2 shown in Figure 6, when an arm short circuit occurs, a detection circuit 42 provided on the individual circuit board 32 corresponding to the IGBT 62p of the upper arm detects the arm short circuit.

[0110] Specifically, let's assume that when the IGBT61n on the lower arm is conducting, an ON command is input to the IGBT on the upper arm. In this case, there are three possible paths for the short-circuit current to flow: one through IGBT61p and IGBT61n, one through IGBT62p and IGBT61n, and one through IGBT63p and IGBT61n.

[0111] In other words, the short-circuit current flowing from the positive terminal P to the negative terminal N is divided at the positive node P2 of the upper arm and flows through all IGBTs 61p, 62p, and 63p of the upper arm. Assuming individual differences in the elements and parasitic impedance of the wiring are negligible, the short-circuit current flows equally through the three IGBTs 61p, 62p, and 63p. The collector-emitter voltages of IGBTs 61p, 62p, and 63p of the upper arm are the same magnitude and higher than the on-voltage during normal operation. Also, the gate-emitter voltage Vge of these IGBTs is the same magnitude. Therefore, it is not necessary to have the same number of detection circuits 42 as the number of parallel-connected IGBTs to detect an arm short circuit; an arm short circuit can be detected with one detection circuit 42, which is fewer than the number of parallel IGBTs.

[0112] As explained with reference to Figure 7, the collector-gate capacitance of an IGBT is highly dependent on the collector-emitter voltage. Therefore, the difference in collector-emitter voltage between normal operation and arm short-circuit operation can be detected as a difference in gate charge characteristics. For example, as shown in Figure 7, whether the IGBT is functioning normally or abnormally can be detected by whether the amount of charge Qg supplied to the gate of the IGBT before the gate-emitter voltage Vge reaches the voltage value VR is greater than or equal to the threshold QR.

[0113] The above explanation describes the case where IGBT61n is short-circuited, but the same applies if IGBT62n or IGBT63n is short-circuited. That is, regardless of which IGBT on the lower arm is short-circuited, if individual differences in the IGBTs and parasitic impedance of the wiring can be ignored, the short-circuit current will flow equally through the three IGBTs on the upper arm. In either case, an arm short-circuit can be detected with one detection circuit 41, which is fewer than the number of IGBTs in parallel.

[0114] Next, we will explain what happens when a load short circuit occurs. There are two types of load short circuits: one when the load is short-circuited while the upper arm is ON, and another when the load is short-circuited while the lower arm is ON. The detection circuit 42 provided in the drive circuit 2 in Figure 6 is connected to the upper arm, so it can detect a load short circuit when the upper arm is ON.

[0115] When the upper arm is turned ON, the collector-emitter voltage of the upper arm IGBT initially drops to the ON voltage, similar to normal turn-on operation. Subsequently, when a load short circuit occurs, the load inductance becomes smaller compared to normal operation, resulting in a larger collector current. Therefore, the collector current increases rapidly, and the collector-emitter voltage rises again. As the collector-emitter voltage rises again, a displacement current flows from the collector terminal to the gate terminal, increasing the gate-emitter voltage and decreasing the gate charge. Thus, a load short circuit can be detected by detecting that the gate-emitter voltage is higher than normal and the gate charge is decreasing.

[0116] Specifically, when a load short circuit occurs while the upper arm is ON, a short-circuit current flows from the positive terminal P to the U-phase load terminal U. The short-circuit current is divided at the positive node P2 of the upper arm and flows through all IGBTs 61p, 62p, and 63p of the upper arm. Assuming individual differences in the elements and parasitic impedance of the wiring are negligible, the short-circuit current flows equally through the three IGBTs 61p, 62p, and 63p. The collector-emitter voltages of IGBTs 61p, 62p, and 63p of the upper arm are the same magnitude, decrease once, and then rise again. Therefore, it is not necessary to have the same number of detection circuits 42 as the number of parallel-connected IGBTs to detect a load short circuit; a load short circuit can be detected with one detection circuit 42, which is fewer than the number of parallel IGBTs.

[0117] [Effects of Embodiment 2] As described above, according to the drive circuit 2 of Embodiment 2, a detection circuit 42 is provided on one of the individual substrates (individual substrates 30a, 32, 30c) corresponding to each of the multiple power semiconductor switching elements (IGBTs 61p, 62p, 63p) connected in parallel. This detection circuit 42 can detect abnormalities in the multiple power semiconductor switching elements connected in parallel.

[0118] Specifically, the detection circuit 42 detects the voltage across the individual gate resistors 52 and also detects the gate-emitter voltage of the IGBT62p. Based on the gate charge characteristics of the IGBT62p obtained from these detected values, the detection circuit 42 performs abnormality detection of the IGBT62p.

[0119] [Modified version of Embodiment 2] The drive circuit 2 in Figure 6 may be configured to drive the lower arm of the main circuit 101. Alternatively, a drive circuit for driving the upper arm of the main circuit 101 and a drive circuit for driving the lower arm of the main circuit 101 may be provided separately. The case in which the drive circuit 2 drives the lower arm of the main circuit 101 will be described below with reference to Figure 8.

[0120] Figure 8 shows an example of the configuration of a drive circuit according to a modified embodiment of the second embodiment. The drive circuit 2 in Figure 8 differs from the drive circuit 2 in Figure 6 in that it drives IGBTs 61n, 62n, and 63n which constitute the lower arm of the main circuit 101, instead of IGBTs 61p, 62p, and 63p which constitute the upper arm of the main circuit 101. The drive circuit 2 in Figure 8 protects multiple power semiconductor elements from abnormal conditions by having a function to detect abnormal conditions of the parallel-connected IGBTs 61n, 62n, and 63n.

[0121] More specifically, the configuration of the drive circuit 2 in Figure 8 and the configuration of the main circuit 101 in Figure 8 are the same as in Figure 6, but the connection between them differs from that in Figure 6. Below, we will mainly explain the differences from that in Figure 6, and parts that are the same as or equivalent to those in Figure 6 will be given the same reference numerals and will not be repeated in the explanation.

[0122] As shown in Figure 8, the common board 10 constituting the drive circuit 2 generates a common drive signal DRS for controlling the on and off states of the IGBTs 61n, 62n, and 63n that constitute the parallel-connected lower arm. The individual boards 30a, 32, and 30c constituting the drive circuit 2 each correspond individually to IGBTs 61n, 62n, and 63n, respectively, and supply the generated drive signal DRS to the corresponding IGBT.

[0123] Specifically, the gate terminal 61n_g of IGBT61n, which constitutes the lower arm, is connected to the drive signal output terminal A1 of the common board 10 via the corresponding individual board 30a. Similarly, the gate terminal 62n_g of IGBT62n, which constitutes the lower arm, is connected to the drive signal output terminal A1 of the common board 10 via the corresponding individual board 32. Similarly, the gate terminal 63n_g of IGBT63n, which constitutes the lower arm, is connected to the drive signal output terminal A1 of the common board 10 via the corresponding individual board 30c.

[0124] On the individual circuit board 32, the individual gate resistor 52 is connected between the drive signal output terminal A1 of the common circuit board 10 and the gate terminal 62n_g of the IGBT 62n corresponding to the individual circuit board 32. In other words, the individual gate resistor 52 is provided on the wiring of the drive signal DRS.

[0125] Furthermore, the individual circuit boards 30a and 30c are equipped with individual gate resistors (not shown). The soft cutoff circuit 21a on individual board 30a is connected to the drive signal wiring (more specifically, node E2a on individual board 30a) that connects the drive signal output terminal A1 on the common board 10 to the gate terminal 61n_g of IGBT61n. The soft cutoff circuit 21b on individual board 32 is connected to the drive signal DRS wiring (more specifically, node E2b on individual board 32) that connects the drive signal output terminal A1 on the common board 10 to the gate terminal 62n_g of IGBT62n. Node E2b is closer to the gate terminal 62n_g than the individual gate resistor 52. The soft cutoff circuit 21c on individual board 30c is connected to the drive signal wiring (more specifically, node E2c on individual board 30c) that connects the drive signal output terminal A1 on the common board 10 to the gate terminal 63n_g of IGBT63n.

[0126] Similar to the case in Figure 6, when the abnormality detection signal DTS is input from the detection circuit 42, the soft cutoff circuits 21a to 21c lower the potential of nodes E2a to E2c, respectively, and clamp the gate-emitter voltage to a predetermined voltage. This temporarily reduces the short-circuit current, thereby lowering the rate of current change when the turn-off circuit 13 performs a turn-off operation.

[0127] The detection circuit 42 on the individual circuit board 32 is connected to both ends of the individual gate resistor 52, thereby detecting the voltage across the individual gate resistor 52. Although not shown in Figure 8, the detection circuit 42 is also connected to the emitter terminal 62n_e of the IGBT 62n that constitutes the lower arm, thereby detecting the gate-emitter voltage.

[0128] The detection circuit 42 detects abnormalities in the IGBT62n based on the gate charge characteristics of the IGBT62n obtained from these detected values. Specifically, the detection circuit 42 detects a voltage equivalent to the gate charge amount by integrating the voltage across the individual gate resistors 52, and also detects the gate-emitter voltage. Since the gate charge characteristics of the IGBT62n differ between normal switching and short-circuit conditions, abnormalities can be detected by appropriately setting thresholds.

[0129] The operation of the detection circuit 42 in the drive circuit 2 shown in Figure 8 will be explained in detail below, specifically in the case of arm short circuit and load short circuit.

[0130] When one of the IGBTs constituting the upper arm is in a conductive state due to a short-circuit failure or an incorrect ON signal, an ON command is input to the parallel-connected IGBT of the lower arm, causing an arm short circuit. In the drive circuit 2 of Embodiment 2 shown in Figure 8, when an arm short circuit occurs, a detection circuit 42 provided on the individual circuit board 32 corresponding to the IGBT 62n of the lower arm detects the arm short circuit.

[0131] Specifically, suppose that when IGBT61p on the upper arm is conducting, an ON command is input to all IGBTs on the lower arm. In this case, there are three possible paths for the short-circuit current to flow: one through IGBT61p and IGBT61n, one through IGBT61p and IGBT62n, and one through IGBT61p and IGBT63n.

[0132] In other words, the short-circuit current flowing from the positive terminal P to the negative terminal N flows through the conducting upper arm IGBT 61p, is divided at the connection node U1, and flows through all the lower arm IGBTs 61n, 62n, and 63n. Assuming that individual differences in IGBTs and parasitic impedance of the wiring are negligible, the short-circuit current flows equally through the three IGBTs 61n, 62n, and 63n. The collector-emitter voltages of the lower arm IGBTs 61n, 62n, and 63n are the same magnitude and higher than the on-voltage during normal operation. Also, the gate-emitter voltage Vge of these IGBTs is the same magnitude. Therefore, it is not necessary to have the same number of detection circuits 42 as the number of parallel-connected IGBTs to detect an arm short circuit; an arm short circuit can be detected with just one detection circuit 42, which is fewer than the number of parallel IGBTs.

[0133] As explained with reference to Figure 7, the collector-gate capacitance of an IGBT is highly dependent on the collector-emitter voltage. Therefore, the difference in collector-emitter voltage between normal operation and when the main circuit is short-circuited can be detected as a difference in gate charge characteristics. For example, as shown in Figure 7, whether the IGBT is functioning normally or abnormally can be detected by whether the amount of charge Qg supplied to the gate of the IGBT before the gate-emitter voltage Vge reaches the voltage value VR is greater than or equal to the threshold QR.

[0134] The above explanation described the case where IGBT61p is short-circuited, but the same applies if IGBT62p or IGBT63p is short-circuited. In other words, regardless of which IGBT on the upper arm is short-circuited, if individual differences in the IGBTs and parasitic impedance of the wiring can be ignored, the short-circuit current will flow equally through the three IGBTs on the lower arm. In either case, an arm short-circuit can be detected with one detection circuit 42, which is fewer than the number of IGBTs in parallel.

[0135] Next, we will explain what happens when a load short circuit occurs. There are two types of load short circuits: one when the load is short-circuited while the upper arm is ON, and another when the load is short-circuited while the lower arm is ON. The detection circuit 42 provided in the drive circuit 2 in Figure 8 is connected to the lower arm, so it can detect a load short circuit when the lower arm is ON.

[0136] When the lower arm is turned ON, the collector-emitter voltage of the lower arm IGBT initially drops to the ON voltage, similar to normal turn-on operation. Subsequently, when a load short circuit occurs, the load inductance becomes smaller compared to normal operation, and a larger collector current flows. As a result, the collector current increases rapidly, and the collector-emitter voltage rises again. With the renewed rise in collector-emitter voltage, a displacement current flows from the collector terminal to the gate terminal, increasing the gate-emitter voltage and decreasing the gate charge. Therefore, a load short circuit can be detected by detecting that the gate-emitter voltage is higher than normal and the gate charge is decreasing.

[0137] Specifically, when a load short circuit occurs while the lower arm is ON, a short-circuit current flows from the U-phase load terminal U to the negative terminal N. The short-circuit current is divided at the connection node U2 connected to the U-phase load terminal U and flows through all IGBTs 61n, 62n, and 63n of the lower arm. Assuming individual differences in the elements and parasitic impedance of the wiring can be ignored, the short-circuit current flows equally through the three IGBTs 61n, 62n, and 63n. The collector-emitter voltages of the IGBTs 61n, 62n, and 63n of the lower arm decrease once and then rise again with the same magnitude. Therefore, it is not necessary to have the same number of detection circuits 42 as the number of parallel-connected IGBTs to detect a load short circuit; a load short circuit can be detected with one detection circuit 42, which is fewer than the number of parallel IGBTs.

[0138] As described above, according to the drive circuit 2 shown in Figure 8, which is a modified example of Embodiment 2, a detection circuit 42 is provided on one of the individual substrates 30a, 32, or 30c corresponding to each of the multiple IGBTs 61n, 62n, and 63n connected in parallel on the lower arm. This detection circuit 42 can detect abnormalities in the multiple IGBTs 61n, 62n, and 63n connected in parallel.

[0139] Embodiment 3. In the drive circuit 3 of Embodiment 3, the method by which the detection circuit 43 detects an abnormal state of the IGBT 62p differs from that of the detection circuit 41 of Embodiment 1 and the detection circuit 42 of Embodiment 2. This will be explained below with reference to Figure 9.

[0140] [Overall configuration of the main circuit and drive circuit] Figure 9 shows an example of the configuration of a drive circuit according to Embodiment 3. In Figure 9, the main circuit 101 for one phase of the power converter and the drive circuit 3 that drives the IGBTs 61p, 62p, and 63p of the upper arm of the main circuit 101 are shown.

[0141] The main circuit 101 in Figure 9 differs from the main circuit 101 in Figures 1 and 6 in that IGBTs 61p, 62p, 63p, 61n, 62n, and 63n each have sense emitter terminals 61p_se, 62p_se, 63p_se, 61n_se, 62n_se, and 63n_se, respectively. In each IGBT, the sense emitter terminal is connected to the emitter terminal by wiring, and this wiring has parasitic inductance (61p_l, 62p_l, 63p_l, 61n_l, 62n_l, 63n_l). For example, a parasitic inductance 61p_l exists between the sense emitter terminal 61p_se and the emitter terminal 61p_e of IGBT 61p. The same applies to the other IGBTs. The other components of the main circuit 101 in Figure 9 are the same as those in Figures 1 and 6, so the same or corresponding parts are denoted by the same reference numerals and their descriptions are not repeated.

[0142] In this disclosure, the collector terminal is also referred to as the first main terminal, the emitter terminal as the second main terminal, and the sense emitter terminal as the sense terminal. The sense terminal is provided to divert a portion of the main current flowing from the first main terminal to the second main terminal.

[0143] The drive circuit 2 comprises a common board 10 and individual boards 30a, 33, and 30c. The common board 10 generates a common drive signal DRS for controlling the on and off states of the parallel-connected IGBTs 61p, 62p, and 63p. The individual boards 30a, 33, and 30c correspond individually to IGBTs 61p, 62p, and 63p, respectively, and supply the generated drive signal DRS to the corresponding IGBT. The configuration and operation of the common board 10 and the individual boards 30a and 30c are the same as in Embodiment 1 described in Figure 1 and Embodiment 2 described in Figure 6, so the same or corresponding parts are denoted by the same reference numerals and the description will not be repeated. Also, the connection relationship between the common board 10 and the individual boards 30a and 30c and the main circuit 101 is the same as in Embodiments 1 and 2, so the description will not be repeated.

[0144] The individual circuit board 33 includes a detection signal output terminal F1, a soft cutoff circuit 21b, and a detection circuit 43. The connections and functions of these components will be explained together when describing the operation of the drive circuit 2.

[0145] [Operation of the drive circuit] Next, the operation of the drive circuit 3 in Figure 9 will be described. Below, the operation of the individual circuit board 33, which differs from the cases of Embodiments 1 and 2, will be mainly described. The operation of the common circuit board 10 and the individual circuit boards 30a and 30c is the same as in Embodiments 1 and 2, except that the detection circuit 43 is used instead of the detection circuit 41 or 42, so a detailed explanation will not be repeated.

[0146] The detection circuit 43 detects an abnormal state of the IGBT62p based on a physical quantity obtained from the corresponding IGBT62p. When the detection circuit 43 detects an abnormal state of the IGBT62p, it outputs a detection signal DTS to the soft cutoff circuit 21b provided on the individual board 33, and also outputs the detection signal DTS to the outside of the individual board 33 via the detection signal output terminal F1. The detection signal DTS output via the detection signal output terminal F1 is input to the logic circuit 14 via the detection signal input terminal D1 of the common board 10. Furthermore, the detection signal DTS is input to the soft cutoff circuit 21a via the detection signal input terminal D2a of the individual board 30a, and to the soft cutoff circuit 21c via the detection signal input terminal D2c of the individual board 30c.

[0147] The connection and operation of the soft cutoff circuit 21b are the same as in Embodiments 1 and 2. That is, it is connected to the wiring of the drive signal DRS that connects the drive signal output terminal A1 of the common board 10 and the gate terminal 62p_g of the IGBT 62p (more specifically, to node E2b of the individual board 31). When the detection signal DTS is input, the soft cutoff circuit 21b lowers the potential of node E2b on the wiring and clamps the gate-emitter voltage to a predetermined voltage. This temporarily reduces the short-circuit current and makes it possible to reduce the rate of current change when the turn-off operation by the turn-off circuit 13 occurs.

[0148] The operation of the detection circuit 43 provided on the individual circuit board 33 will be explained in more detail below. As shown in Figure 9, the detection circuit 43 is connected to the sense emitter terminal 62p_se of the IGBT62p. Furthermore, although not shown in Figure 9, the detection circuit 43 is also connected to the emitter terminal 62p_e of the IGBT62p. Based on the voltage between the sense emitter terminal 62p_se and the emitter terminal 62p_e of the IGBT62p detected by these, abnormalities in the main circuit 101 are detected. As mentioned above, the sense emitter terminal 62p_se and the emitter terminal 62p_e are connected by a wire, but there is a parasitic inductance 62p_l in this wire. When a short circuit occurs, the rapid time change (di / dt) of the main circuit current and this parasitic inductance 62p_l cause a larger induced voltage than under normal conditions to be generated between the sense emitter terminal 62p_se and the emitter terminal 62p_e. Therefore, by setting appropriate thresholds, it is possible to detect anomalies based on the detection of this large induced voltage.

[0149] Based on the above, we will now refer to Figure 9 and describe the method for detecting abnormalities when an arm short circuit or load short circuit occurs in the main circuit 101. First, we will explain the case when an arm short circuit occurs.

[0150] When one of the IGBTs constituting the lower arm is in a conductive state due to a short-circuit failure or an incorrect ON signal, an ON command is input to the IGBT connected in parallel to the upper arm, causing an arm short circuit. In the drive circuit 3 of Embodiment 3 shown in Figure 9, when an arm short circuit occurs, a detection circuit 43 provided on the individual circuit board 33 corresponding to the IGBT 62p of the upper arm detects the arm short circuit.

[0151] Specifically, let's assume that when IGBT61n on the lower arm is conducting, an ON command is input to all IGBTs on the upper arm. In this case, there are three possible paths for the short-circuit current to flow: one through IGBT61p and IGBT61n, one through IGBT62p and IGBT61n, and one through IGBT63p and IGBT61n.

[0152] In other words, the short-circuit current flowing from the positive terminal P to the negative terminal N is divided at the positive node P2 of the upper arm and flows through all IGBTs 61p, 62p, and 63p of the upper arm. Assuming that individual differences in IGBTs and parasitic impedance of the wiring can be ignored, the short-circuit current flows equally through the three IGBTs 61p, 62p, and 63p. The same magnitude of short-circuit current flows through the IGBTs 61p, 62p, and 63p of the upper arm during ON drive, and the sense emitter-emitter voltage rises similarly. Therefore, it is not necessary to have the same number of detection circuits 43 as the number of parallel-connected IGBTs to detect an arm short circuit; an arm short circuit can be detected with just one detection circuit 43, which is fewer than the number of parallel IGBTs. Furthermore, an arm short circuit can be detected in the same way regardless of whether the individual board on which the detection circuit 43 is provided is one of individual boards 30a, 33, or 30c.

[0153] The above explanation describes the case where IGBT61n is short-circuited, but the same applies if IGBT62n or IGBT63n is short-circuited. In other words, regardless of which IGBT on the lower arm is short-circuited, if individual differences in the IGBTs and parasitic impedance of the wiring can be ignored, the short-circuit current will flow equally through the three IGBTs on the upper arm. In either case, an arm short-circuit can be detected with one detection circuit 43, which is fewer than the number of IGBTs in parallel.

[0154] Next, we will explain what happens when a load short circuit occurs. There are two types of load short circuits: one when the load is short-circuited while the upper arm is ON, and another when the load is short-circuited while the lower arm is ON. The detection circuit 43 provided in the drive circuit 3 in Figure 9 is connected to the upper arm, so it can detect a load short circuit when the upper arm is ON.

[0155] Specifically, when a load short circuit occurs while the upper arm is ON, a short-circuit current flows from the positive terminal P to the U-phase load terminal U. The short-circuit current is divided at the positive node P2 of the upper arm and flows through all IGBTs 61p, 62p, and 63p of the upper arm. Assuming that individual differences in IGBTs and parasitic impedance of the wiring can be ignored, the short-circuit current flows equally through the three IGBTs 61p, 62p, and 63p. The same magnitude of short-circuit current flows through the IGBTs 61p, 62p, and 63p of the upper arm while they are ON, and the sense emitter-emitter voltage rises similarly. Therefore, it is not necessary to have the same number of detection circuits 43 as the number of parallel-connected IGBTs to detect a load short circuit; a load short circuit can be detected with just one detection circuit 43, which is fewer than the number of parallel IGBTs.

[0156] [Effects of Embodiment 3] As described above, according to the drive circuit 3 of Embodiment 3, a detection circuit 43 is provided on one of the individual substrates (individual substrates 30a, 33, 30c) corresponding to each of the multiple power semiconductor switching elements (IGBTs 61p, 62p, 63p) connected in parallel. This detection circuit 43 can detect abnormalities in the multiple power semiconductor switching elements connected in parallel.

[0157] Specifically, the detection circuit 43 detects an abnormality in the main circuit 101 by detecting a voltage generated in the parasitic impedance of the wiring connecting the sense emitter terminal 62p_se and the emitter terminal 62p_e of the corresponding IGBT 62p.

[0158] [Modified version of Embodiment 3] The drive circuit 3 in Figure 9 may be configured to drive the lower arm of the main circuit 101. Alternatively, a drive circuit for driving the upper arm of the main circuit 101 and a drive circuit for driving the lower arm of the main circuit 101 may be provided separately. The case in which the drive circuit 3 drives the lower arm of the main circuit 101 will be described below with reference to Figure 10.

[0159] Figure 10 shows an example of the configuration of a drive circuit according to a modification of Embodiment 3. The drive circuit 3 in Figure 10 differs from the drive circuit 3 in Figure 9 in that it drives IGBTs 61n, 62n, and 63n which constitute the lower arm of the main circuit 101, instead of IGBTs 61p, 62p, and 63p which constitute the upper arm of the main circuit 101. The drive circuit 3 in Figure 10 protects multiple power semiconductor elements from abnormal conditions by having a function to detect abnormal conditions of the parallel-connected IGBTs 61n, 62n, and 63n.

[0160] More specifically, the configuration of the drive circuit 3 in Figure 10 and the configuration of the main circuit 101 in Figure 10 are the same as in Figure 9, but the connection between them differs from that in Figure 9. Below, we will mainly explain the differences from that in Figure 9, and parts that are the same as or equivalent to those in Figure 9 will be given the same reference numerals and will not be repeated in the explanation.

[0161] As shown in Figure 10, the common board 10 constituting the drive circuit 3 generates a common drive signal DRS for controlling the on and off states of the IGBTs 61n, 62n, and 63n that constitute the parallel-connected lower arm. The individual boards 30a, 33, and 30c constituting the drive circuit 3 each correspond individually to IGBTs 61n, 62n, and 63n, respectively, and supply the generated drive signal DRS to the corresponding IGBT.

[0162] Specifically, the gate terminal 61n_g of IGBT61n, which constitutes the lower arm, is connected to the drive signal output terminal A1 of the common board 10 via the corresponding individual board 30a. Similarly, the gate terminal 62n_g of IGBT62n, which constitutes the lower arm, is connected to the drive signal output terminal A1 of the common board 10 via the corresponding individual board 33. Similarly, the gate terminal 63n_g of IGBT63n, which constitutes the lower arm, is connected to the drive signal output terminal A1 of the common board 10 via the corresponding individual board 30c.

[0163] The soft cutoff circuit 21a on individual board 30a is connected to the drive signal wiring (more specifically, node E2a on individual board 30a) that connects the drive signal output terminal A1 on the common board 10 to the gate terminal 61n_g of IGBT61n. The soft cutoff circuit 21b on individual board 33 is connected to the drive signal DRS wiring (more specifically, node E2b on individual board 33) that connects the drive signal output terminal A1 on the common board 10 to the gate terminal 62n_g of IGBT62n. The soft cutoff circuit 21c on individual board 30c is connected to the drive signal wiring (more specifically, node E2c on individual board 30c) that connects the drive signal output terminal A1 on the common board 10 to the gate terminal 63n_g of IGBT63n.

[0164] Similar to the case in Figure 9, when the abnormality detection signal DTS is input from the detection circuit 43, the soft cutoff circuits 21a to 21c lower the potential of nodes E2a to E2c, respectively, and clamp the gate-emitter voltage to a predetermined voltage. This temporarily reduces the short-circuit current, making it possible to reduce the rate of current change when the turn-off circuit 13 performs the turn-off operation. As a result, IGBTs 61n, 62n, and 63n are turned off at a slower speed than during normal turn-off operation.

[0165] The detection circuit 43 on the individual board 33 is connected to the sense emitter terminal 62n_se and emitter terminal 62n_e of the corresponding IGBT 62n and detects the voltage between these terminals. Based on the detected sense emitter-emitter voltage of the IGBT 62n, the detection circuit 43 determines an abnormality in the main circuit 101.

[0166] The operation of the detection circuit 43 in the drive circuit 3 of Figure 10 will be described below. The detection circuit 43 determines an abnormality in the main circuit 101 based on the sense emitter-emitter voltage of the IGBT62n.

[0167] Three IGBTs 61n, 62n, and 63n connected in parallel, with a common collector-emitter connection, will have equal voltages applied to each of the parallel-connected IGBTs 61n, 62n, and 63n, assuming individual IGBT variations and parasitic impedances in the wiring are negligible. Similarly, the currents flowing through each of the IGBTs 61n, 62n, and 63n will also be equal.

[0168] The detection circuit 43 provided on the individual circuit board 33 detects abnormalities based on the sense emitter-emitter voltage of the corresponding IGBT62n. Since the sense emitter terminal 62n_se and the emitter terminal 62n_e of the IGBT62n are connected via wiring, a parasitic inductance 62n_l exists between the sense emitter and emitter of the IGBT62n. When a short circuit occurs, a larger induced voltage than under normal conditions is generated due to the rapid time change (di / dt) of the main circuit current and the parasitic inductance 62n_l between the sense emitter and emitter. Therefore, abnormalities can be detected by appropriately setting a threshold.

[0169] Next, we will specifically explain the operation of the detection circuit 43 in the drive circuit 3 of Figure 10 in the case of arm short circuit and load short circuit.

[0170] When one of the IGBTs constituting the upper arm is in a conductive state due to a short-circuit failure or a false ON signal, an ON command is input to the parallel-connected IGBT of the lower arm, causing an arm short circuit. In the drive circuit 3 of Figure 10, when an arm short circuit occurs, a detection circuit 43 provided on the individual circuit board 33 corresponding to the IGBT 62n of the lower arm detects the arm short circuit.

[0171] Specifically, suppose that when IGBT61p on the upper arm is conducting, an ON command is input to all IGBTs on the lower arm. In this case, there are three possible paths for the short-circuit current to flow: one through IGBT61p and IGBT61n, one through IGBT61p and IGBT62n, and one through IGBT61p and IGBT63n.

[0172] In other words, the short-circuit current flowing from the positive terminal P to the negative terminal N flows through the conducting upper arm IGBT 61p, is divided at the connection node U1, and flows through all the lower arm IGBTs 61n, 62n, and 63n. If individual differences in the IGBTs and parasitic impedance of the wiring are negligible, the short-circuit current flows equally through the three IGBTs 61n, 62n, and 63n. The same magnitude of short-circuit current flows through the lower arm IGBTs 61n, 62n, and 63n when they are turned on, and the sense emitter-emitter voltages of these IGBTs rise similarly. Therefore, it is not necessary to have the same number of detection circuits 43 as the number of parallel-connected IGBTs to detect an arm short circuit; an arm short circuit can be detected with just one detection circuit 43, which is fewer than the number of parallel IGBTs.

[0173] The above explanation described the case where IGBT61p is short-circuited, but the same applies if IGBT62p or IGBT63p is short-circuited. In other words, regardless of which IGBT on the upper arm is short-circuited, if individual differences in IGBTs and parasitic impedance of the wiring can be ignored, the short-circuit current will flow equally through the three IGBTs on the lower arm. In either case, an arm short-circuit can be detected with one detection circuit 43, which is fewer than the number of IGBTs in parallel.

[0174] Next, let's discuss load short circuits. There are two types of load short circuits: one where the load is short-circuited when the upper arm is ON, and another where the load is short-circuited when the lower arm is ON. Since the drive circuit 3 in Figure 10 is connected to the lower arm, it can detect load short circuits when the lower arm is ON.

[0175] Specifically, when a load short circuit occurs while the lower arm is ON, a short-circuit current flows from the U-phase load terminal U to the negative terminal N. The short-circuit current is divided at the connection node U2 connected to the U-phase load terminal U and flows through all the IGBTs 61n, 62n, and 63n of the lower arm. Assuming that individual differences in IGBTs and parasitic impedance of the wiring can be ignored, the short-circuit current flows equally through the three IGBTs 61n, 62n, and 63n. The same magnitude of short-circuit current flows through the IGBTs 61n, 62n, and 63n of the lower arm while they are ON, and the sense emitter-emitter voltage rises similarly. Therefore, it is not necessary to have the same number of detection circuits 43 as the number of parallel-connected IGBTs to detect an arm short circuit; an arm short circuit can be detected with just one detection circuit 43, which is fewer than the number of parallel IGBTs.

[0176] As described above, according to the drive circuit 3 of Figure 10, which is a modified example of Embodiment 3, a detection circuit 43 is provided on one of the individual substrates 30a, 31, or 30c corresponding to each of the multiple IGBTs 61n, 62n, and 63n connected in parallel on the lower arm. This detection circuit 43 can detect abnormalities in the multiple IGBTs 61n, 62n, and 63n connected in parallel.

[0177] Embodiment 4. Embodiment 4 describes a case where individual differences in the characteristics of multiple power semiconductor elements connected in parallel and the parasitic impedance of the wiring cannot be ignored.

[0178] In the parallel-connected IGBTs described in Embodiments 1 to 3, the collector terminals of each IGBT were connected to a common high-potential node, and the emitter terminals of each IGBT were connected to a common low-potential node. In this case, assuming that individual differences in the IGBTs and the impedance of the wiring are negligible, the voltage applied to each of the parallel-connected IGBTs will be equal, and the current flowing through each of the IGBTs will also be equal.

[0179] Furthermore, the detection circuits 41 to 43 exemplified in Embodiments 1 to 3 each perform abnormality determination based on the voltage or current characteristics of a corresponding IGBT. In this case, if the voltage and current flowing through each IGBT are the same among the IGBTs, the same determination can be made based on the voltage or current characteristics of any of the parallel-connected IGBTs.

[0180] However, in reality, in systems where multiple power semiconductor elements are connected in parallel, individual differences in IGBTs and parasitic impedance of the wiring often cannot be ignored. In this case, there will be variations in the voltage of each IGBT and the current flowing through each IGBT. Furthermore, the determination results may differ depending on which IGBT the detection circuits 41-43 are connected to.

[0181] The following sections will first explain why there are variations in the voltage and current of multiple power semiconductor elements connected in parallel. Next, they will explain how the path through which short-circuit current flows differs depending on the occurrence of arm short circuits and load short circuits. Furthermore, they will explain the differences in current and voltage of each power semiconductor element when two power semiconductor elements are placed next to each other and when they are placed separately.

[0182] [Causes of voltage and current variations in each IGBT] Figure 11A is a diagram illustrating the reason why there are variations in the current and voltage of each IGBT in a series of IGBTs connected in parallel.

[0183] The main circuit 102a shown in Figure 11A comprises three IGBTs 61p, 62p, and 63p connected in parallel. IGBT 61p is connected between the positive node P1 and the negative node N1, IGBT 62p is connected between the positive node P2 and the negative node N2, and IGBT 63p is connected between P3 and the negative node N3. The positive node P2 is connected to positive nodes P1 and P3 and also to the positive terminal P. The negative node N2 is connected to negative nodes N1 and N3 and also to the negative terminal N. Therefore, the collector terminals 61p_c, 62p_c, and 63p_c of the three IGBTs 61p, 62p, and 63p are connected to the positive terminal P via the common positive node P2. The emitter terminals 61p_e, 62p_e, and 63p_e of the three IGBTs 61p, 62p, and 63p are connected to the negative terminal N via the negative node N1 on the lower arm.

[0184] In this case, the wiring between positive node P1 and positive node P2 has a parasitic resistance of 80a and a parasitic inductance of 90a. The wiring between positive node P2 and positive node P3 has a parasitic resistance of 80b and a parasitic inductance of 90b. The wiring between negative node N1 and negative node N2 has a parasitic resistance of 80c and a parasitic inductance of 90c. The wiring between negative node N2 and negative node N3 has a parasitic resistance of 80d and a parasitic inductance of 90d.

[0185] When IGBTs 61p, 62p, and 63p are ON, the current flowing from the positive terminal P to the negative terminal N is divided at the positive node P2. There are three possible current paths after the division. The balance of the current distribution to each path is determined by the impedance of the current path. In other words, differences in the impedance of the current path cause variations in the voltage and current of the IGBT. This variation becomes particularly large when a steep and large current flows, such as during a short circuit.

[0186] Next, we will explain why there are differences in the on-resistance of each power semiconductor element in a series of power semiconductor elements connected in parallel.

[0187] The impedance of each current path is the sum of the parasitic impedance of the wiring and the on-resistance of the IGBT. For example, in Figure 11A, the impedance of the current path flowing from the positive terminal P through IGBT61p to the negative terminal N is the sum of the parasitic resistances 80a and 80c, the parasitic inductances 90a and 90c, and the on-resistance of IGBT61p.

[0188] On-resistance is the collector-emitter resistance when the IGBT is in the ON state, and it depends on the gate-emitter voltage. It is also affected by individual differences in the IGBTs themselves, but since IGBTs with generally small individual differences are connected in parallel, we will ignore the individual differences of the IGBTs themselves here.

[0189] Figure 11B is a diagram illustrating the reason why there is variation in the on-resistance of each IGBT in a series of IGBTs connected in parallel.

[0190] The main circuit 102b shown in Figure 11B differs from the main circuit 102a in Figure 11A in that it further includes emitter wiring 85e and 85f for connecting the emitter terminals 61p_e, 62p_e, and 63p of IGBTs 61p, 62p, and 63p. These emitter wirings 85e and 85f are provided to obtain a common emitter potential when driving the parallel-connected IGBTs 61p, 62p, and 63p.

[0191] As shown in Figure 11B, the emitter wire 85e connecting the emitter terminal 61p_e of IGBT61p and the emitter terminal 62p_e of IGBT62p has a parasitic resistance of 80e and a parasitic inductance of 90e. The emitter wire 85f connecting the emitter terminal 62p_e of IGBT62p and the emitter terminal 63p_e of IGBT63p also has a parasitic resistance of 80f and a parasitic inductance of 90f. The parasitic impedances (80e, 90e, 80f, 90f) of these emitter wires 85e and 85f are greater than the parasitic impedances (80c, 90c, 80d, 90d) of the main circuit wires 85c and 85d that carry collector current, so no collector current flows through the emitter wires 85e and 85f that connect the emitter terminals of the IGBTs.

[0192] When a steep current flows through the main circuit 102b, such as a short-circuit current, an induced voltage is generated by the parasitic inductance of the current path, and a voltage drop occurs due to the parasitic resistance of the current path. In other words, the voltage is maintained by the parasitic impedance of the current path.

[0193] The emitter wires 85e and 85f, which connect the emitter terminals, are connected in parallel with the negative main circuit wires 85c and 85d. Therefore, the same magnitude of voltage as the voltage held by the parasitic impedances (80e, 90e, 80f, 90f) of the negative main circuit wires 85c and 85d is held by the parasitic impedances (80e, 90e, 80f, 90f) of the emitter wires 85e and 85f.

[0194] Specifically, let's describe the current flowing from the collector terminal 61p_c of IGBT61p to the negative node N1. This current has two paths: one through the main circuit wiring 85c, which has parasitic resistance 80c and parasitic inductance 90c, and another through the emitter wiring 85e, which has parasitic resistance 80e and parasitic inductance 90e. These current paths are in parallel with each other. Since the voltages held in parallel current paths are the same, the sum of the voltages held by the parasitic impedances of the negative main circuit wiring 85c (parasitic resistance 80c and parasitic inductance 90c) is the same as the sum of the voltages held by the parasitic impedances of the emitter wiring 85e (parasitic resistance 80e and parasitic inductance 90e).

[0195] In the above case, the voltage held by the parasitic impedance of the negative main circuit wiring 85c becomes the potential difference between the emitter terminal 61p_e of IGBT61p and the emitter terminal 62p_e of IGBT62p. In other words, the emitter potential of IGBT61p is higher than the emitter potential of IGBT62p, so the gate-emitter voltages of the two IGBTs 61p and 62p are different.

[0196] More generally, in the main circuit 102b, current flows from the emitter terminals 61p_e, 62p_e, and 63p_e of IGBT61p, 62p, and 63p respectively toward the negative node N2. As a result, the emitter potentials of IGBT61p and IGBT63p become higher than the emitter potential of IGBT62p. In this case, comparing the gate-emitter voltages applied to the three IGBTs, the gate-emitter voltage applied to IGBT62p is the largest, so IGBT62p is in the state where it can most easily conduct current, i.e., its on-resistance is the lowest.

[0197] Thus, a voltage difference is created in the emitter wirings 85e and 85f connecting the emitter terminals of the parallel-connected IGBTs 61p, 62p, and 63p, due to the parasitic impedances held by the negative main circuit wirings 85c and 85d. If a steep current, such as a short-circuit current, flows through the main circuit 102b, this voltage difference becomes large, resulting in fluctuations in the gate-emitter voltage applied to the parallel-connected IGBTs 61p, 62p, and 63p, and consequently, fluctuations in the on-resistance.

[0198] In summary, the current balance when the current flowing into the main circuit 102b is divided among the parallel-connected IGBTs 61p, 62p, and 63p is affected by the differences in wiring impedance for each division path and the fluctuations in the on-resistance of the IGBTs due to differences in gate-emitter voltage. The voltage drop in an IGBT is the product of the current flowing through that IGBT and its on-resistance. Therefore, the IGBT with the largest current flowing through it and the IGBT with the largest voltage drop are not necessarily the same among the multiple parallel-connected IGBTs.

[0199] [Differences in how short-circuit current flows depending on the circumstances of the short-circuit fault] Based on the above, we will explain how the path that results in the largest short-circuit current due to differences in path impedance, and the power semiconductor element that has the smallest on-resistance due to differences in gate-emitter voltage, change depending on the occurrence of arm short circuits and load short circuits.

[0200] Figure 12 shows an example of the configuration of the main circuit for one phase of a power converter. Referring to Figure 12, the upper arm of the main circuit 103 is composed of three IGBTs 61p, 62p, and 63p connected in parallel, and the lower arm of the main circuit 103 is composed of three IGBTs 61n, 62n, and 63n connected in parallel.

[0201] IGBT61p and IGBT61n are connected in series between the positive node P1 and the negative node N1 via connecting node U1. IGBT62p and IGBT62n are connected in series between the positive node P2 and the negative node N2 via connecting node U2. IGBT63p and IGBT63n are connected in series between the positive node P3 and the negative node N3 via connecting node U3. Positive node P2 is connected to each of positive nodes P1 and P3, and further connected to the positive terminal P. Negative node N2 is connected to each of negative nodes N1 and N3, and further connected to the negative terminal N. Connecting node U2 is connected to each of connecting nodes U1 and U3, and further connected to the U-phase load terminal U.

[0202] Therefore, the collector terminals of IGBT61p,62p,63p that make up the upper arm are connected to the positive terminal P via the positive node P2. The emitter terminals of IGBT61n,62n,63n that make up the lower arm are connected to the negative terminal N via the negative node N2. The emitter terminals of IGBT61p,62p,63p that make up the upper arm and the collector terminals of IGBT61n,62n,63n that make up the lower arm are connected via connection nodes U1,U2,U3.

[0203] As shown in Figure 12, the wiring connecting positive node P1 and positive node P2 has a parasitic resistance 81a and a parasitic inductance 91a. The wiring connecting positive node P2 and positive node P3 has a parasitic resistance 81b and a parasitic inductance 91b. The wiring connecting connecting node U1 and connecting node U2 has a parasitic resistance 81c and a parasitic inductance 91c. The wiring connecting connecting node U2 and connecting node U3 has a parasitic resistance 81d and a parasitic inductance 91d. The wiring connecting negative node N1 and negative node N2 has a parasitic resistance 81e and a parasitic inductance 91e. The wiring connecting negative node N2 and negative node N3 has a parasitic resistance 81f and a parasitic inductance 91f. For the sake of simplicity, in the following explanation, we will assume that the parasitic resistors 81a to 81f all have the same resistance value, and that the parasitic inductances 91a to 91f all have the same inductance value.

[0204] The following explains the occurrence of arm short circuits and load short circuits according to their respective conditions. First, we will explain the case where an arm short circuit occurs when an ON command is input to an IGBT in the upper arm while IGBT61n, one of the IGBTs in the lower arm, is conducting due to a short circuit fault or a false ON signal. In this case, there are three paths through which the short circuit current flows: a path through IGBT61p and IGBT61n, a path through IGBT62p and IGBT61n, and a path through IGBT63p and IGBT61n. That is, the short circuit current flowing from the positive terminal P to the negative terminal N is divided at the positive node P2 of the upper arm, flows through all of the IGBTs in the upper arm (IGBT61p, 62p, 63p), and then flows to IGBT61n. At this time, the path through which the short circuit current is most likely to flow is the path through IGBT61p, which has the lowest wiring impedance. The element with the lowest ON resistance is IGBT61p, which has the highest gate-emitter voltage.

[0205] Next, we will explain the case where an arm short circuit occurs when an ON command is input to the IGBT on the upper arm while IGBT62n is conducting due to a short-circuit fault or a false ON signal. In this case, there are three paths through which the short-circuit current flows: a path through IGBT61p and IGBT62n, a path through IGBT62p and IGBT62n, and a path through IGBT63p and IGBT62n. That is, the short-circuit current flowing from the positive terminal P to the negative terminal N is divided at the positive node P2 of the upper arm, flows through all IGBTs 61p, 62p, and 63p of the upper arm, and then flows to IGBT62n. At this time, the path through which the short-circuit current flows most easily is the path through IGBT62p, which has the lowest wiring impedance. The element with the lowest ON resistance is IGBT62p, which has the highest gate-emitter voltage.

[0206] Next, we will explain the case where an arm short circuit occurs when an ON command is input to the IGBT on the upper arm while IGBT63n is conducting due to a short-circuit fault or an incorrect ON signal. In this case, there are three paths through which the short-circuit current flows: a path through IGBT61p and IGBT63n, a path through IGBT62p and IGBT63n, and a path through IGBT63p and IGBT63n. That is, the short-circuit current flowing from the positive terminal P to the negative terminal N is divided at the positive node P2 of the upper arm, flows through all IGBTs 61p, 62p, and 63p of the upper arm, and then flows to IGBT63n. At this time, the path through which the short-circuit current flows most easily is the path through IGBT63p, which has the lowest wiring impedance. The element with the lowest ON resistance is IGBT63p, which has the highest gate-emitter voltage.

[0207] Next, we will explain the case where a load short circuit occurs when IGBTs 61p, 62p, and 63p on the upper arm are ON. In this case, the short-circuit current flows from the positive terminal P to the U-phase load terminal U. That is, the short-circuit current is divided at the positive node P2 on the upper arm and flows through all the IGBTs on the upper arm. At this time, the path through which the short-circuit current is most likely to flow is through IGBT 62p, which has the lowest wiring impedance. The element with the lowest ON resistance is IGBT 62p, which has the highest gate-emitter voltage.

[0208] Next, we will explain the case where an arm short circuit occurs when an ON command is input to an IGBT in the lower arm while IGBT61p, one of the IGBTs in the upper arm, is conducting due to a short-circuit fault or a false ON signal. In this case, there are three paths through which the short-circuit current flows: through IGBT61p and IGBT61n, through IGBT61p and IGBT62n, and through IGBT61p and IGBT63n. That is, the short-circuit current flowing from the positive terminal P to the negative terminal N flows through IGBT61p, is divided at connection node U1, and flows through all of the IGBTs in the lower arm: IGBT61n, 62n, and 63n. At this time, the path through which the short-circuit current flows most easily is through IGBT62n, which has the lowest wiring impedance. The element with the lowest ON resistance is 62n, which has the highest gate-emitter voltage.

[0209] Next, we will explain the case where an arm short circuit occurs when an ON command is input to the lower arm IGBT while IGBT62p is conducting due to a short circuit fault or an incorrect ON signal. In this case, the path through which the short-circuit current flows is between IGBT62p and IGBT6 1There are three possible paths: one through n, one through IGBT62p and IGBT62n, and one through IGBT62p and IGBT63n. That is, the short-circuit current flowing from the positive terminal P to the negative terminal N flows through IGBT62p, is divided at connection node U2, and flows through all IGBT61n, 62n, and 63n on the lower arm. In this case, the path through which the short-circuit current flows most easily is the path through IGBT62n, which has the lowest wiring impedance. The element with the lowest on-resistance is IGBT62n, which has the highest gate-emitter voltage.

[0210] Next, we will explain the case where an arm short circuit occurs when an ON command is input to the lower arm IGBT while IGBT63p is conducting due to a short circuit fault or an incorrect ON signal. In this case, the path through which the short-circuit current flows is between IGBT63p and IGBT6 1 There are three possible paths: one through n, one through IGBT63p and IGBT62n, and one through IGBT63p and IGBT63n. That is, the short-circuit current flowing from the positive terminal P to the negative terminal N flows through IGBT63p, is divided at connection node U3, and flows through all IGBTs61n, 62n, and 63n on the lower arm. In this case, the path through which the short-circuit current flows most easily is the path through IGBT63n, which has the lowest wiring impedance. The element with the lowest on-resistance will have the highest gate-emitter voltage. IGBT It is 62n.

[0211] Next, we will explain the case where a load short circuit occurs when IGBTs 61n, 62n, and 63n on the lower arm are turned on. In this case, the short-circuit current flows from the U-phase load terminal U to the negative terminal N. That is, the short-circuit current is divided at the connection node U2 on the positive side of the lower arm and flows through all the IGBTs on the lower arm. At this time, the path through which the short-circuit current flows most easily is through IGBT 62n, which has the lowest wiring impedance, and the element with the lowest on-resistance is IGBT 62n, which has the highest gate-emitter voltage.

[0212] As described above, the current and voltage of which of the multiple power semiconductor elements connected in parallel will be greater will vary depending on the occurrence of arm short circuits and load short circuits. Therefore, it is not possible to predetermine the optimal power semiconductor element for anomaly detection.

[0213] [Differences in current and voltage due to the arrangement of power semiconductor elements] As described above, the variation in current and voltage among multiple power semiconductor elements connected in parallel differs depending on the circumstances of the short-circuit fault. However, the difference in current and voltage between two adjacent power semiconductor elements is smaller than when they are placed far apart. This point will be explained below with reference to the diagram.

[0214] Figure 13 shows another example of the main circuit configuration for one phase of a power converter. Referring to Figure 13, the upper arm of the main circuit 104 consists of five IGBTs 61p to 65p connected in parallel, and the lower arm of the main circuit 104 consists of five IGBTs 61n to 65n connected in parallel. The IGBTs 61p to 65p are arranged in a single row on the main circuit board, and the IGBTs 61n to 65n are arranged in a single row on the same board parallel to the arrangement direction of the IGBTs 61p to 65p.

[0215] IGBT61p and IGBT61n are connected in series between the positive node P1 and the negative node N1 via a connecting node U1. IGBT62p and IGBT62n are connected in series between the positive node P2 and the negative node N2 via a connecting node U2. IGBT63p and IGBT63n are connected in series between the positive node P3 and the negative node N3 via a connecting node U3. IGBT64p and IGBT64n are connected in series between the positive node P4 and the negative node N4 via a connecting node U4. IGBT65p and IGBT65n are connected in series between the positive node P5 and the negative node N5 via a connecting node U5.

[0216] Positive node P3 is connected to positive nodes P2 and P4, respectively, and is further connected to positive terminal P. Positive node P1 is connected to positive node P2, and positive node P5 is connected to positive node P4. Negative node N3 is connected to negative nodes N2 and N4, respectively, and is further connected to negative terminal N. Negative node N1 is connected to negative node N2, and negative node N5 is connected to negative node N4. Connecting node U3 is connected to connecting nodes U2 and U4, respectively, and is further connected to U-phase load terminal U. Connecting node U1 is connected to connecting node U2, and connecting node U5 is connected to connecting node U4.

[0217] Therefore, each collector terminal of IGBT61p~65p constituting the upper arm is connected to the positive terminal P via the positive node P3. Each emitter terminal of IGBT61n~65n constituting the lower arm is connected to the negative terminal N via the negative node N3. The emitter terminals of IGBT61p~65p constituting the upper arm and the collector terminals of IGBT61n~65n constituting the lower arm are connected via connection nodes U1~U5, respectively.

[0218] As shown in Figure 13, the wiring connecting positive nodes P1 and P2 has a parasitic resistance 82a and a parasitic inductance 92a. The wiring connecting positive nodes P2 and P3 has a parasitic resistance 82b and a parasitic inductance 92b. The wiring connecting positive nodes P3 and P4 has a parasitic resistance 82c and a parasitic inductance 92c. The wiring connecting positive nodes P4 and P5 has a parasitic resistance 82d and a parasitic inductance 92d.

[0219] Furthermore, the wiring connecting negative nodes N1 and N2 has a parasitic resistance of 82i and a parasitic inductance of 92i. The wiring connecting negative nodes N2 and N3 has a parasitic resistance of 82j and a parasitic inductance of 92j. The wiring connecting negative nodes N3 and N4 has a parasitic resistance of 82k and a parasitic inductance of 92k. The wiring connecting negative nodes N4 and N5 has a parasitic resistance of 82l and a parasitic inductance of 92l.

[0220] Furthermore, the wiring connecting connection nodes U1 and U2 has a parasitic resistance of 82e and a parasitic inductance of 92e. The wiring connecting connection nodes U2 and U3 has a parasitic resistance of 82f and a parasitic inductance of 92f. The wiring connecting connection nodes U3 and U4 has a parasitic resistance of 82g and a parasitic inductance of 92g. The wiring connecting connection nodes U4 and U5 has a parasitic resistance of 82h and a parasitic inductance of 92h.

[0221] For simplicity, the following explanation assumes that the parasitic resistances 81a to 81l all have the same value R, and the parasitic inductances 91a to 91l all have the same value L. Furthermore, only the parasitic impedance of the wiring used to connect the IGBTs in parallel is considered.

[0222] The following explanation will use the example of a case where an arm short circuit occurs when an ON command is input to IGBT61p~65p, which constitutes the upper arm, while IGBT61n, one of the IGBT61n~65n constituting the lower arm, is short-circuited or is in a conductive state due to a false ON signal input. In this case, the short-circuit current flowing from the positive terminal P to the negative terminal N is divided at the positive node P3 of the upper arm, passes through all IGBT61p~65p constituting the upper arm, and flows to IGBT61n.

[0223] In the above case, compare the path impedances of IGBT61p and IGBT65p, which are located at different positions from each other. Furthermore, compare the path impedances of IGBT61p and IGBT62p, which are located adjacent to each other.

[0224] The wiring impedance of the path from the positive terminal P through IGBT61p to the collector terminal 61n_c of IGBT61n is 2R + 2L, which is the sum of the parasitic resistances 82a and 82b and the parasitic inductances 92a and 92b.

[0225] The wiring impedance of the path from the positive terminal P through IGBT62p to the collector terminal 61n_c of IGBT61n is the sum of the parasitic resistances 82b,82e and the parasitic inductances 92b,92e, which is 2R + 2L.

[0226] The wiring impedance of the path from the positive terminal P through IGBT65p to the collector terminal 61n_c of IGBT61n is 6R + 6L, which is the sum of the parasitic resistances 82c, 82d, 82h, 82g, 82f, 82e and the parasitic inductances 92c, 92d, 92h, 92g, 92f, 92e.

[0227] From the above, it can be seen that when IGBT61n is short-circuited or conducts due to an incorrect ON signal input, the difference in path impedance between IGBT61p and IGBT65p, which are located far apart from each other, is larger than the difference in path impedance between adjacent IGBT61p and IGBT62p.

[0228] [Example of appropriate placement of detection circuit] From the above considerations, when multiple power semiconductor elements are connected in parallel, if the parasitic impedance of the wiring cannot be ignored, differences will occur in the physical quantities obtained depending on the magnitude of the short-circuit current for each path. Therefore, it is necessary to provide detection circuits for multiple power semiconductor elements. Furthermore, it is desirable that the power semiconductor elements to which the detection circuits are connected be arranged as widely and symmetrically as possible. The following describes an example of an appropriate detection circuit connection with specific examples.

[0229] (Example 1: When an odd number of detection circuits are provided for an odd number of power semiconductor elements) Figure 14A shows an example of a drive circuit that drives the upper arm of the main circuit shown in Figure 13. As explained with reference to Figure 13, the upper arm of the main circuit 104 is equipped with five IGBTs 61p to 65p connected in parallel, and these IGBTs are arranged in a row on the main circuit board. Note that the lower arm of the main circuit 104 is not shown in Figure 14A.

[0230] As shown in Figure 14A, the drive circuit 4 comprises a common board 10 and individual boards 31a, 30b, 31c, 30d, and 31e corresponding to IGBTs 61p to 65p, respectively. The individual boards 31a, 31c, and 31e each include detection circuits 41a, 41c, and 41e, respectively. The detection circuits 41a, 41c, and 41e detect abnormalities in the main circuit 104 based on the collector-emitter voltages of the corresponding IGBTs 61p, 63p, and 65p, respectively.

[0231] As described above, when an odd number of power semiconductor elements connected in parallel are arranged in a line, the following is a desirable example of connection when connecting a detection circuit to each of three or more odd numbers of power semiconductor elements. That is, a detection circuit is provided for the central power semiconductor element in the order of arrangement, and detection circuits are also provided for a number of even-numbered power semiconductor elements that are symmetrical with respect to the central power semiconductor element.

[0232] (Example 2: When an even number of detection circuits are provided for an odd number of power semiconductor elements) Figure 14B shows another example of a drive circuit that drives the upper arm of the main circuit shown in Figure 13. As explained with reference to Figure 13, the upper arm of the main circuit 104 is equipped with five IGBTs 61p to 65p connected in parallel, and these IGBTs are arranged in a row on the main circuit board. Note that the lower arm of the main circuit 104 is not shown in Figure 14B.

[0233] As shown in Figure 14B, the drive circuit 5 comprises a common board 10 and individual boards 31a, 30b-30d, and 31e corresponding to IGBTs 61p to 65p, respectively. Individual boards 31a and 31e are each equipped with detection circuits 41a and 41e. Detection circuits 41a and 41e detect abnormalities in the main circuit 104 based on the collector-emitter voltages of the corresponding IGBTs 61p and 65p, respectively.

[0234] As described above, when an odd number of power semiconductor elements connected in parallel are arranged in a line, the following is a desirable example of connection when connecting a detection circuit to each of the even number of power semiconductor elements. That is, a detection circuit is provided for a portion of the even number of power semiconductor elements that are symmetrical with respect to the central power semiconductor element in the arrangement.

[0235] (Example 3: When an odd number of detection circuits are provided for an even number of power semiconductor elements) Figure 14C shows an example of a drive circuit that drives the upper arm of the main circuit in another configuration example. The main circuit 105 in Figure 14C shows the main circuit for one phase of the power converter. The upper arm of the main circuit 105 is composed of six IGBTs 61p to 66p connected in parallel, and the lower arm of the main circuit 105 is composed of six IGBTs 61n to 66n connected in parallel. The IGBTs 61p to 66p are arranged in a row on the main circuit board, and the IGBTs 61n to 66n are arranged in a row on the same board parallel to the arrangement direction of the IGBTs 61p to 66p.

[0236] IGBT61p and IGBT61n are connected in series between the positive node P1 and the negative node N1 via connecting node U1. IGBT62p and IGBT62n are connected in series between the positive node P2 and the negative node N2 via connecting node U2. IGBT63p and IGBT63n are connected in series between the positive node P3 and the negative node N3 via connecting node U3. IGBT64p and IGBT64n are connected in series between the positive node P4 and the negative node N4 via connecting node U4. IGBT65p and IGBT65n are connected in series between the positive node P5 and the negative node N5 via connecting node U5. IGBT66p and IGBT66n are connected in series between the positive node P6 and the negative node N6 via connecting node U6.

[0237] Positive node P2 is connected to positive nodes P1 and P3 respectively, and positive node P3 is connected to positive terminal P via positive node P7. Positive node P5 is connected to positive nodes P4 and P6 respectively, and positive node P4 is connected to positive terminal P via positive node P7. Negative node N2 is connected to negative nodes N1 and N3 respectively, and negative node N3 is connected to negative terminal N via negative node N7. Negative node N5 is connected to negative nodes N4 and N6 respectively, and negative node N4 is connected to negative terminal N via negative node N7. Connecting node U2 is connected to connecting nodes U1 and U3 respectively, and connecting node U3 is connected to connecting node U4. Connecting node U5 is connected to connecting nodes U4 and U6 respectively.

[0238] Therefore, each collector terminal of IGBT61p~66p constituting the upper arm is connected to the positive terminal P via the positive node P7. Each emitter terminal of IGBT61n~66n constituting the lower arm is connected to the negative terminal N via the negative node N7. The emitter terminals of IGBT61p~66p constituting the upper arm and the collector terminals of IGBT61n~66n constituting the lower arm are connected via connection nodes U1~U6, respectively.

[0239] As shown in Figure 14C, the drive circuit 6 comprises a common board 10 and individual boards 30a, 31b, 31c, 30d, 31e, and 30f corresponding to IGBTs 61p to 66p, respectively. Individual boards 31b, 31c, and 31e each include detection circuits 41b, 41c, and 41e, respectively. The detection circuits 41b, 41c, and 41e detect abnormalities in the main circuit 105 based on the collector-emitter voltages of the corresponding IGBTs 62p, 63p, and 65p, respectively.

[0240] As described above, when an even number of power semiconductor elements connected in parallel are arranged in a line, the following is a desirable example of connection when connecting a detection circuit to each of an odd number of power semiconductor elements. That is, when an odd number of detection circuits are provided for an even number of power semiconductor elements, it is simply a matter of dividing the power semiconductor elements into an odd number of blocks in the order of arrangement, and providing a detection circuit for one power semiconductor element in each block. In this case, when N is a positive integer, it is appropriate to divide them into two types: blocks composed of N power semiconductor elements and blocks composed of (N+1) power semiconductor elements. Here, when the number of power semiconductor elements constituting a block is odd, as explained in Example 1, a detection circuit is provided for the central power semiconductor element in the order of arrangement. On the other hand, when the number of power semiconductor elements constituting a block is even, a detection circuit is provided for either one of the two central power semiconductor elements in the order of arrangement.

[0241] (Example 4: When an even number of detection circuits are provided for an even number of power semiconductor elements) Figure 14D shows another example of a drive circuit that drives the upper arm of the main circuit shown in Figure 14C. As explained with reference to Figure 14C, the upper arm of the main circuit 105 is equipped with six IGBTs 61p to 66p connected in parallel, and these IGBTs are arranged in a row on the main circuit board. Note that the lower arm of the main circuit 105 is not shown in Figure 14D.

[0242] As shown in Figure 14D, the drive circuit 7 comprises a common board 10 and individual boards 30a, 31b, 30c, 30d, 31e, and 30f corresponding to IGBTs 61p to 66p, respectively. Individual boards 31b and 31e are equipped with detection circuits 41b and 41e, respectively. Detection circuits 41b and 41e detect abnormalities in the main circuit 105 based on the collector-emitter voltages of the corresponding IGBTs 62p and 65p, respectively.

[0243] As described above, when an even number of power semiconductor elements connected in parallel are arranged in a line, the following is a desirable example of connection when connecting a detection circuit to each of the even number of power semiconductor elements. That is, when an even number of detection circuits are provided for an even number of power semiconductor elements, it is nothing more than dividing the power semiconductor elements into an even number of blocks in the order of arrangement, and providing a detection circuit for one power semiconductor element in each block. In this case, it is appropriate to either make all blocks from the same number of power semiconductor elements, or to divide them into two types: blocks composed of N power semiconductor elements and blocks composed of (N+1) power semiconductor elements, where N is a positive integer. Here, when the number of power semiconductor elements constituting a block is odd, as explained in Example 1, a detection circuit is provided for the central power semiconductor element in the order of arrangement. On the other hand, when the number of power semiconductor elements constituting a block is even, a detection circuit is provided for one of the two central power semiconductor elements in the order of arrangement.

[0244] (summary) In summary, multiple power semiconductor elements connected in parallel are arranged in one or more rows on one or more main circuit boards. A detection circuit is provided for each of the multiple power semiconductor elements in each row, either for one or for some of the power semiconductor elements. Specifically, let's consider the case where an arbitrary first row consisting of K power semiconductor elements contains L power semiconductor elements (L is an integer between 1 and K) associated with each detection circuit. In this case, if we let N be the quotient and M be the remainder when K is divided by L (M is an integer between 0 and L), then K = L × N + M = N × (LM) + (N + 1) × M holds true. Therefore, in order to divide this first row as evenly as possible into L blocks according to the arrangement of the power semiconductor elements, we can either divide it into L blocks, each consisting of N power semiconductor elements (when M=0), or into L blocks, each consisting of N or N+1 power semiconductor elements (when M>0). Furthermore, if the number of power semiconductor elements constituting a block is odd, a detection circuit is provided on the central power semiconductor element; if the number is even, a detection circuit is provided on one of the two central elements. This allows the power semiconductor elements to which the detection circuits are connected to be distributed as much as possible and arranged symmetrically. In addition, if multiple power semiconductor elements connected in parallel are arranged in multiple rows, the symmetry can be further increased by ensuring that each row is associated with the same number of L detection circuits.

[0245] This configuration reduces the difference between the wiring impedance of the current path via the power semiconductor element driven by the individual board 31 equipped with the detection circuit 41 and the wiring impedance of the current path via the power semiconductor element driven by the individual board 30 without the detection circuit 41, thereby enabling detection of abnormalities in the main circuit with higher accuracy.

[0246] Embodiment 5. The driving circuit of Embodiment 5 will be described in the case where it is used in combination with the detection circuits 41 to 43 described in Embodiments 1 to 3.

[0247] The detection circuits 41-43 differ in detection speed, detection accuracy, cost to construct the detection circuit, and circuit size depending on their type. Furthermore, the appropriate anomaly detection method differs depending on the connection method and driving conditions of multiple power semiconductor elements. For these reasons, when using multiple individual boards 31 equipped with anomaly detection means, it may be more effective to use multiple types of anomaly detection methods than to use a single anomaly detection method to detect anomalies in the main circuit. This will be explained in detail below with reference to the drawings.

[0248] [Example of a drive circuit] Figure 15 shows an example of the configuration of a drive circuit according to Embodiment 5. Figure 15 shows an example of the configuration of a drive circuit 8 that drives the IGBTs 61p to 65p of the upper arm of the main circuit 104 shown in Figure 13. Note that the lower arm of the main circuit 104 is not shown in Figure 15.

[0249] As shown in Figure 15, the drive circuit 8 comprises a common board 10 and individual boards 32a, 30b, 31c, 30d, and 32e, which correspond to IGBTs 61p to 65p, respectively.

[0250] The individual boards 32a and 32e each include detection circuits 42a and 42e, respectively, with the configuration described in Embodiment 2. The detection circuits 42a and 42e perform abnormality detection of the main circuit 104 based on the gate charge characteristics of the corresponding IGBTs 61p and 65p, respectively. The individual board 31c includes a detection circuit 41c, respectively, with the configuration described in Embodiment 1. The detection circuit 41c performs abnormality detection of the main circuit 104 based on the collector-emitter voltage of the corresponding IGBT 63p.

[0251] Thus, the drive circuit 8 includes detection circuits 42a and 42e that use an anomaly detection method based on gate charge characteristics, and a detection circuit 41c that uses an anomaly detection method based on collector-emitter voltage. The anomaly detection method based on gate charge characteristics can detect arm shorts at high speed, but it is difficult to detect load shorts. On the other hand, the anomaly detection method based on collector-emitter voltage is difficult to detect at high speed, but it can detect both arm shorts and load shorts.

[0252] Therefore, by using these two types of detection methods to configure the drive circuit 8 as shown in Figure 15, the advantage is obtained that both arm short circuits and load short circuits can be detected, and arm short circuits can be detected at high speed.

[0253] Furthermore, multiple power semiconductor devices corresponding to the detection circuit for each type of detection method may be distributed symmetrically, or power semiconductor elements corresponding to the detection circuit for the entire set of multiple detection methods may be distributed symmetrically.

[0254] Figure 16 shows an example of the configuration of a drive circuit according to a modification of Embodiment 5. Figure 16 shows an example of the configuration of a drive circuit 9 that drives the IGBTs 61p to 65p of the upper arm of the main circuit 104 shown in Figure 13. Note that the lower arm of the main circuit 104 is not shown in Figure 16.

[0255] As shown in Figure 16, the drive circuit 9 comprises a common board 10 and individual boards 30a, 30b, 34c, 30d, and 30e corresponding to IGBTs 61p to 65p, respectively. The individual board 34c has a detection circuit 44c equipped with multiple types of abnormality detection means. Specifically, the detection circuit 44c performs abnormality detection based on the collector-emitter voltage of the corresponding IGBT 63p, as described in Embodiment 1, and also performs abnormality detection based on the gate charge characteristics of the corresponding IGBT 63p, as described in Embodiment 2.

[0256] In this way, by utilizing multiple types of detection methods, a detection circuit 44c with superior detection accuracy and detection speed can be provided. Unlike the case in Figure 16, the drive circuit may include multiple detection circuits equipped with multiple types of detection methods.

[0257] [Effects of Embodiment 5] As described above, the drive circuit of Embodiment 5, by incorporating multiple detection methods, makes it possible to design a drive circuit that can detect abnormalities at low cost and effectively according to the application and operating environment of multiple power semiconductor elements connected in parallel with each other.

[0258] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. For example, it is possible to freely combine the embodiments, or to modify or omit some of the components of each embodiment as appropriate. The scope of this application is indicated by the claims rather than the foregoing description, and all modifications within the meaning and scope equivalent to the claims are intended to be included. [Explanation of Symbols]

[0259] 1-9 Drive circuit, 10 Common board, 11 Switching circuit, 12 Turn-on circuit, 13 Turn-off circuit, 14 Logic operation circuit, 15, 21a-21c Soft cutoff circuit, 16a, 16b NOT circuit, 17 AND circuit, 18 SRFF circuit, 19a, 19b Switching element, 20a, 20b Common gate resistor, 20c Output node, 23 MOSFET, 24, 26 Resistor element, 25 Diode, 30-34 Individual boards, 41-44 Detection circuit, 41A Detection unit, 41B Signal holding unit, 52 Individual gate resistor, 61n-66n, 61p-66p IGBT (Integrated Beam Transformer), 101-105 Main circuit, A1 Drive signal output terminal, CS Control signal, D1, D2c, D2a Detection signal input terminal, DRC Drive command, DRS Drive signal, DTS Detection signal (anomaly detection signal), F1 detection signal output terminal, GND ground, N negative terminal, N1~N7 negative nodes, P positive terminal, P1~P7 positive nodes, U1~U6 connection nodes, S1 control signal input terminal, UU phase load terminal, VDD power supply node.

Claims

1. A drive circuit for driving multiple power semiconductor elements connected in parallel, A common board that generates a common drive signal for controlling the on and off states of all the parallel-connected power semiconductor elements, Equipped with multiple individual circuit boards, Each of the plurality of individual substrates is individually provided for a corresponding power semiconductor element among the plurality of power semiconductor elements, and supplies the drive signal to the corresponding power semiconductor element. Each of the aforementioned plurality of individual circuit boards includes a detection circuit, The detection circuit is a drive circuit that, when it detects an abnormality in the electrical characteristics of a corresponding power semiconductor element, transmits an abnormality detection signal to the plurality of individual boards and the common board, or transmits the abnormality detection signal to the common board without transmitting the abnormality detection signal to the plurality of individual boards, thereby changing the drive signal.

2. The plurality of power semiconductor elements are arranged in one or more rows on one or more main circuit boards. An arbitrary first row composed of K power semiconductor elements includes L power semiconductor elements (where L is an integer between 1 and K) associated with the detection circuit, If we let N be the quotient and M be the remainder when K is divided by L (where M is an integer between 0 and L, and greater than or equal to 0), then the first column is divided into L blocks, each consisting of N power semiconductor elements, or L blocks consisting of N or N+1 power semiconductor elements, according to the arrangement order of the power semiconductor elements. The drive circuit according to claim 1, wherein if the number of power semiconductor elements constituting the block is odd, a detection circuit is provided on the central power semiconductor element, and if the number is even, a detection circuit is provided on either of the two central power semiconductor elements.

3. The aforementioned multiple power semiconductor elements are arranged in multiple rows on one or more main circuit boards. The drive circuit according to claim 2, wherein each column is associated with the same number of L detection circuits.

4. The drive circuit according to claim 2, wherein, in the case where the detection circuit is provided for each of three or more odd-numbered power semiconductor elements in a row in which an odd number of power semiconductor elements are arranged, the detection circuit is provided for the central power semiconductor element in the arrangement order, and the detection circuit is provided for a portion of the power semiconductor elements that are symmetrical with respect to the central power semiconductor element.

5. The drive circuit according to claim 2, wherein, in the case where the detection circuit is provided for each of the even number of power semiconductor elements in a row in which an odd number of power semiconductor elements are arranged, the detection circuit is provided for a portion of the power semiconductor elements that are symmetrical with respect to the central power semiconductor element in the arrangement order.

6. The drive circuit according to claim 2, wherein, in the case where the detection circuit is provided for each of three or more odd-numbered power semiconductor elements in a row in which an even number of power semiconductor elements are arranged, the detection circuit is provided for one of the two central power semiconductor elements in the arrangement order, and the detection circuit is provided for a portion of the power semiconductor elements that are symmetrical with respect to the two central power semiconductor elements.

7. The drive circuit according to claim 2, wherein, in the case where the detection circuit is provided for each of the even number of power semiconductor elements in a row in which an even number of power semiconductor elements are arranged, the detection circuit is provided for a portion of the power semiconductor elements that are symmetrical with respect to the two central power semiconductor elements in the arrangement order.

8. The drive circuit according to any one of claims 1 to 7, wherein the common board changes the logic value of the drive signal to turn off the plurality of power semiconductor elements when it receives the abnormality detection signal from the detection circuit.

9. The drive circuit according to any one of claims 1 to 7, wherein each of the plurality of individual substrates, when it receives the abnormality detection signal from the detection circuit, changes the potential of the drive signal by connecting the transmission path of the drive signal to a reference potential via a resistive element.

10. The drive circuit according to any one of claims 1 to 7, wherein the detection circuit detects an abnormality in a corresponding power semiconductor element based on the voltage between the main terminals of the corresponding power semiconductor element.

11. The drive circuit according to any one of claims 1 to 7, wherein the detection circuit detects an abnormality in a corresponding power semiconductor element based on the gate charge characteristics of the corresponding power semiconductor element.

12. The power semiconductor element corresponding to the detection circuit has a first main terminal, a second main terminal, and a sense terminal for diverting a portion of the main current flowing from the first main terminal to the second main terminal, and the second main terminal and the sense terminal are connected by wiring. The drive circuit according to any one of claims 1 to 7, wherein the detection circuit detects an abnormality in a corresponding power semiconductor element based on the voltage between the second main terminal and the sense terminal.

13. The drive circuit includes a first individual board and a second individual board as the individual boards including the detection circuit, A drive circuit according to any one of claims 1 to 7, wherein the detection circuit included in the first individual substrate detects an abnormality in the corresponding power semiconductor element, and the detection circuit included in the second individual substrate detects an abnormality in the corresponding power semiconductor element.

14. The drive circuit according to any one of claims 1 to 7, wherein the detection circuit detects abnormalities in the corresponding power semiconductor element using multiple different methods.

Images