Silicon carbide semiconductor device and method for manufacturing a silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device and a manufacturing method of the silicon carbide semiconductor device, which can maintain an integration degree of a MOSFET in the MOSFET in which a flat type SBD is built in to the same semiconductor substrate, and can suppress a forward direction characteristic deterioration of a body diode of the MOSFET.SOLUTION: Both of a trench gate type vertical MOSFET 31 and a flat surface type SBD 32 are arranged between all of adjacent gate trenches 7. The flat surface type SBD 32 is formed by a shot key contact part 12a of a second part 3b of an n-type current diffusion region 3 and a conductive film 12. The second part 3b of the n-type current diffusion region 3 is exposed to a front surface of a semiconductor 40 in a center of between the adjacent gate trenches 7, and the circumference is surrounded by a p-type base region 4. The conductive film 12 is one part of a barrier metal, and is provided in the front surface of the semiconductor 40 in a contact hole 13a from the surface of an inter-layer insulation film, 13.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] This invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device. [Background technology]

[0002] Conventionally, semiconductor devices using silicon carbide (SiC) as a semiconductor material (hereinafter referred to as silicon carbide semiconductor devices) are known to incorporate a trench-gate type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a Schottky barrier diode (SBD) formed from a conductive layer arranged in a flat manner on the front surface of the same semiconductor substrate (semiconductor chip).

[0003] In a MOSFET with an integrated SBD on the same semiconductor substrate, when the MOSFET is turned on, the integrated SBD operates simultaneously with the MOSFET and exhibits static characteristics similar to those of the MOSFET's body diode. The MOSFET's body diode has a p-type base region and n - Type drift region and n + This is a parasitic pin (p-intrinsic-n) diode formed at the pn junction with the drain region. Furthermore, when the MOSFET is off, the built-in SBD, which has a lower forward voltage than the MOSFET's body diode, operates preferentially.

[0004] The built-in SBD operates preferentially because the MOSFET body diode and the built-in SBD are n - Because they share a type drift region, the potential of the pn junction of the MOSFET's body diode becomes approximately the same as the potential of the Schottky contact between the conductive layer constituting the built-in SBD and the semiconductor substrate, making it difficult for the MOSFET's body diode to conduct. The MOSFET's body diode will not conduct until a larger-than-usual current flows through the MOSFET or a higher-than-usual voltage is applied to the MOSFET.

[0005] When the body diode conducts, the bipolar operation of the body diode causes n - type drift region to be injected with holes, and n - recombination of electrons and holes in the type drift region causes stacking faults to expand starting from basal plane dislocations in the semiconductor substrate. The expansion of these stacking faults degrades the forward characteristics of the body diode. As described above, incorporating an SBD to make it difficult for the body diode to conduct suppresses the degradation of the forward characteristics of the body diode compared to a conventional MOSFET that does not incorporate an SBD.

[0006] The structure of a conventional silicon carbide semiconductor device will be described. Fig. 26 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. The conventional silicon carbide semiconductor device 110 shown in Fig. 26 is a vertical trench gate type MOSFET 131 incorporating an SBD (hereinafter referred to as a planar SBD) 132 arranged in a planar shape on the front surface of the same semiconductor substrate 140 made of silicon carbide. The unit cells of the MOSFET 131 (functional units of the element) and the unit cells of the planar SBD 132 are alternately and repeatedly arranged in a first direction X parallel to the front surface of the semiconductor substrate 140.

[0007] The semiconductor substrate 140 is formed on an n + type starting substrate 141 with an n - type drift region 102 serving as an n - type epitaxial layer 142 grown epitaxially. On the front surface side of the semiconductor substrate 140 (the main surface on the n - type epitaxial layer 142 side), trenches (hereinafter referred to as gate trenches) 107 embedding the MOS gates of the MOSFET 131 are arranged at predetermined intervals in the first direction X, and one unit cell of the MOSFET 131 or one unit cell of the planar SBD 132 is respectively arranged between each pair of adjacent gate trenches 107.

[0008] The MOSFET 131 has, between adjacent gate trenches 107, an n-type current diffusion region 103, a p-type base region 104, an n + type source region 105 and a p ++It has a p-type contact region 106. p-type base region 104, n + Type source region 105 and p ++ A single unit cell of the MOSFET 131 is formed in the portion between the centers of adjacent gate trenches 107, separated by a type contact region 106. Reference numerals 121 to 123 indicate the p-force that relaxes the electric field applied to the gate insulating film 108 at the bottom surface of the gate trench 107. + This is a type domain.

[0009] The planar SBD132 is positioned between adjacent gate trenches 107 where no MOSFETs 131 are located, and between these adjacent gate trenches 107, there is only an n-type current diffusion region 103 that reaches the surface of the semiconductor substrate 140. One unit cell of the planar SBD132 is formed by the Schottky contact portion 112a between the conductive layer 112 positioned on the surface of the semiconductor substrate 140 and the n-type current diffusion region 103 between the adjacent gate trenches 107 separated only by this n-type current diffusion region 103.

[0010] The gate trenches 107 are arranged in a stripe pattern parallel to the front surface of the semiconductor substrate 140 and in a second direction Y perpendicular to the first direction X. The MOSFET 131 and the planar SBD 132 extend linearly in the second direction Y, parallel to the gate trenches 107. Reference numeral 111 denotes n + Type source region 105 and p ++ This is a conductive layer that makes ohmic contact with the type contact region 106. Reference numerals 101, 109, 113-115 respectively indicate n + These are the drain region, gate electrode, interlayer insulating film, front electrode, and back electrode.

[0011] As a conventional trench-gate type MOSFET, a device has been proposed in which a planar SBD is placed on the surface of the semiconductor substrate between adjacent gate trenches where no MOSFETs are located (see, for example, Patent Documents 1 to 3 below). Another conventional trench-gate type MOSFET has been proposed in which a mesa (groove) extends from the surface of the semiconductor substrate to the n-type current diffusion region in the center between adjacent gate trenches where MOSFETs are located, and a planar SBD is placed on the bottom surface of the mesa (see, for example, Patent Document 4 below). [Prior art documents] [Patent Documents]

[0012] [Patent Document 1] Japanese Patent Publication No. 2019-160898 [Patent Document 2] Japanese Patent Publication No. 2008-021930 [Patent Document 3] Japanese Patent Application Publication No. 11-054748 [Patent Document 4] Japanese Patent Publication No. 2018-182234 [Overview of the project] [Problems that the invention aims to solve]

[0013] However, in the conventional silicon carbide semiconductor device 110 described above (see Figure 26), a planar SBD 132 is placed between predetermined adjacent gate trenches 107 in place of the gate structure of the MOSFET 131. As a result, compared to a MOSFET without an SBD (a MOSFET in which gate structures are placed between all adjacent gate trenches), the integration density of unit cells per unit area of ​​the MOSFET 131 in the plane of the semiconductor substrate 140 decreases, and the on-resistance of the MOSFET 131 increases.

[0014] Furthermore, a pn junction (p) forms a parasitic pin diode (body diode) on MOSFET131. ++Type-type contact area 106, p-type base area 104 and p + Type region 121-123 and n-type current diffusion region 103, n - Type drift region 102 and n + A type drain region 101 and a part of the pn junction (p + In the pn junction between the type region 122 and the n-type current diffusion region 103, the distance d101 between the pn junction and the planar SBD 132 becomes longer. As a result, there is a problem that the body diode is more likely to conduct in the portion away from the planar SBD 132.

[0015] The present invention aims to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that can maintain the integration density of a MOSFET and suppress the degradation of the forward characteristics of the MOSFET body diode, in a MOSFET with a planar SBD built into the same semiconductor substrate, in order to solve the problems of the prior art described above. [Means for solving the problem]

[0016] To solve the above-mentioned problems and achieve the objectives of the present invention, the silicon carbide semiconductor device according to this invention has the following features: A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate made of silicon carbide. A second semiconductor region of a second conductivity type is selectively provided between the front surface of the semiconductor substrate and the first semiconductor region. A third semiconductor region of a first conductivity type is selectively provided between the front surface of the semiconductor substrate and the second semiconductor region. Multiple trenches penetrate the third semiconductor region and the second semiconductor region to reach the first semiconductor region. A gate electrode is provided inside the trench via a gate insulating film. A first conductive film is provided on the front surface of the semiconductor substrate.

[0017] The first conductive film is in ohmic contact with the second semiconductor region and the third semiconductor region. The first electrode is provided on the front surface of the semiconductor substrate and connected to the first conductive film. The second electrode is provided on the back surface of the semiconductor substrate. A first high-concentration region of the second conductivity type is selectively provided on the second electrode side of the bottom surface of the trench, away from the second semiconductor region. The first high-concentration region faces the bottom surface of the trench in the depth direction. A second high-concentration region of the second conductivity type is selectively provided on the second electrode side of the bottom surface of the trench, away from the trench, the second semiconductor region and the first high-concentration region. The first semiconductor region has a first portion and a second portion.

[0018] The first portion reaches the side wall of the trench between adjacent trenches, on the second electrode side of the second semiconductor region, in a direction parallel to the front surface of the semiconductor substrate. The second portion reaches the front surface of the semiconductor substrate between adjacent trenches, at a position in the depth direction opposite to the second high-density region, and is exposed to the front surface of the semiconductor substrate, surrounded by the second semiconductor region. The second conductive film is provided on the front surface of the semiconductor substrate, makes Schottky contact with the second portion, and is connected to the first electrode. A Schottky barrier diode is provided that utilizes the rectifying properties of the Schottky barrier formed at the junction between the second conductive film and the first semiconductor region. The multiple trenches extend in a stripe-like manner in a direction parallel to the front surface of the semiconductor substrate. The third semiconductor region is located between adjacent second portions and the trenches. Of the second semiconductor region, the third portion that makes ohmic contact with the first conductive film on the front surface of the semiconductor substrate is scattered in the direction in which the trenches extend in a stripe-like manner.

[0019] Furthermore, in the silicon carbide semiconductor device according to this invention, the second semiconductor region is a second conductivity type epitaxial layer. The second portion is a first conductivity type epitaxial layer. Conductive type Impurities are introduced into the body. Type 1 It is characterized by being a diffusion region.

[0020] Furthermore, in the silicon carbide semiconductor device according to this invention, the second portion is a first conductivity type epitaxial layer. The second semiconductor region is a second conductivity type epitaxial layer. Conductive type Impurities are introduced into the body. Second type It is characterized by being a diffusion region.

[0021] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, it further comprises a second conductivity type halo region that extends in the depth direction from the pn junction between the second semiconductor region and the third semiconductor region to the pn junction between the second semiconductor region and the first portion.

[0022] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the above-described invention, the third portion is a fourth semiconductor region of a second conductivity type with a higher impurity concentration than the portion of the second semiconductor region excluding the third portion, and the fourth semiconductor region and the third semiconductor region are alternately and repeatedly arranged in a direction in which the trench extends in a stripe shape. Furthermore, the silicon carbide semiconductor device according to this invention, The third part is, Advanced Semiconductor Region 2 The part excluding the aforementioned third part. The fourth semiconductor region of the second conductivity type has a higher impurity concentration than the second semiconductor region. and The fourth semiconductor region and the second portion are alternately and repeatedly arranged in a direction in which the trench extends in a stripe-like manner.

[0023] Furthermore, the silicon carbide semiconductor device according to the present invention is characterized in that, in the invention described above, it further comprises a third high-concentration region of a second conductivity type, which is provided in contact with the second semiconductor region, the first high-concentration region and the second high-concentration region, on the second electrode side of the bottom surface of the trench and at a position facing the fourth semiconductor region in the depth direction, and which is on the second electrode side of the second semiconductor region and reaches the side wall of the trench in a direction parallel to the front surface of the semiconductor substrate.

[0024] Furthermore, the silicon carbide semiconductor device according to the present invention is characterized in that, in the invention described above, it further comprises a third high-concentration region of a second conductivity type, which is provided on the second electrode side of the bottom surface of the trench and at a position facing the fourth semiconductor region in the depth direction, in contact with the second semiconductor region, the first high-concentration region and the second high-concentration region, and away from the trench.

[0025] Furthermore, in the silicon carbide semiconductor device according to this invention, the second part of the invention has a depth of 1 × 10⁻¹⁶ from the front surface of the semiconductor substrate to 0.7 μm. 17 / cm 3 Below Above1st conductivity type impurity concentration one It is characterized by having a box profile of a certain type.

[0026] Furthermore, in the silicon carbide semiconductor device according to this invention, the second semiconductor region is 1 × 10⁻¹⁶ in depth from the front surface of the semiconductor substrate to a depth of 0.7 μm in the invention described above. 17 / cm 3 Below Above 2nd conductivity type impurity concentration one It is characterized by having a box profile of a certain type.

[0027] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the second semiconductor region has a second conductivity type impurity concentration higher than the first conductivity type impurity concentration in the second portion in a depth range from the front surface of the semiconductor substrate to 0.8 μm.

[0028] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the first semiconductor region has a higher impurity concentration in the first and second parts than in other parts of the first semiconductor region.

[0029] Alternatively, in order to solve the above-mentioned problems and achieve the objectives of the present invention, the method for manufacturing a silicon carbide semiconductor device according to this invention is a method for manufacturing a vertical silicon carbide semiconductor device with a trench gate structure, and has the following features: A first step is performed in which a first epitaxial layer of a first conductivity type is grown on the front surface of a starting substrate made of silicon carbide. A second step is performed in which a second conductivity type high-concentration region is selectively formed in the first epitaxial layer by first ion implantation of a second conductivity type impurity, thereby mitigating the electric field applied to the bottom surface of the trench constituting the trench gate structure, and the portion of the first epitaxial layer excluding the second conductivity type high-concentration region becomes the first portion of the first semiconductor region of the first conductivity type. After the second step, a fourth step is performed in which a second epitaxial layer is grown on the surface of the first epitaxial layer.

[0030] A fifth step is performed to selectively form a second portion of the first semiconductor region connected to the first portion of the first semiconductor region, and a second semiconductor region of a second conductivity type surrounding the second portion, on the second epitaxial layer. 、 Third semiconductor region of the first conductivity type And a fourth semiconductor region of the second conductivity type with a higher impurity concentration than the aforementioned second semiconductor region, of Selectively The sixth step of formation is performed, penetrating the third semiconductor region and the second semiconductor region to reach the first epitaxial layer. and extending in a stripe-like manner in a direction parallel to the surface of the second epitaxial layer A seventh step is performed to form a plurality of the trenches. An eighth step is performed to form a halo region of the second conductivity type by ion implantation of a second conductivity type impurity from the side walls of the trenches, extending in the depth direction from the pn junction between the second semiconductor region and the third semiconductor region to the pn junction between the second semiconductor region and the first portion. After the eighth step, a ninth step is performed to form a gate electrode inside the trench via a gate insulating film. After the ninth step, on the surface of the second epitaxial layer ,before Third Semiconductor Area and the fourth semiconductor region A tenth step is performed to form a first conductive film that makes ohmic contact with the material.

[0031] After the ninth step, an eleventh step is performed in which a second conductive film is formed on the surface of the second epitaxial layer to make Schottky contact with the second portion, thereby forming a Schottky barrier diode that utilizes the rectification properties of the Schottky barrier formed at the junction between the second conductive film and the first semiconductor region. A twelfth step is performed in which a first electrode connected to the first conductive film and the second conductive film is formed on the surface of the second epitaxial layer. A thirteenth step is performed in which a second electrode is formed on the back surface of the starting substrate. In the second step, a first high-concentration region of the second conductivity type is selectively formed in the trench formation region within the first epitaxial layer as a second high-concentration region, reaching a position deeper than the trench, and a second high-concentration region of the second conductivity type is selectively formed between adjacent trench formation regions within the first epitaxial layer, separated from the first high-concentration region, reaching a position deeper than the trench.

[0032] In the fourth step, the second epitaxial layer of the second conductivity type is grown, and in the fifth step, the second portion is formed in the depth direction in the portion facing the second high-concentration region by ion implantation of the first conductivity type with an acceleration energy of 700 keV or less, and the portion of the second epitaxial layer excluding the second portion is made the second semiconductor region, or, in the fourth step, the second epitaxial layer of the first conductivity type is grown, and in the fifth step, the second semiconductor region is formed in the depth direction in the portion facing the second high-concentration region by ion implantation of the second conductivity type with an acceleration energy of 700 keV or less, and the portion of the second epitaxial layer excluding the second semiconductor region excluding the second semiconductor region excluding the second portion is made the second portion. In the sixth step, the third semiconductor region is formed between the adjacent second portions and the trench formation region, and the fourth semiconductor region is formed which is scattered in the direction in which the trench formation region extends in a stripe-like manner.

[0033] According to the invention described above, an SBD can be embedded in the same semiconductor substrate as the MOSFET, with unit cells of the MOSFET arranged between all adjacent trenches. [Effects of the Invention]

[0034] According to the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device of the present invention, in a MOSFET in which a planar SBD is embedded on the same semiconductor substrate, the integration density of the MOSFET can be maintained, and the degradation of the forward characteristics of the MOSFET body diode can be suppressed. [Brief explanation of the drawing]

[0035] [Figure 1] This is a plan view showing the layout of the silicon carbide semiconductor device according to Embodiment 1 as seen from the front side of the semiconductor substrate. [Figure 2] This is a cross-sectional view showing the cross-sectional structure along the cutting line A-A' in Figure 1. [Figure 3] This is a cross-sectional view showing the cross-sectional structure along the cutting line B-B' in Figure 1. [Figure 4] This is a cross-sectional view showing the silicon carbide semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 5] This is a cross-sectional view showing the silicon carbide semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 6] This is a cross-sectional view showing the silicon carbide semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 7] This is a cross-sectional view showing the silicon carbide semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 8] This is a cross-sectional view showing the silicon carbide semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 9] This is a cross-sectional view showing the silicon carbide semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 10] This is a cross-sectional view showing the silicon carbide semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 11] This is a cross-sectional view showing the manufacturing process of a comparative example. [Figure 12] This is a cross-sectional view showing the manufacturing process of a comparative example. [Figure 13] This is a cross-sectional view showing another stage in the manufacturing process of the silicon carbide semiconductor device according to Embodiment 1. [Figure 14] This is a cross-sectional view showing another stage in the manufacturing process of the silicon carbide semiconductor device according to Embodiment 1. [Figure 15] This is a plan view showing the layout of the silicon carbide semiconductor device according to Embodiment 2, as seen from the front side of the semiconductor substrate. [Figure 16] Figure 15 is a cross-sectional view showing the cross-sectional structure along the cutting line C-C'. [Figure 17] Figure 15 is a cross-sectional view showing the cross-sectional structure along the cutting line D-D'. [Figure 18] Figure 15 is a cross-sectional view showing the cross-sectional structure along the cutting line D-D'. [Figure 19] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 3. [Figure 20] This is a distribution diagram showing the doping concentration distribution near the second portion of the n-type current diffusion region in Experimental Example 1. [Figure 21]Figure 20 is a distribution diagram showing the n-type doping concentration distribution in the second part of the n-type current diffusion region. [Figure 22] This is a diagram showing the ion implantation conditions for n-type impurities (nitrogen) in Example 1. [Figure 23] This is a distribution map showing the doping concentration distribution near the p-type base region in Experimental Example 2. [Figure 24] Figure 23 is a distribution diagram showing the p-type doping concentration distribution in the p-type base region. [Figure 25] This is a diagram showing the ion implantation conditions for p-type impurities (aluminum) in Example 2. [Figure 26] This is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. [Modes for carrying out the invention]

[0036] Preferred embodiments of the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - prefixes to n and p indicate higher and lower impurity concentrations, respectively, compared to layers or regions without these prefixes. In the following description of embodiments and in the accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted.

[0037] (Embodiment 1) The structure of the silicon carbide (SiC) semiconductor device according to Embodiment 1 will be described. Figure 1 is a plan view showing the layout of the silicon carbide semiconductor device according to Embodiment 1 as seen from the front side of the semiconductor substrate. Figure 1 shows the MOS gate of MOSFET 31 (gate insulating film 8 and gate electrode 9), planar SBD 32 (Schottky contact portion 12a of the conductive layer (second conductive layer) 12), n + Type source region (third semiconductor region) 5, p ++ Type contact region (fourth semiconductor region) 6 and p +The layout (arrangement) of type regions (1st to 3rd high-concentration regions) 21 to 23 is shown.

[0038] Also, Figure 1 shows p + The mold regions 21-23 are shown with the same hatching. The gate electrode 9, the Schottky contact portion 12a of the conductive layer 12, and p ++ Each type contact region 6 is hatched with a different hatching pattern, and p + The type regions 21-23 are shown with different hatching. In Figure 1, n + The mold source region 5 is shown by a dashed line, and the gate insulating film 8 is omitted from the illustration. Figure 2 is a cross-sectional view showing the cross-sectional structure along the cutting line A-A' in Figure 1. Figure 3 is a cross-sectional view showing the cross-sectional structure along the cutting line B-B' in Figure 1.

[0039] The silicon carbide semiconductor device 10 according to Embodiment 1 shown in Figure 1 is a vertical trench gate type MOSFET 31 incorporating an SBD (planar SBD) 32 arranged in a flat plate shape on the front surface of the same semiconductor substrate (semiconductor chip) 40 made of silicon carbide. The unit cells (functional units of the element) of the MOSFET 31 and the unit cells of the planar SBD 32 are alternately and repeatedly arranged in the active region 51 in a first direction X parallel to the front surface of the semiconductor substrate 40. The active region 51 is the region in which the main current (drift current) flows when the MOSFET is turned on, and multiple unit cells of the MOSFET 31 and the planar SBD 32 are arranged therein.

[0040] The edge termination region 52 is the region between the active region 51 and the edge (chip edge) of the semiconductor substrate 40, and surrounds the active region 51. The edge termination region 52 has the function of mitigating the electric field on the front side of the semiconductor substrate 40 and maintaining the breakdown voltage. Breakdown voltage is the limit voltage at which the silicon carbide semiconductor device 10 will not malfunction or break down. Breakdown structures such as a field limiting ring (FLR) or a junction termination extension (JTE) structure are arranged in the edge termination region 52.

[0041] Multiple gate trenches 7, into which the MOS gates of the MOSFET 31 are embedded, are arranged at predetermined intervals in a first direction X. The gate trenches 7 extend in a stripe-like manner in a second direction Y, which is parallel to the front surface of the semiconductor substrate 40 and perpendicular to the first direction X. Both the MOSFET 31 and the planar SBD 32 are positioned between all adjacent gate trenches 7, extending linearly in the second direction Y, parallel to the gate trenches 7. The planar SBD 32 is positioned further from the gate trenches 7 than the MOSFET 31 between adjacent gate trenches 7.

[0042] The p-type base region (second semiconductor region) of MOSFET31 4 (not shown in Figure 1, see Figures 2 and 3), n + Type source region 5 and p ++ The p-type contact region 6 is positioned adjacent to the gate trench 7. The p-type base region 4 extends linearly in the second direction Y, parallel to the gate trench 7. The longitudinal ends (second direction Y) of adjacent p-type base regions 4 are connected near the boundary between the active region 51 and the edge termination region 52. The connection between the longitudinal ends of the p-type base regions 4 extends along the boundary between the active region 51 and the edge termination region 52, surrounding the active region 51.

[0043] n + Type source area 5 and p ++ The type contact region 6 is alternately and repeatedly arranged along the gate trench 7 in the second direction Y. ++ The type contact regions 6 are scattered in the second direction Y, and also scattered in the first direction X, with the gate trenches 7 in between. ++ The width of the type contact region 6 in the second direction Y is n + It may be narrower than the width of the second direction Y of the type source region 5. Figure 1 shows p ++ The planar shape of the type contact region 6 is approximately square, and adjacent p in the second direction Y ++ Between the type contact regions 6, p ++ Adjacent to the type contact region 6 is a roughly rectangular planar shape n that is elongated in the second direction Y. +This shows the case where type source area 5 is placed.

[0044] p (as described later) + Type regions 21-23 are one p of a grid-like planar shape + Constitutes a type domain. + The mold regions 21 and 22 are alternately arranged in the first direction X and extend linearly in the second direction Y parallel to the gate trench 7. + The mold region 21 faces the bottom surface of the gate trench 7 in the depth direction Z. The depth direction Z is the direction from the front surface to the back surface of the semiconductor substrate 40. + The width of the mold region 21 in the short direction (first direction X) is wider than, for example, the width of the gate trench 7 in the short direction (first direction X). + The mold region 21 terminates outside the gate trench 7 (towards the tip end) in the longitudinal direction (second direction Y).

[0045] p + Type regions 21 and 22 terminate at approximately the same position in the longitudinal direction, for example. "Approximately the same position" means that they are at the same position within a range that includes tolerances due to process variations. + The mold region 22 faces the Schottky contact portion 12a of the conductive layer 12 in the depth direction Z. + The width of the mold region 22 in the short direction (first direction X) is wider than, for example, the width of the Schottky contact portion 12a of the conductive layer 12 in the short direction (first direction X). + The type region 23 has a depth direction Z of p ++ It faces the type contact area 6. + The type region 23 extends in a stripe shape in the first direction X, p + In the region where type regions 21 and 22 intersect, these p + It is connected to type regions 21 and 22.

[0046] Approximately in the center between all adjacent gate trenches 7, an n-type current diffusion region (first semiconductor region) 3 (not shown in Figure 1, see Figures 2 and 3) is exposed on the surface of the semiconductor substrate 40 (if the n-type current diffusion region 3 is not provided, the n-type current diffusion region 3 will be described later). -The n-type drift region (first semiconductor region) 2 is exposed. The n-type current diffusion region 3 is exposed on the front surface of the semiconductor substrate 40 if it is in contact with the conductive layer 12 on the front surface of the semiconductor substrate 40. The n-type current diffusion region 3 is located adjacent to the p-type base region 4, at a position further from the gate trench 7 than the p-type base region 4 between adjacent gate trenches 7, and extends linearly in the second direction Y parallel to the gate trench 7.

[0047] The n-type current diffusion region 3 is in Schottky contact with the conductive layer 12 on the front surface of the semiconductor substrate 40 between adjacent gate trenches 7. The Schottky contact portion 12a of the conductive layer 12 extends linearly in the second direction Y, parallel to the gate trenches 7. The longitudinal end (second direction Y) of the Schottky contact portion 12a of the conductive layer 12 may terminate inward (towards the center of the semiconductor substrate 40 (center of the chip)) of the longitudinal end of the gate trench 7. A planar SBD 32 is constructed utilizing the rectifying properties of the Schottky contact formed at the junction surface between the n-type current diffusion region 3 and the conductive layer 12 (Schottky contact portion 12a of the conductive layer 12).

[0048] The planar SBD32 operates simultaneously with MOSFET31 when MOSFET31 is turned on and exhibits static characteristics similar to those of the MOSFET31's body diode. The MOSFET31's body diode is p ++ Type 6 contact area, p-type base area 4 and p + Type regions 21-23 and n-type current diffusion region 3, n - Type drift regions 2 and n + It is a parasitic pin diode formed by the drain region 1 and the pn junction (see Figures 2 and 3). The planar SBD32 has a lower forward voltage than the body diode of MOSFET31, operates preferentially when MOSFET31 is off, and has the function of suppressing the degradation of the forward characteristics of the body diode of MOSFET31.

[0049] Next, the cross-sectional structure of the silicon carbide semiconductor device 10 according to Embodiment 1 will be described. The semiconductor substrate 40 is n + On the front surface of the mold starting substrate 41, n- The first and second epitaxial layers 42 and 43, which form the p-type drift region 2 and the p-type base region 4, are grown epitaxially in sequence. The main surface of the semiconductor substrate 40 on the side of the p-type epitaxial layer 43 is considered the front surface, and n + The main surface on the mold starting substrate 41 side is considered the back surface. In the active region 51, a trench gate structure of the MOSFET 31 is provided on the front surface side of the semiconductor substrate 40, and a planar SBD 32 is provided in a flat plate shape on the front surface of the semiconductor substrate 40.

[0050] The trench gate structure of MOSFET31 is p-type base region 4, n + Type source area 5, p ++ It consists of a type contact region 6, a gate trench 7, a gate insulating film 8, and a gate electrode 9. + The starting substrate 41 is n + It functions as type drain region 1. - Type drift region 2 is n - The type epitaxial layer 42, as described later, p + This is the portion excluding the n-type current diffusion region 21-23 and the n-type current diffusion region 3 described later, p + Type regions 21-23 and n-type current diffusion region 3 and n + These regions are provided in contact with the starting substrate 41. The p-type base region 4 is located between the front surface of the semiconductor substrate 40 and the n - It is located between the drift region 2 and the other region.

[0051] The p-type base region 4 is the n of the p-type epitaxial layer 43. + Type source region 5 and p ++ This is the portion excluding the contact area 6. + Type source region 5 and p ++ The p-type contact region 6 is selectively provided between the front surface of the semiconductor substrate 40 and the p-type base region 4, in contact with the p-type base region 4 and exposed to the front surface of the semiconductor substrate 40. + Type source region 5 and p ++ The contact area 6 is exposed on the front surface of the semiconductor substrate 40, + Type source region 5 and p++ type contact region 6 is in contact with a conductive layer (first conductive layer) 11 described later on the front surface of the semiconductor substrate 40.

[0052] n + -type source region 5 and p ++ -type contact region 6 are adjacent to each other in the second direction Y as described above. n + -type source region 5 and p ++ -type contact region 6 are in contact with a gate insulating film 8 on a sidewall of a gate trench 7. p ++ -type contact region 6 may be arranged spaced apart from the gate trench 7. n + -type source region 5 and p ++ -type contact region 6, a p-type base region 4 may be exposed on the front surface of the semiconductor substrate 40 at a position farther from the gate trench 7 than the foregoing. p ++ -type contact region 6 does not have to be provided, and p ++ -type base region 4 may be exposed on the front surface of the semiconductor substrate 40 in place of the p-type contact region 6.

[0053] n - -type drift region 2 and the p-type base region 4, an n - -type current diffusion region 3 is provided in contact with the n-type drift region 2 and the p-type base region 4. The n-type current diffusion region 3 is a so-called current spreading layer (CSL) that reduces carrier spreading resistance. Between mutually adjacent gate trenches 7, the n-type current diffusion region 3 is closer to the n + -type drain region 1 side than the p-type base region 4, and reaches a sidewall of the gate trench 7 in the first direction X at a deep first portion 3a, and the first portion 3a reaches a position deeper on the n + -type drain region 1 side than the bottom surface of the gate trench 7 in the depth direction Z.

[0054] Furthermore, the n-type current diffusion region 3 reaches the surface of the semiconductor substrate 40 approximately in the center between adjacent gate trenches 7 and is exposed on the surface of the semiconductor substrate 40. The surface region 3b of the n-type current diffusion region 3 that reaches the surface of the semiconductor substrate 40 (hereinafter referred to as the second portion) is adjacent to the p-type base region 4 in a direction parallel to the surface of the semiconductor substrate 40 and is surrounded by the p-type base region 4. That is, between adjacent gate trenches 7, the second portion 3b of the n-type current diffusion region 3 is positioned approximately in the center of the surface region of the semiconductor substrate 40, and the p-type base region 4 is positioned between the second portion 3b and the side wall of the gate trench 7.

[0055] The second portion 3b of the n-type current diffusion region 3 is a box profile in which the impurity concentration is approximately uniform in the depth direction Z from the front surface of the semiconductor substrate 40 (see Figure 21). Approximately uniform impurity concentration means that the impurity concentration is the same within a range that includes tolerances due to process variations. The n-type current diffusion region 3 does not have to be provided. In this case, the p-type base region 4 and n - The n-type drift region 2 is in contact with the n-type current diffusion region 3, and the second part 3b of the n-type current diffusion region 3 is replaced by n - The n-type drift region 2 is exposed on the surface of the semiconductor substrate 40. Here, we will explain using the case where an n-type current diffusion region 3 is provided as an example, but if an n-type current diffusion region 3 is not provided, the n-type current diffusion region 3 is n - This can be interpreted as type drift region 2.

[0056] n - Between the p-type drift region 2 and the p-type base region 4, there is a p-type current diffusion region 3 adjacent to the p-type drift region 2. + Type regions 21-23 are selectively provided. + The mold regions 21-23 are n greater than the bottom surface of the gate trench 7. + It is sufficient that it reaches a deep position on the drain region 1 side. Therefore, p + Type regions 21-23 are n + The drain region 1 may terminate at a shallower position than the n-type current diffusion region 3, and may be surrounded by the n-type current diffusion region 3. + Type regions 21-23 are n +Either the drain region 1 terminates at the same position as the n-type current diffusion region 3, or it reaches a position deeper than the n-type current diffusion region 3, - It may be in contact with type drift region 2.

[0057] p + The type regions 21-23 are electrically connected to the front electrode (first electrode) 14, which will be described later, and have the function of depleting when the MOSFET 31 is off, thereby mitigating the electric field applied to the bottom surface of the gate trench 7. + The mold region 21 (see Figure 2) is provided separately from the p-type base region 4 and faces the bottom surface of the gate trench 7 in the depth direction Z. + The mold region 21 may be exposed to the bottom surface of the gate trench 7. Exposure to the bottom surface of the gate trench 7 means that it is in contact with the gate insulating film 8 at the bottom surface of the gate trench 7. + The p-type region 22 (see Figure 2) is formed between adjacent gate trenches 7, with a p-type base region 4 and p + It is provided separately from the mold region 21.

[0058] p + The mold region 22 faces the Schottky contact portion 12a of the conductive layer 12 in the depth direction Z. + Type regions 21 and 22 are n as described later. - The type epitaxial layers 42 are formed simultaneously by ion implantation and are provided at approximately the same depth and thickness. Approximately the same depth and thickness mean that they are the same depth and thickness within a range that includes tolerances due to process variations, respectively. + n + The part on the drain region 1 side is, as will be described later, n - Ion implantation into the type epitaxial layer 42 allows p + Type regions 21 and 22 are formed simultaneously, p + It reaches approximately the same depth as type regions 21 and 22.

[0059] p + In the mold region 23 (see Figure 3), the depth direction Z is p between adjacent gate trenches 7. ++It is positioned opposite the type contact region 6 and extends in the first direction X to reach the gate trench 7. + The p-type region 23 is adjacent to the second portion 3b of the p-type base region 4 and the n-type current diffusion region 3. + The portion between the n-type regions 23 is the first portion 3a of the n-type current diffusion region 3. Therefore, in the depth direction Z, n + At the position opposite the n-type source region 5, the first portion 3a of the n-type current diffusion region 3 is in contact with the p-type base region 4 and the second portion 3b of the n-type current diffusion region 3.

[0060] p + Type region 23 by p + When type regions 21 and 22 are connected, p + The mold regions 21-23 are fixed at the same potential (the potential of the front surface electrode 14). The gate trench 7 is n in the depth direction Z. + Type source area 5, p ++ The current penetrates the p-type contact region 6 and the p-type base region 4 to reach the n-type current diffusion region 3. Inside the gate trench 7, a gate electrode 9 is provided via a gate insulating film 8. The gate trench 7, gate insulating film 8, and gate electrode 9 constitute the MOS gate of the trench gate structure of the MOSFET 31. One unit cell of the MOSFET 31 is formed in the adjacent portions of the p-type base region 4 separated by one gate trench 7 in the first direction X.

[0061] One Schottky contact portion 12a of the conductive layer 12 constitutes one unit cell of the planar SBD 32. Therefore, one planar SBD 32 is placed between adjacent gate trenches 7, and MOSFETs 31 are placed adjacent to both sides of the planar SBD 32 in the first direction X. Among the pn junctions forming the body diode of the MOSFET 31, the pn junction with the longest distance d1 from the planar SBD 32 is the pn junction directly below the gate trench 7. +This is a pn junction between the n-type region 21 and the n-type current diffusion region 3. Compared to the conventional structure (see reference numeral d101 in Figure 26), the distance d1 between the pn junction forming the body diode of MOSFET 31 and the planar SBD 32 is shorter. All adjacent gate trenches 7 have the same configuration.

[0062] The interlayer insulating film 13 is provided over the entire surface of the front surface of the semiconductor substrate 40 and covers the gate electrode 9. A conductive layer 11 is selectively provided on the front surface of the semiconductor substrate 40 at the contact hole 13a of the interlayer insulating film 13. The conductive layer 11 is n + Type source region 5 and p ++ It is provided only on the type contact area 6, n + Type source region 5 and p ++ The conductive layer is, for example, a nickel silicide (NixSiy, x and y are positive numbers) film that makes ohmic contact with the p-type contact region 6. If the p-type base region 4 is exposed on the front surface of the semiconductor substrate 40, the conductive layer 11 may extend over the p-type base region 4.

[0063] The conductive layer 12 covers the entire surface of the interlayer insulating film 13 and extends onto the front surface of the semiconductor substrate 40 at the contact hole 13a, covering the conductive layer 11 and the second portion 3b of the n-type current diffusion region 3. The conductive layer 12 is, for example, a titanium (Ti) film. The conductive layer 12 functions as a barrier metal, for example, in the portion on the interlayer insulating film 13, preventing the diffusion of metal atoms from the front electrode 14 side to the gate electrode 9 side. The conductive layer 12 also makes Schottky contact with the second portion 3b of the n-type current diffusion region 3 at the contact hole 13a of the interlayer insulating film 13. The planar SBD 32 is formed at this Schottky contact portion 12a of the conductive layer 12.

[0064] The planar SBD32 has an n-type current diffusion region 3, n - Type drift regions 2 and n +The drain region 1 is shared with MOSFET 31. The potential of the pn junction of the body diode of MOSFET 31 is approximately the same as the potential of the Schottky contact portion 12a of the conductive layer 12. The front electrode 14 is provided on the front surface of the semiconductor substrate 40 so as to fill the contact hole 13a. The front electrode 14 is connected to the p-type base region 4, n-type base region 4, via the conductive layer 11. + Type source region 5 and p ++ It is electrically connected to the contact region 6. The front electrode 14 and the conductive layer 11 function as the source electrode of the MOSFET 31.

[0065] The front electrode 14, via the conductive layer 12, has an n-type current diffusion region 3 and n - It is electrically connected to the drift region 2. The front electrode 14 also serves as the anode electrode of the planar SBD 32. The conductive layer 12 functions as the anode electrode of the planar SBD 32. The back surface (n + A back electrode (second electrode) 15 is provided on the entire back surface of the mold starting substrate 41. The back electrode 15 is n + It is electrically connected to the mold starting substrate 41. The back electrode 15 functions as the drain electrode of the MOSFET 31. The back electrode 15 also serves as the cathode electrode of the planar SBD 32.

[0066] Next, the operation of the silicon carbide semiconductor device 10 according to Embodiment 1 will be described. When a positive voltage (drain-source voltage) is applied to the back electrode 15 with respect to the front electrode 14, and a gate voltage equal to or greater than the gate threshold voltage is applied to the gate electrode 9, a channel (n-type inversion layer) is formed in the portion of the p-type base region 4 along the gate trench 7. As a result, n + Type drain region 1 to n - n-type drift region 2, n-type current diffusion region 3 and n through the channel + A drain-source current flows towards the source region 5, and MOSFET 31 turns on.

[0067] On the other hand, when a positive voltage is applied to the back electrode 15 relative to the front electrode 14, and a gate voltage less than the gate threshold voltage is applied to the gate electrode 9, p ++ Type contact area 6, p + Type regions 21-23 and p-type base region 4, and n-type current diffusion region 3, n-type current diffusion region 3, n - Type drift regions 2 and n + When the drain region 1 and the pn junction are reverse-biased, no current flows between the drain and source, and the MOSFET 31 remains in the off state. A depletion layer expands from the pn junction, and the electric field applied to the gate insulating film 8 at the bottom of the gate trench 7 is relaxed.

[0068] Furthermore, when the MOSFET 31 is off, if a negative voltage (the forward voltage of the MOSFET 31's body diode and the planar SBD 32) is applied to the back electrode 15 with respect to the front electrode 14, the planar SBD 32, which has a forward voltage set lower than that of the MOSFET 31's body diode, conducts faster than the MOSFET 31's body diode due to the Schottky barrier formed at the junction surface between the conductive layer 12 and the second portion 3b of the n-type current diffusion region 3, and determined by the electrical properties of the conductive layer 12. Therefore, the MOSFET 31's body diode does not operate. As a result, the degradation of the forward characteristics of the MOSFET 31's body diode is suppressed.

[0069] Next, a method for manufacturing the silicon carbide semiconductor device 10 according to Embodiment 1 will be described. Figures 4 to 10 are cross-sectional views showing the silicon carbide semiconductor device according to Embodiment 1 in the process of manufacturing. Figures 4 to 10 show a portion of Figure 2. Figures 11 and 12 are cross-sectional views showing the comparative example in the process of manufacturing. Figures 11 and 12 show a method for forming the conductive layers 211 and 212 of a normal MOSFET 210 without an SBD, as a comparative example.

[0070] First, as shown in Figure 4, n consists of silicon carbide. + Prepare a starting substrate (starting wafer) 41. + The starting substrate 41 is the n of the MOSFET 31 + Type drain region 1. Next, n+ On the front surface of the mold starting substrate 41, the n after completion of the product (silicon carbide semiconductor device 10) - The thickness of the n-type epitaxial layer 42 is thinner than the product thickness (thickness of the first part 3a of the n-type current diffusion region 3), - The type epitaxial layer 42 is epitaxially grown.

[0071] Next, as shown in Figure 5, n is obtained by photolithography and ion implantation of p-type impurities. - p + Selectively form type regions 21-23 (see Figures 1-3). Next, p + After removing the ion implantation mask (not shown) used to form n-type regions 21-23, n-type impurities were implanted using photolithography and ion implantation. - The first portion 3a of the n-type current diffusion region 3 is formed on the surface region of the type epitaxial layer 42.

[0072] n-type current diffusion region 3 and p + The formation order of n-type current diffusion region 3 and p may be reversed. + The ion implantation mask used to form the type regions 21-23 or the diffusion region formed by ion implantation described later may be, for example, an oxide film (SiO2 film) or a resist film. - The portion of the type epitaxial layer 42 that remains without ion implantation (n-type current diffusion region 3 and p + The part excluding type region 21-23 is n - This results in drift region 2.

[0073] Next, as shown in Figure 6, after removing the ion implantation mask (not shown) used to form the n-type current diffusion region 3, - Further n on the type epitaxial layer 42 - The type epitaxial layer is epitaxially grown to increase its thickness, n - The molded epitaxial layer 42 is made to the product thickness. - The impurity concentration in the portion 42a of the epitaxial layer 42 with increased thickness is, for example, n -The impurity concentration in type drift region 2 may be approximately the same as that in type drift region 2.

[0074] Next, by photolithography and ion implantation of p-type impurities, n - By selectively introducing p-type impurities into the portion 42a of the type epitaxial layer 42 with increased thickness, + The thickness of the mold region 23 (see Figure 3) is increased. This allows p + A single p formed by arranging type regions 21-23 in a predetermined layout (for example, a grid-like planar shape) + Part of the type domain (p + Type region 23) is n - It is exposed on the surface of the type epitaxial layer 42.

[0075] Next, p + After removing the ion implantation mask (not shown) used to form the n-type region 23, n-type impurities were implanted using photolithography and ion implantation. - By introducing n-type impurities into the portion 42a of the n-type epitaxial layer 42 whose thickness has been increased, the thickness of the first portion 3a of the n-type current diffusion region 3 is increased. As a result, the first portion 3a of the n-type current diffusion region 3 is n - Exposed on the surface of the type epitaxial layer 42. n-type current diffusion region 3 and p + The formation order with type region 23 may be reversed.

[0076] Next, as shown in Figure 7, n - A p-type epitaxial layer 43 is epitaxially grown on the surface of the n-type epitaxial layer 42. + A semiconductor substrate (semiconductor wafer) 40 is completed by sequentially epitaxially growing epitaxial layers 42 and 43 on the front surface of the p-type starting substrate 41. The p-type epitaxial layer 43 is formed by the n-type epitaxial layer below. - p exposed on the surface of the type epitaxial layer 42 + It comes into contact with the first portion 3a of the n-type current diffusion region 23 and the n-type current diffusion region 3.

[0077] Next, as shown in Figure 8, a second portion 3b of the n-type current diffusion region 3 is formed by photolithography and ion implantation of n-type impurities at a depth Z opposite to the first portion 3a of the n-type current diffusion region 3, with a depth that penetrates the p-type epitaxial layer 43. This connects the first and second portions 3a and 3b of the n-type current diffusion region 3. Next, the ion implantation mask (not shown) used to form the second portion 3b of the n-type current diffusion region 3 is removed.

[0078] Next, as shown in Figure 9, by repeatedly performing a set of steps consisting of photolithography, ion implantation of impurities, and removal of the ion implantation mask (not shown) under different conditions, n is produced in the surface region of the p-type epitaxial layer 43 in the active region 51. + Type source region 5 and p ++ The n-type contact regions 6 (see Figure 3) are selectively formed. The second part 3b of the n-type current diffusion region 3, n + Type source region 5 and p ++ The formation order of the type contact region 6 may be changed.

[0079] p-type epitaxial layer 43, which remains without ion implantation, + The portion in contact with the type region 23 becomes the p-type base region 4. Next, by photolithography and etching, the p-type is formed in the depth direction Z. + At a position opposite to type region 21, n + Type source area 5, p ++ A gate trench 7 is formed that penetrates the p-type contact region 6 and the p-type base region 4 and reaches the n-type current diffusion region 3. Then, the etching mask used to form the trench is removed.

[0080] Next, the native oxide film on the front surface of the semiconductor substrate 40 and the inner wall of the gate trench 7 is removed by sacrificial oxidation. Then, a gate insulating film 8 is formed along the front surface of the semiconductor substrate 40 and the inner wall of the gate trench 7. Next, a polysilicon (poly-Si) layer is deposited and patterned to fill the gate trench 7 with polysilicon, leaving the portion of the polysilicon layer that will become the gate electrode 9 only inside the gate trench 7.

[0081] Next, after removing the patterning mask (not shown) for the polysilicon layer, an interlayer insulating film 13 is deposited on the surface of the semiconductor substrate 40. Then, the interlayer insulating film 13 is selectively removed by photolithography and etching to open a contact hole 13a, and n + Type source area 5, p ++ The second portion 3b of the n-type contact region 6 and the n-type current diffusion region 3 is exposed.

[0082] Next, a nickel film 11a, which will be the material film for the conductive layer 11, is deposited on the front surface of the semiconductor substrate 40, for example, by sputtering. Then, the nickel film 11a is selectively removed by photolithography and etching, n + Type source region 5 and p ++ The nickel film 11a is left only on the contact region 6. If the p-type base region 4 is exposed in the contact hole 13a of the interlayer insulating film 13, the nickel film 11a may also be left on the p-type base region 4.

[0083] In other words, the nickel film 11a is removed from the area where Schottky contact with the semiconductor substrate 40 is formed in the contact hole 13a of the interlayer insulating film 13, leaving the nickel film 11a only on the area where ohmic contact with the semiconductor substrate 40 is formed. Next, the nickel film 11a is reacted with the semiconductor substrate 40 by heat treatment to silicide the nickel film 11a, + Type source region 5 and p ++ A conductive layer 11 is formed to make ohmic contact with the type contact region 6.

[0084] The nickel film 11a that forms the material film of the conductive layer 11 is preferably selectively removed so as to be separated from the interlayer insulating film 13 and the gate insulating film 8. This prevents the diffusion of nickel atoms from the nickel film 11a to the interlayer insulating film 13 side during the silicide formation of the nickel film 11a. If unreacted nickel film 11a remains on the surface of the conductive layer 11 without being silicided, this unreacted nickel film 11a may be removed by etching.

[0085] Next, as shown in Figure 10, for example, a titanium film, which will become the conductive layer 12, is deposited from the surface of the interlayer insulating film 13 to the entire surface of the front surface of the semiconductor substrate 40 that is exposed to the contact holes 13a of the interlayer insulating film 13, using a sputtering method. As a result, the contact points of the conductive layer 12 with the second portion 3b of the n-type current diffusion region 3 become Schottky contact portions 12a, and a planar SBD 32 is formed.

[0086] The portion of the conductive layer 12 other than the contact point with the second portion 3b of the n-type current diffusion region 3 becomes a barrier metal covering the surface of the interlayer insulating film 13 and the surface of the conductive layer 11. The conductive layers 11 and 12 of the silicon carbide semiconductor device 10 according to this embodiment 1 can be formed using the same formation method as the conductive layers 211 and 212 (nickel silicide film and barrier metal: see Figures 11 and 12) of a normal MOSFET 210 that does not incorporate an SBD.

[0087] For example, in a typical MOSFET 210, as shown in Figure 11, contact holes 213a are formed in the interlayer insulating film 213, and then a nickel film 211a is deposited on the front surface of the semiconductor substrate 40. Next, the nickel film 211a is selectively removed by photolithography and etching, leaving it on the entire surface of the front surface of the semiconductor substrate 240, specifically the portion of the interlayer insulating film 213 exposed to the contact holes 213a.

[0088] Next, the nickel film 211a is reacted with the semiconductor substrate 240 by heat treatment to silicide it, thereby forming a conductive layer 211 that makes ohmic contact with the entire surface of the front surface of the semiconductor substrate 240, specifically the portion exposed to the contact holes 213a of the interlayer insulating film 213. Next, a titanium film (barrier metal) is formed to become a conductive layer 212 that covers the entire surface of the interlayer insulating film 213 and the conductive layer 211.

[0089] The typical trench gate structure configuration of a MOSFET210 is n + Type source region 205 and p ++Except for a slight difference in the arrangement of the type contact region 206, the trench gate structure is almost the same as that of the MOSFET 31 of Embodiment 1. In Figures 11 and 12, reference numerals 201 to 204 and 207 to 209 indicate n + Type drain region, n - These are the n-type drift region, n-type current diffusion region, p-type base region, gate trench, gate insulating film, and gate electrode.

[0090] Thus, the method for forming the conductive layers 211 and 212 of a normal MOSFET 210 is the same as the method for forming the conductive layers 11 and 12 of the silicon carbide semiconductor device 10 according to Embodiment 1. For this reason, in Embodiment 1, the conductive layers 11 and 12 can be formed by using the method for forming the conductive layers 211 and 212 of a normal MOSFET 210 and changing the etching mask used for selective removal of the nickel film 11a which becomes the material film of the conductive layer 11.

[0091] After forming the conductive layer 12 in this manner, a front electrode 14 is formed on the conductive layer 12 using a general method, and a back electrode 15 is formed on the back surface of the semiconductor substrate 40. The order of formation of the front electrode 14 and the back electrode 15 may be reversed. Subsequently, the semiconductor substrate (semiconductor wafer) 40 is diced (cut) to separate it into individual chips, thereby completing the silicon carbide semiconductor device 10 shown in Figures 1-3.

[0092] Figures 13 and 14 are cross-sectional views showing another stage in the manufacturing process of the silicon carbide semiconductor device according to Embodiment 1. Figures 13 and 14 show a portion of Figure 2. In the manufacturing method of the silicon carbide semiconductor device 10 according to Embodiment 1 described above, instead of epitaxially growing a p-type epitaxial layer 43 as the uppermost layer of the semiconductor substrate 40 (see Figure 7), an n-type epitaxial layer (second epitaxial layer) 44 may be epitaxially grown (see Figure 13).

[0093] Specifically, in the same manner as the manufacturing method of the silicon carbide semiconductor device 10 according to Embodiment 1 described above, n + From the preparation of the starting substrate (starting wafer) 41, n -In the portion 42a of the type epitaxial layer 42 in which the thickness has been increased, p + The process is carried out sequentially until the first part 3a of the n-type current diffusion region 23 and n-type current diffusion region 3 is formed (see Figures 4-6). Next, as shown in Figure 13, n - An n-type epitaxial layer 44 is epitaxially grown on the surface of a type-type epitaxial layer 42.

[0094] This means n + A semiconductor substrate (semiconductor wafer) 40 is completed by sequentially epitaxially growing n-type epitaxial layers 42 and 44 on the front surface of a type starting substrate 41. The n-type epitaxial layer 44 is formed by the n-type epitaxial layer below it. - p exposed on the surface of the type epitaxial layer 42 + It comes into contact with the n-type region 23 and the first portion 3a of the n-type current diffusion region 3. The impurity concentration of the n-type epitaxial layer 44 is, for example, approximately the same as the impurity concentration of the n-type current diffusion region 3.

[0095] Next, as shown in Figure 14, photolithography and ion implantation of p-type impurities were performed to create p in the depth direction Z. + A p-type base region 4 is selectively formed opposite the n-type region 23, with a depth that penetrates the n-type epitaxial layer 44. The p-type base region 4 has a box profile in which the impurity concentration is approximately uniform in the depth direction Z from the front surface of the semiconductor substrate 40 (see Figure 24). This creates a connection between the p-type base region 4 and the underlying p-type region. + Type region 23 and come into contact.

[0096] The portion of the n-type epitaxial layer 44 that remains unimplanted with ions (excluding the p-type base region 4) becomes the second portion 3b of the n-type current diffusion region 3. Subsequently, in the same manner as the manufacturing method of the silicon carbide semiconductor device 10 according to Embodiment 1 described above, n + Type source region 5 and p ++ By sequentially carrying out the processes after the formation of the type contact region 6 (see Figures 9 and 10), the silicon carbide semiconductor device 10 shown in Figures 1 to 3 is completed.

[0097] As described above, according to Embodiment 1, in a trench gate type MOSFET, both the unit cell of the MOSFET and the unit cell of the planar SBD are placed between adjacent gate trenches. As a result, since a unit cell of the MOSFET is placed between all adjacent gate trenches, the planar SBD can be embedded on the same semiconductor substrate as the MOSFET while maintaining the integration density of the MOSFET. This embedded planar SBD suppresses the degradation of the forward characteristics of the MOSFET's body diode.

[0098] Furthermore, according to Embodiment 1, by arranging both the MOSFET unit cell and the planar SBD unit cell in the same adjacent gate trench, the MOSFET unit cell and the planar SBD unit cell are in direct contact and adjacent to each other. As a result, compared to the conventional structure where the MOSFET unit cell and the planar SBD unit cell are adjacent with a gate trench in between (see Figure 26), the distance between the MOSFET body diode and the planar SBD is shortened, making it more difficult for the MOSFET body diode to conduct than in the conventional structure.

[0099] Furthermore, for example, when a trench-type SBD, in which an SBD is embedded inside a trench (hereinafter referred to as a Schottky trench), is incorporated into the same semiconductor substrate as a MOSFET, problems arise such as the Schottky trench not being completely filled with a conductive layer, resulting in voids inside the Schottky trench, and the manufacturing process becoming more complex. On the other hand, according to Embodiment 1, by incorporating a planar SBD into the same semiconductor substrate as a MOSFET, the above problems caused by the Schottky trench are avoided, and the process can be simplified compared to a trench-type SBD.

[0100] (Embodiment 2) Next, the structure of the silicon carbide semiconductor device according to Embodiment 2 will be described. Figure 15 is a plan view showing the layout of the silicon carbide semiconductor device according to Embodiment 2 as seen from the front side of the semiconductor substrate. Figure 15 shows the MOS gate of the MOSFET 61, the planar SBD 62 (Schottky contact portion 12b of the conductive layer 12), n+ Type source area 65, p ++ Type contact area 66 and p + The layout of type regions 21, 22, and 67 is shown. Figure 15 shows p + Type regions 21, 22, and 67 are shown with the same hatching.

[0101] Furthermore, Figure 15 shows the gate electrode 9, the Schottky contact portion 12b of the conductive layer 12, and p ++ Each type contact region 66 is hatched with a different hatching pattern, and p + The type regions 21, 22, and 67 are shown with different hatching. In Figure 15, n + The mold source region 65 is shown by a dashed line, and the gate insulating film 8 is omitted from the illustration. Figure 16 is a cross-sectional view showing the cross-sectional structure at the cutting line C-C' in Figure 15. The cross-sectional structure in Figure 16 is the same as in Figure 2, but with reference numeral 12a changed to reference numeral 12b. Figures 17 and 18 are cross-sectional views showing the cross-sectional structure at the cutting line D-D' in Figure 15.

[0102] The silicon carbide semiconductor device 60 according to Embodiment 2 has a p-type base region 64 of the MOSFET 61, n + Type source area 65, p ++ The layout of the type contact region 66 and the planar SBD 62 differs from that of the silicon carbide semiconductor device 10 according to Embodiment 1 (see Figure 1). Specifically, in Embodiment 2, p ++ The type contact regions 66 are scattered in the second direction Y, parallel to the gate trenches 7, approximately in the center between adjacent gate trenches 7. ++ The type contact region 66 is located away from the gate trench 7.

[0103] p adjacent to each other in the second direction Y ++ The area between the type contact regions 66 is the second part 63b of the n-type current diffusion region 63. That is, approximately in the center between adjacent gate trenches 7, p ++ The n-type contact region 66 and the second portion 63b of the n-type current diffusion region 63 are alternately and repeatedly arranged in the second direction Y. ++The width of the first direction X of the type contact region 66 may be wider than the width of the second portion 63b of the n-type current diffusion region 63. ++ The second portion 63b of the n-type contact region 66 and the n-type current diffusion region 63 may have, for example, a roughly square planar shape.

[0104] p ++ The conductive layer 11 on the front surface of the semiconductor substrate 40 is in ohmic contact with the n-type contact region 66. The conductive layer 12 on the front surface of the semiconductor substrate 40 is in Schottky contact with the second portion 63b of the n-type current diffusion region 63. Similar to Embodiment 1, the planar SBD 62 is formed by the Schottky contact portion 12b of the conductive layer 12. Therefore, when viewed from the front surface side of the semiconductor substrate 40, the planar SBD 62 is arranged in a matrix, and the MOSFET 61 is arranged in a grid surrounding the planar SBD 62.

[0105] Compared to Embodiment 1, the area (surface area) of the planar SBD62 is smaller, p ++ Since the area (surface area) of the ohmic contact between the contact region 66 and the conductive layer 11 can be increased, the avalanche resistance of the active region 51 can be improved. + The type source region 65 is gate trench 7 and p ++ Between the type contact region 66 and the gate trench 7, it extends linearly in the second direction Y, parallel to the gate trench 7, along the side wall of the gate trench 7. + The mold source region 65 is in contact with the gate insulating film 8 at the side wall of the gate trench 7.

[0106] p in the depth direction Z ++ At a position opposite the type contact region 66, similar to Embodiment 1, a p is provided to mitigate the electric field applied to the gate insulating film 8 at the bottom surface of the gate trench 7. + A mold region 67 is provided linearly in the first direction X. + The type region 67 is similar to the p in Embodiment 1. + Similar to the type region 23 (see Figure 3), the entire surface may be in contact with the p-type base region 64 (Figure 17), or the depth direction Z may be p ++The p-type base region 64 may be in contact only with the portion facing the type contact region 66 (Figure 18).

[0107] p in the depth direction Z ++ p only in the portion facing the type contact area 66 + When the p-type region 67 is in contact with the p-type base region 64 (Figure 18), the p-type base region 64 and p + The first portion 63a of the n-type current diffusion region 63 is interposed between the n-type region 67 and the p-type region 64. As a result, the n-type current diffusion region is more n-type than the p-type base region 64. + On the drain region 1 side, the entire side wall of the gate trench 7 is surrounded by the first part 63a of the n-type current diffusion region 63, p + Since the area where type region 67 is located can also be operated as a MOSFET 61, the on-resistance of MOSFET 61 is reduced.

[0108] The p-type base region 64 is the portion along the side wall of the gate trench 7, and p ++ Directly below the type contact area 66 (n + The p-type base region 64 is located on the drain region 1 side. The p-type base region 64 has a ladder-like planar shape that surrounds the second portion 63b of the n-type current diffusion region 63 between adjacent gate trenches 7. The p-type base region 64 is p ++ The area between the n-type contact region 66 and the second portion 63b of the n-type current diffusion region 63 may be exposed on the front surface of the semiconductor substrate 40.

[0109] As described above, Embodiment 2 provides the same effects as Embodiment 1. Furthermore, Embodiment 2 allows for a relative increase in the area (surface area) of the MOSFET body diode, thereby improving the avalanche withstand capability of the active region.

[0110] (Embodiment 3) Next, the structure of the silicon carbide semiconductor device according to Embodiment 3 will be described. Figure 19 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 3. The layout of the silicon carbide semiconductor device 70 according to Embodiment 3, as seen from the front side of the semiconductor substrate 40, is the same as in Figure 1. Figure 19 shows the cross-sectional structure at the cutting line A-A' in Figure 1 (n + This corresponds to the cross-sectional structure of the cross section passing through the type source region 5. p ++ The cross-sectional structure passing through the type contact region 6 is the same as in Figure 3.

[0111] The difference between the silicon carbide semiconductor device 70 according to Embodiment 3 and the silicon carbide semiconductor device 10 according to Embodiment 1 (see Figures 1-3) is that n + Directly below type source area 5 (n + In the drain region 1 side, a p-type high-concentration region 71 with a higher impurity concentration than the p-type base region 4 is provided inside the p-type base region 4. The p-type high-concentration region 71 is n + Located directly below the type source region 5, with the p-type base region 4 and n in the depth direction Z. + From the pn junction with the source region 5, a pn junction is reached between the p-type base region 4 and the first portion 3a of the n-type current diffusion region 3.

[0112] The p-type high-concentration region 71 is provided away from the side wall of the gate trench 7. Between the p-type high-concentration region 71 and the gate trench 7, a channel (n-type inversion layer) is formed adjacent to the p-type high-concentration region 71 when the MOSFET 31 is turned on. The p-type high-concentration region 71 is composed of a p-type base region 4 and an n-type + The pn junction with the p-type source region 5 and the pn junction between the p-type base region 4 and the first portion 3a of the n-type current diffusion region 3 function as so-called halo regions, suppressing the depletion layer extending into the p-type base region 4.

[0113] The manufacturing method for the silicon carbide semiconductor device 70 according to Embodiment 3 is as follows: In the manufacturing method for the silicon carbide semiconductor device 10 according to Embodiment 1 (see Figures 4-10), after the formation of the gate trench 7 and before the formation of the gate insulating film 8, p-type impurities are implanted in one or more stages (hereinafter referred to as oblique ion implantation) from oblique directions to both side walls of the gate trench 7. By providing a high-concentration p-type region 71, the thickness of the p-type epitaxial layer 43 can be reduced and the channel shortened.

[0114] Therefore, the depth of the second portion 3b of the n-type current diffusion region 3 (see Figures 7 and 8) and the p-type base region 4 (see Figures 13 and 14) can be made shallower, and the acceleration energy for ion implantation to form these regions can be lowered. Specifically, for example, with ion implantation at an acceleration energy of about 700 keV, the second portion 3b of the n-type current diffusion region 3 and the p-type base region 4 can be formed with a range of about 0.8 μm from the front surface (ion implantation surface) of the semiconductor substrate 40, having a box profile from the front surface of the semiconductor substrate 40 to a depth of about the range, and penetrating the epitaxial layers 43 and 44 in the depth direction Z.

[0115] For example, when nitrogen is ion-implanted into the p-type epitaxial layer 43 to form the second portion 3b of the n-type current diffusion region 3 (see Figures 7 and 8), the area from the front surface of the semiconductor substrate 40 to a depth of about 0.7 μm is 1 × 10⁻¹⁰ 17 / cm 3 A second portion 3b of the n-type current diffusion region 3 with a box profile and an impurity concentration of a certain degree may be formed. For example, when aluminum is ion-implanted into the n-type epitaxial layer 44 to form a p-type base region 4 (see Figures 13 and 14), the area from the front surface of the semiconductor substrate 40 to a depth of about 0.8 μm may be 1 × 10⁻⁶. 17 / cm 3 A p-type base region 4 with a box profile of a certain impurity concentration may be formed.

[0116] By applying Embodiment 3 to the silicon carbide semiconductor device according to Embodiment 2 (Figures 15-18), n +A p-type high-concentration region 71 may be provided directly below the type source region 65.

[0117] As described above, Embodiment 3 provides the same effects as Embodiments 1 and 2. Furthermore, by providing a p-type high-concentration region that forms a halo region, Embodiment 3 improves the trade-off relationship between on-resistance and short-circuit withstand capability even if the thickness of the uppermost epitaxial layer where the second portion of the n-type current diffusion region 3 and the p-type base region are formed is reduced to shorten the channel. Moreover, since Embodiment 3 allows for a reduction in the thickness of the p-type base region and the second portion of the n-type current diffusion region, high-energy (MeV) ion implantation is not required to form these regions. This prevents increased costs due to capital investment in high-energy ion implantation equipment.

[0118] For example, if the thickness of the p-type base region and the second portion of the n-type current diffusion region is thick, it is necessary to perform high-intensity ion implantation to form the p-type base region or the second portion of the n-type current diffusion region, or to deposit the epitaxial layer in multiple stages and perform ion implantation each time the p-type epitaxial layer is deposited. If the epitaxial layer is deposited in multiple stages and ion implantation is performed each time the p-type epitaxial layer is deposited, the number of steps increases. On the other hand, according to Embodiment 3, it is sufficient to deposit the epitaxial layer once and form the second portion of the p-type base region or n-type current diffusion region 3 by one or more stages (multiple times) of ion implantation at a low acceleration energy into this epitaxial layer, thus preventing an increase in the number of steps.

[0119] (Experimental Example 1) Figures 20 and 21 show the results of a simulation of the impurity concentration distribution in the second portion 3b of the n-type current diffusion region 3, which is formed in the p-type epitaxial layer 43 by ion implantation of n-type impurities according to the manufacturing method of the silicon carbide semiconductor device 10 according to Embodiment 1 (see Figures 7 and 8), for the silicon carbide semiconductor device 70 described above (hereinafter referred to as Experimental Example 1). Figure 20 is a distribution diagram showing the doping concentration distribution near the second portion of the n-type current diffusion region in Experimental Example 1. Figure 21 is a distribution diagram showing the n-type doping concentration distribution in the second portion of the n-type current diffusion region in Figure 20. In the annotations for Figure 20, the n-type impurity concentration is shown as a positive value and the p-type impurity concentration is shown as a negative value (the same applies to Figure 23).

[0120] In Experimental Example 1, the impurity concentration and thickness of the p-type epitaxial layer 43 were set to 1.3 × 10⁻⁶, respectively. 17 / cm 3 The degree and thickness were set to approximately 0.8 μm. The impurity concentration in the second part 3b of the n-type current diffusion region 3 was 1.2 × 10⁻⁶. 17 / cm 3 To achieve this, the system was configured to perform nitrogen (N) ion implantation in seven stages with different acceleration energies and doses, using an acceleration energy of 700 keV or less. The ambient temperature during this ion implantation was set to room temperature (25°C). These ion implantation conditions are shown in Figure 22. Figure 22 is a diagram showing the ion implantation conditions for n-type impurities (nitrogen) in Example 1. In Figure 22, each row shows the ion implantation conditions for one stage.

[0121] As shown in Figures 20 and 21, even if nitrogen ion implantation to form the second portion 3b of the n-type current diffusion region 3 is performed with a low acceleration energy of, for example, around 700 keV, rather than high-intensity ion implantation, the range of the second portion 3b of the n-type current diffusion region 3 to a depth of 0.7 μm from the surface of the semiconductor substrate 40 is 1 × 10⁻¹⁶ 17 / cm 3 It was confirmed that a box profile with a nearly uniform impurity concentration can be achieved to the extent described above. The relatively low impurity concentration area 72 near the front surface (ion implantation surface) of the semiconductor substrate 40 is removed by sacrificial oxidation and therefore does not remain in the final product.

[0122] (Experimental Example 2) Figures 23 and 24 show the results of a simulation of the impurity concentration distribution of the p-type base region 4 formed by ion implantation of p-type impurities into the n-type epitaxial layer 44 according to another example of the manufacturing method of the silicon carbide semiconductor device 10 according to Embodiment 1 (see Figures 13 and 14), for the silicon carbide semiconductor device 70 described above (hereinafter referred to as Experimental Example 2). Figure 23 is a distribution diagram showing the doping concentration distribution near the p-type base region in Experimental Example 2. Figure 24 is a distribution diagram showing the p-type doping concentration distribution in the p-type base region of Figure 23.

[0123] In Experimental Example 2, the impurity concentration and thickness of the n-type epitaxial layer 44 were set to 3.0 × 10⁻⁶. 16 / cm 3 The degree and size were set to approximately 0.8 μm. The impurity concentration in the p-type base region 4 was 1 × 10⁻⁶. 17 / cm 3 To achieve this, the system was configured to perform ion implantation of aluminum (Al) in eight stages with different acceleration energies and doses, using acceleration energies below 700 keV. The ambient temperature during this ion implantation was set to room temperature (500°C). These ion implantation conditions are shown in Figure 25. Figure 25 is a diagram showing the ion implantation conditions for p-type impurities (aluminum) in Example 2. In Figure 25, each row shows the ion implantation conditions for one stage.

[0124] As shown in Figures 23 and 24, even if aluminum ion implantation to form the p-type base region 4 is performed at a low acceleration energy of, for example, around 700 keV, rather than at high-intensity ion implantation, the p-type base region 4 can be implanted in a depth range of 0.7 μm from the surface of the semiconductor substrate 40 to 1 × 10⁻¹⁶ 17 / cm 3 It was confirmed that a box profile with a nearly uniform impurity concentration can be obtained to the extent described above.

[0125] Furthermore, it was confirmed that the p-type impurity concentration in the p-type base region 4 was higher than the n-type impurity concentration in the n-type epitaxial layer 44 (second portion 3b of the n-type current diffusion region 3) in the range from the front surface of the semiconductor substrate 40 (surface of the n-type epitaxial layer 44) to a depth of 0.8 μm. The relatively low impurity concentration in the portion 73 near the front surface (ion implantation surface) of the semiconductor substrate 40 is removed by sacrificial oxidation and therefore does not remain in the final product.

[0126] As described above, the present invention can be modified in various ways without departing from the spirit of the invention, and in the embodiments and examples described above, for example, the dimensions of each part, the impurity concentration, etc., can be set in various ways according to the required specifications. Furthermore, the present invention will produce the same effects when applied to wide bandgap semiconductors other than silicon carbide (for example, gallium (Ga)). Furthermore, the present invention will also hold true when the conductivity type (n-type, p-type) is reversed. [Industrial applicability]

[0127] As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention are suitable for trench gate structure MOSFETs with a planar SBD embedded in the same semiconductor substrate. [Explanation of Symbols]

[0128] 1 n + Type drain region 2 n - Type drift region 3 n-type current diffusion region 3a n-type current diffusion region, first part 3b Second part of the n-type current diffusion region 4.64 p-type base region 5.65 n + Type source area 6,66 p ++ Type Contact Area 7 Gate Trench 8 gate insulating film 9. Postal Service 10,60,70 Silicon Carbide Semiconductor Devices 11,12 Conductive layer 11a Nickel film 12a, 12b Schottky contact area between the conductive layer and the semiconductor substrate 13 Interlayer insulating film 13a Contact Hole 14 Front surface electrodes 15 Backside electrode pp. 21-23, 67 + type area 31,61 MOSFET 32,62 Planar SBD 40 Semiconductor substrates 41 n + Mold starting substrate 42 n - Type epitaxial layer 42a n - Part with increased thickness of the type epitaxial layer 43 p-type epitaxial layer 44 n-type epitaxial layer 51 Active area 52 Edge Termination Region 71 p-type high concentration region 72. Parts removed by sacrificial oxidation of the p-type epitaxial layer 73. Parts removed by sacrificial oxidation of the n-type epitaxial layer d1 Distance between the MOSFET body diode and the planar SBD X First direction parallel to the front surface of the semiconductor substrate Y: A second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction. Z-direction (depth)

Claims

1. A semiconductor substrate made of silicon carbide, A first semiconductor region of a first conductivity type provided inside the semiconductor substrate, A second semiconductor region of a second conductivity type is selectively provided between the front surface of the semiconductor substrate and the first semiconductor region, A third semiconductor region of a first conductivity type is selectively provided between the front surface of the semiconductor substrate and the second semiconductor region, A plurality of trenches that penetrate the third semiconductor region and the second semiconductor region and reach the first semiconductor region, A gate electrode is provided inside the trench via a gate insulating film, A first conductive film is provided on the front surface of the semiconductor substrate and makes ohmic contact with the second semiconductor region and the third semiconductor region, A first electrode is provided on the front surface of the semiconductor substrate and connected to the first conductive film, A second electrode provided on the back surface of the semiconductor substrate, A first high-concentration region of a second conductivity type is selectively provided on the second electrode side of the trench, separated from the second semiconductor region, and facing the trench bottom surface in the depth direction. A second high-concentration region of a second conductivity type is selectively provided on the second electrode side of the bottom surface of the trench, away from the trench, the second semiconductor region, and the first high-concentration region, Equipped with, The first semiconductor region is, Between adjacent trenches, a first portion reaches the side wall of the trench in a direction parallel to the front surface of the semiconductor substrate, on the second electrode side of the second semiconductor region, Between adjacent trenches, a second portion reaches the surface of the semiconductor substrate at a position in the depth direction opposite to the second high-density region, is exposed to the surface of the semiconductor substrate, and is surrounded by the second semiconductor region. A second conductive film is provided on the front surface of the semiconductor substrate, making Schottky contact with the second portion and connected to the first electrode, A Schottky barrier diode is provided, which utilizes the rectification properties of a Schottky barrier formed at the junction surface between the second conductive film and the first semiconductor region. The multiple trenches extend in a stripe-like pattern in a direction parallel to the front surface of the semiconductor substrate, The third semiconductor region is positioned between the adjacent second portions and the trench. A silicon carbide semiconductor device characterized in that, of the second semiconductor region, the third portion that makes ohmic contact with the first conductive film on the front surface of the semiconductor substrate is dotted in a direction in which the trenches extend in a stripe-like pattern.

2. The second semiconductor region is a second conductivity type epitaxial layer, The silicon carbide semiconductor device according to claim 1, characterized in that the second portion is a first conductivity type diffusion region formed by introducing a first conductivity type impurity into the second conductivity type epitaxial layer.

3. The second portion is a first conductive epitaxial layer, The silicon carbide semiconductor device according to claim 1, characterized in that the second semiconductor region is a second conductivity type diffusion region formed by introducing a second conductivity type impurity into the first conductivity type epitaxial layer.

4. The silicon carbide semiconductor device according to any one of claims 1 to 3, further comprising a second conductivity type halo region extending in the depth direction from the pn junction between the second semiconductor region and the third semiconductor region to the pn junction between the second semiconductor region and the first portion.

5. The third portion is a fourth semiconductor region of the second semiconductor region with a higher impurity concentration than the portion of the second semiconductor region excluding the third portion. The silicon carbide semiconductor device according to any one of claims 1 to 4, characterized in that the fourth semiconductor region and the third semiconductor region are alternately and repeatedly arranged in a direction in which the trench extends in a stripe-like manner.

6. The third portion is a fourth semiconductor region of the second semiconductor region with a higher impurity concentration than the portion of the second semiconductor region excluding the third portion. The silicon carbide semiconductor device according to any one of claims 1 to 4, characterized in that the fourth semiconductor region and the second portion are alternately and repeatedly arranged in a direction in which the trench extends in a stripe-like manner.

7. The silicon carbide semiconductor device according to claim 5, further comprising a third high-concentration region of a second conductivity type, provided in contact with the second semiconductor region, the first high-concentration region and the second high-concentration region, on the second electrode side of the trench and facing the fourth semiconductor region in the depth direction, and extending to the side wall of the trench in a direction parallel to the front surface of the semiconductor substrate on the second electrode side of the second semiconductor region.

8. The silicon carbide semiconductor device according to claim 6, further comprising a third high-concentration region of a second conductivity type, provided in contact with the second semiconductor region, the first high-concentration region and the second high-concentration region, and separated from the trench, at a position on the second electrode side of the bottom surface of the trench and facing the fourth semiconductor region in the depth direction.

9. The second portion is 1 × 10¹⁶ in depth from the front surface of the semiconductor substrate to a depth of 0.7 μm. 17 / cm 3 The silicon carbide semiconductor device according to claim 2, characterized in that the first conductivity type impurity concentration has a uniform box profile.

10. The second semiconductor region is 1 × 10¹⁶ in depth from the front surface of the semiconductor substrate to a depth of 0.7 μm. 17 / cm 3 The silicon carbide semiconductor device according to claim 3, characterized in that the second conductivity type impurity concentration has a uniform box profile.

11. The silicon carbide semiconductor device according to claim 10, characterized in that the second semiconductor region has a second conductivity type impurity concentration higher than the first conductivity type impurity concentration in the second portion in a depth range of 0.8 μm from the front surface of the semiconductor substrate.

12. The silicon carbide semiconductor device according to any one of claims 1 to 10, characterized in that the first semiconductor region has a higher impurity concentration in the first portion and the second portion than in other portions of the first semiconductor region.

13. A method for manufacturing a vertical silicon carbide semiconductor device with a trench gate structure, A first step involves growing a first epitaxial layer of a first conductivity type on the front surface of a starting substrate made of silicon carbide, A second step involves selectively forming a high-concentration region of the second conductivity type in the first epitaxial layer by first ion implantation of a second conductivity type impurity, thereby mitigating the electric field applied to the bottom surface of the trenches constituting the trench gate structure, and making the portion of the first epitaxial layer excluding the high-concentration region of the second conductivity type a first portion of the first semiconductor region of the first conductivity type. A fourth step is to grow a second epitaxial layer on the surface of the first epitaxial layer, after the second step described above. A fifth step of selectively forming a second portion of the first semiconductor region connected to the first portion of the first semiconductor region, and a second semiconductor region of a second conductivity type surrounding the second portion, in the second epitaxial layer. A sixth step in which a third semiconductor region of a first conductivity type and a fourth semiconductor region of a second conductivity type with a higher impurity concentration than the second semiconductor region are selectively formed on the surface region of the second semiconductor region. A seventh step of forming a plurality of trenches that penetrate the third semiconductor region and the second semiconductor region to reach the first epitaxial layer and extend in a stripe-like manner in a direction parallel to the surface of the second epitaxial layer, An eighth step involves ion implantation of a second conductivity type impurity from the side wall of the trench to form a second conductivity type halo region that extends in the depth direction from the pn junction between the second semiconductor region and the third semiconductor region to the pn junction between the second semiconductor region and the first portion, After the eighth step, a ninth step is to form a gate electrode inside the trench via a gate insulating film, A tenth step is to form a first conductive film on the surface of the second epitaxial layer that makes ohmic contact with the third semiconductor region and the fourth semiconductor region, after the ninth step described above. A 11th step is to form a Schottky barrier diode by forming a second conductive film on the surface of the second epitaxial layer that makes Schottky contact with the second portion, thereby utilizing the rectification properties of the Schottky barrier formed at the junction between the second conductive film and the first semiconductor region. A 12th step involves forming the first conductive film and a first electrode connected to the second conductive film on the surface of the second epitaxial layer, A 13th step involves forming a second electrode on the back surface of the starting substrate, Includes, In the second step described above, Within the first epitaxial layer, in the trench formation region, a first high-concentration region of the second conductivity type is selectively formed as the second high-concentration region, extending to a position deeper than the trench. Furthermore, within the first epitaxial layer, between adjacent trench formation regions, a second high-concentration region of a second conductivity type is selectively formed, separated from the first high-concentration region and reaching a position deeper than the trench. In the fourth step described above, the second epitaxial layer of the second conductivity type is grown, In the fifth step, by ion implantation of a first conductivity type with an acceleration energy of 700 keV or less, the second portion is formed in the depth direction in the portion facing the second high-concentration region, and the portion of the second epitaxial layer excluding the second portion is made the second semiconductor region. Alternatively, in the fourth step, the second epitaxial layer of the first conductivity type is grown, In the fifth step, the second semiconductor region penetrating the second epitaxial layer in the depth direction is formed by ion implantation of a second conductivity type with an acceleration energy of 700 keV or less, and the portion of the second epitaxial layer excluding the second semiconductor region and facing the second high-concentration region in the depth direction is defined as the second portion. A method for manufacturing a silicon carbide semiconductor device, characterized in that, in the sixth step, the third semiconductor region is formed between the adjacent second portions and the trench formation region, and the fourth semiconductor region is formed which is scattered in the direction in which the trench formation region extends in a stripe-like manner.

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