Silicon carbide semiconductor device and method for manufacturing a silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device capable of achieving a high breakdown voltage and lower resistance by shortening a cell pitch and a method for manufacturing the silicon carbide semiconductor device.SOLUTION: A silicon carbide semiconductor device 10 comprises: a silicon carbide semiconductor substrate 11 of a first conductivity type; a first semiconductor layer 12 of the first conductivity type; a second semiconductor layer 13 of a second conductivity type; a first semiconductor region 14 of the first conductivity type; a trench 16; a gate insulation film 17; a gate electrode 18; a first high-concentration region 21 of the second conductivity type provided in a position facing the trench 16 in a depth direction; second high-concentration regions 15 and 22 of the second conductivity type in contact with the first semiconductor region 14 selectively provided between trenches 16, the upper surface thereof exposed to a surface of the second semiconductor layer 13 and a part of the lower surface thereof in contact with an upper surface of the first high concentration region 21; a first electrode 44; and a second electrode 45. The second high-concentration regions 15 and 22 are periodically arranged in a depth direction of the trench 16.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] This invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device. [Background technology]

[0002] Silicon carbide (SiC) is expected to be the next-generation semiconductor material to replace silicon (Si). Semiconductor devices using silicon carbide as the semiconductor material (hereinafter referred to as silicon carbide semiconductor devices) have various advantages compared to conventional semiconductor devices using silicon as the semiconductor material, such as being able to reduce the resistance of the device in the ON state to a fraction of that of silicon, and being usable in environments with higher temperatures (above 200°C). This is due to the inherent characteristics of the material itself, such as the fact that the band gap of silicon is about three times larger than that of silicon, and the dielectric breakdown field strength is nearly an order of magnitude greater than that of silicon.

[0003] To date, silicon carbide semiconductor devices that have been commercialized include Schottky barrier diodes (SBDs) and vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) with planar gate or trench gate structures.

[0004] A planar gate structure is a MOS gate structure in which a MOS gate is provided in a flat plate shape on the front surface of a semiconductor substrate. A trench gate structure is a MOS gate structure in which a MOS gate is embedded in a trench formed on the front surface of a semiconductor substrate (semiconductor chip), and a channel (inversion layer) is formed along the side wall of the trench in a direction perpendicular to the front surface of the semiconductor substrate. Therefore, compared to a planar gate structure in which the channel is formed along the front surface of the semiconductor substrate, the unit cell (elementary component) density per unit area can be increased, and the current density per unit area can be increased, making it advantageous in terms of cost.

[0005] FIG. 14 is a cross-sectional view taken along line A-A' of FIG. 16 showing the structure of a conventional silicon carbide semiconductor device. FIG. 15 is a cross-sectional view taken along line B-B' of FIG. 16 showing the structure of a conventional silicon carbide semiconductor device. FIG. 16 is a plan view showing the structure of a conventional silicon carbide semiconductor device. The conventional silicon carbide semiconductor device 110 shown in FIGS. 14 and 15 is a vertical MOSFET having a trench gate structure on a semiconductor substrate (semiconductor chip) 140 made of silicon carbide. In FIGS. 14 and 15, only the active region is shown, and the edge termination region is omitted.

[0006] The semiconductor substrate 140 is made of n-type + starting substrate 141, on the front surface of which an n-type - silicon carbide layer 142 to serve as an n-type drift region 112 is epitaxially grown. The semiconductor substrate 140 has a main surface on the n-type - silicon carbide layer 142 side as a front surface, and a main surface on the n-type - starting substrate 141 side as a back surface. A drain electrode 145 is provided over the entire back surface of the semiconductor substrate 140 (the back surface of the n-type + starting substrate 141). The n-type + starting substrate 141 is an n-type + drain region 111. +

[0007] An n-type - current spreading region 120 is provided on the surface side of the n-type drift region 112 opposite to the n-type + silicon carbide substrate 111 side. In the surface layer of the n-type current spreading region 120, between trenches 116, a p-type + region 122 composed of a lower p-type region portion 123 and an upper p-type region portion 124 is selectively provided. Further, in the n-type current spreading region 120, a p-type + region 121 is selectively provided at a position facing the bottom of the trench 116 in the depth direction. The MOS gate of the trench gate structure is composed of a p-type base region 113, an n-type + source region 114, a p-type + contact region 115, a trench 116, a gate insulating film 117, and a gate electrode 118. + ++ ​​​

[0008] Furthermore, an interlayer insulating film 119 is provided on the gate electrode 118, and an opening in the interlayer insulating film 119 is provided with n + Type source region 114 and p ++ An ohmic electrode 143 is provided in contact with the type contact region 115. A barrier metal 138 is provided on the ohmic electrode 143 and the interlayer insulating film 119 to prevent the diffusion of metal atoms toward the gate electrode 118. A source electrode 144 is provided on the barrier metal 138.

[0009] p + The n-type regions 121 and 122 are fixed at the potential of the source electrode 144 and have the function of depleting (or depleting the n-type current diffusion region 120, or both) when the MOSFET (silicon carbide semiconductor device 110) is off, thereby mitigating the electric field applied to the gate insulating film 117 below the trench 116. + The mold region 121 is provided separately from the p-type base region 113 and faces the bottom surface of the trench 116 in the depth direction. + Type region 121 is p ++ A deep p-type structure is created beneath the contact region 115, at a location separate from the trench 116, to prevent current from flowing beneath the trench 116 during avalanche generation and to prevent the potential beneath the trench 116 from rising. Also, as shown in Figure 16, p + Type region 121 is p + The source electrode 144 is electrically connected by being periodically connected in the depth direction to the mold region 123. Figure 14 shows p + Type region 121 and p + Figure 15 is a cross-sectional view of the portion where the mold region 123 is not connected, and p + Type region 121 and p + This is a cross-sectional view of the portion where the mold regions 123 are connected. + The mold region 122 is in contact with the p-type base region 113 on its upper surface and is electrically connected to the source electrode 144 via the p-type base region 113.

[0010] Furthermore, a semiconductor device is known in which an electric field blocking layer perpendicular to the trench is provided below the trench, and the electric field blocking layer is electrically connected to a p-type base region by a p-type deep layer (see, for example, Patent Document 1 below). Furthermore, a semiconductor device is known in which a plurality of linear p-type deep layers extending in a first direction inclined at 45 degrees with respect to the longitudinal direction of the trench are arranged at equal intervals below the trench, and a plurality of linear p-type deep layers extending in a second direction inclined at 45 degrees with respect to the longitudinal direction of the trench and perpendicular to the first direction are arranged at equal intervals, and the p-type deep layers are electrically connected to a p-type base region (see, for example, Patent Document 2 below). Furthermore, a semiconductor device is known in which a trench having a striped planar pattern is provided, the base region is periodically provided in a direction parallel to the trench, and at the bottom of the trench, a part of the base region extends in a direction parallel to the trench, and the base regions are connected to each other (see, for example, Patent Document 3 below). Furthermore, a semiconductor device is known that comprises a carrier transport layer of a first conductivity type, an injection control region of a second conductivity type provided on the upper surface of the carrier transport layer, a carrier supply region of the first conductivity type provided above the injection control region, a base contact region of the second conductivity type provided above the injection control region, a trench penetrating the injection control region and reaching the carrier transport layer, an upper embedding region of the second conductivity type in contact with the lower surface of the injection control region, and a lower embedding region of the second conductivity type in contact with the lower surface of the upper embedding region and the bottom surface of the trench, wherein the lower embedding regions are separated from each other between the trenches via the carrier transport layer (see, for example, Patent Document 4 below). [Prior art documents] [Patent Documents]

[0011] [Patent Document 1] Japanese Patent Publication No. 2020-120072 [Patent Document 2] Patent No. 4640439 [Patent Document 3] Patent No. 6848382 [Patent Document 4] International Publication No. 2022 / 137789 [Overview of the project] [Problems that the invention aims to solve]

[0012] However, in conventional silicon carbide semiconductor devices, the structure of each cell is complex, making it difficult to shorten the cell pitch. Therefore, it is particularly difficult to reduce resistance in SiC, which has low channel mobility. In addition, the complex structure results in a narrow p-type region at the pn junction, which makes electric field concentration more likely and leads to a decrease in breakdown voltage.

[0013] On the other hand, in order to reduce resistance, p in the depth direction + Type region 121 and p + Reducing the number of connections to type region 122 reduces the p below trench 116. + In type region 121, p is connected to source electrode 144. ++ Part far from the contact area 115 to form This can occur, and if a high current is passed through the built-in pn diode, there is a risk that a large load will be placed on the gate insulating film 117.

[0014] The purpose of this invention is to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that can achieve high voltage resistance and low resistance by shortening the cell pitch, in order to solve the problems of the conventional technology described above. [Means for solving the problem]

[0015] To solve the above-mentioned problems and achieve the objectives of the present invention, the silicon carbide semiconductor device according to this invention has the following features: A first semiconductor layer of a first conductivity type with a lower impurity concentration than that of the silicon carbide semiconductor substrate is provided on the front surface of a first conductivity type silicon carbide semiconductor substrate. A second semiconductor layer of a second conductivity type is provided on the surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate. A first semiconductor region of a first conductivity type is selectively provided on the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate. A trench is provided that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer. A gate electrode is provided inside the trench via a gate insulating film. A first high-concentration region of a second conductivity type is provided inside the first semiconductor layer at a position opposite to the trench in the depth direction. A second high-concentration region of a second conductivity type is selectively provided between the trenches inside the first semiconductor layer and the second semiconductor layer, in contact with the first semiconductor region, with its upper surface exposed to the surface of the second semiconductor layer and a portion of its lower surface in contact with the upper surface of the first high-concentration region. A first electrode is provided on the surface of the second high-concentration region and the first semiconductor region. A second electrode is provided on the back surface of the silicon carbide semiconductor substrate. The second high-concentration region is located in the trench. This is the longitudinal direction when viewed from above. They are arranged periodically in the depth direction.

[0016] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the second high-concentration region is composed of an upper second high-concentration region on the first electrode side and a lower second high-concentration region on the second electrode side, and the upper second high-concentration region has a higher impurity concentration than the lower second high-concentration region.

[0017] Furthermore, the silicon carbide semiconductor device according to this invention, in the above-described invention, the second high-concentration region , in the direction adjacent to the aforementioned first high-concentration region The width is characterized by being wider than the distance between adjacent first high-concentration regions. Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the second high-concentration region is arranged spaced apart from the trench.

[0018] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the first high-concentration region is in contact with the bottom of the trench, the peak of the impurity concentration is in the central part, and the bottom of the trench is located on the first electrode side of the peak of the impurity concentration in the first high-concentration region.

[0019] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the above-described invention, a third high-concentration region of a second conductivity type is selectively provided in a region where the second high-concentration region is not provided, connecting adjacent first high-concentration regions.

[0020] Furthermore, the silicon carbide semiconductor device according to the present invention is characterized in that, in the region where the second high-concentration region is not provided, a fourth high-concentration region of a second conductivity type with a higher impurity concentration than the second semiconductor layer is selectively provided on the surface of the first semiconductor layer between adjacent first high-concentration regions, on the surface opposite to the silicon carbide semiconductor substrate side.

[0021] To solve the above-mentioned problems and achieve the objectives of the present invention, the method for manufacturing a silicon carbide semiconductor device according to this invention has the following features. First, a first step is performed in which a first semiconductor layer of the first conductivity type with a lower impurity concentration than that of the silicon carbide semiconductor substrate is formed on the front surface of the first conductivity type silicon carbide semiconductor substrate. Next, a first semiconductor layer is formed on the surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side. 2A second step is performed to form a conductive second semiconductor layer. Next, a third step is performed to form a first high-concentration region of the second conductivity type inside the first semiconductor layer. Next, a fourth step is performed to selectively form a second high-concentration region of the second conductivity type inside the first and second semiconductor layers, such that the upper surface is exposed to the surface of the second semiconductor layer and a portion of the lower surface is in contact with the upper surface of the first high-concentration region. Next, a fifth step is performed to selectively form a first semiconductor region of the first conductivity type on the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side. Next, a sixth step is performed to form a trench that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer. Next, a gate electrode is formed inside the trench via a gate insulating film. 7 The process is carried out. Next, the first electrode is formed on the surface of the second high-concentration region and the first semiconductor region. 8 The process is carried out. Next, a second electrode is formed on the back surface of the silicon carbide semiconductor substrate. 9 The process is carried out. In the third step, the first high-concentration region is formed at a position opposite the trench in the depth direction, and in the fourth step, the second high-concentration region is in contact with the first semiconductor region, and between the trenches, the trench This is the longitudinal direction when viewed from above. It is formed periodically in the depth direction. Furthermore, the method for manufacturing a silicon carbide semiconductor device according to this invention is characterized in that, in the above-described invention, the fourth step comprises the second high-concentration region being composed of an upper second high-concentration region on the first electrode side and a lower second high-concentration region on the second electrode side, and the impurity concentration of the upper second high-concentration region being higher than the impurity concentration of the lower second high-concentration region. Furthermore, the method for manufacturing a silicon carbide semiconductor device according to this invention is characterized in that, in the above-described invention, it further includes a tenth step of selectively forming a third high-concentration region of a second conductivity type connecting adjacent first high-concentration regions in a region within the first semiconductor layer where the second high-concentration region is not provided. Furthermore, the method for manufacturing a silicon carbide semiconductor device according to this invention is characterized in that, in the above-described invention, it further includes a tenth step of selectively forming a fourth high-concentration region of a second conductivity type having a higher impurity concentration than the second semiconductor layer on the surface of the first semiconductor layer between adjacent first high-concentration regions on the side opposite to the silicon carbide semiconductor substrate side, in a region within the second semiconductor layer where the second high-concentration region is not provided.

[0022] According to the invention described above, p below the trench + p between trenches provided at the same depth as the type region (first high-concentration region of the second conductivity type) + The type region is eliminated, and the bottom surface is p + It is in contact with a part of the upper surface of the type region, and the upper surface is p ++ p in contact with the type contact region (upper second high-density region) + A type region (lower second high-concentration region) is provided, p + Type domain and p ++ It connects to the type contact region. This simplifies the structure per cell and shortens the cell pitch, enabling low resistance in SiCMOSFETs with low channel mobility. Furthermore, the p below the trench +The width of the mold region can be increased, and the flat portion of the pn junction can be widened, which reduces electric field concentration and increases the breakdown voltage. + By widening the mold region, the current path through the JFET becomes longer, which suppresses the saturation current and improves the short-circuit withstand capability. [Effects of the Invention]

[0023] According to the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device of the present invention, the cell pitch can be shortened to achieve high voltage resistance and low resistance. [Brief explanation of the drawing]

[0024] [Figure 1] This is a cross-sectional view taken along line A-A' in Figure 3A, showing the structure of a silicon carbide semiconductor device according to Embodiment 1. [Figure 2] This is a cross-sectional view taken along line B-B' in Figure 3A, showing the structure of a silicon carbide semiconductor device according to Embodiment 1. [Figure 3A] This is a perspective view showing the structure of a silicon carbide semiconductor device according to Embodiment 1. [Figure 3B] This is a top view of the silicon carbide semiconductor device according to Embodiment 1, in which p+ type regions and p++ type contact regions are arranged alternately. [Figure 4] This is a cross-sectional view (part 1) showing the state of a silicon carbide semiconductor device during the manufacturing process according to Embodiment 1. [Figure 5] This is a cross-sectional view (part 2) showing the silicon carbide semiconductor device according to Embodiment 1 in the process of manufacturing. [Figure 6] This is a cross-sectional view (part 3) showing the silicon carbide semiconductor device in the process of being manufactured according to Embodiment 1. [Figure 7] This is a cross-sectional view (part 4) showing the silicon carbide semiconductor device according to Embodiment 1 in the process of manufacturing. [Figure 8] This is a cross-sectional view taken along line A-A' in Figure 9, showing the structure of a silicon carbide semiconductor device according to Embodiment 2. [Figure 9] This is a perspective view showing the structure of a silicon carbide semiconductor device according to Embodiment 2. [Figure 10] This is a perspective view showing the impurity concentration distribution of the silicon carbide semiconductor device according to Embodiment 1. [Figure 11] This is a perspective view showing the impurity concentration distribution of the silicon carbide semiconductor device according to Embodiment 2. [Figure 12] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 3. [Figure 13] This is a perspective view showing the impurity concentration distribution of the silicon carbide semiconductor device according to Embodiment 3. [Figure 14] This is a cross-sectional view taken along line A-A' in Figure 16, showing the structure of a conventional silicon carbide semiconductor device. [Figure 15] This is a cross-sectional view taken along line B-B' in Figure 16, showing the structure of a conventional silicon carbide semiconductor device. [Figure 16] This is a plan view showing the structure of a conventional silicon carbide semiconductor device. [Modes for carrying out the invention]

[0025] Preferred embodiments of the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the attached drawings. In this specification and the attached drawings, layers or regions prefixed with n or p mean that electrons or holes are the majority carriers, respectively. Furthermore, the + and - prefixes to n and p mean that they have a higher and lower impurity concentration than layers or regions without them, respectively. In the following description of embodiments and attached drawings, the same reference numerals are used for similar components, and redundant explanations are omitted. In this specification, in the notation of Miller indices, "-" means a bar attached to the exponent immediately following it, and a "-" before the exponent indicates a negative exponent. Furthermore, it is preferable to include up to 5% in the description of being the same or equivalent, taking into account manufacturing variations.

[0026] (Embodiment 1) The structure of the silicon carbide semiconductor device according to Embodiment 1 will now be described. Figure 1 is a cross-sectional view taken along line A-A' of Figure 3A showing the structure of the silicon carbide semiconductor device according to Embodiment 1. Figure 2 is a cross-sectional view taken along line B-B' of Figure 3A showing the structure of the silicon carbide semiconductor device according to Embodiment 1. Figure 3A is a perspective view showing the structure of the silicon carbide semiconductor device according to Embodiment 1. The silicon carbide semiconductor device 10 according to Embodiment 1 shown in Figures 1 to 3A is a vertical MOSFET equipped with a trench gate structure on a semiconductor substrate (semiconductor chip) 40 made of silicon carbide (SiC).

[0027] Figures 1 to 3A show only the active region where current flows when the device is ON, and omit the depiction of the edge termination region, which is enclosed in a roughly rectangular shape around the active region and where the breakdown voltage structure is located. The breakdown voltage structure has the function of maintaining the breakdown voltage by mitigating the electric field near the boundary between the active region and the edge termination region. Breakdown voltage is the limit voltage at which the drain-source voltage does not increase further even if the drain-source current increases due to avalanche breakdown in the pn junction.

[0028] Multiple unit cells (functional units of the element) of the same structure (element structure) of the MOSFET are arranged adjacent to each other on the semiconductor substrate 40. The semiconductor substrate 40 is made of n + n - n becomes a type drift region (first semiconductor layer of the first conductivity type) 12 - The semiconductor substrate 40 is formed by epitaxially growing a silicon carbide layer 42. - The main surface on the side of the silicon carbide layer 42 is designated as the front surface (first main surface), n + The main surface on the mold starting substrate 41 side is designated as the back surface (second main surface).

[0029] n + The starting substrate 41 is n + This is a type drain region 11. When the semiconductor substrate 40 forms each part of the active region, n - n is in the drift region 12. - The silicon carbide layer 42 is formed by sequentially growing multiple layers epitaxially. -The drift region 12 is n - This is the portion of the silicon carbide layer 42 where the impurity concentration remains the same as during epitaxial growth, without the formation of a diffusion region due to ion implantation. - The drift region 12 is n + It is in contact with the mold starting substrate 41 and is provided extending from the active region to the tip edge. - The type silicon carbide layer 42 is formed by a single-stage epitaxial growth, with a p-type base region 13, n + Type source area 14, p ++ Type 15 contact region, n-type current diffusion region 20 and p + The mold regions 21 and 22 may be formed by ion implantation.

[0030] The active region of Embodiment 1 is provided with a trench gate structure. The trench gate structure consists of a p-type base region (second semiconductor layer of the second conductivity type) 13, n + Type source region (first semiconductor region of the first conductivity type) 14, p ++ It consists of a p-type contact region (second high-concentration region of the second conductivity type, upper second high-concentration region) 15, a trench 16, a gate insulating film 17, and a gate electrode 18. + Type source region 14 and p ++ The contact area 15 is n - This is a diffusion region formed by ion implantation inside the type silicon carbide layer 42. The p-type base region 13 is formed between the front surface of the semiconductor substrate 40 and n - It is provided throughout the entire area between the type drift region 12 and the surrounding area.

[0031] n + Type source region 14 and p ++ The type contact region 15 is selectively provided between the front surface of the semiconductor substrate 40 and the p-type base region 13, and contacts the p-type base region 13 at its bottom (bottom surface: the back edge of the semiconductor substrate 40). + Type source region 14 is p ++ It is provided in contact with the type contact area 15. + Type source region 14 and p ++The contact area 15 makes ohmic contact with the ohmic electrode 43 on its upper surface (the front edge of the semiconductor substrate 40).

[0032] n - Between the p-type drift region 12 and the p-type base region 13, n is greater than the bottom surface of the trench 16. + Deep within the drain region 11 side (back side of the semiconductor substrate 40), there are n-type current diffusion regions 20 and p + Type region (first high-concentration region of the second conductivity type) 21, p + Type regions (second high-concentration region of second conductivity type, lower second high-concentration region) 22 are selectively provided. n-type current diffusion region 20 and p + Type regions 21 and 22 are n - This is a diffusion region formed by ion implantation inside the n-type silicon carbide layer 42. The n-type current diffusion region 20 is p + n is more n than type regions 21 and 22. + It is preferable that the drain region 11 reaches a deep position.

[0033] The n-type current spreading region 20 is a so-called current spreading layer (CSL) that reduces the carrier spreading resistance. The n-type current spreading region 20 is p + Between the type regions 21 and 22, it is in contact with these regions and extends in a direction parallel to the front surface of the semiconductor substrate 40, reaching the trench 16 and contacting the gate insulating film 17. The n-type current diffusion region 20 is in contact with the p-type base region 13 at its upper surface and at its bottom n - It is in contact with the drift region 12.

[0034] The n-type current diffusion region 20 does not need to be provided. If the n-type current diffusion region 20 is not provided, instead of the n-type current diffusion region 20, - The type drift region 12 reaches the p-type base region 13, and the p-type base region 13 and p + The elements are in contact with the mold regions 21 and 22, and extend to the trench 16 in a direction parallel to the front surface of the semiconductor substrate 40, and are in contact with the gate insulating film 17.

[0035] p +The type regions 21 and 22 are fixed to the potential of a source electrode 44 described later, and have a function of depleting when the MOSFET (silicon carbide semiconductor device 10) is turned off (or depleting the n-type current diffusion region 20, or both) to relax the electric field applied to the gate insulating film 17. p + The type region 21 is provided separately from the p-type base region 13, and faces the bottom surface of the trench 16 in the depth direction. p + The type region 21 is p + It is electrically connected to the source electrode 44 by being partially coupled to the type region 22. FIG. 1 shows p + a cross-section of a portion where the type region 22 is not provided, and FIG. 2 shows p + where the type region 22 is provided, p + a cross-section of a portion where the type region 22 and p + the type region 21 are coupled.

[0036] p + the type region 21 may be in contact with the gate insulating film 17 at the bottom surface of the trench 16, or may be separated from the bottom surface of the trench 16. p + the width of the type region 21 is equal to or wider than the width of the trench 16. For example, p + the width of the type region 21 is preferably at least twice as wide as the width of the trench 16. p + by making the width of the type region 21 wider than the width of the trench 16, p + the type region 21 also faces the bottom corner portion (the boundary between the side wall and the bottom surface) of the trench 16 in the depth direction. Thereby, p + the electric field relaxation effect in the vicinity of the bottom surface of the trench 16 by the type region 21 is further enhanced.

[0037] p + the type region 22 is p + a region connecting the type region 21 and p ++ the type contact region 15, and is provided separately from the trenches 16 at the center between adjacent trenches 16. p + the type region 22 is in contact with p ++ the type contact region 15 at an upper surface thereof, and p ++ is electrically connected to the source electrode 44 via the type contact region 15. p+ The type region 22 is provided for connection, so p + The impurity concentration may be lower than that in the type region 21.

[0038] p + Type region 22 is p ++ It has the same width as the contact area 15. + The depth of type region 22 is p + Shallower than type region 21, p + The lower surface of type region 22 is p + At the same depth as the top surface of the mold region 21 (the front edge of the semiconductor substrate 40), p + The lower surface of the mold region 22 (the back edge of the semiconductor substrate 40) is p + It is in contact with a portion of the upper surface of the mold region 21.

[0039] Thus, in this invention, p + p between the trenches 16, which are provided at the same depth as the mold region 21 + Type region (conventional structure p + The type region 122 (see Figures 14 and 15) is eliminated, and the JFET structure per cell (the structure of the part where current escapes between the trenches 16) is unified. Furthermore, p + Type region 21 and p ++ The connection with the type contact area 15 is a deep p in the center between the trenches 16. + This is achieved by creating type region 22.

[0040] In Figure 3A, only one is shown between the trenches 16, p ++ The contact area 15 is the trench 16 This is the longitudinal direction when viewed from above. In the depth direction, they are arranged in a periodically striped structure, p + Type region 22 is p ++ The type contact region 15 is arranged periodically in a stripe structure in the region where it is located. In Figure 3A, in the B-B' section, p + Type region 22 and p ++ Although type contact regions 15 are arranged, their arrangement may be alternating. Figure 3B shows a silicon carbide semiconductor device according to Embodiment 1. + Type region and p ++This is a top view when the type contact regions are arranged alternately. As shown in Figure 3B, p + Type region 22B and p ++ A type contact region 15B is positioned, and p between the trenches 16 in the A-A' section + Type regions 22A, C and p ++ Type contact areas 15A and 15C may be provided.

[0041] For example, p + The width L1 of the type region 21 is 1.1 to 2.3 μm, and p + The distance L2 between type regions 21 is 0.3 to 1.5 μm, and p + The distance L3 between the upper surface of the mold region 21 and the lower surface of the p-type base region 13 is 0.1 to 0.5 μm. Also, the thickness L4 of the p-type base region 13 is 0.2 to 0.5 μm, n + The thickness L5 of the mold source region 14 is 0.1 to 0.5 μm. The cell pitch L6 (distance between the centers of the trenches 16) is approximately 2.6 μm. Also, p + The width L7 of the type region 22 is 1.0 to 1.6 μm, and p + The length L8 in the depth direction of the mold region 22 is 0.8 to 4.5 μm, and p + The spacing L9 in the depth direction of the mold region 22 is 1.0 μm or more.

[0042] Also, in Figure 3A, p + Type region 22 and p ++ The contact region 15 is cubic in shape, but may also be cylindrical. By making it cylindrical, p + Type region 22 and p ++ If the position of the type contact region 15 shifts, it is possible to prevent the region where the channel is formed from disappearing. + Type region 22 and p ++ The contact area 15 is separated from the trench 16, but may be in contact with the trench 16.

[0043] In this way, by simplifying the structure per cell, the cell pitch can be shortened, and by shortening the cell pitch, it is possible to achieve low resistance in SiCMOSFETs with low channel mobility. Furthermore, there is more room in the structure between the trenches 16, and the p below the trench 16 is smaller than in the conventional structure. + The width of the type region 21 can be increased, and the flat portion of the pn junction can be widened, thereby mitigating electric field concentration and increasing the breakdown voltage. For example, p + The width L1 of the type region 21 is the width of the JFET region, that is, the adjacent p + The distance L2 between the type regions 21 can be made wider. In this case, the path Lj(from the bottom surface of the p-type base region 13 to the p-type base region 13) through which the current flows in the JFET is wider. + By increasing the distance to the bottom surface of the mold region 21, the saturation current can be suppressed and the short-circuit withstand capability can be improved.

[0044] In Figures 2 and 3A, p + The p-type region connecting the p-type region 21 and the source electrode 44 is p + Type region 22 and p ++ The contact region 15 has a two-layer structure, but it may also have a single-layer structure. In this case, p + Only type region 22 is provided, p + The type region 21 and the source electrode 44 may be connected, or p ++ Only the type contact area 15 is provided, p + The mold region 21 and the source electrode 44 may be connected.

[0045] Also, p + In the mold region 21, the peak of the impurity concentration in the depth direction may be in the central part (see Figures 10 and 11). In this case, the bottom of the trench 16 is p + It is located on the source electrode 44 side of the peak position of the impurity concentration in type region 21. This is done so that when the depletion layer expands, p + The peak of the electric field strength is formed in a region deeper than the central part of the mold region 21. In other words, the peak of the electric field strength can be separated from the gate insulating film 17. Therefore, the maximum peak value of the electric field strength can be reduced, and a higher breakdown voltage can be achieved.

[0046] Trench 16 is n in the depth direction + The n-type current diffusion region 20 penetrates the p-type source region 14 and the p-type base region 13 (if the n-type current diffusion region 20 is not provided, then n - It reaches the type drift region 12). Trench 16 is p + The trench may terminate inside the mold region 21. The trench 16 extends, for example, in a stripe shape parallel to the front surface of the semiconductor substrate 40, reaching the outer periphery (not shown) of the active region. Inside the trench 16, a gate electrode 18 is provided via a gate insulating film 17.

[0047] The interlayer insulating film 19 is provided over the entire surface of the front surface of the semiconductor substrate 40 and covers the gate electrode 18. The ohmic electrode (first electrode) 43 is provided on the portion of the front surface of the semiconductor substrate 40 that is exposed to the contact hole of the interlayer insulating film 19. The ohmic electrode 43 is located in the contact hole of the interlayer insulating film 19 and on the front surface of the semiconductor substrate 40. + Type source region 14 and p ++ The ohmic contact is made to the contact region 15. The ohmic electrode 43 is, for example, a nickel silicide film (NixSiy, where x and y are arbitrary integers).

[0048] The source electrode (first electrode) 44 is provided on the interlayer insulating film 19 so as to fill the contact holes of the interlayer insulating film 19. The source electrode 44 is provided over almost the entire central part of the active region, and the source electrode 44 is connected to the ohmic electrode 43 via n + Type source area 14, p ++ Type contact region 15, p-type base region 13, and p + It is electrically connected to type regions 21 and 22.

[0049] A barrier metal 38 may be provided on the ohmic electrode 43 and the interlayer insulating film 19 to prevent the diffusion of metal atoms toward the gate electrode 18. The barrier metal 38 is made of, for example, titanium (Ti) or titanium nitride (TiN). The barrier metal 38 may have a two-layer structure of Ti on the semiconductor substrate 40 side and TiN. In this case, the source electrode 44 is provided on the barrier metal 38.

[0050] The drain electrode (second electrode) 45 is on the back surface (n) of the semiconductor substrate 40. + The entire surface of the back surface of the mold starting substrate 41 is provided, n + Type drain region 11(n + Ohmic contact is made with the starting substrate 41), n + It is electrically connected to the drain region 11.

[0051] (Method for manufacturing a silicon carbide semiconductor device according to Embodiment 1) Next, a method for manufacturing a silicon carbide semiconductor device according to Embodiment 1 will be described. Figures 4 to 7 are cross-sectional views showing the state of the silicon carbide semiconductor device during the manufacturing process according to Embodiment 1. First, n + Type starting substrate (n + On the front surface of the mold starting wafer 41, n - n is in the drift region 12. - The n-type silicon carbide layer 42a is epitaxially grown. The state up to this point is shown in Figure 4. Next, n-type impurities are ion-implanted. - The lower part of the n-type current diffusion region 20 is formed in the n-type silicon carbide layer 42a. Next, by photolithography and ion implantation of p-type impurities, n - In the surface region of the type silicon carbide layer 42a, p + A type region 21 is selectively formed.

[0052] Next, n - On the silicon carbide layer 42a, n - n is in the drift region 12. - A silicon carbide layer 42b is epitaxially grown. Next, n-type impurities are ion-implanted. -The upper part of the n-type current diffusion region 20 is formed in the n-type silicon carbide layer 42b. This state is shown in Figure 5. Next, n - On the silicon carbide layer 42b, n - n is in the drift region 12. - The silicon carbide layer 42c is epitaxially grown. In the process up to this point, n + n - A semiconductor substrate (semiconductor wafer) 40 of a predetermined thickness is completed by stacking silicon carbide layers 42 (42a to 42c).

[0053] Next, by photolithography and ion implantation of p-type impurities, n - A p-type base region 13 is formed inside the silicon carbide layer 42c. Next, by photolithography and ion implantation of n-type impurities, - n + The type source region 14 is selectively formed. This state is shown in Figure 6.

[0054] Next, by photolithography and ion implantation of p-type impurities, n - Type silicon carbide layer 42b and n - Inside the type silicon carbide layer 42c, the bottom surface is p + p + A type region 22 is formed. Next, by photolithography and ion implantation of p-type impurities, n - In the surface region of the type silicon carbide layer 42c, p ++ A type contact region 15 is selectively formed. The state up to this point is shown in Figure 7. In this way, p + By forming a deep type region 22, p ++ Type contact area 15 and p below trench 16 + Connect type region 21. + Type region 22 and p ++ The type contact region 15 can be formed in the same process as photolithography and ion implantation of p-type impurities, eliminating the need for conventional p-type impurities. + p between type regions 21 + By eliminating the process of forming the mold region and reducing the number of steps, costs can be lowered.

[0055] Here, p + Although the type region 22 was formed by a single ion implantation, it may also be formed by multiple ion implantations. For example, n - After forming type silicon carbide layer 42b, p + Forming the lower region of type region 22, n - After forming type silicon carbide layer 42c, p + The upper region of type region 22 may be formed. Also, n - In the surface region of the type silicon carbide layer 42c, p + Forms a type region 22, p + By ion implanting p-type impurities onto the surface of type region 22, ++ A p-type contact region 15 may be formed. Also, a p-type base region 13 and n + Either or both of the type source regions 14 are formed by epitaxial growth, p + Type region 22 and p ++ The contact region 15 may be formed by ion implantation.

[0056] n - The portion of the silicon carbide layer 42 (42a~42c) that is not ion-implanted and remains at the same impurity concentration as during epitaxial growth is n - This results in a type drift region 12. Next, a heat treatment is performed to activate the impurities ion-implanted in the silicon carbide layer 42. This heat treatment for impurity activation may be performed each time impurities are ion-implanted into the silicon carbide layers 42a to 42c. Next, a trench 16, a gate insulating film 17, and a gate electrode 18 are formed by a general method.

[0057] Next, an interlayer insulating film 19 is formed over the entire surface of the front surface of the semiconductor substrate 40. Then, a source electrode 44, a gate pad (not shown), a passivation film (surface protective film: not shown), and a drain electrode 45 are formed using a general method. The portion of the source electrode 44 that is exposed to the opening of the passivation film becomes the source pad. After that, the semiconductor wafer is diced (cut) to separate it into individual chips, thereby completing the silicon carbide semiconductor device 10 shown in Figures 1 to 3A.

[0058] As explained above, according to the silicon carbide semiconductor device of Embodiment 1, p under the trench + p between trenches located at the same depth as the mold region + The type region is eliminated, and the bottom surface is p + It is in contact with a part of the upper surface of the type region, and the upper surface is p ++ p in contact with the type contact area + A type region is established, p + Type domain and p ++ It connects to the type contact region. This simplifies the structure per cell and shortens the cell pitch, enabling low resistance in SiCMOSFETs with low channel mobility. Furthermore, the p below the trench + The width of the mold region can be increased, and the flat portion of the pn junction can be widened, which reduces electric field concentration and increases the breakdown voltage. + By widening the mold region, the current path through the JFET becomes longer, which suppresses the saturation current and improves the short-circuit withstand capability.

[0059] (Embodiment 2) Next, the structure of the silicon carbide semiconductor device according to Embodiment 2 will be described. Figure 8 is a cross-sectional view taken along line A-A' in Figure 9, showing the structure of the silicon carbide semiconductor device according to Embodiment 2. Figure 9 is a perspective view showing the structure of the silicon carbide semiconductor device according to Embodiment 2. The cross-sectional view taken along line B-B' in Figure 9 is the same as that of Embodiment 1, so its description is omitted (see Figure 2).

[0060] In the silicon carbide semiconductor device according to Embodiment 2, p + Type region 22 and p ++ In the area where the type contact region 15 is not provided, p + A type protection region (third high-concentration region of the second conductivity type) 23 is selectively provided. + The type protection area 23 is p + At an impurity concentration similar to that of type region 21, adjacent p + Type region 21 and p + It is electrically connected to type region 21. +The type protection area 23 is, for example, as shown in Figures 8 and 9, p + With a thickness similar to that of type region 21, p + It is located at a shallower position than the mold region 21, p + A portion of the side of the type protection area 23 is p + It is in contact with a part of the side surface of type region 21. Also, p + The type protection area 23 is p + With a thickness similar to that of type region 21, p + It may be provided at the same depth as the mold region 21.

[0061] Figure 10 is a perspective view showing the impurity concentration distribution of the silicon carbide semiconductor device according to Embodiment 1. Figure 11 is a perspective view showing the impurity concentration distribution of the silicon carbide semiconductor device according to Embodiment 2. In the silicon carbide semiconductor device according to Embodiment 1, as shown in Figure 10, p + Type region 22 and p ++ In areas where the type contact region 15 is not provided, there is a wide JFET region 24. In this case, punch-through is likely to occur in the thin p-type base region 13 directly above the wide JFET region 24, which may lead to a decrease in breakdown voltage. For this reason, in Embodiment 2, as shown in Figure 11, p + p tangent to type region 21 + By providing a protective region 23, a decrease in withstand voltage is avoided. In Figure 11, p + The type protection area 23 is p + With a thickness similar to that of type region 21, p + This shows the case where it is provided at the same depth as the mold region 21. Also, as shown in Figure 11, p + The type protection area 23 is p + Similar to type region 21, the peak of impurity concentration may be in the central region.

[0062] (Method for manufacturing a silicon carbide semiconductor device according to Embodiment 2) Next, a method for manufacturing a silicon carbide semiconductor device according to Embodiment 2 will be described. The silicon carbide semiconductor device according to Embodiment 2 is manufactured using the method for manufacturing a silicon carbide semiconductor device according to Embodiment 1, n -After epitaxial growth of the type silicon carbide layer 42b (see Figure 5), photolithography and ion implantation of p-type impurities were performed, resulting in n - In the surface region of the type silicon carbide layer 42b, p + It can be manufactured by selectively forming the mold protection region 23.

[0063] As described above, the silicon carbide semiconductor device of Embodiment 2 has the same effects as Embodiment 1. Furthermore, p + Type domain and p ++ In the area where no type contact region is provided, p under the trench + p connecting type regions + A mold protection region is selectively provided. This prevents punch-through in the thin p-type base region directly above it, thereby avoiding a decrease in withstand voltage.

[0064] (Embodiment 3) Next, the structure of the silicon carbide semiconductor device according to Embodiment 3 will be described. Figure 12 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 3. In Embodiment 3, the perspective view is almost the same as that of Embodiment 1, so its description is omitted (see Figure 3A). Figure 12 is a cross-sectional view corresponding to the A-A' section in Figure 1. The cross-sectional view corresponding to the B-B' section is the same as that of Embodiment 1, so its description is omitted (see Figure 2).

[0065] In the silicon carbide semiconductor device according to Embodiment 3, p + Type region 22 and p ++ In the p-type base region 13 on the region where the type contact region 15 is not provided, a high concentration of p + A type base region (the fourth high-concentration region of the second conductivity type) 25 is selectively provided. + The p-type base region 25 has an impurity concentration about twice as high as that of the p-type base region 13, and its width is equal to the width of the JFET region, that is, the width of adjacent p-type base regions. + The distance L2 between the type regions 21 is about the same, and the thickness is about the same as that of the p-type base region 13. High concentration p + The thickness of the type base region 25 may be thicker than the p-type base region 13.

[0066] Figure 13 is a perspective view showing the impurity concentration distribution of the silicon carbide semiconductor device according to Embodiment 3. The silicon carbide semiconductor device according to Embodiment 3 is similar to the silicon carbide semiconductor device according to Embodiment 2 in that it contains p + A protective region 23 may be provided. Figure 13 shows high concentration p + Similar to the base region 25, p + The impurity concentration distribution when a type protection region 23 is provided is shown. In the silicon carbide semiconductor device according to Embodiment 1, as shown in Figure 10, p + Type region 22 and p ++ In areas where the type contact region 15 is not provided, there is a wide JFET region 24. In this case, punch-through is likely to occur in the thin p-type base region 13 directly above the wide JFET region 24, which may lead to a decrease in breakdown voltage. For this reason, in Embodiment 3, as shown in Figure 13, a high-concentration p-type base region 13 with a high impurity concentration is provided directly above the JFET region 24. + By providing the mold base region 25, the characteristics of the silicon carbide semiconductor device are not deteriorated, and a decrease in breakdown voltage is avoided.

[0067] (Method for manufacturing a silicon carbide semiconductor device according to Embodiment 3) Next, a method for manufacturing a silicon carbide semiconductor device according to Embodiment 3 will be described. The silicon carbide semiconductor device according to Embodiment 3 is manufactured using the method for manufacturing a silicon carbide semiconductor device according to Embodiment 1, n - After forming a p-type base region 13 inside the type silicon carbide layer 42c (see Figure 6), the impurity concentration in a portion of the p-type base region 13 is increased by photolithography and ion implantation of p-type impurities, thereby achieving a high concentration of p + It can be manufactured by selectively forming the mold base region 25.

[0068] As explained above, the silicon carbide semiconductor device of Embodiment 3 has the same effects as Embodiment 1. Furthermore, p + Type domain and p ++ In the p-type base region on the region where no type contact region is provided, a high concentration of p +A selective mold base region 25 is provided. This prevents punch-through in the thin p-type base region 13 directly above it, thereby avoiding a decrease in withstand voltage.

[0069] As described above, the present invention can be modified in various ways without departing from the spirit of the invention, and in each of the embodiments described above, for example, the dimensions of each part, the impurity concentration, etc. can be set in various ways according to the required specifications. Furthermore, although the embodiments described above have been explained using a MOSFET having a trench structure as an example, the invention can also be applied to other semiconductor devices having a trench structure, such as IGBTs. [Industrial applicability]

[0070] As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machines, and igniters for automobiles. [Explanation of Symbols]

[0071] 10, 110 Silicon Carbide Semiconductor Devices 11, 111 n + Type drain region (n + (Silicon carbide substrate) 12, 112 n - Type drift region 13, 113 p-type base region 14, 114 n + Type source area 15, 115 p ++ Type Contact Area 16, 116 Trench 17, 117 gate insulating film 18, 118 gate electrodes 19, 119 Interlayer insulating film 20, 120 n-type current diffusion region 21, 121 p under the trench + type area 22 The central p between adjacent trenches + type area 23 pages+ type protection area 24 Wide JFET region 25 high concentration p + Type-based domain 38, 138 Barrier Metal 40, 140 semiconductor substrates 41, 141 n + Mold starting substrate 42, 142 n - mold silicon carbide layer 43, 143 Ohmic electrodes 44, 144 source electrodes 45, 145 Drain electrode 122 p between adjacent trenches + type area 123 p between adjacent trenches + Lower part of the type domain 124 p between adjacent trenches + Top of the type region

Claims

1. A silicon carbide semiconductor substrate of the first conductivity type, A first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is provided on the front surface of the silicon carbide semiconductor substrate, A second semiconductor layer of a second conductivity type is provided on the surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side, A first semiconductor region of a first conductivity type is selectively provided on the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side, A trench that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer, A gate electrode is provided inside the trench via a gate insulating film, A first high-concentration region of a second conductivity type is provided inside the first semiconductor layer at a position opposite to the trench in the depth direction, A second high-concentration region of a second conductivity type is selectively provided between the trenches inside the first semiconductor layer and the second semiconductor layer, in contact with the first semiconductor region, with its upper surface exposed to the surface of the second semiconductor layer and a portion of its lower surface in contact with the upper surface of the first high-concentration region. A first electrode provided on the surface of the second high-concentration region and the first semiconductor region, A second electrode provided on the back surface of the silicon carbide semiconductor substrate, Equipped with, The second high-concentration region is periodically arranged in the depth direction, which is the longitudinal direction when viewed from above the trench, and consists of an upper second high-concentration region on the first electrode side and a lower second high-concentration region on the second electrode side. The silicon carbide semiconductor device is characterized in that the upper second high-concentration region has a higher impurity concentration than the lower second high-concentration region.

2. The silicon carbide semiconductor device according to Claim 1, characterized in that the width of the second high-concentration region in the direction adjacent to the first high-concentration region is wider than the distance between adjacent first high-concentration regions.

3. The silicon carbide semiconductor device according to claim 1, characterized in that the second high-concentration region is spaced apart from the trench.

4. The first high-concentration region is in contact with the bottom of the trench, and the peak of the impurity concentration is in the central part. The silicon carbide semiconductor device according to claim 1, characterized in that the bottom of the trench is located on the first electrode side of the peak of the impurity concentration in the first high-concentration region.

5. The silicon carbide semiconductor device according to Claim 1, characterized in that a third high-concentration region of a second conductivity type is selectively provided in a region where the second high-concentration region is not provided, connecting adjacent first high-concentration regions.

6. The silicon carbide semiconductor device according to Claim 1, characterized in that, in a region where the second high-concentration region is not provided, a fourth high-concentration region of a second conductivity type having a higher impurity concentration than the second semiconductor layer is selectively provided on the surface of the first semiconductor layer between adjacent first high-concentration regions, on the surface opposite to the silicon carbide semiconductor substrate side.

7. A silicon carbide semiconductor substrate of the first conductivity type, A first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is provided on the front surface of the silicon carbide semiconductor substrate, A second semiconductor layer of a second conductivity type is provided on the surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side, A first semiconductor region of a first conductivity type is selectively provided on the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side, A trench that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer, A gate electrode is provided inside the trench via a gate insulating film, A first high-concentration region of a second conductivity type is provided inside the first semiconductor layer at a position opposite to the trench in the depth direction, A second high-concentration region of a second conductivity type is selectively provided between the trenches inside the first semiconductor layer and the second semiconductor layer, in contact with the first semiconductor region, with its upper surface exposed to the surface of the second semiconductor layer and a portion of its lower surface in contact with the upper surface of the first high-concentration region. A first electrode provided on the surface of the second high-concentration region and the first semiconductor region, A second electrode provided on the back surface of the silicon carbide semiconductor substrate, Equipped with, The second high-concentration region is periodically arranged in the depth direction, which is the longitudinal direction when viewed from above the trench. A silicon carbide semiconductor device characterized in that, in a region where the second high-concentration region is not provided, a third high-concentration region of a second conductivity type is selectively provided, connecting adjacent first high-concentration regions.

8. A silicon carbide semiconductor substrate of the first conductivity type, A first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is provided on the front surface of the silicon carbide semiconductor substrate, A second semiconductor layer of a second conductivity type is provided on the surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side, A first semiconductor region of a first conductivity type is selectively provided on the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side, A trench that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer, A gate electrode is provided inside the trench via a gate insulating film, A first high-concentration region of a second conductivity type is provided inside the first semiconductor layer at a position opposite to the trench in the depth direction, A second high-concentration region of a second conductivity type is selectively provided between the trenches inside the first semiconductor layer and the second semiconductor layer, in contact with the first semiconductor region, with its upper surface exposed to the surface of the second semiconductor layer and a portion of its lower surface in contact with the upper surface of the first high-concentration region. A first electrode provided on the surface of the second high-concentration region and the first semiconductor region, A second electrode provided on the back surface of the silicon carbide semiconductor substrate, Equipped with, The second high-concentration region is periodically arranged in the depth direction, which is the longitudinal direction when viewed from above the trench. A silicon carbide semiconductor device characterized in that, in a region where the second high-concentration region is not provided, a fourth high-concentration region of a second conductivity type with a higher impurity concentration than the second semiconductor layer is selectively provided on the surface of the first semiconductor layer between adjacent first high-concentration regions, on the surface opposite to the silicon carbide semiconductor substrate side.

9. A first step of forming a first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate on the front surface of the first conductivity type silicon carbide semiconductor substrate, A second step is to form a second semiconductor layer of a second conductivity type on the surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side, A third step involves forming a first high-concentration region of a second conductivity type inside the first semiconductor layer, A fourth step of selectively forming a second high-concentration region of a second conductivity type within the first semiconductor layer and the second semiconductor layer, wherein the upper surface is exposed to the surface of the second semiconductor layer and a portion of the lower surface is in contact with the upper surface of the first high-concentration region, A fifth step of selectively forming a first semiconductor region of a first conductivity type on the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side, A sixth step of forming a trench that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer, A seventh step involves forming a gate electrode inside the trench via a gate insulating film, An eighth step of forming a first electrode on the surface of the second high-concentration region and the first semiconductor region, A ninth step involves forming a second electrode on the back surface of the silicon carbide semiconductor substrate, Includes, In the third step, the first high-concentration region is formed at a position opposite the trench in the depth direction, In the fourth step described above, The second high-concentration region is in contact with the first semiconductor region, periodically formed in the depth direction which is the longitudinal direction of the trench when viewed from above, between the trenches, and is composed of an upper second high-concentration region on the first electrode side and a lower second high-concentration region on the second electrode side. A method for manufacturing a silicon carbide semiconductor device, characterized in that the impurity concentration in the upper second high-concentration region is higher than the impurity concentration in the lower second high-concentration region.

10. A first step of forming a first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate on the front surface of the first conductivity type silicon carbide semiconductor substrate, A second step is to form a second semiconductor layer of a second conductivity type on the surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side, A third step involves forming a first high-concentration region of a second conductivity type inside the first semiconductor layer, A fourth step of selectively forming a second high-concentration region of a second conductivity type within the first semiconductor layer and the second semiconductor layer, wherein the upper surface is exposed to the surface of the second semiconductor layer and a portion of the lower surface is in contact with the upper surface of the first high-concentration region, A fifth step of selectively forming a first semiconductor region of a first conductivity type on the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side, A sixth step of forming a trench that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer, A seventh step involves forming a gate electrode inside the trench via a gate insulating film, An eighth step of forming a first electrode on the surface of the second high-concentration region and the first semiconductor region, A ninth step involves forming a second electrode on the back surface of the silicon carbide semiconductor substrate, Includes, In the third step, the first high-concentration region is formed at a position opposite the trench in the depth direction, In the fourth step, the second high-concentration region is in contact with the first semiconductor region and periodically formed in the depth direction, which is the longitudinal direction of the trench when viewed from above, between the trenches. A method for manufacturing a silicon carbide semiconductor device, further comprising a tenth step of selectively forming a third high-concentration region of a second conductivity type that connects adjacent first high-concentration regions in a region within the first semiconductor layer where the second high-concentration region is not provided.

11. A first step of forming a first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate on the front surface of the first conductivity type silicon carbide semiconductor substrate, A second step is to form a second semiconductor layer of a second conductivity type on the surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side, A third step involves forming a first high-concentration region of a second conductivity type inside the first semiconductor layer, A fourth step of selectively forming a second high-concentration region of a second conductivity type within the first semiconductor layer and the second semiconductor layer, wherein the upper surface is exposed to the surface of the second semiconductor layer and a portion of the lower surface is in contact with the upper surface of the first high-concentration region, A fifth step of selectively forming a first semiconductor region of a first conductivity type on the surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side, A sixth step of forming a trench that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer, A seventh step involves forming a gate electrode inside the trench via a gate insulating film, An eighth step of forming a first electrode on the surface of the second high-concentration region and the first semiconductor region, A ninth step involves forming a second electrode on the back surface of the silicon carbide semiconductor substrate, Includes, In the third step, the first high-concentration region is formed at a position opposite the trench in the depth direction, In the fourth step, the second high-concentration region is in contact with the first semiconductor region and periodically formed in the depth direction, which is the longitudinal direction of the trench when viewed from above, between the trenches. A method for manufacturing a silicon carbide semiconductor device, further comprising a tenth step of selectively forming a fourth high-concentration region of a second conductivity type with a higher impurity concentration than the second semiconductor layer on the surface of the first semiconductor layer between adjacent first high-concentration regions, on the surface opposite to the silicon carbide semiconductor substrate side, in a region within the second semiconductor layer where the second high-concentration region is not provided.

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