Manufacturing method for semiconductor devices

Abstract

To provide a method for manufacturing a semiconductor device capable of suppressing fluctuations and variations of a gate threshold voltage due to ion implantation into a contact trench and achieving miniaturization.SOLUTION: A method for manufacturing a semiconductor device includes forming a first trench 11 from the upper surface side of a semiconductor substrate of a first conductivity type, embedding an electrode structure (6, 7) of an insulation gate type in the first trench 11, forming a base region 3 of a second conductivity type in contact with the first trench 11 in an upper part of the semiconductor substrate, forming a first main electrode region 4 of the first conductivity type in contact with the first trench 11 in an upper part of the base region 3, forming a second trench 14 by removing a part of the first main electrode region 4, ion-implanting a first impurity of the first conductivity type into the whole of a sidewall surface of the second trench 14 from an obliquely upper direction, forming a contact region of the second conductivity type at a bottom of the second trench 14 by ion-implanting a second impurity of the second conductivity type into the bottom of the second trench 14, and forming a second main electrode region of the second conductivity type on the lower surface side of the semiconductor substrate.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device. [Background Art]

[0002] Conventionally, in a semiconductor device such as an insulated gate bipolar transistor (IGBT) having a trench gate structure, problems such as a decrease in latch-up tolerance are concerned due to an increase in resistance accompanying the miniaturization of the contact in the mesa portion between gate trenches, and thus a reduction in contact resistance is required. As a method for reducing contact resistance, a contact trench is formed in a mesa portion between gate trenches, and contact is established not only on the bottom surface of the contact trench but also on the side wall surfaces, thereby increasing the area of the contact to achieve lower resistance.

[0003] When forming a contact trench, it is common to ion-implant a p-type impurity such as boron (B) into the bottom surface of the contact trench to form a contact region having a higher impurity concentration than the p-type base region so as to be in contact with the base region, thereby lowering the contact resistance.

[0004] Patent Document 1 discloses that, in a method for manufacturing a power MOSFET, a p-type impurity is ion-implanted perpendicularly to a contact trench to form a p + region at the bottom of the contact trench, and an n-type impurity is ion-implanted into the upper side of the side wall surface of the contact trench from an obliquely upward direction to form an n + source region on the upper side of the side wall surface of the contact trench. [Prior Art Literature] [Patent Literature]

[0005] [Patent Document 1] Japanese Patent No. 5034151 Specification [Summary of the Invention] [Problem to be Solved by the Invention]

[0006] As described above, when ion implanting p-type impurities perpendicular to the bottom surface of a contact trench, if the contact trench has a tapered shape, the p-type impurities are implanted not only on the bottom surface of the contact trench but also on the side walls. During ion implantation, the p-type impurities collide with interstitial atoms of the semiconductor substrate and scatter, causing their distribution to spread laterally. When p-type impurities reach the vicinity of the gate trench, they become a cause of fluctuations (increases) and variations in the gate threshold voltage. Therefore, in order to stabilize the electrical characteristics, it is necessary to ensure the width of the mesa between the gate trenches, which limits miniaturization.

[0007] The present invention aims to provide a method for manufacturing a semiconductor device that can suppress fluctuations and variations in gate threshold voltage caused by ion implantation into contact trenches, thereby enabling miniaturization. [Means for solving the problem]

[0008] To achieve the above objective, one aspect of the present invention is a method for manufacturing a semiconductor device, comprising the steps of: (a) forming a first trench from the upper surface of a semiconductor substrate of a first conductivity type; (b) embedding an insulated gate type electrode structure in the first trench; (c) forming a base region of a second conductivity type on the upper part of the semiconductor substrate in contact with the first trench; (d) forming a first main electrode region of a first conductivity type on the upper part of the base region in contact with the first trench; (e) removing a part of the first main electrode region to form a second trench; (f) ion implanting a first impurity of a first conductivity type onto the entire side wall surface of the second trench from an oblique upward direction; (g) ion implanting a second impurity of a second conductivity type onto the bottom surface of the second trench to form a contact region of a second conductivity type at the bottom of the second trench; and (h) forming a second main electrode region of a second conductivity type on the lower surface of the semiconductor substrate. [Effects of the Invention]

[0009] According to the present invention, it is possible to suppress fluctuations and variations in the gate threshold voltage caused by ion implantation into the contact trench, thereby providing a method for manufacturing a semiconductor device that enables miniaturization. [Brief explanation of the drawing]

[0010] [Figure 1] This is a plan view showing an example of a semiconductor device according to the first embodiment. [Figure 2] This is a cross-sectional view taken from the direction of line AA in Figure 1. [Figure 3] This is an enlarged cross-sectional view of region A in Figure 2. [Figure 4] This is a cross-sectional view of an example of a semiconductor device manufacturing method according to the first embodiment. [Figure 5] This is a cross-sectional view of a process following Figure 4, showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] This is a cross-sectional view of a process following Figure 5, showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] This is a cross-sectional view of a process following Figure 6, showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] This is a cross-sectional view of a process following Figure 7, showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] This is a cross-sectional view of a process following Figure 8, showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 10] This is a cross-sectional view of a process following Figure 9, showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 11] This is a cross-sectional view of a process following Figure 10, showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 12] This is a cross-sectional view of a process following Figure 11, showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 13] This is a cross-sectional view of a process following Figure 12, showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 14] This is a cross-sectional view of the process of manufacturing a semiconductor device according to a comparative example. [Figure 15] This graph shows the relationship between dose, acceleration energy, and lateral diffusion distance in oblique ion implantation. [Figure 16] This graph shows the relationship between dose, tilt angle, and lateral diffusion distance in oblique ion implantation. [Figure 17] This is a cross-sectional view of an example of a semiconductor device manufacturing method according to the second embodiment. [Figure 18] This is a cross-sectional view of an example of a semiconductor device manufacturing method according to the third embodiment. [Figure 19] This is a cross-sectional view of an example of a semiconductor device manufacturing method according to the fourth embodiment. [Figure 20] This is a cross-sectional view of a process following Figure 19, showing an example of a method for manufacturing a semiconductor device according to the fourth embodiment. [Modes for carrying out the invention]

[0011] The first to fourth embodiments of the present invention will be described below with reference to the drawings. In the drawings referred to in the following description, identical or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from reality. Therefore, specific thicknesses and dimensions should be determined by referring to the following description. Furthermore, it goes without saying that there are parts where the relationships and ratios of dimensions differ between drawings.

[0012] In the following explanation, the "first main electrode region" and the "second main electrode region" refer to the main electrode regions of a semiconductor device through which the main current flows in or out. The "first main electrode region" refers to the semiconductor region that is either the emitter region or the collector region in the case of an insulated-gate bipolar transistor (IGBT). In the case of a field-effect transistor (FET) or electrostatic induction transistor (SIT), it refers to the semiconductor region that is either the source region or the drain region. In the case of an electrostatic induction thyristor (SI thyristor) or gate turn-off thyristor (GTO), it refers to the semiconductor region that is either the anode region or the cathode region. Furthermore, the "second main electrode region" refers to the region that is either the emitter region or the collector region that is not the first main electrode region in the case of an IGBT. In the case of an FET or SIT, it refers to the semiconductor region that is either the source region or the drain region that is not the first main electrode region. In the case of an SI thyristor or GTO, it refers to the region that is either the anode region or the cathode region that is not the first main electrode region. In other words, if the "first main electrode region" is the source region, then the "second main electrode region" means the drain region. If the "first main electrode region" is the emitter region, then the "second main electrode region" means the collector region. If the "first main electrode region" is the anode region, then the "second main electrode region" means the cathode region. Note that when simply referred to as the "main electrode region," it comprehensively means either the first main electrode region or the second main electrode region, whichever is technically and contextually appropriate.

[0013] Furthermore, the definitions of directions such as up and down in the following explanation are merely for explanatory convenience and do not limit the technical concept of the present invention. For example, it is obvious that if an object is rotated 90° and observed, up and down will be converted to left and right and read accordingly, and if it is rotated 180° and observed, up and down will be inverted and read accordingly.

[0014] Furthermore, the following explanation uses the case where the first conductivity type is n-type and the second conductivity type is p-type as an example. However, it is also acceptable to choose the conductivity types in the reverse relationship, with the first conductivity type being p-type and the second conductivity type being n-type. Also, the "+" and "-" attached to "n" and "p" indicate semiconductor regions with relatively higher or lower impurity concentrations, respectively, compared to semiconductor regions without "+" and "-" markings. However, even if two semiconductor regions are marked with the same "n," this does not mean that the impurity concentrations in each semiconductor region are exactly the same.

[0015] (First Embodiment) <Structure of a semiconductor device> Figure 1 is a plan view of a portion of the active region of the semiconductor device according to the first embodiment, viewed from the top (front) side. As shown in Figure 1, the semiconductor device according to the first embodiment includes a transistor section 101, which includes a transistor element such as an IGBT, and a diode section 102, which includes a diode element, on the same semiconductor chip. For example, the semiconductor device according to the first embodiment is a reverse-conducting IGBT (RC-IGBT) that includes an IGBT, which is the transistor section 101, and a freewheeling diode (FWD), which is the diode section 102 and is connected in antiparallel to the IGBT, on the same semiconductor chip. The transistor section 101 and the diode section 102 may be arranged alternately in the left-right direction in Figure 1.

[0016] Figure 2 shows a cross-section obtained by cutting through the transistor section 101 and diode section 102 in Figure 1 with line AA. As shown in Figure 2, the semiconductor device according to the first embodiment includes a semiconductor substrate 10. The semiconductor substrate 10 is made of, for example, a silicon (Si) substrate. However, the semiconductor substrate 10 is not limited to a Si substrate, and may be a semiconductor substrate made of a semiconductor with a wider band gap than Si (wide bandgap semiconductor), such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), or aluminum nitride (AlN).

[0017] The semiconductor substrate 10 is a first conductivity type (n -The transistor section 101 includes an n-type drift layer 1. In the transistor section 101, an n-type storage layer 2 with a higher impurity concentration than the drift layer 1 is provided on the upper surface of the drift layer 1. The lower surface of the storage layer 2 is in contact with the upper surface of the drift layer 1. By providing the storage layer 2, the carrier injection promotion effect (IE effect) can be enhanced, and the on-voltage can be reduced.

[0018] In the transistor section 101, the upper surface of the storage layer 2 has a second conductivity type (p - A base region 3 of type ( ) is provided. The lower surface of the base region 3 is in contact with the upper surface of the storage layer 2. On the upper surface side of the base region 3, n + The first main electrode regions (emitter regions) 4a and 4b of the type are provided. The lower surfaces of the emitter regions 4a and 4b are in contact with the upper surface of the base region 3. The impurity concentration in the emitter regions 4a and 4b is higher than the impurity concentration in the drift layer 1 and the storage layer 2.

[0019] On the other hand, in the diode section 102, no storage layer like the one in the transistor section 101 is provided on the upper surface of the drift layer 1. However, an n-type storage layer with a higher impurity concentration than the drift layer 1 may also be provided on the upper surface of the drift layer 1 in the diode section 102. In the diode section 102, on the upper surface of the drift layer 1, p - A type anode region 13 is provided. The lower surface of the anode region 13 is in contact with the upper surface of the drift layer 1. The anode region 13 extends to the upper surface of the semiconductor substrate 10. The anode region 13 may be provided to the same depth as the base region 3 of the transistor section 101 and with the same impurity concentration.

[0020] In the transistor section 101 and the diode section 102, a plurality of trenches (gate trenches) 11 are provided spaced apart from each other in a depth direction perpendicular to the upper surface of the semiconductor substrate 10, extending from the upper surface of the semiconductor substrate 10. In the transistor section 101, the gate trenches 11 penetrate the emitter regions 4a, 4b, the base region 3, and the storage layer 2 to reach the drift layer 1. The sides (sidewalls) of the gate trenches 11 are in contact with the sides of the emitter regions 4a, 4b, the base region 3, and the storage layer 2. In the diode section 102, the gate trenches 11 penetrate the anode region 13 to reach the drift layer 1. The sides of the gate trenches 11 are in contact with the sides of the anode region 13.

[0021] In the parallel direction of the gate trenches 11, a mesa region is provided between adjacent gate trenches 11, consisting of the upper part of the semiconductor substrate 10. The mesa region is the area of ​​the semiconductor substrate 10 sandwiched between adjacent gate trenches 11, and is the area above the deepest part of the gate trenches 11. The mesa region of the transistor section 101 is provided with the upper part of the drift layer 1, the storage layer 2, the base region 3, and the emitter regions 4a and 4b. The mesa region of the diode section 102 is provided with the upper part of the drift layer 1 and the anode region 13.

[0022] A gate insulating film 6 is provided so as to cover the bottom and sides of the gate trench 11. As the gate insulating film 6, for example, a single layer film of any one of the following can be used: silicon dioxide film (SiO2 film), silicon oxynitride (SiON) film, strontium oxide (SrO) film, silicon nitride (Si3N4) film, aluminum oxide (Al2O3) film, magnesium oxide (MgO) film, yttrium oxide (Y2O3) film, hafnium oxide (HfO2) film, zirconium oxide (ZrO2) film, tantalum oxide (Ta2O5) film, or bismuth oxide (Bi2O3) film, or a composite film made by stacking multiple of these.

[0023] A gate electrode 7 is embedded inside the gate trench 11 via a gate insulating film 6. The gate insulating film 6 and the gate electrode 7 constitute an insulated gate electrode structure (6, 7). As a material for the gate electrode 7, for example, a polysilicon film (doped polysilicon film) obtained by adding impurities such as phosphorus (P) and boron (B) at a high impurity concentration can be used.

[0024] Among the plurality of insulated gate electrode structures (6, 7) in the transistor portion 101, some of the insulated gate electrode structures (6, 7) are gate trench portions connected to a gate runner, and the remaining insulated gate electrode structures (6, 7) may be dummy trench portions not connected to the gate runner. Further, the plurality of insulated gate electrode structures (6, 7) in the diode portion 102 may be dummy trench portions not connected to the gate runner.

[0025] As shown in FIG. 1, in a planar pattern, the plurality of gate trenches 11 each have linear (stripe-shaped) portions extending parallel to each other in one direction (the vertical direction in FIG. 1). In the diode portion 102, the anode region 13 has a linear (stripe-shaped) portion extending parallel to the extending direction of the gate trench 11.

[0026] In the transistor portion 101, parallel to the extending direction (longitudinal direction) of the gate trench 11, p + -type contact regions 5a and n + -type emitter regions 4a are provided alternately and periodically, and p + -type contact regions 5b and n + -type emitter regions 4b are provided alternately and periodically. The contact region 5a is in contact with the emitter region 4a. The contact region 5b is in contact with the emitter region 4b. The contact regions 5a and 5b are provided on the upper surface side of the base region 3 shown in FIG. 2. The lower surfaces of the contact regions 5a and 5b are in contact with the upper surface of the base region 3. The impurity concentration of the contact regions 5a and 5b is higher than that of the base region 3.

[0027] As shown in Figure 2, an interlayer insulating film 20 is provided on the upper surface of the semiconductor substrate 10 and the insulated gate type electrode structure (6,7). The interlayer insulating film 20 is composed of single-layer films such as undoped silicon oxide films (SiO2 films) that do not contain phosphorus (P) or boron (B), referred to as "NSG," phosphorus-doped silicon oxide films (PSG films), boron-doped silicon oxide films (BSG films), boron and phosphorus-doped silicon oxide films (BPSG films), silicon nitride films (Si3N4 films), and high-temperature oxide films (HTO films), or multilayer films of these.

[0028] The interlayer insulating film 20 located on the mesa portion between the gate trenches 11 of the semiconductor substrate 10 is provided with contact holes 20a that penetrate the interlayer insulating film 20. A trench (contact trench) 14 is provided in the mesa portion between the gate trenches 11 of the semiconductor substrate 10 so as to be continuous with the contact holes 20a. The contact trench 14 is provided in the depth direction perpendicular to the upper surface of the mesa portion of the semiconductor substrate 10.

[0029] Contact plugs 30 made of tungsten (W) or the like are embedded in the contact trench 14 and contact hole 20a via a titanium silicide (TiSi2) layer and a barrier metal film (not shown) made of titanium nitride (TiN).

[0030] Figure 3 shows an enlarged view of region A surrounding the contact trench 14 of the transistor section 101 in Figure 2. The surrounding areas of the other contact trenches 14 shown in Figure 2 have a similar structure to the enlarged view shown in Figure 3. As shown in Figure 3, the interlayer insulating film 20 comprises a first insulating film 21 made of an HTO film or the like, and a second insulating film 22 made of a BPSG film or the like, provided on the upper surface of the first insulating film 21. The thickness of the emitter regions 4a and 4b is, for example, approximately 0.3 μm or more and less than 0.6 μm. The spacing between adjacent gate trenches 11 is, for example, approximately 0.5 μm or more and 1.0 μm or less.

[0031] As shown in Figure 3, a contact trench 14 is provided above the emitter regions 4a and 4b, which are located in the mesa between adjacent gate trenches 11. The contact trench 14 has a tapered shape (forward taper shape) that narrows from the opening at the top towards the bottom. The width W1 of the opening of the contact trench 14 is wider than the width W2 of the bottom surface of the contact trench 14. The side walls of the contact trench 14 may be perpendicular to the upper surface of the emitter region 4.

[0032] The opening width W1 of the contact trench 14 is, for example, greater than 0.1 μm and less than or equal to 0.5 μm. The width W2 of the bottom of the contact trench 14 is, for example, 0.1 μm or more and less than 0.5 μm. The taper angle θ1 of the side wall of the contact trench 14 is, for example, 80° or more and less than 90°. The depth D1 from the opening to the bottom of the contact trench 14 is, for example, 0.2 μm or more and less than or equal to 1.0 μm.

[0033] Below the bottom surface of the contact trench 14, there is a higher impurity concentration of p than in the base region 3. + A contact area 15 of a specific type is provided. The bottom surface of the contact area 15 is located deeper than the bottom surfaces of the emitter areas 4a and 4b. The contact area 15 is in contact with the base area 3. The maximum lateral width of the contact area 15 is wider than the width W2 of the bottom of the contact trench 14. The contact area 15 makes ohmic contact with the contact plug 30. The contact area 15 reduces the contact resistance with the contact plug 30.

[0034] At the end of the contact trench 14 in the emitter region 4a, 4b that is in contact with the side wall surface, n + side wall injection regions 16a, 16b and n +The mold is provided with suppression regions 17a and 17b. The sides of the sidewall injection regions 16a and 16b are in contact with the sidewall surface of the contact trench 14. The upper ends of the sidewall injection regions 16a and 16b are in contact with the first insulating film 21. The lower ends of the sidewall injection regions 16a and 16b are in contact with the contact region 15. The width of the sidewall injection regions 16a and 16b is, for example, 0.05 μm or more and 0.2 μm or less.

[0035] The sidewall implantation regions 16a and 16b are n-type regions formed when p-type impurities are ion-implanted into the emitter regions 4a and 4b via the sidewall surface of the contact trench 14 during ion implantation of p-type impurities to form the contact region 15, if the contact trench 14 has a tapered shape. The sidewall implantation regions 16a and 16b have a lower impurity concentration than the emitter regions 4a and 4b because the n-type impurities are compensated for (canceled out) by the ion-implanted p-type impurities. However, because the impurity concentration in the emitter regions 4a and 4b is sufficiently high, they are in ohmic contact with the contact plug 30.

[0036] The suppression regions 17a and 17b are spaced apart from the contact trench 14 and are in contact with the sides of the side wall injection regions 16a and 16b that are opposite to the side wall surface of the contact trench 14. The upper ends of the suppression regions 17a and 17b are in contact with the first insulating film 21. The lower ends of the suppression regions 17a and 17b are in contact with the contact region 15. The lower ends of the suppression regions 17a and 17b extend to the underside of the bottom surface of the contact trench 14, surrounding the corner formed by the bottom surface and the side wall surface of the contact trench 14.

[0037] The suppression regions 17a and 17b are n-type regions formed by ion implantation of n-type impurities into the emitter regions 4a and 4b from an oblique upward direction via the sidewall surface of the contact trench 14. The suppression regions 17a and 17b have a higher impurity concentration than the sidewall implantation regions 16a and 16b in order to compensate for (cancel out) the p-type impurities ion-implanted into the sidewall implantation regions 16a and 16b. The side of the suppression regions 17a and 17b facing the emitter regions 4a and 4b may have a higher impurity concentration than the emitter regions 4a and 4b. The suppression regions 17a and 17b have the function of suppressing the lateral spread of p-type impurities by compensating for the p-type impurities ion-implanted into the sidewall implantation regions 16a and 16b.

[0038] The lower surface of the contact plug 30 embedded in the contact trench 14 makes ohmic contact with the contact region 15. The side surface of the contact plug 30 makes ohmic contact with the side wall injection regions 16a and 16b. In the diode section 102 shown in Figure 2, the contact plug 30 makes ohmic contact with the contact region 15 located above the anode region 13.

[0039] As shown in Figure 2, a surface electrode 40 is provided on the interlayer insulating film 20. In the transistor section 101, the surface electrode 40 is electrically connected to the emitter regions 4a, 4b and contact regions 5a, 5b via the contact plug 30 and functions as an emitter electrode. In the diode section 102, the surface electrode 40 is electrically connected to the anode region 13 via the contact plug 30 and functions as an anode electrode. The surface electrode 40 can be made of metals such as aluminum (Al), Al alloys, or copper (Cu). Examples of Al alloys include Al-silicon (Si), Al-Si-copper (Cu), and Al-Cu.

[0040] In Figure 1, the interlayer insulating film 20, surface electrode 40, side wall injection regions 16a, 16b, and suppression regions 17a, 17b shown in Figure 2 are omitted. The contact plug 30 has a linear (striped) portion that extends parallel to the longitudinal direction of the gate trench 11 on the planar pattern. The contact region 15 hidden beneath the contact plug 30 also extends parallel to the contact plug 30. In the transistor section 101, the contact plug 30 is provided between the emitter regions 4a, 4b and the contact regions 5a, 5b. In the diode section 102, the contact plug 30 is provided between the anode regions 13. Note that the contact plug 30 may be of other shapes, such as a hole shape, rather than being linear.

[0041] As shown in Figure 2, in the transistor section 101 and the diode section 102, an n-type field stop (FS) layer 8 with a higher impurity concentration than the drift layer 1 is provided on the lower side of the drift layer 1. The upper surface of the FS layer 8 is in contact with the lower surface of the drift layer 1. The FS layer 8 prevents the depletion layer, which extends from the lower side of the base region 3 and the anode region 13, from reaching the second main electrode region (collector region) 9 and the cathode region 12, which will be described later.

[0042] In the transistor section 101, on the lower side of the FS layer 8, p + A collector region 9 of type 1 is provided. The upper surface of the collector region 9 is in contact with the lower surface of the FS layer 8. The impurity concentration of the collector region 9 is higher than that of the base region 3. On the other hand, in the diode portion 102, the lower surface of the FS layer 8 has n with a higher impurity concentration than that of the FS layer 8. + A cathode region 12 of a certain type is provided. The upper surface of the cathode region 12 is in contact with the lower surface of the FS layer 8. The cathode region 12 is Collector area 9 It is located at the same depth. The side surface of the cathode region 12 is in contact with the side surface of the collector region 9.

[0043] A back electrode 50 is provided on the lower side of the collector region 9 and the cathode region 12. The back electrode 50 can be made of, for example, a single layer of gold (Au) or a metal film stacked in the order of titanium (Ti), nickel (Ni), and gold (Au). The back electrode 50 functions as a collector electrode in the transistor section 101 and as a cathode electrode in the diode section 102.

[0044] When the semiconductor device according to the first embodiment is in operation, in the transistor section 101, with the surface electrode 40 at ground potential, a positive voltage is applied to the back electrode 50, and a positive voltage above a threshold is applied to the gate electrode 7, an inversion layer (channel) is formed on the side of the gate trench 11 in the base region 3, and the device enters an ON state. In the ON state, current flows from the back electrode 50 to the surface electrode 40 via the collector region 9, FS layer 8, drift layer 1, storage layer 2, the inversion layer of the base region 3, and the emitter regions 4a and 4b.

[0045] On the other hand, if the voltage applied to the gate electrode 7 is below the threshold, an inversion layer is not formed in the base region 3, resulting in an off state, and no current flows from the back electrode 50 to the front electrode 40. The diode section 102 conducts a reverse current when the transistor section 101 turns off.

[0046] <Manufacturing method for semiconductor devices> Next, an example of a method for manufacturing a semiconductor device according to the first embodiment will be described. It should be noted that the method for manufacturing a semiconductor device described below is merely an example, and it is of course possible to achieve this through various other manufacturing methods, including this modification, as long as they fall within the scope of the claims.

[0047] First, as shown in Figure 4, the first conductivity type (n - A semiconductor substrate 10 made of a silicon (Si) wafer of a specific type is prepared. Next, a portion of the drift layer 1 is selectively removed from the upper surface of the semiconductor substrate 10 using photolithography and dry etching. As a result, as shown in Figure 5, a plurality of gate trenches 11 are formed on the upper surface of the semiconductor substrate 10.

[0048] Next, a gate insulating film 6 is formed on the bottom and sides of the gate trench 11 by thermal oxidation or chemical vapor deposition (CVD). Then, a polysilicon film (doped polysilicon film) with high concentrations of impurities such as phosphorus (P) and boron (B) is deposited by CVD or the like, filling the inside of the gate trench 11 through the gate insulating film 6. Subsequently, the polysilicon film and the gate insulating film 6 on the semiconductor substrate 10 are selectively removed by photolithography and dry etching. As a result, as shown in Figure 6, an insulated gate electrode structure (6,7) consisting of the gate insulating film 6 and the gate electrode 7 of the polysilicon film is formed inside the gate trench 11.

[0049] Next, the p of the transistor section 101 is applied to the entire upper surface of the drift layer 1. - p of the base region 3 and diode section 102 - p-type impurities such as boron (B) are ion-implanted to simultaneously form the anode region 13 of the type. After that, the photoresist film is removed.

[0050] Next, a photoresist film is applied to the upper surface of the drift layer 1, and the photoresist film is patterned using photolithography. The patterned photoresist film is used as an ion implantation mask to ion implant n-type impurities such as phosphorus (P) or arsenic (As) to form the n-type storage layer 2 of the transistor section 101. After that, the photoresist film is removed.

[0051] Next, a photoresist film is applied to the upper surface of the drift layer 1, and the photoresist film is patterned using photolithography. The patterned photoresist film is used as an ion implantation mask for the p of the transistor section 101. + p-type impurities such as boron (B) are ion-implanted to form the type contact regions 5a and 5b (see Figure 1). The photoresist film is then removed.

[0052] Next, a photoresist film is applied to the upper surface of the drift layer 1, and the photoresist film is patterned using photolithography technology. The patterned photoresist film is used as an ion implantation mask for the n of the transistor section 101. + N-type impurities are ion-implanted to form emitter regions 4a and 4b. The photoresist film is then removed. The order of ion implantation for forming the storage layer 2, the base region 3 and anode region 13, the emitter regions 4a and 4b, and the contact regions 5a and 5b is not particularly limited and can be changed.

[0053] Next, the impurity ions implanted in the semiconductor substrate 10 are activated by heat treatment. As a result, as shown in Figure 7, in the transistor section 101, an n-type storage layer 2 and a p-type storage layer are formed on the upper part of the semiconductor substrate 10. - Base region of type 3, n + emitter region 4 and p of type + A type of contact region (see Figure 1) is formed. Also, in the diode portion 102, p is formed on the upper part of the semiconductor substrate 10. - A type anode region 13 is formed.

[0054] Next, an interlayer insulating film 20 is deposited on the upper surfaces of the insulated gate electrode structure (6,7), emitter region 4, and anode region 13 using a CVD method or the like. Then, a photoresist film is applied to the upper surface of the interlayer insulating film 20, and the photoresist film is patterned using photolithography. Using the patterned photoresist film as an etching mask, a portion of the interlayer insulating film 20 is selectively removed by dry etching. As a result, contact holes 20a are opened in the interlayer insulating film 20, exposing a portion of the emitter region 4 and anode region 13. Furthermore, using the interlayer insulating film 20 as an etching mask, a portion of the emitter region 4 and anode region 13 is selectively removed by dry etching. As a result, as shown in Figure 8, a contact trench 14 is formed above the emitter region 4 and anode region 13, continuous with the contact holes 20a.

[0055] Figure 9 is a cross-sectional view of the process following Figure 8, and is an enlarged view of region A in Figure 8. As shown in Figure 9, n-type impurities such as phosphorus (P) are ion-implanted into the side walls of both contact trenches 14 from two oblique upward directions that are oblique to the vertical direction of the bottom surface of the contact trench 14. Examples of n-type impurities that can be ion-implanted include phosphorus (P), arsenic (As), nitrogen (N), etc., and here we will use P. Ion implantation into one side wall of the contact trench 14 (right side in Figure 9) and ion implantation into the other side wall of the contact trench 14 (left side in Figure 9) may be performed simultaneously from both directions, or sequentially from one direction at a time.

[0056] The ion implantation angle θ2 is, for example, between 5° and 15° with respect to the vertical direction of the bottom surface of the contact trench 14. The ion implantation angle θ2 can be appropriately adjusted depending on the depth, opening width, taper angle, etc. of the contact trench 14. The ion implantation acceleration energy is, for example, between 30 keV and 200 keV. The ion implantation dose is, for example, 3 × 10⁻⁶. 13 ions / cm 2 The above is 1 x 10 15 ions / cm 2 The following is the extent of 5 x 10 13 ions / cm 2 The above is 1 x 10 14 ions / cm 2 The following conditions are more preferable. By injecting n-type impurities under these conditions, the lateral diffusion of p-type impurities injected in subsequent processes can be suppressed. If the contact plug 30 has a hole shape or other shape, the impurities can be injected from multiple directions in separate steps.

[0057] When ion implanting n-type impurities as shown in Figure 9, ions are implanted into the entire side wall surface of the contact trench 14. Ion implantation is also performed so as to include the corner formed by the bottom surface and the side wall surface of the contact trench 14. The width W4 of the end of the bottom surface of the contact trench 14 that is ion implanted is, for example, about 1 / 10 to 1 / 4 of the total width W2 of the bottom surface of the contact trench 14. Alternatively, ions may be implanted only into the entire side wall surface of the contact trench 14, excluding the corner formed by the bottom surface and the side wall surface of the contact trench 14.

[0058] Furthermore, ion implantation is performed in a manner that avoids the central part of the bottom surface of the contact trench 14. The width W3 of the central part of the bottom surface of the contact trench 14 that is not ion implanted is, for example, between 1 / 2 and 4 / 5 of the total width W2 of the bottom surface of the contact trench 14. By avoiding ion implantation in the central part of the bottom surface of the contact trench 14, an increase in contact resistance can be suppressed. By setting these conditions, it is possible to suppress the lateral diffusion of p-type impurities ion-implanted in the central part of the bottom surface of the contact trench 14 without affecting the resistance value of the contact region 15. Note that if the dose of n-type impurities implanted into the side walls of the contact trench 14 is more than an order of magnitude lower than the dose of p-type impurities implanted into the bottom surface of the contact trench 14, the n-type impurities implanted in the central part of the bottom surface of the contact trench 14 will be negligibly low, so it is not necessary to avoid the central part.

[0059] Next, as shown in Figure 10, p-type impurities are ion-implanted into the bottom surface of the contact trench 14. For example, p-type impurities are ion-implanted into the bottom surface of the contact trench 14 from a direction approximately perpendicular to the bottom surface of the contact trench 14. Examples of p-type impurities that can be ion-implanted include boron (B), boron fluoride (BF2), and aluminum (Al), and here we will use BF2. When ion-implanting p-type impurities as shown in Figure 10, if the contact trench 14 has a tapered shape, p-type impurities are ion-implanted not only into the bottom surface of the contact trench 14 but also into the side walls on both sides of the contact trench 14.

[0060] The dose for ion implantation of p-type impurities in Figure 10 is, for example, 3 × 10⁻⁶. 15 ions / cm 2 The above 5 x 10 15 ions / cm 2 The following is an example: Comparing the ion implantation of n-type impurities in Figure 9 with that of p-type impurities in Figure 10, the dose for ion implantation of n-type impurities in Figure 9 is lower than the dose for vertical ion implantation of p-type impurities in Figure 10. The dose for ion implantation of n-type impurities in Figure 9 is, for example, between 1% and 10% of the dose for vertical ion implantation of p-type impurities in Figure 10.

[0061] The acceleration energy for ion implantation of p-type impurities in Figure 10 is, for example, between 10 keV and 50 keV. Comparing the ion implantation of n-type impurities in Figure 9 with that of p-type impurities in Figure 10, the acceleration energy for ion implantation of n-type impurities in Figure 9 is higher than that for p-type impurities in Figure 10. Therefore, the ion-implanted n-type impurities in Figure 9 are implanted at a deeper position perpendicular to the sidewall surface of the contact trench 14 than the ion-implanted p-type impurities in Figure 10.

[0062] During ion implantation of p-type impurities as shown in Figure 10, the p-type impurities implanted on the bottom surface of the contact trench 14 are distributed in the depth direction according to a Gaussian distribution, depending on the ion species and acceleration energy. Furthermore, the p-type impurities collide with and scatter interstitial atoms of the semiconductor substrate 10, and are distributed laterally, extending beyond the width W2 of the bottom surface of the contact trench 14. In addition, p-type impurities implanted on the side walls of the contact trench 14 also collide with and scatter interstitial atoms of the semiconductor substrate 10, and are distributed laterally.

[0063] In the semiconductor device manufacturing method according to the first embodiment, an example was given in which ion implantation of p-type impurities (as shown in Figure 10) is performed after ion implantation of n-type impurities (as shown in Figure 9). However, the order of ion implantation is not limited. That is, ion implantation of n-type impurities (as shown in Figure 9) may be performed after ion implantation of p-type impurities (as shown in Figure 10).

[0064] After ion implantation of n-type impurities (Figure 9) and p-type impurities (Figure 10), the implanted n-type and p-type impurities are activated by heat treatment such as rapid short-time heat treatment (RTA). In the case of RTA, the n-type and p-type impurities hardly diffuse. As a result, as shown in Figure 11, p-type impurities are implanted on the underside of the bottom surface of the contact trench 14, in contact with the base region 3. + A type contact region 15 is formed. The contact region 15 is the region where p-type impurities were ion-implanted on the bottom surface of the contact trench 14 during the ion implantation of p-type impurities as shown in Figure 10. The emitter region 4 is divided by the contact region 15, becoming emitter regions 4a and 4b adjacent to the contact region 15.

[0065] Furthermore, in the regions of the emitter regions 4a and 4b that are in contact with the side walls of the contact trenches 14, n + Side wall implantation regions 16a and 16b are formed. Side wall implantation regions 16a and 16b are the regions where p-type impurities were ion-implanted on the side wall surface of the contact trench 14 during ion implantation of p-type impurities as shown in Figure 10.

[0066] Furthermore, in the emitter regions 4a and 4b, on the side opposite to the side wall surface of the contact trench 14 in the side wall injection regions 16a and 16b, n + The following suppression regions 17a and 17b are formed. The suppression regions 17a and 17b are the regions where n-type impurities are ion-implanted between the side wall surface of the contact trench 14 and the corner formed by the side wall surface and bottom surface of the contact trench 14 during ion implantation of n-type impurities as shown in Figure 9.

[0067] The suppression regions 17a and 17b compensate (cancel out) the p-type impurities in the sidewall injection regions 16a and 16b, thereby reducing the lateral spread of p-type impurities in the sidewall injection regions 16a and 16b. Furthermore, the lower parts of the suppression regions 17a and 17b compensate (cancel out) the p-type impurities in the upper part near the side surface of the contact region 15, thereby reducing the lateral spread of p-type impurities in the contact region 15.

[0068] Next, contact plugs 30 are embedded in the contact trenches 14 and contact holes 20a via a barrier metal film using sputtering, vapor deposition, or dry etching. Then, as shown in Figure 12, surface electrodes 40 are deposited on the upper surfaces of the contact plugs 30 and the interlayer insulating film 20 using sputtering or vapor deposition.

[0069] Next, the semiconductor substrate 10 is ground from the bottom side by back grinding or chemical mechanical polishing (CMP) to adjust the thickness of the semiconductor substrate 10 to the product thickness. Then, n-type impurities such as phosphorus (P) or selenium (Se) are ion-implanted over the entire bottom surface of the semiconductor substrate 10 to form an n-type FS layer 8.

[0070] Next, at an acceleration energy lower than the ion implantation acceleration energy for forming the n-type FS layer 8 across the entire lower surface of the semiconductor substrate 10, p + p-type impurities such as boron (B) are ion-implanted to form a collector region 9 of the type.

[0071] Next, a photoresist film is applied to the underside of the drift layer 1, and the photoresist film is patterned using photolithography. The patterned photoresist film is used as an ion implantation mask, n + n-type impurities such as phosphorus (P) are ion-implanted to form a cathode region 12 of type n.

[0072] Next, the impurity ions implanted in the semiconductor substrate 10 are activated by heat treatment. As a result, as shown in Figure 13, an n-type FS layer 8 is formed at the bottom of the semiconductor substrate 10. Also, in the transistor section 101, p + A collector region 9 of type 9 is formed, and in the diode section 102, n + A cathode region 12 of the type is formed.

[0073] Next, a back surface electrode 50 made of gold (Au) or the like is formed on the entire lower surface of the semiconductor substrate 10 by sputtering or vapor deposition. After that, the semiconductor device according to the first embodiment shown in Figures 1 to 3 is completed by cutting (dicing) the semiconductor substrate 10 into individual pieces.

[0074] Here, a method for manufacturing a semiconductor device according to a comparative example will be described. The method for manufacturing a semiconductor device according to the comparative example differs from the method for manufacturing a semiconductor device according to the first embodiment in that, of the ion implantation of n-type impurities in Figure 9 and the ion implantation of p-type impurities in Figure 10, only the ion implantation of p-type impurities in Figure 10 is performed, without performing the ion implantation of n-type impurities in Figure 9. The other steps in the method for manufacturing a semiconductor device according to the comparative example are the same as those in the method for manufacturing a semiconductor device according to the first embodiment.

[0075] After ion implantation of p-type impurities as shown in Figure 10, heat treatment is performed, resulting in the p-type impurities being placed on the underside of the bottom surface of the contact trench 14, as shown in Figure 14. + A type-type contact region 15 is formed. n-type sidewall injection regions 16a and 16b are formed in the regions of the emitter regions 4a and 4b that are in contact with the sidewall surfaces of the contact trenches 14, but suppression regions 17a and 17b as shown in Figure 11 are not formed.

[0076] In the semiconductor device manufacturing method according to the comparative example, similar to the semiconductor device manufacturing method according to the first embodiment, when p-type impurities are ion-implanted on the bottom and side walls of the contact trench 14 as shown in Figure 10, the p-type impurities ion-implanted collide with interstitial atoms of the semiconductor substrate 10 and scatter, spreading and distributing laterally. As miniaturization progresses and the mesa region between the gate trenches 11 narrows, the p-type impurities scattered during ion implantation of p-type impurities as shown in Figure 10 reach the vicinity of the gate trenches 11, increasing the impurity concentration (channel carrier concentration) in the base region 3. As a result, fluctuations (increases) and variations in the gate threshold voltage occur. Therefore, in order to stabilize the electrical characteristics, the miniaturization of the opening width W1 of the contact trench 14 and the width of the mesa region between the gate trenches 11 is limited.

[0077] In contrast, according to the semiconductor device manufacturing method of the first embodiment, by performing ion implantation of n-type impurities as shown in Figure 9, an n-type impurity of the opposite conductivity type to that of p-type impurities as shown in Figure 10 is doped, and suppression regions 17a and 17b are formed to cover the sides of the side wall implantation regions 16a and 16b. This makes it possible to compensate for the p-type impurities implanted on the side wall surface of the contact trench 14 during ion implantation of p-type impurities as shown in Figure 10, and to suppress the lateral spread of p-type impurities.

[0078] Furthermore, since the suppression regions 17a and 17b are formed to cover the upper part of the side surface of the contact region 15, the lateral spread of p-type impurities in the contact region 15 can be suppressed. Moreover, by extending the lower ends of the suppression regions 17a and 17b down to below the bottom surface of the contact trench 14 so as to surround the corner formed by the bottom surface and side wall surface of the contact trench 14, the lateral spread of p-type impurities in the contact region 15 can be further suppressed.

[0079] In this way, the lateral spread of p-type impurities injected into the side walls of the contact trench 14 and the p-type impurities in the lower contact region 15 of the bottom surface of the contact trench 14 can be suppressed, thereby suppressing fluctuations (increases) and variations in the gate threshold voltage. As a result, the opening width W1 of the contact trench 14 and the width of the mesa between the gate trenches 11 can be narrowed, enabling miniaturization of the semiconductor device.

[0080] Furthermore, it eliminates the need for other ultra-shallow implantation devices such as plasma immersion doping devices and cluster ion implanters, making it possible to form shallow junctions using conventional ion implanters.

[0081] Figure 15 shows the simulation results for the relationship between dose, acceleration energy, and lateral diffusion distance of P during ion implantation of the n-type impurity shown in Figure 9. The conditions for ion implantation of the n-type impurity shown in Figure 9 are as follows: P is used as the n-type impurity, the acceleration energy is varied from 40 keV to 140 keV, and the dose is 1 × 10⁻⁶. 13ions / cm 2 ~1 × 10 15 ions / cm 2 The conditions for ion implantation of p-type impurities in Figure 10 were as follows: BF2 was used as the p-type impurity, the acceleration voltage was 30 keV, and the dose was 3 × 10⁻⁶. 15 ions / cm 2 The injection angle θ2 was set to 0°.

[0082] As shown in Figure 15, it can be seen that the lateral diffusion of P is suppressed as the dose and acceleration energy increase. Furthermore, by adjusting the acceleration energy, the dose can be increased to 5 × 10⁻⁶. 13 ions / cm 2 ~1 × 10 15 / ions / cm 2 In this case, the dose is 1 × 10 13 ions / cm 2 It can be seen that the lateral diffusion distance can be reduced to approximately L1, which is half of the lateral diffusion distance L2 in the case shown.

[0083] Figure 16 shows the simulation results for the relationship between the dose, implantation angle (tilt angle), and lateral diffusion distance of P during ion implantation of the n-type impurity shown in Figure 9. The conditions for ion implantation of the n-type impurity in Figure 9 are as follows: P is used as the n-type impurity, the acceleration energy is 120 keV, and the dose is 1 × 10⁻⁶. 12 ions / cm 2 ~1 × 10 15 ions / cm 2 The implantation angle θ2 was varied from 9° to 13°. The conditions for ion implantation of p-type impurities in Figure 10 were as follows: BF2 was used as the p-type impurity, the acceleration energy was 30 keV, and the dose was 3 × 10⁻⁶. 15 ions / cm 2 The injection angle θ2 was set to 0°.

[0084] As shown in Figure 16, it can be seen that the lateral diffusion of P is suppressed as the dose increases. Also, when the dose is 5 × 10⁻⁶ 13 ions / cm 2 ~1 × 10 15 ions / cm2 In this case, the dose is 1 × 10 12 ions / cm 2 ~1 × 10 13 ions / cm 2 It can be seen that the lateral diffusion distance can be reduced to approximately L1, which is half of the lateral diffusion distance L2 in the case shown.

[0085] (Second Embodiment) The method for manufacturing a semiconductor device according to the second embodiment is as shown in Figure 17, when forming the contact trench 14, n + The manufacturing method of the semiconductor device according to the first embodiment differs in that the contact trench 14 is formed so as to penetrate the emitter regions 4a and 4b of the type. The bottom surface of the contact trench 14 is p - It is located inside the base region 3 of the type.

[0086] In the semiconductor device manufacturing method according to the second embodiment, n-type impurities are ion-implanted into the side walls on both sides of the contact trench 14, from an oblique direction relative to the vertical direction of the bottom surface of the contact trench 14 shown in Figure 17, similar to the ion implantation of n-type impurities in Figure 9. At this time, the ion implantation is carried out in a manner that includes the corners formed by the bottom surface and side walls of the contact trench 14, while avoiding the central part of the bottom surface of the contact trench 14. Also, similar to the ion implantation of p-type impurities in Figure 10, p-type impurities are ion-implanted into the bottom surface of the contact trench 14, from a direction perpendicular to the bottom surface of the contact trench 14 shown in Figure 17.

[0087] Subsequently, by heat treatment, as shown in Figure 17, p is formed on the underside of the bottom surface of the contact trench 14. + A contact region 15 of a certain type is formed. The contact region 15 is formed inside the base region 3. The side surface is in contact with the side wall surface of the contact trench 14. + The side wall injection regions 16a and 16b of the mold are formed. The side wall injection regions 16a and 16b are in contact with the side opposite to the side wall surface of the contact trench 14. + Type-specific suppression regions 17a and 17b are formed.

[0088] Other steps in the method for manufacturing the semiconductor device according to the second embodiment are the same as those in the method for manufacturing the semiconductor device according to the first embodiment, so redundant explanations will be omitted.

[0089] According to the semiconductor device manufacturing method of the second embodiment, even when the contact trench 14 penetrates the emitter regions 4a and 4b, the lateral spread of p-type impurities injected into the side wall surface of the contact trench 14 and the p-type impurities in the contact region 15 below the bottom surface of the contact trench 14 can be suppressed, thereby suppressing fluctuations (increases) and variations in the gate threshold voltage.

[0090] (Third embodiment) The method for manufacturing a semiconductor device according to the third embodiment is as shown in Figure 18, when forming the contact trench 14, n + The method for manufacturing a semiconductor device according to the second embodiment is similar in that it forms a contact trench 14 so as to penetrate the emitter regions 4a and 4b of the type. However, the method for manufacturing a semiconductor device according to the third embodiment is different in that the lower side of the bottom surface of the contact trench 14 is p + The contact area 15 of type p - The difference from the semiconductor device manufacturing method according to the second embodiment is that it penetrates the base region 3 of the type and reaches the upper part of the n-type storage layer 2.

[0091] In the semiconductor device manufacturing method according to the third embodiment, similar to the ion implantation of n-type impurities in Figure 9, 18 n-type impurities are ion-implanted into the side walls of the contact trench 14, as shown in Figure 10, from an oblique direction relative to the vertical direction of the bottom surface of the contact trench 14. During this process, the ion implantation is carried out in a manner that includes the corners formed by the bottom surface and side walls of the contact trench 14, while avoiding the central part of the bottom surface of the contact trench 14. Furthermore, similar to the ion implantation of p-type impurities in Figure 10, 18 A p-type impurity is ion-implanted into the bottom surface of the contact trench 14 from a direction perpendicular to the bottom surface of the contact trench 14 shown in the diagram.

[0092] Subsequently, by heat treatment, as shown in Figure 18, p is formed on the underside of the bottom surface of the contact trench 14. + A contact region 15 of the type is formed. The side surface is in contact with the side wall surface of the contact trench 14. + The side wall injection regions 16a and 16b of the mold are formed. The side wall injection regions 16a and 16b are in contact with the side opposite to the side wall surface of the contact trench 14. + Type-specific suppression regions 17a and 17b are formed.

[0093] Other steps in the manufacturing method of the semiconductor device according to the third embodiment are the same as those in the manufacturing method of the semiconductor device according to the first embodiment, so redundant explanations will be omitted.

[0094] According to the semiconductor device manufacturing method of the third embodiment, even when the contact trench 14 penetrates the emitter regions 4a and 4b and the contact region 15 reaches the top of the storage layer 2, the lateral spread of p-type impurities injected into the side wall surface of the contact trench 14 and the p-type impurities in the contact region 15 below the bottom surface of the contact trench 14 can be suppressed, thereby suppressing fluctuations (increases) and variations in the gate threshold voltage.

[0095] (Fourth embodiment) The method for manufacturing a semiconductor device according to the fourth embodiment differs from the method for manufacturing a semiconductor device according to the first embodiment in that, as shown in Figure 19, one of the adjacent gate trenches 11 (the one on the right in Figure 19) is a dummy trench, and the other gate trench 11 (the one on the left in Figure 19) is a gate trench that functions as an IGBT.

[0096] In the semiconductor device manufacturing method according to the fourth embodiment, instead of ion implanting n-type impurities as shown in Figure 9, as shown in Figure 19, n-type impurities are ion implanted into the left gate trench 11 side wall, which is the gate trench portion functioning as an IGBT, among the side walls of the contact trench 14 on both sides. At this time, the ion implantation is carried out including the corner formed by the bottom surface and the side wall surface of the contact trench 14, while avoiding the central part of the bottom surface of the contact trench 14. On the other hand, n-type impurities are not ion implanted into the right gate trench 11 side wall, which is the dummy trench portion.

[0097] Furthermore, similar to the ion implantation of p-type impurities in Figure 10, p-type impurities are ion-implanted into the bottom surface of the contact trench 14, as shown in Figure 19, from a direction perpendicular to the bottom surface of the contact trench 14.

[0098] Subsequently, by performing heat treatment, as shown in Figure 20, p is formed on the underside of the bottom surface of the contact trench 14. + A contact region 15 of the type is formed. The side surface is in contact with the side wall surface of the contact trench 14. + The side wall injection regions 16a and 16b of the mold are formed. Also, on the left side, which is the gate trench 11, the side wall injection region 16a is in contact with the side opposite to the side wall surface of the contact trench 14. + A type of suppression region 17a is formed. On the other hand, on the right side of the gate trench 11, which is a dummy trench, n + A type-specific inhibition region is not formed.

[0099] Other steps in the manufacturing method of the semiconductor device according to the fourth embodiment are the same as those in the manufacturing method of the semiconductor device according to the first embodiment, so redundant explanations will be omitted.

[0100] According to the semiconductor device manufacturing method of the fourth embodiment, if one of the adjacent gate trenches 11 is a dummy trench or the like and does not function as an element, ion implantation of n-type impurities is selectively performed on the side wall surface of the contact trench 14 that functions as an element. This suppresses the lateral spread of p-type impurities implanted on the side wall surface of the contact trench 14 and the p-type impurities in the contact region 15 below the bottom surface of the contact trench 14 toward the side that functions as an element, thereby suppressing fluctuations (increases) and variations in the gate threshold voltage.

[0101] (Other embodiments) Although the first to fourth embodiments have been described above, the descriptions and drawings that constitute part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure.

[0102] For example, while RC-IGBTs were used as examples of semiconductor devices according to the first to fourth embodiments, the method is also applicable to IGBTs other than RC-IGBTs. For example, it is applicable to reverse-blocking insulated-gate bipolar transistors (RB-IGBTs) and to IGBTs alone. Also, the p of the IGBT in the transistor section 101 shown in Figure 2 + The collector area 9 of type n + This can also be applied to MOSFETs with a drain region of a certain type.

[0103] Furthermore, the configurations disclosed in the first to fourth embodiments can be combined as appropriate, within a non-contradictory range. Thus, it goes without saying that the present invention includes various embodiments not described herein. Therefore, the technical scope of the present invention is determined solely by the inventive features relating to the claims that are appropriate from the above description. [Explanation of Symbols]

[0104] 1…Drift layer 2…Accumulation layer 2…Accumulation layer 3…Base area 4, 4a, 4b... Emitter region 5a, 5b... Contact area 6…Gate insulating film 7… Gate gate 8…Field Stop (FS) Layer 9...Collector area 10… Semiconductor substrates 11…Trench (gate trench) 12... Cathode region 13…Anode region 14…Trench coat (contact trench coat) 15… Contact area 16a, 16b…side wall injection area 17a,17b...Suppression area 20…Interlayer insulating film 20a... Contact hole 21…First insulating film 22...Second insulating film 30... Contact plug 40…Surface electrode 50…Back electrode 101... Transistor section 102... Diode section

Claims

1. A step of forming a first trench from the upper surface side of a first-conductivity semiconductor substrate, The process involves embedding an insulated gate type electrode structure in the first trench, A step of forming a base region of a second conductivity type on the upper part of the semiconductor substrate in contact with the first trench, A step of forming a first main electrode region of a first conductivity type in contact with the first trench on the upper part of the base region, A step of removing a portion of the first main electrode region to form a second trench, The process involves ion implanting a first impurity of the first conductivity type onto the entire side wall surface of the second trench from an oblique upward direction, The process involves forming a contact region of the second conductivity type at the bottom of the second trench by ion implanting a second impurity of the second conductivity type into the bottom of the second trench, The process of forming a second main electrode region of a second conductivity type on the lower surface side of the semiconductor substrate, Includes, A method for manufacturing a semiconductor device, characterized in that the step of ion implanting the first impurity includes the corner formed by the bottom surface of the second trench and the side wall surface of the second trench.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that the step of ion implanting the first impurity is performed while avoiding the central part of the bottom surface of the second trench.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that the opening width of the second trench is wider than the width of the bottom surface of the second trench.

4. The method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that the step of ion implanting the first impurity is performed by ion implanting on the side walls on both sides of the second trench.

5. A step of forming a first trench from the upper surface side of a semiconductor substrate of a first conductivity type, The process involves embedding an insulated gate type electrode structure in the first trench, A step of forming a base region of a second conductivity type on the upper part of the semiconductor substrate in contact with the first trench, A step of forming a first main electrode region of a first conductivity type in contact with the first trench on the upper part of the base region, A step of removing a portion of the first main electrode region to form a second trench, The process involves ion implanting a first impurity of the first conductivity type onto the entire side wall surface of the second trench from an oblique upward direction, The process involves forming a contact region of the second conductivity type at the bottom of the second trench by ion implanting a second impurity of the second conductivity type into the bottom of the second trench, The process of forming a second main electrode region of a second conductivity type on the lower surface side of the semiconductor substrate, Includes, A method for manufacturing a semiconductor device, characterized in that the step of ion implanting the first impurity is performed by ion implanting only one side wall surface of the second trench.

6. The method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that the dose amount for ion implantation of the first impurity is 1% or more and 10% or less relative to the dose amount for ion implantation of the second impurity.

7. The method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that the acceleration energy for ion implantation of the first impurity is higher than the acceleration energy for ion implantation of the second impurity.

8. A step of forming a first trench from the upper surface side of a semiconductor substrate of a first conductivity type, The process involves embedding an insulated gate type electrode structure in the first trench, A step of forming a base region of a second conductivity type on the upper part of the semiconductor substrate in contact with the first trench, A step of forming a first main electrode region of a first conductivity type in contact with the first trench on the upper part of the base region, A step of removing a portion of the first main electrode region to form a second trench, The process involves ion implanting a first impurity of the first conductivity type onto the entire side wall surface of the second trench from an oblique upward direction, The process involves forming a contact region of the second conductivity type at the bottom of the second trench by ion implanting a second impurity of the second conductivity type into the bottom of the second trench, The process of forming a second main electrode region of a second conductivity type on the lower surface side of the semiconductor substrate, Includes, A method for manufacturing a semiconductor device, characterized in that the first impurity is phosphorus and the second impurity is boron.

9. The step of forming the second trench involves forming the second trench such that the bottom surface of the second trench is located inside the first main electrode region. The step of forming the contact region is to form the contact region so as to be in contact with the base region. A method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that it is as described above.

10. The step of forming the second trench involves forming the second trench such that the bottom surface of the second trench is located inside the base region. The step of forming the contact region is to form the contact region so as to be in contact with the base region. A method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that it is as described above.

11. A method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that the insulated gate electrode structure, the base region, the first main electrode region, and the second main electrode region constitute an insulated gate bipolar transistor.

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