Nitride semiconductor device and method for manufacturing a nitride semiconductor device

Abstract

To provide a nitride semiconductor device and a method for manufacturing the same with which it is possible to secure high breakdown voltage and secure high electron mobility to be usable for base stations for mobile phone communication, communication devices for radio astronomy, and communication devices for satellite communication.SOLUTION: A nitride semiconductor device 1 comprises: a channel layer 22; a barrier layer 24 including In on the channel layer; an n-type first nitride semiconductor layer 30S; an n-type second nitride semiconductor layer 30D; a source electrode 40S; a drain electrode 40D; and a gate electrode 40G disposed on the barrier layer between the source electrode and the drain electrode in a plan view. A first recess 20S and a second recess 20D are formed in the barrier layer and the channel layer by being spaced from each other. The first nitride semiconductor layer is formed in the first recess, but is not formed on the barrier layer, and the second nitride semiconductor layer has a first region 31 existing inside of an upper edge of the second recess in a plan view and a second region 32 on the barrier layer leading to the first region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a nitride semiconductor device and a method for manufacturing a nitride semiconductor device. [Background Art]

[0002] A high electron mobility transistor (HEMT) using a GaN-based nitride semiconductor can operate at high output and is used as a transmission-side element in wireless communication, radar, and the like. In recent years, higher output has been demanded in order to extend the wireless communication distance and the radar detection distance. For higher output, a structure using InAlGaN containing In as a barrier layer has been studied.

[0003] Also, in HEMTs, a technique of using a low-resistance regrowth layer containing impurities at a high concentration to reduce the ohmic resistance of the source electrode and the drain electrode has also been studied. [Prior Art Documents] [Patent Documents]

[0004] [Patent Document 1] Japanese National Publication of International Patent Application No. 2017-539073 [Patent Document 2] U.S. Pat. No. 9,252,247 [Patent Document 3] U.S. Patent Application Publication No. 2022 / 0140126 [Patent Document 4] Japanese Patent Laid-Open No. 2016-115931 [Summary of Invention] [Problem to be Solved by Invention]

[0005] When a regrowth layer is combined with a structure using InAlGaN as a barrier layer, it is difficult to achieve both ensuring high breakdown voltage and ensuring high electron mobility. A decrease in breakdown voltage can lead to a decrease in yield.

[0006] The object of this disclosure is to provide a nitride semiconductor device and a method for manufacturing a nitride semiconductor device that can achieve both high voltage resistance and high electron mobility. [Means for solving the problem]

[0007] According to one embodiment of the present disclosure, a nitride semiconductor device is provided, comprising: a channel layer; an In-containing barrier layer on the channel layer; an n-type first nitride semiconductor layer; an n-type second nitride semiconductor layer; a source electrode provided on the first nitride semiconductor layer; a drain electrode provided on the second nitride semiconductor layer; and a gate electrode provided on the barrier layer between the source electrode and the drain electrode in a plan view, wherein a first recess and a second recess are formed in the barrier layer and the channel layer, apart from each other; the first nitride semiconductor layer is formed in the first recess and not on the barrier layer; and the second nitride semiconductor layer has a first region located inside the upper edge of the second recess in a plan view, and a second region connected to the first region and on the barrier layer. [Effects of the Invention]

[0008] According to this disclosure, it is possible to achieve both high voltage resistance and high electron mobility. [Brief explanation of the drawing]

[0009] [Figure 1] This is a cross-sectional view showing the structure of a nitride semiconductor device according to the first embodiment. [Figure 2] This is a cross-sectional view showing an enlarged portion of Figure 1. [Figure 3] This is a cross-sectional view (part 1) showing a method for manufacturing a nitride semiconductor device according to the first embodiment. [Figure 4] This is a cross-sectional view (part 2) showing a method for manufacturing a nitride semiconductor device according to the first embodiment. [Figure 5] This is a cross-sectional view (part 3) showing a method for manufacturing a nitride semiconductor device according to the first embodiment. [Figure 6] It is a cross-sectional view (part 4) illustrating the method for manufacturing a nitride semiconductor device according to the first embodiment. [Figure 7] It is a cross-sectional view (part 5) illustrating the method for manufacturing a nitride semiconductor device according to the first embodiment. [Figure 8] It is a cross-sectional view (part 6) illustrating the method for manufacturing a nitride semiconductor device according to the first embodiment. [Figure 9] It is a cross-sectional view (part 7) illustrating the method for manufacturing a nitride semiconductor device according to the first embodiment. [Figure 10] It is a cross-sectional view (part 8) illustrating the method for manufacturing a nitride semiconductor device according to the first embodiment. [Figure 11] It is a cross-sectional view (part 9) illustrating the method for manufacturing a nitride semiconductor device according to the first embodiment. [Figure 12] It is a diagram showing a discrete package according to the second embodiment. [Figure 13] It is a wiring diagram showing a PFC circuit according to the third embodiment. [Figure 14] It is a wiring diagram showing a power supply device according to the fourth embodiment. [Figure 15] It is a wiring diagram showing an amplifier according to the fifth embodiment. DESCRIPTION OF EMBODIMENTS

[0010] The inventors of the present application have conducted intensive studies to investigate the cause why it is difficult to ensure both high breakdown voltage and high electron mobility when the barrier layer contains In in a conventional nitride semiconductor device including a regrown layer. As a result, it has been found that when a regrown layer is formed at a low temperature to avoid detachment of In from an already formed barrier layer, pits are likely to be formed in the regrown layer. The portion of the regrown layer where a pit is formed becomes thinner than a designed value, resulting in high resistance. For this reason, an electric field tends to concentrate in the portion of the regrown layer where the pit is formed, which leads to a decrease in breakdown voltage. On the other hand, when the regrown layer is formed at a high temperature to avoid the formation of pits, In detaches from the barrier layer, the concentration of two-dimensional electron gas (two dimensional gas: 2DEG) decreases, and electron mobility decreases. Based on these findings, the inventors of the present application conducted intensive studies to achieve both high breakdown voltage and high electron mobility, and arrived at the embodiments described below.

[0011] Hereinafter, embodiments of the present disclosure will be specifically described with reference to the accompanying drawings. In the present specification and the drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to omit redundant description.

[0012] (First Embodiment) First, the first embodiment will be described. The first embodiment relates to a GaN-based HEMT, that is, a nitride semiconductor device including a field effect transistor (field effect transistor: FET). FIG. 1 is a cross-sectional view showing the structure of the nitride semiconductor device according to the first embodiment.

[0013] As shown in FIG. 1, the nitride semiconductor device 1 according to the first embodiment includes a substrate 10, an epitaxial layer 20, a first nitride semiconductor layer 30S, a second nitride semiconductor layer 30D, a source electrode 40S, a drain electrode 40D, a gate electrode 40G, and a passivation film 50.

[0014] The epitaxial layer 20 is provided on the substrate 10. The epitaxial layer 20 includes, for example, a buffer layer 21, a channel layer 22, a spacer layer 23, and a barrier layer 24.

[0015] The substrate 10 is, for example, a SiC substrate. The buffer layer 21 is provided on the substrate 10. The buffer layer 21 is, for example, an AlN layer, a GaN layer, or an AlGaN layer. The buffer layer 21 may have a superlattice structure including both an AlN layer and a GaN layer.

[0016] The channel layer 22 is provided on the buffer layer 21. The channel layer 22 is, for example, a GaN layer not intentionally doped with impurities that impart conductivity type (i-GaN layer). The thickness of the channel layer 22 is, for example, 1 μm to 5 μm.

[0017] The spacer layer 23 is provided on the channel layer 22. The spacer layer 23 is, for example, an AlN layer or an AlGaN layer. The thickness of the spacer layer 23 is, for example, 0.5 nm to 5 nm.

[0018] The barrier layer 24 is provided on the spacer layer 23. The barrier layer 24 contains In. The barrier layer 24 is, for example, an n-type InAlGaN layer. The composition of the barrier layer 24 is, for example, In 1-x-y Al x Ga y N represented by InxAlyGa1-x-yN (0≦x<1, 0≦y<1, 0<x+y<1). The thickness of the barrier layer 24 is, for example, 4 nm to 10 nm. The epitaxial layer 20 may have a cap layer such as a GaN layer on the barrier layer 24.

[0019] An element isolation region defining the element region is formed in the epitaxial layer 20, and within the element region, a first recess 20S for the source and a second recess 20D for the drain are formed in the epitaxial layer 20. The first recess 20S and the second recess 20D are separated from each other. The first recess 20S and the second recess 20D are formed, for example, from the upper surface of the barrier layer 24 to a position deeper than the upper surface of the channel layer 22. In other words, the first recess 20S and the second recess 20D are formed in at least the barrier layer 24, the spacer layer 23 and the channel layer 22.

[0020] The first nitride semiconductor layer 30S is formed within the first recess 20S and is not formed on top of the barrier layer 24. In a plan view, the first nitride semiconductor layer 30S is located inside the upper edge of the first recess 20S.

[0021] The second nitride semiconductor layer 30D has a first region 31 and a second region 32. The first region 31 is located inside the upper edge of the second recess 20D in a plan view. Most of the first region 31 is formed within the second recess 20D. A portion of the first region 31 may be above the upper surface of the epitaxial layer 20. The second region 32 is connected to the first region 31 and is located above the barrier layer 24. The second region 32 overlaps the channel layer 22 in a plan view.

[0022] The first nitride semiconductor layer 30S and the second nitride semiconductor layer 30D contain, for example, Si or Ge as n-type impurities. The first nitride semiconductor layer 30S and the second nitride semiconductor layer 30D contain n-type impurities at a higher concentration than, for example, the barrier layer 24. The concentration of n-type impurities in the first nitride semiconductor layer 30S and the second nitride semiconductor layer 30D is, for example, 1 × 10⁻⁶. 19 / cm 3 The above is the case. The first nitride semiconductor layer 30S and the second nitride semiconductor layer 30D are, for example, n-type GaN layers or InGaN layers. The first nitride semiconductor layer 30S and the second nitride semiconductor layer 30D contain single crystals. For example, the majority of each of the first nitride semiconductor layer 30S and the second nitride semiconductor layer 30D is made of single crystals. The first region 31 and the second region 32 contain single crystals. The majority of each of the first region 31 and the second region 32 is made of single crystals.

[0023] A source electrode 40S is formed on a first nitride semiconductor layer 30S, and a drain electrode 40D is formed on a second nitride semiconductor layer 30D. A passivation film 50 is formed on the barrier layer 24, covering the source electrode 40S and the drain electrode 40D. The passivation film 50 has an opening 50G located between the source electrode 40S and the drain electrode 40D in a plan view, and a gate electrode 40G is formed on the passivation film 50 that contacts the barrier layer 24 through the opening 50G.

[0024] The source electrode 40S and the drain electrode 40D include, for example, a Ti film and an Al film on the Ti film. The gate electrode 40G includes, for example, a Ni film. The gate electrode 40G may further include an Au film on the Ni film. The source electrode 40S is in ohmic contact with the first nitride semiconductor layer 30S, and the drain electrode 40D is in ohmic contact with the second nitride semiconductor layer 30D. The gate electrode 40G is in Schottky contact with the epitaxial layer 20. The passivation film 50 is, for example, a film of an oxide, nitride, or oxynitride of Si, Al, Hf, Zr, Ti, Ta, or W, and is preferably a SiN film. The thickness of the passivation film 50 is, for example, 2 nm to 500 nm.

[0025] In the nitride semiconductor device 1, a two-dimensional electron gas (2DEG) 29 exists near the upper surface of the channel layer 22. For example, the bottom surfaces of the first recess 20S and the second recess 20D are located deeper than the 2DEG 29.

[0026] Here, the second nitride semiconductor layer 30D and the barrier layer 24 will be described. Figure 2 is a cross-sectional view showing an enlarged portion of Figure 1.

[0027] As shown in Figure 2, a pit 30X may be present near the inner wall surface of the second recess 20D in the first region 31. As will be described in detail later, crystal growth occurs from the bottom surface and inner wall surface of the second recess 20D during the formation of the second nitride semiconductor layer 30D, so the pit 30X may be formed. In addition, the barrier layer 24 has a third region 25 that overlaps with the second region 32 in a plan view, and a fourth region 26 that is closer to the gate electrode 40G than the third region 25 in a plan view, and the concentration of In in the third region 25 may be lower than the concentration of In in the fourth region 26. Also, the concentration of 2DEG 29 is lower below the third region 25 than below the fourth region 26.

[0028] A pit similar to the pit 30X may be present near the inner wall surface of the first recess 20S of the first nitride semiconductor layer 30S.

[0029] Next, a method for manufacturing the nitride semiconductor device 1 according to the first embodiment will be described. Figures 3 to 11 are cross-sectional views showing the method for manufacturing the nitride semiconductor device 1 according to the first embodiment.

[0030] First, as shown in Figure 3, an epitaxial layer 20 including a buffer layer 21, a channel layer 22, a spacer layer 23, and a barrier layer 24 is formed on the substrate 10. The epitaxial layer 20 can be formed by crystal growth methods such as metal-organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE).

[0031] When forming an epitaxial layer 20 by the MOCVD method, for example, a mixed gas of trimethylaluminum (TMA) gas as the Al source, trimethylgallium (TMG) gas as the Ga source, trimethylindium (TMI) gas as the In source, and ammonia (NH3) gas as the N source is used. At this time, the supply and flow rates of TMA gas, TMG gas, and TMI gas are appropriately set according to the composition of the nitride semiconductor layer to be grown. The flow rate of NH3 gas, which is a common raw material for each nitride semiconductor layer, is set to, for example, about 100 ccm to 10 LM.

[0032] Next, an element isolation region is formed in the epitaxial layer 20 to define the element region. In forming the element isolation region, for example, a photoresist pattern that exposes the region where the element isolation region is to be formed is formed on the epitaxial layer 20, and ion implantation of Ar or the like is performed using this pattern as a mask. Alternatively, dry etching using a chlorine-based gas may be performed using this pattern as an etching mask.

[0033] Subsequently, as shown in Figure 4, a SiN film 71 is formed on the barrier layer 24, and a photoresist mask 72 is formed on the SiN film 71. The photoresist mask 72 has openings 72S and 72D. The region where the first nitride semiconductor layer 30S and the first recess 20S are formed is exposed through opening 72S. The region where the second nitride semiconductor layer 30D is formed is exposed through opening 72D.

[0034] Next, as shown in Figure 5, the portions of the SiN film 71 exposed from the opening 72S and the portion exposed from the opening 72D are removed by dry etching using a fluorine-based gas such as SF6 gas. At this time, the epitaxial layer 20 is not etched because it is resistant to the fluorine-based gas. As a result, a first opening 71S connected to the opening 72S and a second opening 71D connected to the opening 72D are formed in the SiN film 71.

[0035] Next, as shown in Figure 6, the photoresist mask 72 is removed and a photoresist mask 73 is formed on the barrier layer 24 and the SiN film 71. The photoresist mask 73 has a third opening 73S and a fourth opening 73D formed therein. The entire first opening 71S is exposed from the third opening 73S. From the third opening 73S, a portion of the SiN film 71 around the first opening 71S is also exposed in an annular shape. The region where the second recess 20D is formed is exposed from the fourth opening 73D. The photoresist mask 73 covers the region where the second region 32 of the second nitride semiconductor layer 30D is formed. The photoresist mask 73 covers at least a portion of the inner wall surface of the second opening 71D.

[0036] Subsequently, as shown in Figure 7, dry etching using a chlorine-based gas removes the portion of the barrier layer 24, the spacer layer 23, and a portion of the channel layer 22 that is exposed from the third opening 73S and the fourth opening 73D. At this time, the SiN film 71 is not etched because it is resistant to the chlorine-based gas. As a result, a first recess 20S connected to the first opening 71S and a second recess 20D connected to the third opening 73S are formed in the epitaxial layer 20. In other words, the shape of the first recess 20S on the second recess 20D side depends on the shape of the first opening 71S of the SiN film 71, while the shape of the second recess 20D on the first recess 20S side depends on the shape of the fourth opening 73D of the photoresist mask 73 and does not depend on the shape of the first opening 71S.

[0037] Next, as shown in Figure 8, the photoresist mask 73 is removed. On the upper surface of the barrier layer 24, the first recess 20S side is covered by the SiN film 71 and is not exposed from the first opening 71S, while the second recess 20D side is not covered by the SiN film 71 and is exposed from the second opening 71D.

[0038] Next, as shown in Figure 9, a first nitride semiconductor layer 30S and a second nitride semiconductor layer 30D are formed on the epitaxial layer 20. The first nitride semiconductor layer 30S and the second nitride semiconductor layer 30D can be formed, for example, by the MOCVD method. At this time, the SiN film 71 functions as a growth mask. Therefore, the first nitride semiconductor layer 30S is formed in the first recess 20S, and the second nitride semiconductor layer 30D is formed in the second recess 20D and on the region exposed from the second opening 71D of the barrier layer 24. Thus, the second nitride semiconductor layer 30D has a first region 31 and a second region 32.

[0039] During the formation of the second region 32, disorder inevitably occurs in the crystals within the third region 25 of the barrier layer 24, and the concentration of 2DEG29 decreases below the third region 25, as shown in Figure 2. Furthermore, during the formation of the first nitride semiconductor layer 30S and the second nitride semiconductor layer 30D, some of the In contained in the third region 25 may detach through the second opening 71D. This detachment of some of the In may also lead to a decrease in the concentration of 2DEG29 below the third region 25.

[0040] After forming the first nitride semiconductor layer 30S and the second nitride semiconductor layer 30D, the SiN film 71 is removed by wet etching, as shown in Figure 10. Next, a source electrode 40S is formed on the first nitride semiconductor layer 30S, and a drain electrode 40D is formed on the second nitride semiconductor layer 30D. The source electrode 40S and the drain electrode 40D can be formed, for example, by the lift-off method. That is, a photoresist pattern is formed that exposes the respective regions where the source electrode 40S and the drain electrode 40D will be formed, a metal film is formed by vapor deposition using this pattern as a growth mask, and this pattern is removed together with the metal film on top of it. In the formation of the metal film, for example, a Ti film is formed, and an Al film is formed on top of it. After that, for example, heat treatment is performed in a nitrogen atmosphere at 400°C to 1000°C to establish ohmic contact.

[0041] Next, as shown in Figure 11, a passivation film 50 is formed on the barrier layer 24 to cover the source electrode 40S and the drain electrode 40D. The passivation film 50 can be formed, for example, by plasma CVD. The passivation film 50 may also be formed by ALD or sputtering. Next, an opening 50G is formed in the passivation film 50. In forming the opening 50G, for example, a photoresist pattern that exposes the region where the opening 50G is to be formed is formed on the passivation film 50 by photolithography, and dry etching is performed using a fluorine-based gas with this pattern as an etching mask. After that, a gate electrode 40G that contacts the barrier layer 24 through the opening 50G is formed on the passivation film 50. The gate electrode 40G can be formed, for example, by the lift-off method. That is, a photoresist pattern that exposes the region where the gate electrode 40G will be formed is formed, a metal film is formed by vapor deposition using this pattern as a growth mask, and this pattern is removed together with the metal film on top of it. In the formation of a metal film, for example, a Ni film is formed.

[0042] In this way, the nitride semiconductor device 1 according to the first embodiment can be manufactured.

[0043] In addition, other films that satisfy the following conditions may be used as regrowth masks instead of the SiN film 71. Firstly, they cause little damage to the epitaxial layer 20 during formation. Secondly, they allow the formation of the first opening 71S and the second opening 71D. Thirdly, they are resistant to the temperatures during the formation of the first nitride semiconductor layer 30S and the second nitride semiconductor layer 30D. Fourthly, they can be selectively removed from the epitaxial layer 20. If these conditions are met, other films may be used as regrowth masks instead of the SiN film 71.

[0044] After forming the gate electrode 40G, an insulating film such as a SiN film may be formed on top of it, and a metal film may be formed thereon to form a field plate structure.

[0045] In the nitride semiconductor device 1, the barrier layer 24 contains In. This allows for a high concentration of 2DEG29, ensuring high electron mobility. Furthermore, the presence of the spacer layer 23 facilitates obtaining excellent crystallinity in the barrier layer 24. Moreover, the nitride semiconductor device 1 has a first nitride semiconductor layer 30S and a second nitride semiconductor layer 30D. Therefore, even with the spacer layer 23 and the barrier layer 24, the ohmic resistance between the source electrode 40S and the drain electrode 40D and 2DEG29 can be kept low.

[0046] Furthermore, the second nitride semiconductor layer 30D has a first region 31 and a second region 32. As described above, when the second region 32 is formed, disorder inevitably occurs in the crystal in the third region 25 of the barrier layer 24, and as shown in Figure 2, the concentration of 2DEG29 is lower below the third region 25 than below the fourth region 26. As a result, the resistance is higher below the third region 25 than below the fourth region 26, and the electric field is more likely to concentrate below the third region 25. Therefore, even if there is a high resistance portion in the first region 31 due to the pit 30X, the range over which the electric field is likely to concentrate is broadened, and the electric field concentration near the pit 30X is mitigated. As a result, dielectric breakdown associated with electric field concentration is suppressed, and a high breakdown voltage can be obtained.

[0047] Furthermore, if the concentration of In in the third region 25 is lower than the concentration of In in the fourth region 26, the concentration of 2DEG29 below the third region 25 becomes even lower, further mitigating the electric field concentration near the pit 30X. As a result, a higher breakdown voltage can be obtained.

[0048] Furthermore, the first nitride semiconductor layer 30S is formed within the first recess 20S and not on the barrier layer 24. Compared to the potential difference between the gate electrode 40G and the drain electrode 40D, the potential difference between the gate electrode 40G and the source electrode 40S is small. Therefore, even if pits similar to pits 30X exist in the first nitride semiconductor layer 30S, the electric field is unlikely to concentrate near these pits, and dielectric breakdown is unlikely to occur. Also, because the first nitride semiconductor layer 30S is not formed on the barrier layer 24, a decrease in 2DEG29 is unlikely, and an increase in resistance can be suppressed. Furthermore, if the distance between the source electrode 40S and the gate electrode 40G is small, and a part of the first nitride semiconductor layer 30S also exists on the barrier layer 24 on the gate electrode 40G side, there is a risk of large parasitic capacitance occurring between the first nitride semiconductor layer 30S and the gate electrode 40G. In contrast, the nitride semiconductor device 1 can suppress the occurrence of such large parasitic capacitance.

[0049] (Second Embodiment) Next, a second embodiment will be described. The second embodiment relates to a discrete package of HEMT. Figure 12 is a diagram showing a discrete package according to the second embodiment.

[0050] In the second embodiment, as shown in Figure 12, the back surface of the semiconductor device 1210, which has the same structure as in the first embodiment, is fixed to the land (die pad) 1233 using a die attach agent 1234 such as solder. A wire 1235d, such as an Al wire, is connected to a drain pad 1226d to which a drain electrode 40D is connected, and the other end of the wire 1235d is connected to a drain lead 1232d which is integrated with the land 1233. A wire 1235s, such as an Al wire, is connected to a source pad 1226s connected to a source electrode 40S, and the other end of the wire 1235s is connected to a source lead 1232s which is independent of the land 1233. A wire 1235g, such as an Al wire, is connected to a gate pad 1226g connected to a gate electrode 40G, and the other end of the wire 1235g is connected to a gate lead 1232g which is independent of the land 1233. Then, the land 1233 and semiconductor device 1210, etc., are packaged with mold resin 1231, with a portion of the gate lead 1232g, a portion of the drain lead 1232d, and a portion of the source lead 1232s protruding.

[0051] Such discrete packages can be manufactured, for example, as follows: First, the semiconductor device 1210 is fixed to the land 1233 of the lead frame using a die attach agent 1234 such as solder. Next, the gate pad 1226g is connected to the gate lead 1232g of the lead frame, the drain pad 1226d is connected to the drain lead 1232d of the lead frame, and the source pad 1226s is connected to the source lead 1232s of the lead frame by bonding using wires 1235g, 1235d, and 1235s. After that, sealing is performed using a molding resin 1231 by the transfer molding method. Subsequently, the lead frame is detached.

[0052] (Third embodiment) Next, a third embodiment will be described. The third embodiment relates to a PFC (Power Factor Correction) circuit equipped with a HEMT. Figure 13 is a wiring diagram showing the PFC circuit according to the third embodiment.

[0053] The PFC circuit 1250 includes a switch element (transistor) 1251, a diode 1252, a choke coil 1253, capacitors 1254 and 1255, a diode bridge 1256, and an AC power supply (AC) 1257. The drain electrode of the switch element 1251 is connected to the anode terminal of the diode 1252 and one terminal of the choke coil 1253. The source electrode of the switch element 1251 is connected to one terminal of the capacitor 1254 and one terminal of the capacitor 1255. The other terminal of the capacitor 1254 is connected to the other terminal of the choke coil 1253. The other terminal of the capacitor 1255 is connected to the cathode terminal of the diode 1252. A gate driver is connected to the gate electrode of the switch element 1251. AC 1257 is connected between both terminals of the capacitor 1254 via the diode bridge 1256. DC power is connected between both terminals of the capacitor 1255. In this embodiment, the switch element 1251 is a semiconductor device having the same structure as in the first embodiment.

[0054] When manufacturing the PFC circuit 1250, for example, the switch element 1251 is connected to the diode 1252 and the choke coil 1253 using solder or the like.

[0055] (Fourth Embodiment) Next, a fourth embodiment will be described. The fourth embodiment relates to a power supply device equipped with a HEMT, which is suitable for server power supplies. Figure 14 is a wiring diagram showing the power supply device according to the fourth embodiment.

[0056] The power supply unit is equipped with a high-voltage primary circuit 1261, a low-voltage secondary circuit 1262, and a transformer 1263 located between the primary circuit 1261 and the secondary circuit 1262.

[0057] The primary circuit 1261 is provided with a PFC circuit 1250 according to the third embodiment, and an inverter circuit, such as a full-bridge inverter circuit 1260, connected between the terminals of the capacitor 1255 of the PFC circuit 1250. The full-bridge inverter circuit 1260 is provided with a plurality (in this case, four) of switch elements 1264a, 1264b, 1264c, and 1264d.

[0058] The secondary circuit 1262 is provided with multiple (in this case, three) switching elements 1265a, 1265b, and 1265c.

[0059] In this embodiment, the switch element 1251 of the PFC circuit 1250 constituting the primary circuit 1261, and the switch elements 1264a, 1264b, 1264c, and 1264d of the full-bridge inverter circuit 1260, are semiconductor devices having the same structure as in the first embodiment. On the other hand, the switch elements 1265a, 1265b, and 1265c of the secondary circuit 1262 are ordinary MIS-type FETs (field-effect transistors) made of silicon.

[0060] (Fifth embodiment) Next, a fifth embodiment will be described. The fifth embodiment relates to an amplifier equipped with a HEMT. Figure 15 is a wiring diagram showing the amplifier according to the fifth embodiment.

[0061] The amplifier includes a digital pre-distortion circuit 1271, mixers 1272a and 1272b, and a power amplifier 1273.

[0062] The digital pre-distortion circuit 1271 compensates for the nonlinear distortion of the input signal. The mixer 1272a mixes the input signal, which has been compensated for the nonlinear distortion, with the AC signal. The power amplifier 1273 has a semiconductor device with the same structure as in the first embodiment and amplifies the input signal mixed with the AC signal. In this embodiment, for example, by switching a switch, the output signal can be mixed with the AC signal in the mixer 1272b and sent to the digital pre-distortion circuit 1271. This amplifier can be used as a high-frequency amplifier or a high-power amplifier. The high-frequency amplifier can be used, for example, in transceivers for mobile phone base stations, radar equipment, and microwave generators.

[0063] In this disclosure, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon substrate, an AlN substrate, a GaN substrate, or a diamond substrate may be used as the substrate. The substrate may be conductive, semi-insulating, or insulating.

[0064] The structures of the gate electrode, source electrode, and drain electrode are not limited to those of the embodiments described above. For example, they may be composed of single layers. Furthermore, the method of forming them is not limited to the lift-off method. In addition, if ohmic characteristics can be obtained, the heat treatment after the formation of the source electrode and drain electrode may be omitted. Heat treatment may be performed after the formation of the gate electrode.

[0065] In the above embodiment, a Schottky gate structure is used as the gate electrode structure, but an MIS (metal-insulator-semiconductor) gate structure may also be used.

[0066] Nitride semiconductor devices can be used, for example, in base stations for mobile phone communications, communication equipment for radio astronomy, and communication equipment for satellite communications.

[0067] Although preferred embodiments have been described in detail above, the invention is not limited to the embodiments described above, and various modifications and substitutions can be made to the embodiments described above without departing from the scope of the claims.

[0068] The various aspects of this disclosure are summarized below as an appendix.

[0069] (Note 1) Channel layer and A barrier layer containing In on the channel layer, n-type first nitride semiconductor layer, n-type second nitride semiconductor layer, A source electrode provided on the first nitride semiconductor layer, A drain electrode provided on the second nitride semiconductor layer, In a plan view, between the source electrode and the drain electrode, a gate electrode is provided on the barrier layer, It has, The barrier layer and the channel layer have a first recess and a second recess formed apart from each other. The first nitride semiconductor layer is formed within the first recess and is not formed on the barrier layer. The second nitride semiconductor layer is In plan view, the first region is located inside the upper edge of the second recess, Connected to the first region, and to the second region on the barrier layer, A nitride semiconductor device characterized by having the following features. (Note 2) The aforementioned barrier layer is A third region that overlaps with the aforementioned second region in a plan view, In a plan view, the fourth region is on the gate electrode side of the third region, It has, The nitride semiconductor device according to Appendix 1, characterized in that the concentration of In in the third region is lower than the concentration of In in the fourth region. (Note 3) The composition of the barrier layer is, In 1-x-y Al x Gay The nitride semiconductor device according to Supplementary Note 1 or 2, which is represented by N (0≦x<1, 0≦y<1, 0<x+y<1). (Supplementary Note 4) The nitride semiconductor device according to any one of Supplementary Notes 1 to 3, wherein a pit is formed in the second nitride semiconductor layer. (Supplementary Note 5) The nitride semiconductor device according to any one of Supplementary Notes 1 to 4, wherein the second region contains a single crystal. (Supplementary Note 6) The nitride semiconductor device according to any one of Supplementary Notes 1 to 5, wherein the first nitride semiconductor layer and the second nitride semiconductor layer contain an n-type impurity at a higher concentration than the barrier layer. (Supplementary Note 7) The nitride semiconductor device according to any one of Supplementary Notes 1 to 6, further comprising a spacer layer between the channel layer and the barrier layer. (Supplementary Note 8) a step of forming an In-containing barrier layer on a channel layer; a step of forming a first recess and a second recess spaced apart from each other in the barrier layer and the channel layer; a step of forming an n-type first nitride semiconductor layer in the first recess, and forming an n-type second nitride semiconductor layer having a first region located inside the upper edge of the second recess in plan view and a second region connected to the first region and located on the barrier layer; a step of forming a source electrode on the first nitride semiconductor layer; a step of forming a drain electrode on the second nitride semiconductor layer; a step of forming a gate electrode on the barrier layer between the source electrode and the drain electrode in plan view; and the method comprises: A method for manufacturing a nitride semiconductor device, wherein the first nitride semiconductor layer is not formed on the barrier layer. (Supplementary Note 9) An amplifier comprising the nitride semiconductor device according to any one of Supplementary Notes 1 to 7. (Supplementary Note 10) A power supply device having a nitride semiconductor device as described in any one of the appendices 1 to 7. [Explanation of Symbols]

[0070] 1: Nitride semiconductor equipment 10: Circuit board 20: Epitaxial layer 20S: First recess 20D: Second recess 21: Buffer Layer 22: Channel Layer 23: Spacer layer 24: Barrier layer 25: Third area 26: 4th area 29:2DEG 30S: First nitride semiconductor layer 30D: Second nitride semiconductor layer 30X: Pit 31:First area 32:Second area 40D: Drain electrode 40G: Gateway 40S: Source electrode

Claims

1. Channel layer and A barrier layer containing In on the channel layer, n-type first nitride semiconductor layer, n-type second nitride semiconductor layer, A source electrode provided on the first nitride semiconductor layer, A drain electrode provided on the second nitride semiconductor layer, In a plan view, between the source electrode and the drain electrode, a gate electrode is provided on the barrier layer, It has, The barrier layer and the channel layer have a first recess and a second recess formed apart from each other. The first nitride semiconductor layer is formed within the first recess and is not formed on the barrier layer. The second nitride semiconductor layer is In plan view, the first region is located inside the upper edge of the second recess, Connected to the first region, and to the second region on the barrier layer, A nitride semiconductor device characterized by having the following features.

2. The aforementioned barrier layer is A third region that overlaps with the second region in a plan view, In a plan view, the fourth region is on the gate electrode side of the third region, It has, The nitride semiconductor device according to claim 1, characterized in that the concentration of In in the third region is lower than the concentration of In in the fourth region.

3. The composition of the barrier layer is In １－ｘ－ｙ Al ｘ Ga ｙ The nitride semiconductor device according to claim 1 or 2, characterized in that it is represented by N (0 ≤ x < 1, 0 ≤ y < 1, 0 < x + y < 1).

4. The nitride semiconductor device according to claim 1 or 2, characterized in that pits are formed in the second nitride semiconductor layer.

5. The nitride semiconductor device according to claim 1 or 2, characterized in that the second region includes a single crystal.

6. The nitride semiconductor device according to claim 1 or 2, characterized in that the first nitride semiconductor layer and the second nitride semiconductor layer contain n-type impurities at a higher concentration than the barrier layer.

7. A step of forming a barrier layer containing In on top of a channel layer, The steps include forming a first recess and a second recess in the barrier layer and the channel layer, with the two recesses separated from each other, A step of forming an n-type first nitride semiconductor layer in the first recess, and forming an n-type second nitride semiconductor layer having a first region located inside the upper edge of the second recess in a plan view, and a second region connected to the first region and above the barrier layer, A step of forming a source electrode on the first nitride semiconductor layer, A step of forming a drain electrode on the second nitride semiconductor layer, A step of forming a gate electrode on the barrier layer between the source electrode and the drain electrode in a plan view, It has, A method for manufacturing a nitride semiconductor device, characterized in that the first nitride semiconductor layer is not formed on the barrier layer.

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