semiconductor element

Abstract

To suppress hole injection to a drift region.SOLUTION: In a semiconductor element, a semiconductor substrate has: an IGBT region that is a range overlapping with a collector region; and a diode region that is a range overlapping with a cathode region. A part of a plurality of inter-trench semiconductor regions has a hole injection suppression structure having an n-type barrier region in contact with a body region from below, and a pillar region extending from the barrier region to an emitter electrode and in Schottky contact with the emitter electrode. The IGBT region has a boundary region formed by the plurality of inter-trench semiconductor regions existing between a main region and the diode region. The hole injection suppression structure is provided in the diode region and each inter-trench semiconductor region in the boundary region. A width of the boundary region in the second direction is 80% or more of a thickness of the semiconductor substrate.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The technology disclosed in the present specification relates to a semiconductor device.

[0002] Patent Document 1 discloses a semiconductor device including an IGBT (Insulated Gate Bipolar Transistor) and a diode. A plurality of trenches are provided on the upper surface of a semiconductor substrate across an IGBT region and a diode region. A trench insulating film and a trench electrode are disposed in each trench. The trench electrode is insulated from the semiconductor substrate by the trench insulating film. The trench electrode in the IGBT region functions as a gate electrode. In a range including the upper surface of the semiconductor substrate, a p-type body region and an n-type drift region are provided across the IGBT region and the diode region. The drift region is in contact with the body region from the lower side. A channel is formed in the body region within the IGBT region. The body region within the diode region functions as an anode. Further, a p-type collector region is provided below the drift region in the IGBT region. An n-type cathode region is provided below the drift region in the diode region. Furthermore, a hole injection suppression structure is provided in a semiconductor region sandwiched between a plurality of trenches (hereinafter referred to as an inter-trench semiconductor region). The hole injection suppression structure includes an n-type barrier region in contact with the body region from the lower side, and an n-type pillar region extending from the barrier region to an emitter electrode. The pillar region is in Schottky contact with the emitter electrode. The hole injection suppression structure is provided over the entire IGBT region and diode region. When the hole injection suppression structure is provided, injection of holes from the body region to the drift region is suppressed when the diode is turned on. Therefore, recovery current is suppressed when the diode performs a recovery operation. Prior Art Literature Patent Literature

[0003] Patent Document 1 Japanese Patent Publication No. 2016-225345 [Overview of the project] [Problems that the invention aims to solve]

[0004] In the semiconductor device described in Patent Document 1, a hole injection suppression structure is provided throughout both the IGBT region and the diode region. When a hole injection suppression structure is provided within the IGBT region, the injection of holes from the body region to the drift region can be suppressed at the boundary between the IGBT region and the diode region. On the other hand, if a hole injection suppression structure is provided throughout the entire IGBT region, leakage current is more likely to occur within the IGBT region. This specification proposes a technique for effectively suppressing hole injection into the drift region when a hole injection suppression structure is provided only partially within the IGBT region. [Means for solving the problem]

[0005] A first semiconductor device disclosed herein comprises a semiconductor substrate, an emitter electrode in contact with the upper surface of the semiconductor substrate, and a collector electrode in contact with the lower surface of the semiconductor substrate. The semiconductor substrate has a p-type collector region in contact with the collector electrode and an n-type cathode region in contact with the collector electrode. When the semiconductor substrate is viewed along its thickness, the region overlapping with the collector region is an IGBT region, and the region overlapping with the cathode region is a diode region. When the direction along the boundary between the IGBT region and the diode region on the upper surface is defined as the first direction, and the direction from the IGBT region toward the diode region on the upper surface is defined as the second direction, a plurality of trenches are provided on the upper surface extending along the first direction, and the plurality of trenches are arranged at intervals in the second direction. The inner surface of each trench is covered with a trench insulating film. A trench electrode is arranged in each trench. A plurality of inter-trench semiconductor regions, which are semiconductor regions sandwiched between the plurality of trenches, are arranged in each of the IGBT region and the diode region. Each of the inter-trench semiconductor regions within the IGBT region and the diode region has a p-type body region that is in contact with the emitter electrode and the trench insulating film. At least a portion of the inter-trench semiconductor region within the IGBT region has an n-type emitter region that is in contact with the emitter electrode and the trench insulating film above the body region. The semiconductor substrate is distributed across the IGBT region and the diode region and has an n-type drift region located below the body region. A portion of the plurality of inter-trench semiconductor regions has a hole injection suppression structure having an n-type barrier region that is in contact with the body region from below and a pillar region that extends from the barrier region to the emitter electrode and is in Schottky contact with the emitter electrode. The IGBT region has a main region composed of a plurality of inter-trench semiconductor regions that are not provided with the hole injection suppression structure, and a boundary region composed of a plurality of inter-trench semiconductor regions located between the main region and the diode region.The hole injection suppression structure is provided in the semiconductor regions between trenches within the diode region and the boundary region. The width of the boundary region in the second direction is 80% or more of the thickness of the semiconductor substrate.

[0006] When the width of the boundary region is 80% or more of the thickness of the semiconductor substrate, hole injection into the drift region can be effectively suppressed, and the reverse recovery current of the diode can be effectively suppressed. [Brief explanation of the drawing]

[0007] [Figure 1] Plan view of the semiconductor device of Example 1. [Figure 2] Cross-sectional view of the semiconductor device of Example 1 (cross-sectional view along line AA in Figure 1). [Figure 3] A graph showing the relationship between the W / T value and the recovery charge Qrr. [Figure 4] Cross-sectional view of the semiconductor device of Example 2. [Figure 5] Cross-sectional view of the semiconductor device in Example 3 [Figure 6] Cross-sectional view of a modified semiconductor element [Figure 7] Cross-sectional view of the semiconductor device in Example 4 [Figure 8] Cross-sectional view of a modified semiconductor element [Modes for carrying out the invention]

[0008] In the first semiconductor device described above, the work function at the interface between the pillar region and the emitter electrode within the boundary region may be lower than the work function at the interface between the pillar region and the emitter electrode within the diode region.

[0009] This configuration allows for more effective suppression of hole injection into drift regions at the boundary.

[0010] In the first semiconductor device described above, each of the trench electrodes in the main region may be a gate electrode. Alternatively, at least one of the trench electrodes in the boundary region may be a dummy electrode connected to the emitter electrode.

[0011] A second semiconductor element disclosed herein comprises a semiconductor substrate, an emitter electrode in contact with the upper surface of the semiconductor substrate, and a collector electrode in contact with the lower surface of the semiconductor substrate. The semiconductor substrate has a p-type collector region in contact with the collector electrode and an n-type cathode region in contact with the collector electrode. When the semiconductor substrate is viewed along the thickness direction, the region overlapping with the collector region is an IGBT region, and the region overlapping with the cathode region is a diode region. When the direction along the boundary between the IGBT region and the diode region on the upper surface is defined as the first direction, and the direction from the IGBT region toward the diode region on the upper surface is defined as the second direction, a plurality of trenches are provided on the upper surface extending along the first direction, and the plurality of trenches are arranged at intervals in the second direction. The inner surface of each trench is covered with a trench insulating film. A trench electrode is arranged in each trench. A plurality of inter-trench semiconductor regions, which are semiconductor regions sandwiched between the plurality of trenches, are arranged in each of the IGBT region and the diode region. Each of the inter-trench semiconductor regions within the IGBT region and the diode region has a p-type body region that is in contact with the emitter electrode and the trench insulating film. At least a portion of the inter-trench semiconductor region within the IGBT region has an n-type emitter region that is in contact with the emitter electrode and the trench insulating film above the body region. The semiconductor substrate is distributed across the IGBT region and the diode region and has an n-type drift region located below the body region. A portion of the plurality of inter-trench semiconductor regions has a hole injection suppression structure having an n-type barrier region that is in contact with the body region from below and a pillar region that extends from the barrier region to the emitter electrode and is in Schottky contact with the emitter electrode. The IGBT region has a main region composed of a plurality of inter-trench semiconductor regions that are not provided with the hole injection suppression structure, and a boundary region composed of a plurality of inter-trench semiconductor regions located between the main region and the diode region.The hole injection suppression structure is provided in each of the trench-inter-semiconductor regions within the diode region and the boundary region. The work function at the interface between the pillar region and the emitter electrode in the boundary region is lower than the work function at the interface between the pillar region and the emitter electrode in the diode region.

[0012] This configuration effectively suppresses the injection of holes into the drift region at the boundary.

[0013] A third semiconductor device disclosed herein comprises a semiconductor substrate, an emitter electrode in contact with the upper surface of the semiconductor substrate, and a collector electrode in contact with the lower surface of the semiconductor substrate. The semiconductor substrate has a p-type collector region in contact with the collector electrode and an n-type cathode region in contact with the collector electrode. When the semiconductor substrate is viewed along the thickness direction, the region overlapping with the collector region is an IGBT region, and the region overlapping with the cathode region is a diode region. When the direction along the boundary between the IGBT region and the diode region on the upper surface is defined as the first direction, and the direction from the IGBT region toward the diode region on the upper surface is defined as the second direction, a plurality of trenches are provided on the upper surface extending along the first direction, and the plurality of trenches are arranged at intervals in the second direction. The inner surface of each trench is covered with a trench insulating film. A trench electrode is arranged in each trench. A plurality of inter-trench semiconductor regions, which are semiconductor regions sandwiched between the plurality of trenches, are arranged in each of the IGBT region and the diode region. Each of the inter-trench semiconductor regions within the IGBT region and the diode region has a p-type body region that is in contact with the emitter electrode and the trench insulating film. At least a portion of the inter-trench semiconductor region within the IGBT region has an n-type emitter region that is in contact with the emitter electrode and is in contact with the trench insulating film above the body region. The semiconductor substrate is distributed across the IGBT region and the diode region and has an n-type drift region located below the body region. A portion of the plurality of inter-trench semiconductor regions has a hole injection suppression structure having an n-type barrier region that is in contact with the body region from below and a pillar region that extends from the barrier region to the emitter electrode and is in Schottky contact with the emitter electrode. A portion of the plurality of inter-trench semiconductor regions has a floating structure whose upper surface is covered by an interlayer insulating film.The IGBT region comprises a main region composed of a plurality of inter-trench semiconductor regions that are not provided with the hole injection suppression structure, and a boundary region composed of a plurality of inter-trench semiconductor regions located between the main region and the diode region. Each inter-trench semiconductor region within the diode region has the hole injection suppression structure. Each inter-trench semiconductor region within the boundary region has at least one of the hole injection suppression structure and the floating structure.

[0014] This configuration effectively suppresses the injection of holes into the drift region at the boundary. [Examples]

[0015] As shown in Figure 1, the semiconductor element 10 of Embodiment 1 has a semiconductor substrate 12 made of silicon. As shown in Figure 1, when viewed from above, the semiconductor substrate 12 is divided into an element portion 14 and an outer peripheral portion 17. The element portion 14 is further divided into a plurality of IGBT regions 15 and a plurality of diode regions 16. IGBTs are provided in the IGBT regions 15, and diodes are provided in the diode regions 16. Each of the IGBT regions 15 and diode regions 16 has a rectangular shape that is long in the x direction. In the y direction, the IGBT regions 15 and diode regions 16 are arranged alternately. Therefore, the boundary between the IGBT regions 15 and diode regions 16 extends along the x direction. Although not shown, a voltage-resistant structure such as a guard ring is provided on the outer peripheral portion 17. Signal electrode pads 18 are also provided on the outer peripheral portion 17. One of the signal electrode pads 18 is a gate pad that controls the gate voltage of the IGBT.

[0016] Figure 2 shows a cross-section of the semiconductor element 10 cut along the y-direction in the area spanning the IGBT region 15 and the diode region 16. A p-type collector region 20 and an n-type cathode region 22 are located in the area including the lower surface 12b of the semiconductor substrate 12. The collector region 20 is located within the IGBT region 15, and the cathode region 22 is located within the diode region 16. In other words, when the semiconductor substrate 12 is viewed along the thickness direction, the area overlapping with the collector region 20 is the IGBT region 15, and the area overlapping with the cathode region 22 is the diode region 16.

[0017] Multiple trenches 60 are provided on the upper surface 12a of the semiconductor substrate 12. On the upper surface 12a of the semiconductor substrate 12, each trench 60 extends along the x-direction. On the upper surface 12a of the semiconductor substrate 12, the multiple trenches 60 are arranged at intervals in the y-direction. Multiple trenches 60 are provided within both the IGBT region 15 and the diode region 16. Hereinafter, the region within the semiconductor region of the semiconductor substrate 12 sandwiched between two trenches 60 will be referred to as the inter-trench semiconductor region 66. Multiple inter-trench semiconductor regions 66 are provided within both the IGBT region 15 and the diode region 16. The inner surface of each trench 60 is covered with a trench insulating film 62. A trench electrode 64 is placed inside each trench 60. The trench electrode 64 is insulated from the semiconductor substrate 12 by the trench insulating film 62.

[0018] An interlayer insulating film 68 and an emitter electrode 70 are provided on an upper portion of the semiconductor substrate 12. The interlayer insulating film 68 covers the top surface of the trench electrode 64 in the IGBT region 15. The emitter electrode 70 is formed of a metal (for example, an AlSi alloy). The emitter electrode 70 is provided so as to extend from the IGBT region 15 across to the diode region 16, and covers the top surface 12a and the interlayer insulating film 68. The trench electrode 64 in the IGBT region 15 is insulated from the emitter electrode 70 by the interlayer insulating film 68. Although not shown in the drawings, the trench electrode 64 in the IGBT region 15 is connected to a gate pad via a wiring. The trench electrode 64 in the IGBT region 15 is a gate electrode 64a whose potential can be changed by the gate pad. The trench electrode 64 in the diode region 16 is connected to the emitter electrode 70. The trench electrode 64 in the diode region 16 is a dummy electrode 64b fixed at the same potential as the emitter electrode 70.

[0019] A collector electrode 72 is provided on a lower portion of the semiconductor substrate 12. The collector electrode 72 is provided so as to extend from the IGBT region 15 across to the diode region 16, and covers the bottom surface 12b. The collector region 20 and the cathode region 22 are in ohmic contact with the collector electrode 72.

[0020] Each inter-trench semiconductor region 66 in the IGBT region 15 and the diode region 16 has a p-type upper body region 34. The upper body region 34 is in contact with the emitter electrode 70 and is also in contact with the trench insulating film 62 on the side surface of the trench 60. The upper body region 34 includes a contact region 34a and a low-concentration region 34b having a lower p-type impurity concentration than the contact region 34a. The contact region 34a is disposed at a position including the top surface 12a, and is in ohmic contact with the emitter electrode 70. The low-concentration region 34b is in contact with the contact region 34a from a lower side thereof. The low-concentration region 34b is in contact with the trench insulating film 62 on the side surface of the trench 60.

[0021] Each inter-trench semiconductor region 66 within the IGBT region 15 has an n-type emitter region 32. Each emitter region 32 is positioned including the upper surface 12a and is in ohmic contact with the emitter electrode 70. Each emitter region 32 is also in contact with the trench insulating film 62 on the side surface of the trench 60. The low-concentration region 34b is in contact with each emitter region 32 from below. Each emitter region 32 is in contact with the trench insulating film 62 above the low-concentration region 34b. In this embodiment, the emitter region 32 is not provided within the diode region 16, but there is no problem if the emitter region 32 is provided within the diode region 16.

[0022] Each inter-trench semiconductor region 66 within the IGBT region 15 and the diode region 16 has an n-type barrier region 30. The n-type impurity concentration in the barrier region 30 is lower than that of the emitter region 32. The barrier region 30 is located below the low-concentration region 34b. The barrier region 30 is in contact with the trench insulating film 62 on the side surface of the trench 60.

[0023] Each inter-trench semiconductor region 66 within the IGBT region 15 and the diode region 16 has a p-type lower body region 28. The p-type impurity concentration in the lower body region 28 is lower than that in the contact region 34a. The lower body region 28 is located below the barrier region 30. The lower body region 28 is in contact with the trench insulating film 62 on the side of the trench 60. The lower body region 28 is separated from the upper body region 34 by the barrier region 30. In other words, the barrier region 30 separates the p-type body region into the upper body region 34 and the lower body region 28.

[0024] The IGBT region 15 has a main region 15a and a boundary region 15b. The boundary region 15b is a region adjacent to the diode region 16 and has multiple inter-trench semiconductor regions 66. The main region 15a is a region located at a distance in the y-direction from the diode region 16 and has multiple inter-trench semiconductor regions 66. In other words, the region between the main region 15a and the diode region 16 is the boundary region 15b. Each inter-trench semiconductor region 66 within the diode region 16 and the boundary region 15b is provided with an n-type pillar region 26. Each inter-trench semiconductor region 66 within the main region 15a is not provided with a pillar region 26. In other words, the boundary region 15b is a region adjacent to the diode region 16 and composed of multiple inter-trench semiconductor regions 66 having pillar regions 26, and the main region 15a is a region located at a distance from the diode region 16 and composed of multiple inter-trench semiconductor regions 66 not having pillar regions 26. The n-type impurity concentration in the pillar region 26 is lower than that in the emitter region 32. Each pillar region 26 extends from the barrier region 30 to the emitter electrode 70. Each pillar region 26 is in Schottky contact with the emitter electrode 70. Hereinafter, the set of barrier region 30 and pillar region 26 is referred to as the hole injection suppression structure 31. Hole injection suppression structures 31 are provided in each inter-trench semiconductor region 66 within the diode region 16 and the boundary region 15b. Hole injection suppression structures 31 are not provided in each inter-trench semiconductor region 66 within the main region 15a.

[0025] The semiconductor substrate 12 has an n-type intermediate region 24. The intermediate region 24 is distributed across the IGBT region 15 and the diode region 16. The intermediate region 24 is located between the upper structure of the semiconductor substrate 12 (i.e., the upper body region 34, emitter region 32, barrier region 30, lower body region 28, etc.) and the lower structure (i.e., the collector region 20 and cathode region 22). The intermediate region 24 has a drift region 24a and a buffer region 24b.

[0026] The drift region 24a is an n-type region having a lower n-type impurity concentration than the barrier region 30 and the pillar region 26. The drift region 24a is distributed across the IGBT region 15 and the diode region 16. The drift region 24a is located below the upper body region 34, the barrier region 30, and the lower body region 28. The drift region 24a is in contact with the lower body region 28 from below. In addition, the drift region 24a is in contact with the trench insulating film 62 at the lower end of each trench 60.

[0027] The buffer region 24b is an n-type region having an n-type impurity concentration higher than that of the drift region 24a and lower than that of the cathode region 22. The buffer region 24b is distributed across the IGBT region 15 and the diode region 16. The buffer region 24b is in contact with the drift region 24a from below. The buffer region 24b is in contact with the collector region 20 and the cathode region 22 from above.

[0028] In Figure 2, the width W is the width of the boundary region 15b in the y-direction, and the thickness T is the thickness of the semiconductor substrate 12. In Example 1, the width W is 80% or more of the thickness T.

[0029] An IGBT is formed within the IGBT region 15. The IGBT switches when a higher potential is applied to the collector electrode 72 than to the emitter electrode 70. When a potential higher than the gate threshold is applied to the gate electrode 64a, channels are formed in the upper body region 34 and the lower body region 28 within the range adjacent to the trench insulating film 62. As a result, the IGBT turns on, and current flows from the collector electrode 72 to the emitter electrode 70. When the potential of the gate electrode 64a is lowered to a potential lower than the gate threshold, the channels disappear, and the IGBT turns off.

[0030] A diode is formed within the diode region 16. When a potential higher than that of the collector electrode 72 is applied to the emitter electrode 70, holes are injected from the upper body region 34 into the drift region 24a within the diode region 16, as shown by arrow 100 in Figure 2. As a result, the electrical resistance of the drift region 24a decreases due to conductivity modulation. Therefore, electrons flow from the collector electrode 72 to the collector electrode 70 via the cathode region 22, buffer region 24b, drift region 24a, lower body region 28, barrier region 30, and upper body region 34. In other words, the diode turns on. Also, when the diode is turned on, as shown by arrow 102, holes are injected from the upper body region 34 into the drift region 24a within the boundary region 15b adjacent to the diode region 16. However, in Example 1, the injection of holes into the drift region 24a is suppressed by the hole injection suppression structure 31. In other words, in the hole injection suppression structure 31, the barrier region 30 is connected to the emitter electrode 70, which has a low potential, by the pillar region 26, so the potential of the barrier region 30 is reduced. Therefore, the injection of holes from the upper body region 34 into the drift region 24a is suppressed. Since the hole injection suppression structure 31 is provided in the diode region 16 and the boundary region 15b, the injection of holes into the drift region 24a is suppressed in the diode region 16 and the boundary region 15b. That is, the injection of holes indicated by arrows 100 and 102 is suppressed.

[0031] When the diode is ON, if the potential applied to the emitter electrode 70 is switched to a lower potential than that applied to the collector electrode 72, the diode performs a recovery operation. That is, holes present in the drift region 24a are discharged to the emitter electrode 70, causing a momentary reverse current (a so-called recovery current) to flow through the diode. In Embodiment 1, when the diode is ON, the injection of holes into the drift region 24a is suppressed in both the diode region 16 and the boundary region 15b, so fewer holes are discharged from the drift region 24a to the emitter electrode 70 during the recovery operation. Therefore, a recovery current is less likely to occur.

[0032] As explained above, the hole injection suppression structure 31 is provided in the diode region 16 and the boundary region 15b, thereby suppressing the recovery current. Figure 3 shows the results of measuring the recovery charge Qrr generated in semiconductor devices with different boundary region 15b widths W. The recovery charge Qrr is the total amount of charge flowing as recovery current (i.e., the value obtained by integrating the recovery current generated in the diode with respect to time). The horizontal axis shows the value W / T, which is obtained by dividing the width W by the thickness T. As shown in Figure 3, in the range of W / T from 0 to 0.8, the recovery charge Qrr decreases rapidly as the value W / T increases. In the range of W / T above 0.8, the recovery charge Qrr decreases gradually as the value W / T increases. From Figure 3, it can be seen that the recovery charge Qrr can be effectively reduced by setting the value W / T to 0.8 or higher. As described above, in the semiconductor device 10 of Example 1, the value W / T is 0.8 or higher, so the recovery charge Qrr can be effectively reduced. The value W / T may be 8.0 or less (i.e., the width W is 8.0 times or less the thickness of the semiconductor substrate 12). [Examples]

[0033] The switching element of Example 2 shown in Figure 4 differs from that of Example 1 in that the emitter electrode 70 has a first metal layer 70a and a second metal layer 70b. The other configurations of the switching element of Example 2 are the same as those of Example 1.

[0034] The first metal layer 70a and the second metal layer 70b are composed of different metals. The second metal layer 70b covers the upper surface 12a within the boundary region 15b. Within the boundary region 15b, the second metal layer 70b makes ohmic contact with the contact region 34a and the emitter region 32, and Schottky contact with the pillar region 26. The first metal layer 70a covers the upper surface 12a within the diode region 16 and the main region 15a. The first metal layer 70a also covers the upper surface of the second metal layer 70b. Within the diode region 16 and the main region 15a, the first metal layer 70a makes ohmic contact with the contact region 34a and the emitter region 32, and Schottky contact with the pillar region 26. The materials of the first metal layer 70a and the second metal layer 70b are selected such that the work function φBn2 at the interface between the second metal layer 70b and the pillar region 26 is lower than the work function φBn1 at the interface between the first metal layer 70a and the pillar region 26. For example, the first metal layer 70a may be made of an AlSi alloy, and the second metal layer 70b may be made of titanium.

[0035] In Example 2, the work function at the interface between the pillar region 26 and the emitter electrode 70 is low within the boundary region 15b, so the potential of the barrier region 30 within the boundary region 15b tends to be lower when the diode is ON. Therefore, when the diode is ON, hole injection into the drift region 24a within the boundary region 15b can be suppressed more effectively. Consequently, the recovery current can be effectively suppressed within the boundary region 15b.

[0036] In Example 2, the width W may be 80% or more of the thickness T, or it may be less than 80% of the thickness T. [Examples]

[0037] The switching element of Embodiment 3 shown in Figure 5 differs from Embodiment 1 in that the trench electrode 64 located within a portion of the trenches 60x in the boundary region 15b is a dummy electrode 64b. The other configurations of the switching element of Embodiment 3 are the same as those of Embodiment 1. With this configuration, the potential within the boundary region 15b is more easily stabilized.

[0038] In Figure 5, dummy electrodes 64b were provided in some of the trenches 60 within the boundary region 15b, but dummy electrodes 64b may be provided in all of the trenches 60 within the boundary region 15b.

[0039] Furthermore, as shown in Figure 6, Example 2 and Example 3 may be combined. [Examples]

[0040] In the switching element of Example 4 shown in Figure 7, the upper surface 12a of a portion of the inter-trench semiconductor region 66x within the boundary region 15b is covered by an interlayer insulating film 68. In the inter-trench semiconductor region 66x covered by the interlayer insulating film 68, the upper body region 34 is insulated from the emitter electrode 70, and the potential of the upper body region 34 is floating. Hereinafter, the structure in which the upper body region 34 is insulated from the emitter electrode 70 by the interlayer insulating film 68 will be referred to as the floating structure. The other inter-trench semiconductor regions 66 within the boundary region 15b (i.e., inter-trench semiconductor regions 66 that do not have the floating structure) have a hole injection suppression structure 31. The other configurations of the switching element of Example 4 are the same as those of Example 1.

[0041] In the switching element of Example 4, when the diode is turned on, no holes are injected from the upper body region 34 to the drift region 24a in the inter-trench semiconductor region 66 having a floating structure. Furthermore, in the other inter-trench semiconductor regions 66 within the boundary region 15b (i.e., inter-trench semiconductor regions 66 without a floating structure), the hole injection suppression structure 31 suppresses the injection of holes from the upper body region 34 to the drift region 24a. Therefore, recovery current is less likely to occur in the diode.

[0042] In Example 4, the width W may be 80% or more of the thickness T, or it may be less than 80% of the thickness T.

[0043] Furthermore, Example 4 may be combined with at least one of Examples 2 and 3.

[0044] In the above-described embodiments 1 to 4, barrier regions 30 were provided in each inter-trench semiconductor region 66 within the main region 15a, but barrier regions 30 are not required to be provided in each inter-trench semiconductor region 66 within the main region 15a.

[0045] Furthermore, in the above-described embodiments 1 to 4, a dummy electrode 64b was provided in the trench 60 within the diode region 16, but a gate electrode 64a may also be provided in at least a portion of the trench 60 within the diode region 16.

[0046] Furthermore, although the semiconductor elements of Examples 1 to 4 described above had a lower body region 28, the techniques of Examples 1 to 4 may also be applied to semiconductor elements that do not have a lower body region 28. For example, Figure 8 shows an example in which the technique of Example 1 is applied to a semiconductor element that does not have a lower body region 28. As shown in Figure 8, the lower body region 28 may not exist, and the drift region 24a may be in contact with the barrier region 30 from below.

[0047] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of Symbols]

[0048] 15: IGBT region, 15a: Main region, 15b: Boundary region, 16: Diode region, 20: Collector region, 22: Cathode region, 24a: Drift region, 26: Pillar region, 28: Lower body region, 30: Barrier region, 31: Hole injection suppression structure, 32: Emitter region, 34: Upper body region, 60: Trench

Claims

1. A semiconductor device, Semiconductor substrate and The emitter electrode in contact with the upper surface of the semiconductor substrate, A collector electrode in contact with the lower surface of the semiconductor substrate, It has, The aforementioned semiconductor substrate A p-type collector region in contact with the collector electrode, n-type cathode region in contact with the collector electrode, It has, When the semiconductor substrate is viewed along the thickness direction, the area overlapping with the collector region is the IGBT region, and the area overlapping with the cathode region is the diode region. When the direction along the boundary between the IGBT region and the diode region on the upper surface is defined as the first direction, and the direction from the IGBT region toward the diode region on the upper surface is defined as the second direction, a plurality of trenches are provided on the upper surface extending along the first direction, and the plurality of trenches are arranged at intervals in the second direction. The inner surface of each trench is covered with a trench insulating film. A trench electrode is placed in each of the trenches. Multiple inter-trench semiconductor regions, which are semiconductor regions sandwiched between the multiple trenches, are arranged in each of the IGBT region and the diode region. Each of the trench-inter-semiconductor regions within the IGBT region and the diode region has a p-type body region in contact with the emitter electrode and the trench insulating film. At least a portion of the trench-inter-semiconductor region within the IGBT region has an n-type emitter region that is in contact with the emitter electrode and is in contact with the trench insulating film above the body region. The semiconductor substrate is distributed across the IGBT region and the diode region, and has an n-type drift region located below the body region. A hole injection suppression structure is provided in which a portion of the multiple trench-inter-semiconductor regions has an n-type barrier region that contacts the body region from below, and a pillar region that extends from the barrier region to the emitter electrode and is in Schottky contact with the emitter electrode. The IGBT region comprises a main region composed of a plurality of inter-trench semiconductor regions that are not provided with the hole injection suppression structure, and a boundary region composed of a plurality of inter-trench semiconductor regions located between the main region and the diode region. The hole injection suppression structure is provided in the semiconductor regions between trenches within the diode region and the boundary region. The width of the boundary region in the second direction is 80% or more of the thickness of the semiconductor substrate. Semiconductor element.

2. The semiconductor element according to claim 1, wherein the work function at the interface between the pillar region and the emitter electrode within the boundary region is lower than the work function at the interface between the pillar region and the emitter electrode within the diode region.

3. Each of the trench electrodes in the main region is a gate electrode, The semiconductor device according to claim 1 or 2, wherein at least one of the trench electrodes in the boundary region is a dummy electrode connected to the emitter electrode.

4. A semiconductor device, Semiconductor substrate and The emitter electrode in contact with the upper surface of the semiconductor substrate, A collector electrode in contact with the lower surface of the semiconductor substrate, It has, The aforementioned semiconductor substrate A p-type collector region in contact with the collector electrode, n-type cathode region in contact with the collector electrode, It has, When the semiconductor substrate is viewed along the thickness direction, the area overlapping with the collector region is the IGBT region, and the area overlapping with the cathode region is the diode region. When the direction along the boundary between the IGBT region and the diode region on the upper surface is defined as the first direction, and the direction from the IGBT region toward the diode region on the upper surface is defined as the second direction, a plurality of trenches are provided on the upper surface extending along the first direction, and the plurality of trenches are arranged at intervals in the second direction. The inner surface of each trench is covered with a trench insulating film. A trench electrode is placed in each of the trenches. Multiple inter-trench semiconductor regions, which are semiconductor regions sandwiched between the multiple trenches, are arranged in each of the IGBT region and the diode region. Each of the trench-inter-semiconductor regions within the IGBT region and the diode region has a p-type body region in contact with the emitter electrode and the trench insulating film. At least a portion of the trench-inter-semiconductor region within the IGBT region has an n-type emitter region that is in contact with the emitter electrode and is in contact with the trench insulating film above the body region. The semiconductor substrate is distributed across the IGBT region and the diode region, and has an n-type drift region located below the body region. A hole injection suppression structure is provided in which a portion of the multiple trench-inter-semiconductor regions has an n-type barrier region that contacts the body region from below, and a pillar region that extends from the barrier region to the emitter electrode and is in Schottky contact with the emitter electrode. The IGBT region comprises a main region composed of a plurality of inter-trench semiconductor regions that are not provided with the hole injection suppression structure, and a boundary region composed of a plurality of inter-trench semiconductor regions located between the main region and the diode region. The hole injection suppression structure is provided in the semiconductor regions between trenches within the diode region and the boundary region. The work function at the interface between the pillar region and the emitter electrode within the boundary region is lower than the work function at the interface between the pillar region and the emitter electrode within the diode region. Semiconductor element.

5. A semiconductor device, Semiconductor substrate and The emitter electrode in contact with the upper surface of the semiconductor substrate, A collector electrode in contact with the lower surface of the semiconductor substrate, It has, The aforementioned semiconductor substrate A p-type collector region in contact with the collector electrode, n-type cathode region in contact with the collector electrode, It has, When the semiconductor substrate is viewed along the thickness direction, the area overlapping with the collector region is the IGBT region, and the area overlapping with the cathode region is the diode region. When the direction along the boundary between the IGBT region and the diode region on the upper surface is defined as the first direction, and the direction from the IGBT region toward the diode region on the upper surface is defined as the second direction, a plurality of trenches are provided on the upper surface extending along the first direction, and the plurality of trenches are arranged at intervals in the second direction. The inner surface of each trench is covered with a trench insulating film. A trench electrode is placed in each of the trenches. Multiple inter-trench semiconductor regions, which are semiconductor regions sandwiched between the multiple trenches, are arranged in each of the IGBT region and the diode region. Each of the trench-inter-semiconductor regions within the IGBT region and the diode region has a p-type body region in contact with the emitter electrode and the trench insulating film. At least a portion of the trench-inter-semiconductor region within the IGBT region has an n-type emitter region that is in contact with the emitter electrode and is in contact with the trench insulating film above the body region. The semiconductor substrate is distributed across the IGBT region and the diode region, and has an n-type drift region located below the body region. A hole injection suppression structure is provided in which a portion of the multiple trench-inter-semiconductor regions has an n-type barrier region that contacts the body region from below, and a pillar region that extends from the barrier region to the emitter electrode and is in Schottky contact with the emitter electrode. A portion of the multiple trench-inter-semiconductor regions has a floating structure in which the upper surface is covered by an interlayer insulating film. The IGBT region comprises a main region composed of a plurality of inter-trench semiconductor regions that are not provided with the hole injection suppression structure, and a boundary region composed of a plurality of inter-trench semiconductor regions located between the main region and the diode region. Each of the trench-inter-semiconductor regions within the diode region has the hole injection suppression structure. Each of the inter-trench semiconductor regions within the boundary region has at least one of the hole injection suppression structure and the floating structure. Semiconductor element.

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