Semiconductor equipment

Abstract

Provided is a semiconductor device comprising an active part and a temperature-sensitive part, the semiconductor device comprising: a semiconductor substrate; and an interlayer insulating film provided above the semiconductor substrate. The active part includes an active trench part provided on a front surface of the semiconductor substrate, and an active contact part provided in the interlayer insulating film above the active trench part. The temperature-sensitive part has a temperature-sensitive diode provided above the semiconductor substrate, and a temperature-sensitive contact part provided in the interlayer insulating film above the temperature-sensitive diode. The contact width of the temperature-sensitive contact part is larger than the contact width of the active contact part. In the depth direction of the semiconductor substrate, the extension depth of the temperature-sensitive trench contact portion extending from an upper surface of the temperature-sensitive diode in the depth direction of the semiconductor substrate is shallower than the extension depth of the plurality of active trench contact portions extending from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background Art]

[0002] Patent Document 1 describes "a semiconductor device including an integrated PN diode temperature sensor and a method for manufacturing the same". [Prior Art Documents] [Patent Documents] [Patent Document 1] US Patent Application Publication No. 2019 / 0172770 Specification General Disclosure

[0003] According to a first aspect of the present invention, there is provided a semiconductor device including an active portion and a temperature-sensitive portion, the semiconductor device comprising: a semiconductor substrate of a first conductivity type; and an interlayer insulating film provided above a front surface of the semiconductor substrate, wherein the active portion has an active trench portion provided on the front surface of the semiconductor substrate, and an active contact portion provided in the interlayer insulating film, the temperature-sensitive portion has a temperature-sensitive diode provided above the front surface of the semiconductor substrate or on a front surface side of the semiconductor substrate, and a temperature-sensitive contact portion provided in the interlayer insulating film above the temperature-sensitive diode, and a contact width of the temperature-sensitive contact portion is larger than a contact width of the active contact portion.

[0004] In the above semiconductor device, a temperature-sensitive contact width at which the temperature-sensitive contact portion contacts the temperature-sensitive diode may be larger than a first active contact width at which the active contact portion contacts an upper surface of a mesa portion of the semiconductor substrate.

[0005] In any one of the above semiconductor devices, a temperature-sensitive contact width at which the temperature-sensitive contact portion contacts the temperature-sensitive diode may be larger than a second active contact width at which the active contact portion contacts the active trench portion.

[0006] In any one of the above semiconductor devices, a side wall of the temperature-sensitive contact portion may be in contact with the interlayer insulating film from an upper end to a lower end thereof.

[0007] In any of the semiconductor devices described above, the temperature-sensing portion may have a recessed region on the upper surface of the semiconductor substrate. The temperature-sensing diode may be provided in the recessed region.

[0008] In any of the above semiconductor devices, the height position of the upper surface of the interlayer insulating film in the active portion may be the same as the height position of the upper surface of the interlayer insulating film in the recess region in the depth direction of the semiconductor substrate.

[0009] In any of the semiconductor devices described above, the temperature-sensing portion may have a housing portion provided below the temperature-sensing contact portion. The bottom corner of the temperature-sensing contact portion may be in contact with the temperature-sensing diode. The bottom surface of the temperature-sensing contact portion may be in contact with the housing portion.

[0010] In any of the semiconductor devices described above, the side surface of the temperature-sensitive diode may be in contact with the side surface of the housing.

[0011] In any of the semiconductor devices described above, the interlayer insulating film may include a first interlayer insulating film provided above the temperature-sensitive diode, and a second interlayer insulating film provided between the temperature-sensitive diode and the semiconductor substrate in the depth direction of the semiconductor substrate.

[0012] In any of the semiconductor devices described above, the upper surface of the second interlayer insulating film may be in contact with the lower surface of the temperature-sensitive diode and the lower surface of the housing portion.

[0013] In any of the above semiconductor devices, the housing portion may be a region of the first interlayer insulating film located below the temperature-sensitive contact portion.

[0014] In any of the above semiconductor devices, the housing portion may be the second interlayer insulating film provided above the semiconductor substrate.

[0015] In any of the above semiconductor devices, the housing portion may have a polycrystalline semiconductor with a conductivity different from that of the contact region of the temperature-sensitive diode.

[0016] In any of the above semiconductor devices, the housing portion may have a polycrystalline semiconductor having the same conductivity type as the contact region of the temperature-sensitive diode and a lower doping concentration than the contact region.

[0017] In any of the semiconductor devices described above, the bottom surface of the temperature-sensitive contact portion may be in contact with the temperature-sensitive diode and the housing portion.

[0018] In any of the semiconductor devices described above, the temperature-sensitive contact portion may include a barrier metal film provided at the bottom corner of the temperature-sensitive contact portion and a plug portion provided in contact with the inside of the barrier metal film.

[0019] In any of the semiconductor devices described above, the temperature-sensitive diode may be in contact with the bottom surface of the temperature-sensitive contact portion from the bottom surface corner to an area of ​​10% to 40% of the bottom surface of the temperature-sensitive contact portion.

[0020] In any of the semiconductor devices described above, the side wall of the temperature-sensing contact portion may be in contact with the temperature-sensing diode and the first interlayer insulating film. The temperature-sensing diode may be in contact with the side wall of the temperature-sensing contact portion from the bottom corner to an area of ​​10% to 90% of the side wall of the temperature-sensing contact portion.

[0021] In any of the semiconductor devices described above, the temperature-sensing portion may have a temperature-sensing trench contact portion that extends in the depth direction of the semiconductor substrate from the upper surface of the interlayer insulating film to a position lower than the upper surface of the temperature-sensing diode.

[0022] In any of the semiconductor devices described above, the active portion may have an active trench contact portion that extends in the depth direction of the semiconductor substrate from the upper surface of the interlayer insulating film downward from the front surface of the semiconductor substrate.

[0023] In any of the above semiconductor devices, the temperature-sensitive diode may comprise: a temperature-sensitive anode region provided above the semiconductor substrate; and a temperature-sensitive cathode region provided above the semiconductor substrate and disposed in contact with the temperature-sensitive anode region.

[0024] Any of the above semiconductor devices may further comprise a well region of a second conductivity type provided on a front surface of the semiconductor substrate. The temperature-sensitive portion may be provided above the well region or on a front surface side of the semiconductor substrate in the well region.

[0025] According to a second aspect of the present invention, there is provided a semiconductor device comprising: an active portion having a plurality of active trench contact portions provided on a front surface of a semiconductor substrate of a first conductivity type; and a temperature-sensitive portion provided above the semiconductor substrate or on a front surface side of the semiconductor substrate, wherein the temperature-sensitive portion comprises: a temperature-sensitive diode provided above the semiconductor substrate; an interlayer insulating film provided above the temperature-sensitive diode; and a temperature-sensitive trench contact portion provided extending from an upper surface of the interlayer insulating film to a position lower than an upper surface of the temperature-sensitive diode in a depth direction of the semiconductor substrate, wherein an extension depth by which the temperature-sensitive trench contact portion extends from the upper surface of the temperature-sensitive diode in the depth direction of the semiconductor substrate is smaller than an extension depth by which each of the plurality of active trench contact portions extends from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate.

[0026] In the above semiconductor device, the temperature-sensitive portion may have a recess region in which a depression is provided on an upper surface of the semiconductor substrate. The temperature-sensitive diode may be provided in the recess region.

[0027] In any of the above semiconductor devices, a contact width at which the temperature-sensitive trench contact portion is in contact with the temperature-sensitive diode may be larger than a contact width of each of the plurality of active trench contact portions.

[0028] In any of the semiconductor devices described above, a contact width at which the temperature-sensitive trench contact portion contacts the temperature-sensitive diode may be smaller than the contact width of each of the plurality of active trench contact portions.

[0029] Any of the semiconductor devices described above may include a well region of a second conductivity type provided on a front surface of the semiconductor substrate. The temperature-sensitive portion may be provided above the well region or on the front surface side of the semiconductor substrate in the well region.

[0030] According to a third aspect of the present invention, there is provided a semiconductor device including a main region and an outer peripheral region, the semiconductor device comprising: a semiconductor substrate of a first conductivity type; and an interlayer insulating film provided above a front surface of the semiconductor substrate, wherein the main region has a main region contact portion provided in the interlayer insulating film, the outer peripheral region includes: a polycrystalline portion provided above the front surface of the semiconductor substrate or on the front surface side of the semiconductor substrate; and a first outer peripheral region contact portion provided in the interlayer insulating film above the polycrystalline portion, and a contact width of the first outer peripheral region contact portion is larger than a contact width of the main region contact portion.

[0031] In the semiconductor device described above, a sidewall of the first outer peripheral region contact portion may be in contact with the interlayer insulating film from an upper end to a lower end thereof.

[0032] In any of the semiconductor devices described above, the outer peripheral region may have a recess region in which a recess is provided on an upper surface of the semiconductor substrate. The polycrystalline portion may be provided in the recess region.

[0033] In any of the semiconductor devices described above, in a depth direction of the semiconductor substrate, a height position of an upper surface of the interlayer insulating film in the main region may be the same as a height position of an upper surface of the interlayer insulating film in the recess region.

[0034] In any of the semiconductor devices described above, the outer peripheral region may have a housing portion provided below the first outer peripheral region contact portion. The bottom corner of the first outer peripheral region contact portion may be in contact with the polycrystalline portion. The bottom surface of the first outer peripheral region contact portion may be in contact with the housing portion.

[0035] In any of the semiconductor devices described above, the side surface of the polycrystalline portion may be in contact with the side surface of the housing portion.

[0036] In any of the above semiconductor devices, the housing portion may be a region of the interlayer insulating film located below the first outer peripheral region contact portion.

[0037] In any of the semiconductor devices described above, the bottom surface of the first peripheral region contact portion may be in contact with the polycrystalline portion and the housing portion.

[0038] In any of the semiconductor devices described above, the first peripheral region contact portion may include a barrier metal film provided at the bottom corner of the first peripheral region contact portion and a plug portion provided in contact with the inside of the barrier metal film.

[0039] In any of the semiconductor devices described above, the polycrystalline portion may be in contact with the bottom surface of the first peripheral region contact portion from the bottom surface corner to an area of ​​10% to 40% of the bottom surface of the first peripheral region contact portion.

[0040] In any of the semiconductor devices described above, the sidewall of the first peripheral region contact portion may be in contact with the polycrystalline portion and the interlayer insulating film. The polycrystalline portion may be in contact with the sidewall of the peripheral region contact portion from the bottom corner to an area of ​​10% to 90% of the sidewall of the first peripheral region contact portion.

[0041] In any of the semiconductor devices described above, the peripheral region may have a first peripheral region trench contact portion that extends in the depth direction of the semiconductor substrate from the upper surface of the interlayer insulating film to below the upper surface of the polycrystalline portion.

[0042] In any of the semiconductor devices described above, the main region may have a main region trench contact portion that extends in the depth direction of the semiconductor substrate from the upper surface of the interlayer insulating film downward from the front surface of the semiconductor substrate.

[0043] Any of the above semiconductor devices may include a gate trench portion provided on the front surface of the semiconductor substrate and having a gate conductive portion, and a gate metal layer provided above the semiconductor substrate and electrically connected to the gate conductive portion. The polycrystalline portion may be connected to the gate metal layer via the first outer peripheral region contact portion and connected to the gate conductive portion.

[0044] Any of the above semiconductor devices may include a dummy trench portion provided on the front surface of the semiconductor substrate and having a dummy conductive portion, and an emitter electrode provided above the semiconductor substrate and electrically connected to the semiconductor substrate. The polycrystalline portion may be connected to the emitter electrode via the first outer peripheral region contact portion and to the dummy conductive portion.

[0045] Any of the above semiconductor devices may include a second conductivity type guard ring provided on the front surface of the semiconductor substrate between the main region and the edge of the semiconductor substrate, and an edge metal layer provided above the semiconductor substrate and electrically connected to the guard ring. The polycrystalline portion may be connected to the edge metal layer via the first outer peripheral region contact portion.

[0046] A fourth embodiment of the present invention provides a semiconductor device comprising a main region and a peripheral region, wherein the main region has a plurality of main region trench contact portions provided on the front surface of a first conductivity type semiconductor substrate, the peripheral region has a polycrystalline portion provided above the semiconductor substrate, an interlayer insulating film provided above the polycrystalline portion, and a peripheral region trench contact portion provided extending in the depth direction of the semiconductor substrate from the upper surface of the interlayer insulating film downward from the upper surface of the polycrystalline portion, wherein the extension depth of the peripheral region trench contact portions extending from the upper surface of the polycrystalline portion in the depth direction of the semiconductor substrate is shallower than the extension depth of the plurality of main region trench contact portions extending from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate.

[0047] In the semiconductor device described above, the outer peripheral region may have a recess region in which a depression is provided on the upper surface of the semiconductor substrate. The polycrystalline portion may be provided in the recess region.

[0048] In any of the semiconductor devices described above, the contact width of the outer peripheral trench contact portion in contact with the polycrystalline portion may be larger than the contact width of each of the multiple main trench contact portions.

[0049] In any of the semiconductor devices described above, the contact width of the outer peripheral trench contact portion in contact with the polycrystalline portion may be smaller than the contact width of each of the multiple main trench contact portions.

[0050] Any of the above semiconductor devices may include a gate trench portion provided on the front surface of the semiconductor substrate and having a gate conductive portion, and a gate metal layer provided above the semiconductor substrate and electrically connected to the gate conductive portion. The polycrystalline portion may be connected to the gate metal layer via the outer peripheral trench contact portion and connected to the gate conductive portion.

[0051] Any of the above semiconductor devices may include a dummy trench portion provided on the front surface of the semiconductor substrate and having a dummy conductive portion, and an emitter electrode provided above the semiconductor substrate and electrically connected to the semiconductor substrate. The polycrystalline portion may be connected to the emitter electrode via the outer peripheral trench contact portion and to the dummy conductive portion.

[0052] Any of the above semiconductor devices may include a second-conductivity type guard ring provided on the front surface of the semiconductor substrate between the main region and the edge of the semiconductor substrate, and an edge metal layer provided above the semiconductor substrate and electrically connected to the guard ring. The polycrystalline portion may be connected to the edge metal layer via the outer peripheral region trench contact portion.

[0053] In any of the semiconductor devices described above, the outer peripheral region may have a second outer peripheral trench contact portion that extends from the upper surface of the interlayer insulating film to below the upper surface of the semiconductor substrate in the depth direction of the semiconductor substrate, in the region where the polycrystalline portion is not provided. The extension depth of the first outer peripheral trench contact portion from the upper surface of the polycrystalline portion to the depth direction of the semiconductor substrate may be shallower than the extension depth of the second outer peripheral trench contact portion from the front surface of the semiconductor substrate to the depth direction of the semiconductor substrate.

[0054] In any of the semiconductor devices described above, the outer peripheral region may have a second outer peripheral region trench contact portion that extends from the upper surface of the interlayer insulating film to below the upper surface of the semiconductor substrate in the depth direction of the semiconductor substrate, in the region where the polycrystalline portion is not provided. The extension depth of the first outer peripheral region trench contact portion from the upper surface of the polycrystalline portion to the depth direction of the semiconductor substrate and the extension depth of the second outer peripheral region trench contact portion from the front surface of the semiconductor substrate to the depth direction of the semiconductor substrate may be shallower than the extension depth of the plurality of main region trench contact portions from the front surface of the semiconductor substrate to the depth direction of the semiconductor substrate.

[0055] A fourth embodiment of the present invention provides a semiconductor device comprising a main region and a pad region, wherein the main region has a plurality of main region trench contact portions provided on the front surface of a first conductivity type semiconductor substrate, the pad region has a pad for connecting to an external circuit, a polycrystalline portion provided above the semiconductor substrate, an interlayer insulating film provided above the polycrystalline portion, and a pad region trench contact portion provided extending in the depth direction of the semiconductor substrate from the upper surface of the interlayer insulating film to below the upper surface of the polycrystalline portion, wherein the extension depth of the pad region trench contact portion extending from the upper surface of the polycrystalline portion in the depth direction of the semiconductor substrate is shallower than the extension depth of the plurality of main region trench contact portions extending from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate.

[0056] It should be noted that the above summary of the invention does not enumerate all of its features. Furthermore, subcombinations of these features may also constitute an invention. [Brief explanation of the drawing]

[0057] [Figure 1A] An example of an enlarged view of the top surface of the semiconductor device 100 is shown. [Figure 1B] An example of a cross-section from a-a' in Figure 1A is shown. [Figure 2A] An enlarged view of the top surface of a modified example of the semiconductor device 100 is shown. [Figure 2B] An example of a cross-section between b and b' in Figure 2A is shown. [Figure 3] An example of a top view of the semiconductor device 100 is shown. [Figure 4A] An example of a cross-section of a semiconductor device 100 equipped with a temperature-sensing element 180 is shown. [Figure 4B] Another example of a cross-section of the semiconductor device 100 equipped with a temperature-sensing element 180 is shown. [Figure 4C] A cross-section of a modified semiconductor device 100 equipped with a temperature-sensing element 180 is shown. [Figure 5A]A cross-section of a modified semiconductor device 100 equipped with a temperature-sensing element 180 is shown. [Figure 5B] A cross-section of a modified semiconductor device 100 equipped with a temperature-sensing element 180 is shown. [Figure 6A] An example of an enlarged cross-sectional view of semiconductor device 100 is shown. [Figure 6B] This shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. [Figure 6C] This shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. [Figure 7A] This shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. [Figure 7B] This shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. [Figure 7C] This shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. [Figure 8A] A cross-section of a modified semiconductor device 100 equipped with a temperature-sensing element 180 is shown. [Figure 8B] A cross-section of a modified semiconductor device 100 equipped with a temperature-sensing element 180 is shown. [Figure 8C] A cross-section of a modified semiconductor device 100 equipped with a temperature-sensing element 180 is shown. [Figure 9] An example of an enlarged view of the top surface of the semiconductor device 100 is shown. [Figure 10A] An example of a d-d' section is shown in Figure 9. [Figure 10B] An example of a d-d' section is shown in Figure 9. [Figure 11A] An example of a d-d' section is shown in Figure 9. [Figure 11B] An example of a d-d' section is shown in Figure 9. [Figure 12A] An example of a d-d' section is shown in Figure 9. [Figure 12B] An example of an enlarged view of the d-d' section in Figure 9 is shown. [Figure 13A] An example of a d-d' section is shown in Figure 9. [Figure 13B] An example of an enlarged view of the d-d' section in Figure 9 is shown. [Figure 14A]An example of the e-e' section in Figure 9 is shown. [Figure 14B] An example of the e-e' section in Figure 9 is shown. [Figure 15A] An example of the e-e' section in Figure 9 is shown. [Figure 15B] An example of the e-e' section in Figure 9 is shown. [Figure 16A] An example of the e-e' section in Figure 9 is shown. [Figure 16B] An example of an enlarged view of the e-e' cross section in Figure 9 is shown. [Figure 17A] An example of the e-e' section in Figure 9 is shown. [Figure 17B] An example of an enlarged view of the e-e' cross section in Figure 9 is shown. [Figure 18A] An example of a top view of the semiconductor device 100 is shown. [Figure 18B] An example of region R in Figure 18A is shown. [Figure 19A] An example of the f-f' section in Figure 18B is shown. [Figure 19B] An example of the f-f' section in Figure 18B is shown. [Figure 19C] An example of the f-f' section in Figure 18B is shown. [Figure 20A] An example of the f-f' section in Figure 18B is shown. [Figure 20B] An example of the f-f' section in Figure 18B is shown. [Figure 21A] An example of the f-f' section in Figure 18B is shown. [Figure 21B] An example of an enlarged view of the f-f' section in Figure 18B is shown. [Figure 21C] An example of an enlarged view of the f-f' section in Figure 18B is shown. [Figure 21D] An example of an enlarged view of the f-f' section in Figure 18B is shown. [Figure 22A] An example of the f-f' section in Figure 18B is shown. [Figure 22B] An example of the f-f' section in Figure 18B is shown. [Figure 22C]An example of an enlarged view of the f-f' section in Figure 18B is shown. [Figure 22D] An example of an enlarged view of the f-f' section in Figure 18B is shown. [Figure 22E] An example of an enlarged view of the f-f' section in Figure 18B is shown. [Figure 23A] An example of the f-f' section in Figure 18B is shown. [Figure 23B] An example of an enlarged view of the f-f' section in Figure 18B is shown. [Figure 23C] An example of an enlarged view of the f-f' section in Figure 18B is shown. [Figure 24A] An example of the f-f' section in Figure 18B is shown. [Figure 24B] An example of the f-f' section in Figure 18B is shown. [Figure 24C] An example of an enlarged view of the f-f' section in Figure 18B is shown. [Figure 24D] An example of an enlarged view of the f-f' section in Figure 18B is shown. [Figure 25] An example of a g-g' cross section is shown in Figure 18A. [Figure 26] An example of a g-g' cross section is shown in Figure 18A. [Figure 27] An example of a g-g' cross section is shown in Figure 18A. [Figure 28] An example of a g-g' cross section is shown in Figure 18A. [Figure 29] This is an example of the electrical connections of various parts of the semiconductor device 100. [Modes for carrying out the invention]

[0058] The present invention will be described below through embodiments, but these embodiments are not intended to limit the scope of the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0059] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "top," and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the top surface, and the other surface as the bottom surface. The directions of "top" and "bottom" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted.

[0060] In this specification, technical matters may be described using the Cartesian coordinate axes, the X, Y, and Z axes. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z and -Z axes.

[0061] In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X and Y axes, may be referred to as the horizontal direction.

[0062] In this specification, the terms "identical" or "equal" may include cases where there are errors due to manufacturing variations, etc. Such errors are, for example, within 10%.

[0063] In this specification, the conductivity type of a doped region containing impurities is described as either P-type or N-type. In this specification, impurities may specifically refer to either N-type donors or P-type acceptors, and may be referred to as dopants. In this specification, doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor exhibiting either an N-type conductivity or a P-type conductivity.

[0064] In this specification, doping concentration means the concentration of the donor or acceptor at thermal equilibrium. In this specification, net doping concentration means the net concentration obtained by adding the charge polarity of the donor concentration (where the donor concentration is the concentration of positive ions) and the acceptor concentration (where the acceptor concentration is the concentration of negative ions). For example, if the donor concentration is ND and the acceptor concentration is NA, the net doping concentration at any given position will be ND-NA. In this specification, net doping concentration may sometimes be simply referred to as doping concentration.

[0065] Donors have the function of supplying electrons to a semiconductor. Acceptors have the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, VOH defects, which are formed by the bonding of vacancies (V), oxygen (O), and hydrogen (H) in a semiconductor; Si-iH defects, which are formed by the bonding of interstitial silicon (Si-i) and hydrogen; and CiOi-H defects, which are formed by the bonding of interstitial carbon (Ci), interstitial oxygen (Oi), and hydrogen, all function as electron donors. In this specification, these defects may be referred to as hydrogen donors.

[0066] In this specification, when P+ or N+ is mentioned, it means a higher doping concentration than P or N, and when P- or N- is mentioned, it means a lower doping concentration than P or N. Furthermore, when P++ or N++ is mentioned in this specification, it means a higher doping concentration than P+ or N+.

[0067] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electrical activation state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by voltage-capacitance (CV) spectroscopy. Alternatively, the carrier concentration measured by spheroidal resistance (SR) spectroscopy may be used as the net doping concentration. A carrier refers to an electron or hole charge carrier. The carrier concentration measured by CV or SR spectroscopy may be the value at thermal equilibrium. Furthermore, in the N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in that region may be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in that region may be used as the acceptor concentration. In this specification, the doping concentration in the N-type region may be referred to as the donor concentration, and the doping concentration in the P-type region may be referred to as the acceptor concentration.

[0068] Furthermore, if the concentration distribution of donor, acceptor, or net doping has a peak, the peak value may be used as the concentration of donor, acceptor, or net doping in that region. In cases where the concentrations of donor, acceptor, or net doping are nearly uniform, the average value of the concentrations of donor, acceptor, or net doping in that region may be used as the concentration of donor, acceptor, or net doping.

[0069] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. When measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state within the range where current flows. The decrease in carrier mobility occurs because carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc. The reason for the decrease in carrier concentration is as follows: In the SR method, spreading resistance is measured, and the carrier concentration is converted from the measured value of spreading resistance. At this time, the carrier mobility of the crystalline state is used. On the other hand, at locations where lattice defects are introduced, the carrier concentration is calculated using the carrier mobility of the crystalline state, even though the carrier mobility is reduced. Therefore, the value will be lower than the actual carrier concentration, i.e., the donor or acceptor concentration.

[0070] The donor or acceptor concentrations calculated from carrier concentrations measured by the CV method or SR method may be lower than the chemical concentrations of the elements that represent the donor or acceptor. For example, in silicon semiconductors, the donor concentrations of phosphorus or arsenic, or the acceptor concentrations of boron, are approximately 99% of their respective chemical concentrations. On the other hand, the donor concentration of hydrogen, which is a donor in silicon semiconductors, is approximately 0.1% to 10% of the hydrogen chemical concentration. This specification adopts the SI unit system. In this specification, units of distance and length may be expressed in cm (centimeters). In this case, calculations may be performed by converting to m (meters). Regarding the numerical representation of powers of 10, for example, the representation of 1E+16 is 1 × 10⁻⁶ 16 This indicates that the 1E-16 designation is 1 × 10 -16 This indicates.

[0071] Figure 1A shows an example of an enlarged view of the top surface of the semiconductor device 100. The semiconductor device 100 in this example is a semiconductor chip equipped with a transistor section 70. The semiconductor device 100 is not limited to a transistor, as long as it is a semiconductor element having a MOS gate structure on the semiconductor substrate 10. The configuration shown in this figure may be arranged periodically or continuously in the +X axis direction and the -X axis direction.

[0072] The transistor section 70 is the region obtained by projecting the collector region 22, which is provided on the back side of the semiconductor substrate 10, onto the upper surface of the semiconductor substrate 10. The collector region 22 will be described later. The transistor section 70 includes a transistor such as an IGBT. In this example, the transistor section 70 is an IGBT. However, the transistor section 70 may also be other transistors such as a MOSFET.

[0073] In this figure, the region around the active area 120 of the semiconductor device 100 is shown, and other regions are omitted. The active area 120 is the part where the main current flows between the front surface 21 and the back surface 23 of the semiconductor substrate 10. The active area 120 will be described later. For example, an edge termination structure may be provided in the negative region in the Y-axis direction of the semiconductor device 100 in this example. The edge termination structure mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure has, for example, a guard ring, a field plate, a resurf, or a structure combining these. In this example, for convenience, the negative edge in the Y-axis direction is described, but the same applies to other edges of the semiconductor device 100.

[0074] The semiconductor substrate 10 is a substrate formed of a semiconductor material. The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, another compound semiconductor substrate, or a diamond semiconductor substrate. In this example, the semiconductor substrate 10 is a silicon substrate. In this specification, when simply referred to as a "top view," it means viewing from the top side of the semiconductor substrate 10. The semiconductor substrate 10 has a front surface 21 and a back surface 23, as described later.

[0075] The semiconductor device 100 in this example comprises a gate trench 40, a dummy trench 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 also includes an emitter electrode 52 and a gate metal layer 50 located above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and gate metal layer 50 are examples of front-side metal layers. The gate trench 40 is an example of a MOS gate structure provided by the semiconductor device 100. While the semiconductor device 100 in this example is a transistor with a MOS gate structure, it may also be a diode with a MOS gate structure.

[0076] The emitter electrode 52 is located above the gate trench 40, dummy trench 30, emitter region 12, base region 14, contact region 15, and well region 17. The gate metal layer 50 is located above the connection portion 25 and the well region 17.

[0077] The emitter electrode 52 and the gate metal layer 50 are formed from a metal-containing material. At least a portion of the emitter electrode 52 may be formed from a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate metal layer 50 may be formed from a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate metal layer 50 may have a barrier metal film formed of titanium or a titanium compound in the layer below the region formed of aluminum or the like. The emitter electrode 52 and the gate metal layer 50 are provided separated from each other.

[0078] The emitter electrode 52 and gate metal layer 50 are provided above the semiconductor substrate 10, with an interlayer insulating film 38 in between. The interlayer insulating film 38 is omitted in Figure 1A. Contact holes 54, 55, and 56 are provided through the interlayer insulating film 38.

[0079] The contact hole 55 electrically connects the gate metal layer 50 and the gate conductive part within the transistor section 70 via the connection section 25. A barrier metal film made of titanium or a titanium compound and / or a plug made of tungsten may be formed inside the contact hole 55.

[0080] The contact hole 56 connects the emitter electrode 52 to the dummy conductive part in the dummy trench 30. A barrier metal film made of titanium or a titanium compound and / or a plug made of tungsten may be formed inside the contact hole 56.

[0081] The connection portion 25 is connected to the front-side metal layer, such as the emitter electrode 52 or the gate metal layer 50. In one example, the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion. In this example, the connection portion 25 may be provided extending in the X-axis direction and electrically connected to the gate conductive portion. The connection portion 25 may also be provided between the emitter electrode 52 and the dummy conductive portion. In this example, the connection portion 25 is not provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is made of a conductive material such as polysilicon doped with impurities. In this example, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0082] The gate trench portion 40 is an example of an active trench portion 122 provided on the front surface 21 of the semiconductor substrate 10. That is, the active trench portion 122 may be a trench portion provided in the active portion 120. The gate trench portion 40 is arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The gate trench portion 40 in this example may have two extended portions 41 that extend along an extension direction (in this example, the Y-axis direction) that is parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connecting portion 43 that connects the two extended portions 41.

[0083] It is preferable that at least a portion of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extended portions 41 of the gate trench portion 40, electric field concentration at the ends of the extended portions 41 can be mitigated. In the connection portion 43 of the gate trench portion 40, the gate metal layer 50 may be electrically connected to the gate conductive portion via the connection portion 25.

[0084] The dummy trench portion 30 is an example of an active trench portion 122 provided on the front surface 21 of the semiconductor substrate 10. That is, the active trench portion 122 may be a trench portion provided on the active portion 120. The dummy trench portion 30 is a trench portion electrically connected to the emitter electrode 52. The dummy trench portion 30, like the gate trench portion 40, is arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). In this example, the dummy trench portion 30 has an I-shape on the front surface 21 of the semiconductor substrate 10, but like the gate trench portion 40, it may have a U-shape on the front surface 21 of the semiconductor substrate 10. That is, the dummy trench portion 30 may have two extended portions that extend along the stretching direction and a connecting portion that connects the two extended portions.

[0085] The transistor section 70 in this example has a structure in which two gate trench sections 40 and two dummy trench sections 30 are arranged in a repeating pattern. That is, the transistor section 70 in this example has gate trench sections 40 and dummy trench sections 30 in a 1:1 ratio. For example, the transistor section 70 has one dummy trench section 30 between two extended sections 41.

[0086] However, the ratio of the gate trench portion 40 to the dummy trench portion 30 is not limited to this example. The ratio of the gate trench portion 40 may be greater than the ratio of the dummy trench portion 30, and vice versa. The ratio of the gate trench portion 40 to the dummy trench portion 30 may be 2:3 or 2:4. Furthermore, the transistor portion 70 may have all trenches as gate trench portions 40 and not have dummy trench portions 30.

[0087] The well region 17 is a second conductivity type region located on the front surface 21 side of the semiconductor substrate 10, closer to the drift region 18, which will be described later. The well region 17 is an example of a well region located on the peripheral side of the active portion 120. The well region 17 is, for example, of the P+ type. The well region 17 is formed within a predetermined range from the edge of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. A portion of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side is formed in the well region 17. The bottom of the extending end of the gate trench portion 40 and the dummy trench portion 30 may be covered by the well region 17.

[0088] The contact holes 54 are formed above the emitter region 12 and the contact region 15 in the transistor section 70. The contact holes 54 are not provided above the well regions 17 provided at both ends in the Y-axis direction. Thus, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 may be provided by extending in the stretching direction.

[0089] The mesa portion 71 is a mesa portion provided adjacent to the trench portion in a plane parallel to the front surface 21 of the semiconductor substrate 10. The mesa portion is the part of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be the portion from the front surface 21 of the semiconductor substrate 10 to the depth of the deepest bottom of each trench portion. The extended portion of each trench portion may be considered as one trench portion. That is, the region sandwiched between two extended portions may be considered as the mesa portion.

[0090] The mesa portion 71 is provided in the transistor portion 70 adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface 21 of the semiconductor substrate 10. In the mesa portion 71, the emitter region 12 and the contact region 15 are provided alternately in the stretching direction.

[0091] The base region 14 is a second conductivity type region provided on the front surface 21 side of the semiconductor substrate 10. The base region 14 is, for example, P-type. The base region 14 may be provided at both ends of the mesa portion 71 in the Y-axis direction on the front surface 21 of the semiconductor substrate 10. Note that Figure 1A shows only one end of the base region 14 in the Y-axis direction.

[0092] The emitter region 12 is a first conductivity type region with a higher doping concentration than the drift region 18. In this example, the emitter region 12 is N+ type. An example of a dopant for the emitter region 12 is arsenic (As). The emitter region 12 is provided on the front surface 21 of the mesa portion 71, in contact with the gate trench portion 40. The emitter region 12 may extend in the X-axis direction from one of the two trench portions flanking the mesa portion 71 to the other. The emitter region 12 is also provided below the contact hole 54.

[0093] Furthermore, the emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30.

[0094] The contact region 15 is located above the base region 14 and is a region of a second conductivity type with a higher doping concentration than the base region 14. In this example, the contact region 15 is of type P+. In this example, the contact region 15 is located on the front surface 21 of the mesa portion 71. The contact region 15 may be located in the X-axis direction from one of the two trench portions flanking the mesa portion 71 to the other. The contact region 15 may or may not be in contact with the gate trench portion 40 or the dummy trench portion 30. In this example, the contact region 15 is in contact with both the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also located below the contact hole 54.

[0095] Figure 1B shows an example of the a-a' cross-section in Figure 1A. The a-a' cross-section is the XZ plane passing through the emitter region 12 in the transistor section 70. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, a collector electrode 24, and an active contact portion 124 in the a-a' cross-section. The collector electrode 24 is an example of a back-side metal layer provided in contact with the back surface 23 of the semiconductor substrate 10. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0096] The drift region 18 is a region of a first conductivity type provided on the semiconductor substrate 10. In this example, the drift region 18 is N-type. The drift region 18 may be a region remaining on the semiconductor substrate 10 without other doping regions being formed. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0097] The buffer region 20 is a first-conductivity region located on the back surface 23 side of the semiconductor substrate 10, relative to the drift region 18. In this example, the buffer region 20 is N-type. The doping concentration of the buffer region 20 is higher than that of the drift region 18. The buffer region 20 may function as a field stop layer to prevent the depletion layer extending from the underside of the base region 14 from reaching the collector region 22 of the second-conductivity region. The buffer region 20 may be omitted.

[0098] The collector region 22 is located below the buffer region 20 in the transistor section 70. The collector region 22 has a second conductivity type. In this example, the collector region 22 is of type P+.

[0099] The collector electrode 24 is formed on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a conductive material such as metal. The material of the collector electrode 24 may be the same as or different from the material of the emitter electrode 52.

[0100] The base region 14 is a second conductivity type region located above the drift region 18. The base region 14 is located in contact with the gate trench portion 40. The base region 14 may be located in contact with the dummy trench portion 30.

[0101] The emitter region 12 is provided above the base region 14. The emitter region 12 is provided between the base region 14 and the front surface 21. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30.

[0102] The storage region 16 is a first conductivity type region located on the front surface 21 side of the semiconductor substrate 10, relative to the drift region 18. In this example, the storage region 16 is of type N+. However, the storage region 16 does not necessarily have to be provided.

[0103] The accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration in the accumulation region 16 is higher than the doping concentration in the drift region 18. The ion implantation dose in the accumulation region 16 is 1.0E+12cm -2 The above is 1.0E+13cm -2 The following may be the case. Also, the ion implantation dose for the accumulation region 16 is 3.0E+12cm². -2 The above is 6.0E+12cm -2 The following is also possible: By providing a storage region 16, the carrier injection promotion effect (IE effect) can be enhanced, and the on-voltage of the transistor section 70 can be reduced.

[0104] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the front surface 21. Each trench may be an active trench 122 of the active section 120. Each trench extends from the front surface 21 to the drift region 18. In regions where at least one of the emitter region 12, base region 14, contact region 15, and storage region 16 is provided, each trench penetrates these regions as well and reaches the drift region 18. The statement that a trench penetrates a doping region is not limited to those manufactured in the order of forming the doping region before forming the trenches. Even when doping regions are formed between trenches after the trenches have been formed, the trenches are still included in the statement that they penetrate a doping region.

[0105] The gate trench portion 40 has a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, on the inside of the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 by an interlayer insulating film 38.

[0106] The gate conductive portion 44 includes a region in the depth direction of the semiconductor substrate 10 that faces an adjacent base region 14 on the mesa portion 71 side, with the gate insulating film 42 in between. When a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is created on the surface layer of the interface in contact with the gate trench within the base region 14.

[0107] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is formed inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 may be covered with an interlayer insulating film 38 on the front surface 21.

[0108] The interlayer insulating film 38 is provided above the semiconductor substrate 10. In this example, the interlayer insulating film 38 is provided in contact with the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. The interlayer insulating film 38 is provided with one or more contact holes 54 for electrically connecting the emitter electrode 52 and the semiconductor substrate 10. Similarly, contact holes 55 and 56 may be provided through the interlayer insulating film 38. The interlayer insulating film 38 may be a BPSG (Boro-phospho Silicate Glass) film, a BSG (borosilicate glass) film, a PSG (Phosphosilicate glass) film, an HTO film, or a laminate of these materials. The thickness of the interlayer insulating film 38 is, for example, 1.0 μm, but is not limited thereto.

[0109] The active contact portion 124 is provided in the interlayer insulating film 38 above the active trench portion 122. The active contact portion 124 may include a first active contact portion 1241 and a second active contact portion 1242, which will be described later. The first active contact portion 1241 may be in contact with the upper surface of the mesa portion of the semiconductor substrate 10. The first active contact portion 1241 may have a contact hole 54 and a metal layer filled inside the contact hole 54. The inside of the contact hole 54 may be filled with the same material as the emitter electrode 52, or with a different material than the emitter electrode 52. The active contact portion 124 may include a barrier metal film 1243 provided in the contact hole 54 and in contact with the semiconductor substrate 10. The active contact portion 124 may include a plug portion 1244 that is in contact with the barrier metal film 1243 and is provided to fill the contact hole 54. The barrier metal film 1243 of the active contact portion 124 may contain titanium or a titanium compound. The plug portion 1244 of the active contact portion 124 may contain a plug metal such as tungsten. In addition, an alloy layer may be formed in contact with the barrier metal film 1243, consisting of an alloy of the metal contained in the barrier metal film 1243 and a layer such as the semiconductor substrate 10 located below the contact hole 54. Furthermore, in the layer such as the semiconductor substrate 10 located below the contact hole 54, a region with a high concentration of impurities may be formed at the location in contact with the alloy layer. The active contact portion 124 in this example is an example of a main region contact portion 224 provided in the main region 220, which will be described later.

[0110] The back-side lifetime control region 151 may be provided in the transistor section 70. However, the back-side lifetime control region 151 may be omitted. The back-side lifetime control region 151 is a region in which a lifetime killer is intentionally formed by injecting impurities into the semiconductor substrate 10. In one example, the back-side lifetime control region 151 is formed by injecting helium into the semiconductor substrate 10. The back-side lifetime control region 151 may also be formed by injecting protons. By providing the back-side lifetime control region 151, the turn-off time can be reduced and the tail current suppressed, thereby reducing losses during switching.

[0111] Lifetime killers are carrier recombination centers. Lifetime killers may be lattice defects. For example, lifetime killers may be vacancies, double vacancies, composite defects between these and elements constituting the semiconductor substrate 10, or dislocations. Lifetime killers may also be noble gas elements such as helium and neon, or metallic elements such as platinum. Electron beams or protons may be used to form lattice defects.

[0112] The lifetime killer concentration is the concentration of carrier recombination centers. The lifetime killer concentration may also be the concentration of lattice defects. For example, the lifetime killer concentration may be the concentration of vacancies such as vacancies and double vacancies, the concentration of composite defects between these vacancies and the elements constituting the semiconductor substrate 10, or the concentration of dislocations. Furthermore, the lifetime killer concentration may also be the chemical concentration of noble gas elements such as helium and neon, or the chemical concentration of metallic elements such as platinum.

[0113] The rear-side lifetime control region 151 may be formed by injection from the rear surface 23 side. This makes it easier to avoid affecting the front surface 21 side of the semiconductor device 100. For example, the rear-side lifetime control region 151 is formed by irradiating with helium or protons from the rear surface 23 side. Here, whether the rear-side lifetime control region 151 is formed by injection from the front surface 21 side or the rear surface 23 side can be determined by obtaining the state of the front surface 21 side by the SR method or by measuring the leakage current.

[0114] Figure 2A shows an enlarged top view of a modified example of the semiconductor device 100. The semiconductor device 100 in this example includes a transistor section 70 and a diode section 80. The configuration shown in this figure may be arranged periodically or continuously in the +X axis direction and the -X axis direction.

[0115] The semiconductor device 100 in this example includes a gate trench 40, a dummy trench 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17, all located inside the front surface 21 of the semiconductor substrate 10. The gate trench 40 and the dummy trench 30 are examples of active trenches 122, respectively.

[0116] The dummy trench portion 30 in this example may have a U-shape on the front surface 21 of the semiconductor substrate 10, similar to the gate trench portion 40. That is, the dummy trench portion 30 may have two extended portions 31 that extend along the stretching direction and a connecting portion 33 that connects the two extended portions 31.

[0117] The semiconductor device 100 in this example includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other. The transistor section 70 in this example includes a boundary section 90 located at the boundary between the transistor section 70 and the diode section 80. However, the semiconductor device 100 does not necessarily have to include the boundary section 90.

[0118] The boundary portion 90 is provided in the transistor portion 70 and is adjacent to the diode portion 80. The boundary portion 90 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. In this example, the boundary portion 90 does not have an emitter region 12. In this example, the trench portion of the boundary portion 90 is a dummy trench portion 30. In this example, the boundary portion 90 is arranged such that both ends in the X-axis direction are dummy trench portions 30.

[0119] The contact holes 54 are located above the base region 14 in the diode section 80. The contact holes 54 are located above the contact region 15 in the boundary section 90. None of the contact holes 54 are located above the well regions 17 located at both ends in the Y-axis direction.

[0120] The mesa portion 91 is provided at the boundary portion 90. The mesa portion 91 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. In this example, the mesa portion 91 has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0121] The mesa portion 81 is provided in the diode portion 80 in the region sandwiched between adjacent dummy trench portions 30. The mesa portion 81 has a base region 14 on the front surface 21 of the semiconductor substrate 10. In this example, the mesa portion 81 has a well region 17 on the negative side in the Y-axis direction.

[0122] The emitter region 12 is provided in the mesa portion 71, but it does not need to be provided in the mesa portions 81 and 91. The contact region 15 is provided in the mesa portions 71 and 91, but it does not need to be provided in the mesa portion 81.

[0123] Figure 2B shows an example of a b-b' cross-section in Figure 2A. The semiconductor device 100 in this example includes a rear-side lifetime control region 151 and a front-side lifetime control region 152. However, the semiconductor device 100 does not necessarily have to include either the rear-side lifetime control region 151 or the front-side lifetime control region 152. The semiconductor device 100 in this example includes a collector region 22 and a cathode region 82 on the rear side 23 of the buffer region 20.

[0124] The contact area 15 is provided above the base area 14 in the mesa portion 91. The contact area 15 is provided in contact with the dummy trench portion 30 in the mesa portion 91. In other cross-sections, the contact area 15 may be provided on the front surface 21 of the mesa portion 71.

[0125] The storage region 16 is provided in the transistor section 70 and the diode section 80. In this example, the storage region 16 is provided across the entire surface of the transistor section 70 and the diode section 80. However, the storage region 16 does not necessarily have to be provided in the diode section 80.

[0126] The cathode region 82 is located below the buffer region 20 in the diode section 80. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80. That is, the collector region 22 is located below the boundary 90 in this example.

[0127] The rear-side lifetime control region 151 may be provided in both the transistor section 70 and the diode section 80, in only the transistor section 70, or in only the diode section 80. This allows the semiconductor device 100 in this example to speed up the turn-off operation of the transistor section 70 or the reverse recovery operation of the diode section 80, thereby further improving switching losses. The rear-side lifetime control region 151 may be formed in the same manner as the rear-side lifetime control region 151 in other embodiments.

[0128] The front-side lifetime control region 152 is provided on the front surface 21 side of the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. In this example, the front-side lifetime control region 152 is provided in the drift region 18. The front-side lifetime control region 152 may be provided in both the transistor section 70 and the diode section 80, or it may be provided only in the diode section 80. The front-side lifetime control region 152 may be provided in the diode section 80 and the boundary section 90, and may not be provided in part of the transistor section 70. The front-side lifetime control region 152 can reduce reverse recovery loss by suppressing hole injection from the transistor section 70 and the diode section 80.

[0129] The front-side lifetime control region 152 may be formed by any method among the methods for forming the back-side lifetime control region 151. The elements and dose amounts used to form the back-side lifetime control region 151 and the front-side lifetime control region 152 may be the same or different.

[0130] The front-side lifetime control region 152 is provided extending from the diode portion 80 to the transistor portion 70. The front-side lifetime control region 152 may be formed by introducing a lifetime killer from the front surface 21 of the semiconductor substrate 10. The front-side lifetime control region 152 may also be formed by irradiation from the back surface 23 of the semiconductor substrate 10. In this example, the front-side lifetime control region 152 is provided below the gate trench portion 40. When particle beams or the like used to form the front-side lifetime control region 152 pass through the MOS gate structure of the semiconductor device 100, defects may occur at the interface between the gate oxide film and the semiconductor substrate.

[0131] The semiconductor device 100 may be a power semiconductor device for controlling power, etc. The semiconductor device 100 in this example may have a vertical semiconductor structure in which a metal layer is provided on the back surface 23 side of the semiconductor substrate 10. However, the semiconductor device 100 may have a horizontal semiconductor structure in which a metal layer is not provided on the back surface 23 side.

[0132] In this example, the semiconductor device 100 is described using an RC-IGBT with a trench gate structure as an example. However, the semiconductor device 100 may also be a semiconductor device with a planar gate structure, or another semiconductor device such as a diode. The semiconductor device 100 may include an N-channel MOSFET or a P-channel MOSFET.

[0133] Figure 3 shows an example of a top view of the semiconductor device 100. The semiconductor device 100 in this example includes a temperature sensing element 180. In this example, only some components of the semiconductor device 100 are shown, and some components have been omitted.

[0134] The semiconductor substrate 10 has edges 102 when viewed from above. In this example, the semiconductor substrate 10 has two pairs of edges 102 that face each other when viewed from above. In this example, the X axis and Y axis are parallel to one of the edges 102.

[0135] The semiconductor substrate 10 is provided with an active section 120. The active section 120 is a region where the main current flows in the depth direction between the front surface 21 and the back surface 23 of the semiconductor substrate 10 when the semiconductor device 100 is operating. An emitter electrode 52 is provided above the active section 120, but it is omitted in this figure.

[0136] The active section 120 may be provided with at least one of a transistor section 70 including a transistor element such as an IGBT, and a diode section 80 including a diode element such as a freewheeling diode (FWD). In the example shown in Figure 3, the transistor section 70 and the diode section 80 are arranged alternately along a predetermined arrangement direction (in this example, the X-axis direction) on the front surface 21 of the semiconductor substrate 10. In other examples, the active section 120 may be provided with only one of the transistor section 70 and the diode section 80. That is, the active section 120 may be provided with only the transistor section 70 as shown in Figure 1A, or with both the transistor section 70 and the diode section 80 as shown in Figure 2A, or with only the diode section 80.

[0137] In this example, the region where the transistor section 70 is located is denoted by the symbol "I", and the region where the diode section 80 is located is denoted by the symbol "F". The transistor section 70 and the diode section 80 may each have a longitudinal length in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than the width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of the gate trench section 40 and the dummy trench section 30.

[0138] The diode portion 80 may be the region obtained by projecting the cathode region 82, which is provided on the back surface 23 of the semiconductor substrate 10, onto the upper surface of the semiconductor substrate 10. The region obtained by projecting the cathode region 82 onto the upper surface of the semiconductor substrate 10 may be located inside the diode portion 80. On the back surface 23 of the semiconductor substrate 10, a P+ type collector region 22 may be provided in the region other than the cathode region 82.

[0139] The edge termination structure 140 is provided on the front surface 21 of the semiconductor substrate 10. In a top view, the edge termination structure 140 is provided between the active portion 120 and the edge 102. The edge termination structure 140 mitigates electric field concentration on the front surface 21 side of the semiconductor substrate 10. The edge termination structure 140 may include at least one of a guard ring, a field plate, and a resurf, which are provided in an annular shape surrounding the active portion 120.

[0140] The semiconductor device 100 may have one or more pads on the semiconductor substrate 10. In this example, the semiconductor device 100 includes a gate pad 112, a sense electrode 114, an anode pad 116, and a cathode pad 118. Each pad may be located near an edge 102 of the semiconductor substrate 10. The vicinity of the edge 102 refers to the area between the edge 102 and the emitter electrode 52 in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as wires.

[0141] A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to the gate conductive portion 44 of the gate trench portion 40 of the active portion 120. The semiconductor device 100 may be provided with gate wiring connecting the gate pad 112 and the gate trench portion 40. The gate wiring may be configured by combining either the gate metal layer 50 or the connection portion 25, or both, as appropriate.

[0142] The sense electrode 114 is electrically connected to a current sensing unit 115 located below the sense electrode 114. The sense electrode 114 detects the current flowing through the current sensing unit 115. The current sensing unit 115 detects the current flowing through the transistor unit 70. The current sensing unit 115 has a structure corresponding to the transistor unit 70. The current flowing through the current sensing unit 115 is smaller than the current flowing through the transistor unit 70. The current sensing unit 115 may have a current flowing through it that is proportional to the current flowing through the transistor unit 70, simulating the operation of the transistor unit 70. The ratio of the current flowing through the current sensing unit 115 to the current flowing through the transistor unit 70 is set appropriately. By using the current sensing unit 115, the current flowing through the transistor unit 70 can be monitored.

[0143] The temperature-sensing element 180 is located on or inside the semiconductor substrate 10. In this example, the temperature-sensing element 180 is located between the transistor sections 70 in the central part of the semiconductor device 100. The temperature-sensing element 180 detects the temperature of the active section 120. The temperature-sensing element 180 may have a diode formed of single-crystal or polycrystalline silicon. The temperature-sensing element 180 is used to detect the temperature of the semiconductor device 100 and protect the semiconductor chip (semiconductor substrate 10) from overheating. The temperature-sensing element 180 is connected to a constant current source. When the temperature of the semiconductor device 100 changes, the forward voltage of the current flowing through the temperature-sensing element 180 changes. The semiconductor device 100 can detect the temperature based on the change in the forward voltage of the temperature-sensing element 180.

[0144] The anode pad 116 is electrically connected to the temperature-sensing anode region 182 of the temperature-sensing unit 180. The anode pad 116 is electrically connected to the temperature-sensing anode region 182 of the temperature-sensing unit 180 by an anode wiring section 117 which is electrically connected to the temperature-sensing anode region 182. The temperature-sensing anode region 182 will be described later.

[0145] The cathode pad 118 is electrically connected to the temperature-sensing cathode region 181 of the temperature-sensing unit 180. The cathode pad 118 is electrically connected to the temperature-sensing cathode region 181 of the temperature-sensing unit 180 by a cathode wiring section 119 which is electrically connected to the temperature-sensing cathode region 181. The temperature-sensing cathode region 181 will be described later.

[0146] Figure 4A shows an example of a cross-section of a semiconductor device 100 equipped with a temperature-sensing section 180. The cross-section in this example is a cross-sectional view along the line c-c' in Figure 3, and is the XZ plane passing through the contact hole 54 in the active section 120. The temperature-sensing section 180 includes a temperature-sensing diode 183 and a temperature-sensing contact section 188. The interlayer insulating film 38 may include a first interlayer insulating film 36 and a second interlayer insulating film 37. The interlayer insulating film 38 may be thinner than the emitter electrode 52. The first interlayer insulating film 36 may be thinner than the emitter electrode 52, and the second interlayer insulating film 37 may be thinner than the emitter electrode 52. The temperature-sensing contact section 188 may have a barrier metal film 1882 and a plug section 1884. The barrier metal film 1882 and plug section 1884 of the temperature-sensing contact section 188 will be described later.

[0147] The temperature-sensitive diode 183 is provided above the semiconductor substrate 10. Above may be in the positive direction in the Z-axis direction with respect to the front surface 21 of the semiconductor substrate 10. The temperature-sensitive diode 183 may be a PN diode including a temperature-sensitive anode region 182 provided above the semiconductor substrate 10 and a temperature-sensitive cathode region 181 provided above the semiconductor substrate 10 and in contact with the temperature-sensitive anode region 182. The temperature-sensitive cathode region 181 may be formed of an N-type semiconductor and function as the cathode of the PN diode. The temperature-sensitive anode region 182 may be formed of a P-type semiconductor and function as the anode of the PN diode. The materials of the temperature-sensitive cathode region 181 and the temperature-sensitive anode region 182 may be polycrystalline semiconductors, and one example may be polysilicon.

[0148] A well region 17 may be provided in the semiconductor substrate 10 below the temperature-sensitive diode 183. The well region 17 provided below the temperature-sensitive diode 183 may be the same as the well region 17 provided on the peripheral side of the active portion 120 in Figure 1A, and may be formed by the same process.

[0149] The temperature-sensitive contact portion 188 is provided in the interlayer insulating film 38 above the temperature-sensitive diode 183. The interlayer insulating film 38 on which the temperature-sensitive contact portion 188 is provided may be the first interlayer insulating film 36. The temperature-sensitive contact portion 188 may have a contact hole 58 and a metal layer filled inside the contact hole 58. The side wall of the temperature-sensitive contact portion 188 may be in contact with the interlayer insulating film 38 from its upper end to its lower end. That is, the contact hole 58 may be provided penetrating the first interlayer insulating film 36.

[0150] The contact width Wd of the temperature-sensitive contact portion 188 in contact with the temperature-sensitive diode 183 may be greater than the contact width of the active contact portion 124. The contact width Wd of the temperature-sensitive contact portion 188 may be greater than the first active contact width Wt1 of the first active contact portion 1241. The first active contact width Wt1 may be the width of the first active contact portion 1241 in contact with the upper surface of the mesa portion 71 of the semiconductor substrate 10. The active contact portion 124 in this example is an example of a main region contact portion 224 provided in the main region 220, which will be described later.

[0151] The cathode wiring section 119 is electrically connected to the temperature-sensitive cathode region 181 via the contact hole 58. The cathode wiring section 119 may be made of a metallic material. The cathode wiring section 119 may be made of the same material as the emitter electrode 52. The temperature-sensitive cathode region 181 may be electrically connected to the cathode pad 118 by the cathode wiring section 119.

[0152] The anode wiring section 117 is electrically connected to the temperature-sensitive anode region 182 via the contact hole 58. The anode wiring section 117 may be made of a metallic material. The anode wiring section 117 may be made of the same material as the emitter electrode 52. The temperature-sensitive anode region 182 may be electrically connected to the anode pad 116 by the anode wiring section 117.

[0153] The first interlayer insulating film 36 may be provided above the temperature-sensitive diode 183. The first interlayer insulating film 36 may be a BPSG film, a BSG film, a PSG film, an HTO film, or a laminate of these materials.

[0154] The second interlayer insulating film 37 may be provided between the temperature-sensitive diode 183 and the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The second interlayer insulating film 37 may be any oxide film. The second interlayer insulating film 37 may be the same thermal oxide film as the gate insulating film 42 or the dummy insulating film 32. The second interlayer insulating film 37 may be a BPSG film, a BSG film, a PSG film, or an HTO film.

[0155] Figure 4B shows another example of a cross-section of the semiconductor device 100 equipped with a temperature-sensing section 180. In this example, the cross-section is the XZ plane passing through the contact hole 56 in the active section 120. The active contact section 124 may include a second active contact section 1242.

[0156] The second active contact portion 1242 may be in contact with the active trench portion 122. In this example, the second active contact portion 1242 is in contact with the dummy trench portion 30. The second active contact portion 1242 may have a contact hole 56 and a metal layer filled inside the contact hole 56. The inside of the contact hole 56 may be filled with the same material as the emitter electrode 52, or with a different material than the emitter electrode 52.

[0157] The contact width Wd of the temperature-sensing contact portion 188 in contact with the temperature-sensing diode 183 may be greater than the contact width of the active contact portion 124. The contact width Wd of the temperature-sensing contact portion 188 may be greater than the second active contact width Wt2 of the second active contact portion 1242. The second active contact width Wt2 may be the width of the second active contact portion 1242 in contact with the active trench portion 122.

[0158] Figure 4C shows a cross-section of a modified semiconductor device 100 equipped with a temperature-sensing section 180. This example of the semiconductor device 100 differs from the embodiment in Figure 4A in that the temperature-sensing section 180 has a temperature-sensing trench contact section 1885, and the active section 120 has an active trench contact section 1245. In this example, the differences from the embodiment in Figure 4A will be explained in particular, and other aspects may be the same as the embodiment in Figure 4A. That is, the contact width of the temperature-sensing contact section 188 may be larger than the contact width of the active contact section 124.

[0159] The active portion 120 may have a plurality of active trench contact portions 1245 that extend in the depth direction of the semiconductor substrate 10 from the upper surface of the interlayer insulating film 38 downward from the front surface 21 of the semiconductor substrate 10. The active trench contact portion 1245 is an example of an active contact portion 124. The active trench contact portion 1245 is a portion that is deeper on the back surface 23 side than the front surface 21 of the semiconductor substrate 10. The active contact portion 124 in this example is an example of a main region contact portion 224 provided in the main region 220, which will be described later. The active trench contact portion 1245 in this example is an example of a main region trench contact portion 2245.

[0160] In the depth direction of the semiconductor substrate 10, the extension depth Dd of the temperature-sensitive trench contact portion 1885 extending from the upper surface of the temperature-sensitive diode in the depth direction of the semiconductor substrate may be the same as the extension depth Dt of the multiple active trench contact portions 1245 extending from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10.

[0161] The contact width Wtd of the temperature-sensitive trench contact portion 1885 in contact with the temperature-sensitive diode 183 may be larger than, the same as, or smaller than the contact width Wtt1 of the first active contact portion 1241. The contact width Wtd of the temperature-sensitive trench contact portion 1885 may be the width at which the temperature-sensitive trench contact portion 1885 contacts the upper surface of the temperature-sensitive diode 183. The first active contact width Wtt1 may be the width at which the first active contact portion 1241 contacts the upper surface of the mesa portion 71 of the semiconductor substrate 10. In the embodiment shown in Figure 4B, the active trench contact portion 1245 and the temperature-sensitive trench contact portion 1885 may also be present, similar to this example.

[0162] As described above, in the semiconductor device 100 of this example, the contact width of the temperature-sensitive contact portion 188 is larger than the contact width of the active contact portion 124. By making the contact width of the temperature-sensitive contact portion 188 larger than that of the active contact portion 124, the semiconductor device 100 can be manufactured stably even when miniaturized, and stable characteristics can be obtained. In this case, the active contact portion 124 and the temperature-sensitive contact portion 188 may be formed by different processes.

[0163] Figure 5A shows a cross-section of a modified example of the semiconductor device 100 equipped with a temperature-sensing portion 180. The semiconductor device 100 in this example differs from the embodiment in Figure 4A in that it has a recessed region 194. In this example, the differences from the embodiment in Figure 4A will be explained in particular, and other aspects may be the same as those of the embodiment in Figure 4A. That is, the contact width of the temperature-sensing contact portion 188 may be larger than the contact width of the active contact portion 124. The active contact portion 124 in this example is an example of a main region contact portion 224 provided in the main region 220, which will be described later.

[0164] The temperature-sensing portion 180 may have a recessed region 194 on the upper surface of the semiconductor substrate 10. The temperature-sensing diode 183 may be provided in the recessed region 194. The temperature-sensing diode 183 may be provided above the insulating film 196 in the recessed region 194. The insulating film 196 may be any oxide film. The insulating film 196 may be the same thermal oxide film as the edge termination structure 140, gate insulating film 42, or dummy insulating film 32, etc. The insulating film 196 may be a BPSG film, a BSG film, a PSG film, or an HTO film.

[0165] In the depth direction of the semiconductor substrate 10, the height position of the upper surface of the interlayer insulating film 38 in the active portion 120 may be the same as the height position of the upper surface of the interlayer insulating film 38 in the recess region 194. Being the same height position may include being substantially the same. Being substantially the same height position means that the distance from the front surface 21 of the semiconductor substrate 10 to the upper surface of the interlayer insulating film 38 in the active portion 120 and the distance from the front surface 21 of the semiconductor substrate 10 to the upper surface of the interlayer insulating film 38 in the recess region 194 are within 20% of the average value of both, or within 10% of the average value. When the height position of the upper surface of the interlayer insulating film 38 in the active portion 120 and the height position of the upper surface of the interlayer insulating film in the recess region 194 are substantially the same, the active contact portion 124 and the temperature-sensitive contact portion 188 can be formed simultaneously by the same etching process. In other words, if the upper surfaces of both the interlayer insulating film 38 in the active portion 120 and the interlayer insulating film 38 in the recess region 194 are at the same height from the front surface 21 of the semiconductor substrate 10, then no shift in the exposure focus occurs during the photolithography process. This allows for smaller dimensional tolerances for the interlayer insulating film, emitter electrode, etc. Furthermore, the active contact portion 124 and the temperature-sensitive contact portion 188 can be formed with the same dimensional tolerance. This allows for easier manufacturing with fewer steps compared to forming each contact portion in separate processes. However, if the contact width of the temperature-sensitive contact portion 188 is larger than the contact width of the active contact portion 124, the active contact portion 124 and the temperature-sensitive contact portion 188 may be formed by different processes. In this example, there may also be an active trench contact portion 1245 and a temperature-sensitive trench contact portion 1885.

[0166] Figure 5B shows a cross-section of a modified example of the semiconductor device 100 equipped with a temperature-sensing section 180. The semiconductor device 100 in this example differs from the embodiments in Figures 4A and 5A in that the temperature-sensing section 180 has a housing section 198. In this example, the differences from the embodiments in Figures 4A and 5A will be explained in particular, and other aspects may be the same as those in Figures 4A and / or 5A. That is, the contact width of the temperature-sensing contact section 188 may be larger than the contact width of the active contact section 124. The active contact section 124 in this example is an example of a main region contact section 224 provided in the main region 220, which will be described later.

[0167] The housing portion 198 is provided below the temperature-sensitive contact portion 188. The material of the housing portion 198 may be the same as the material of the first interlayer insulating film 36, the same as the material of the second interlayer insulating film 37, and the same as the material of the temperature-sensitive diode 183. The detailed configuration of the housing portion 198 will be described later.

[0168] Figure 6A shows an example of an enlarged cross-sectional view of the semiconductor device 100. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the temperature sensing section 180.

[0169] The bottom corner portion 1880 of the temperature-sensing contact portion 188 may be in contact with the temperature-sensing diode 183. The bottom corner portion 1880 of the temperature-sensing contact portion 188 may be the intersection of the bottom surface of the temperature-sensing contact portion 188 and the side surface of the temperature-sensing contact portion 188. Contact between the bottom corner portion 1880 and the temperature-sensing diode 183 may mean contact with the temperature-sensing diode 183 on its upper surface, contact with the temperature-sensing diode 183 on its side surface, or contact with the temperature-sensing diode 183 in an internal region of the temperature-sensing diode 183. In this example, the bottom corner portion 1880 is in contact with the temperature-sensing diode 183 on its upper surface.

[0170] The temperature-sensitive contact portion 188 in this example has two bottom corner portions 1880. One of the two bottom corner portions 1880 may be in contact with the temperature-sensitive diode 183. The other bottom corner portion 1880 may or may not be in contact with the housing portion 198. In this example, one bottom corner portion 1880a of the temperature-sensitive contact portion 1880a is in contact with the temperature-sensitive cathode region 181 of the temperature-sensitive diode 183, and the other bottom corner portion 1880b is in contact with the housing portion 198.

[0171] The bottom surface of the temperature-sensitive contact portion 188 may be in contact with the housing portion 198. The bottom surface of the temperature-sensitive contact portion 188 may be the surface between the two bottom corner portions 1880 of the temperature-sensitive contact portion 188. When the bottom surface of the temperature-sensitive contact portion 188 is in contact with the housing portion 198, it may be the bottom surface in contact with the housing portion 198 on the upper surface of the housing portion 198, or it may be the bottom surface in contact with the housing portion 198 in an internal region of the housing portion 198. In this example, the bottom surface of the temperature-sensitive contact portion 188 is in contact with the housing portion 198 on the upper surface of the housing portion 198.

[0172] The bottom surface of the temperature-sensing contact portion 188 may be in contact with the temperature-sensing diode 183 and the housing portion 198. In this example, one bottom corner portion 1880a of the temperature-sensing contact portion 188a is in contact with the temperature-sensing cathode region 181 of the temperature-sensing diode 183, and the other bottom corner portion 1880b is in contact with the housing portion 198, so that the bottom surface of the temperature-sensing contact portion 188a is in contact with the temperature-sensing diode 183 and the housing portion 198.

[0173] The thermosensitive diode 183 may be in contact with the bottom surface of the thermosensitive contact portion 188 from the bottom surface corner 1880 to an area of ​​10% to 40% of the bottom surface of the thermosensitive contact portion 188. That is, the ratio of the area of ​​the bottom surface of the thermosensitive contact portion 188 that is in contact with the thermosensitive diode 183 to the area of ​​the bottom surface of the thermosensitive contact portion 188 may be 10% to 40%. Referring to Figure 5A, length L1 is the length of the bottom surface of the thermosensitive contact portion 188 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Length L2 is the length of the bottom surface of the thermosensitive contact portion 188 that is in contact with the thermosensitive diode 183 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Therefore, the ratio of length L2 to length L1 may be 10% to 40%. In this example, the temperature-sensitive diode 183 is in contact with the bottom surface of the temperature-sensitive contact portion 188a from the bottom surface corner 1880a to 25% of the bottom surface of the temperature-sensitive contact portion 188. That is, the ratio of length L2 to length L1 in this example is 25%.

[0174] In the above explanation, the bottom surface, bottom corner 1880a, and bottom corner 1880b of the temperature-sensitive contact portion 188a that is in contact with the temperature-sensitive cathode region 181 were used as examples, but the same may apply to the temperature-sensitive contact portion 188b that is in contact with the temperature-sensitive anode region 182. That is, the bottom corner 1880 of the temperature-sensitive contact portion 188b may be in contact with the temperature-sensitive diode 183, the bottom surface of the temperature-sensitive contact portion 188b may be in contact with the housing portion 198, the bottom surface of the temperature-sensitive contact portion 188b may be in contact with both the temperature-sensitive diode 183 and the housing portion 198, and the temperature-sensitive diode 183 may be in contact with the bottom surface of the temperature-sensitive contact portion 188b from the bottom corner 1880 to an area of ​​10% to 40% of the bottom surface of the temperature-sensitive contact portion 188b. Furthermore, the lengths L1 and L2 of the temperature-sensitive contact portion 188b may be the same as those of the temperature-sensitive contact portion 188a.

[0175] In this example, the temperature-sensitive contact portion 188 is provided with its bottom corner portion 1880 in contact with the temperature-sensitive diode 183 and its bottom surface in contact with the housing portion 198. This ensures reliable electrical connection between the anode pad 116 and cathode pad 118 and the temperature-sensitive diode 183. If the plug portion 1884 and barrier metal film 1882 near the center of the bottom surface of the temperature-sensitive contact portion 188 are removed by over-etching during the etch-back process of the plug portion 1884, a void may form inside the temperature-sensitive contact portion 188. Even in that case, the electrical connection can be ensured by the barrier metal film 1882 and / or plug portion 1884 remaining on the bottom corner portion 1880 of the temperature-sensitive contact portion 188. The barrier metal film 1882 and plug portion 1884 will be described later.

[0176] In this example, the temperature-sensing contact portion 188 is provided with its bottom surface in contact with the housing portion 198. Therefore, even if a void occurs inside the area near the center of the bottom surface of the temperature-sensing contact portion, the impact on the electrical connection between the temperature-sensing contact portion 188 and the temperature-sensing diode 183 at the bottom corner portion 1880 is suppressed. This makes it possible to improve the yield of semiconductor device 100 having the desired characteristics. In this example, the temperature-sensing portion 180 ensures the electrical connection between the temperature-sensing contact portion 188 and the temperature-sensing diode 183 at the bottom corner portion 1880, rather than at the center of the bottom surface of the temperature-sensing contact portion 188. As a result, even if a void is formed in the area near the center of the temperature-sensing contact portion 188 that is in contact with the housing portion 198, stable quality can be obtained and the yield can be improved.

[0177] The temperature-sensitive contact portion 188 may have a barrier metal film 1882 and a plug portion 1884. In this example, the barrier metal film 1882 and the plug portion 1884 are formed of different materials, but they may be formed of the same material.

[0178] The barrier metal film 1882 may be provided on the bottom corner portion 1880 of the temperature-sensitive contact portion 188. In this example, the barrier metal film 1882 is provided over the entire side and bottom surface of the temperature-sensitive contact portion 188, but is not limited thereto. The barrier metal film 1882 may be provided covering at least the bottom corner portion 1880, and may not cover the central part of the bottom surface of the temperature-sensitive contact portion 188. The barrier metal film 1882 may extend beyond the contact hole 58 and be provided above the first interlayer insulating film 36. The material of the barrier metal film 1882 may be titanium or a titanium compound, etc.

[0179] The plug portion 1884 may be provided in contact with the inside of the barrier metal film 1882. In this example, the plug portion 1884 is provided by filling the temperature-sensitive contact portion 188, but is not limited to this. The plug portion 1884 may be provided in a part of the temperature-sensitive contact portion 188, and may extend beyond the contact hole 58 and above the first interlayer insulating film 36. When the plug portion 1884 is provided in a part of the temperature-sensitive contact portion 188, the remaining area of ​​the temperature-sensitive contact portion 188 may be filled with the same material as the anode wiring portion 117 or the cathode wiring portion 119. The material of the plug portion 1884 may be a plug metal such as tungsten.

[0180] The side surface of the temperature-sensitive diode 183 may be in contact with the side surface of the housing portion 198. In this example, the temperature-sensitive cathode region 181 and the temperature-sensitive anode region 182 of the temperature-sensitive diode 183 are in contact with the side surface of the housing portion 198.

[0181] The upper surface of the second interlayer insulating film 37 may be in contact with the lower surface of the temperature-sensitive diode 183 and the lower surface of the housing portion 198. In this example, the upper surface of the second interlayer insulating film 37 is in contact with the lower surface of the housing portion 198 which is in contact with the temperature-sensitive cathode region 181, the lower surface of the temperature-sensitive cathode region 181, the lower surface of the temperature-sensitive anode region 182, and the lower surface of the housing portion 198 which is in contact with the temperature-sensitive anode region 182.

[0182] The housing portion 198 may be a region of the first interlayer insulating film 36 located below the temperature-sensitive contact portion 188. The housing portion 198 may be formed in the process of providing the first interlayer insulating film 36, and may be formed from the same material as the first interlayer insulating film 36. When the housing portion 198 is formed as a region of the first interlayer insulating film 36 located below the temperature-sensitive contact portion 188, the housing portion 198 is a virtual region, as shown by the dotted line in Figure 6A. That is, the housing portion 198 may be formed integrally as part of the first interlayer insulating film 36.

[0183] Figure 6B shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the temperature sensing section 180. The semiconductor device 100 in this example differs from the embodiment in Figure 6A in that the shapes of the first interlayer insulating film 36 and the second interlayer insulating film 37 are different. In this example, the differences from the embodiment in Figure 6A will be explained in particular, and other aspects may be the same as those of the embodiment in Figure 6A.

[0184] The second interlayer insulating film 37 may have a recess 200 on its upper surface. The temperature-sensing diode 183 may be provided in the recess 200 of the second interlayer insulating film 37. The recess 200 may be formed by etching the upper surface of the second interlayer insulating film 37. In this example, the upper surface of the temperature-sensing diode 183 may be the same as the upper surface of the recess 200, and lower than the upper surface of the recess 200. Yo stomach.

[0185] The housing portion 198 may be a second interlayer insulating film 37 provided above the semiconductor substrate 10. The housing portion 198 may be formed in the process of providing the second interlayer insulating film 37, and may be formed from the same material as the second interlayer insulating film 37. When the housing portion 198 is formed as the second interlayer insulating film 37, the housing portion 198 is a virtual region, as shown by the dotted line in Figure 6B. That is, the housing portion 198 may be formed integrally as part of the second interlayer insulating film 37. Note that if the upper surface of the temperature-sensitive diode 183 is above the upper surface of the recess 200, the lower end of the temperature-sensitive contact portion 188 does not reach the second interlayer insulating film 37, but is located in the first interlayer insulating film 36. The housing portion 198 may be considered as part of the first interlayer insulating film 36, or it may be considered as consisting of both the first interlayer insulating film 36 and the second interlayer insulating film 37. Furthermore, even if the portion of the second interlayer insulating film 37 that does not have a recess 200 is narrow, and the lower end of the temperature-sensitive contact portion 188 is located at the boundary between the first interlayer insulating film 36 and the second interlayer insulating film 37, the housing portion 198 may be considered as part of the second interlayer insulating film 37, or it may be considered to consist of both the first interlayer insulating film 36 and the second interlayer insulating film 37.

[0186] Figure 6C shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the temperature sensing portion 180. The semiconductor device 100 in this example differs from the embodiments in Figures 6A and 6B in that a housing portion 198 is provided separately from the first interlayer insulating film 36 and the second interlayer insulating film 37. In this example, the differences from the embodiments in Figures 6A and 6B will be explained in particular, and other aspects may be the same as those in Figures 6A and / or 6B. The housing portion 198 in this example is provided in the region of the first interlayer insulating film 36 corresponding to the housing portion 198 in Figure 6A, but it may also be provided in the region of the second interlayer insulating film 37 corresponding to the housing portion 198 in Figure 6B.

[0187] The housing portion 198 may have a polysilicon of a different conductivity type than the contact region 300 of the thermosensing diode 183. The contact region 300 of the thermosensing diode 183 may be the thermosensing cathode region 181 or the thermosensing anode region 182 of the thermosensing diode 183 in contact with the housing portion 198. In this example, the housing portion 198a is in contact with the thermosensing cathode region 181. Therefore, the housing portion 198a may have a polysilicon of a different conductivity type than the thermosensing cathode region 181, which is the contact region 300 of the thermosensing diode 183. That is, the housing portion 198a may have P-type polysilicon or undoped polysilicon. In this example, the housing portion 198b is in contact with the thermosensing anode region 182. Therefore, the housing portion 198b may have a polysilicon of a different conductivity type than the thermosensing anode region 182, which is the contact region 300 of the thermosensing diode 183. In other words, the housing portion 198b may have N-type polysilicon or undoped polysilicon.

[0188] In this example, the temperature-sensing contact portion 188 has a bottom corner portion 1880 that contacts the temperature-sensing diode 183. In this example, the temperature-sensing contact portion 188 is provided with its bottom surface in contact with the housing portion 198. The contact area 300 between the housing portion 198 and the housing portion 198 of the temperature-sensing diode 183 may have the same potential.

[0189] When the housing portion 198 and the contact area 300 of the temperature-sensitive diode 183 are at the same potential, the housing portion 198 andNo current flows between the temperature-sensitive diode 183, and the operation of the temperature-sensitive diode 183 is not affected by the housing portion 198. For example, if the housing portion 198a has P-type polysilicon, which has a different conductivity type than the temperature-sensitive cathode region 181, the housing portion 198a and the temperature-sensitive cathode region 181 have the same potential, so virtually no current flows through the PN junction at the contact interface. Therefore, the operation of the temperature-sensitive diode 183 is not affected by the housing portion 198. Similarly, even if the housing portion 198b has N-type polysilicon, which has a different conductivity type than the temperature-sensitive anode region 182, the housing portion 198b and the temperature-sensitive anode region 182 have the same potential, so the PN junction at the contact interface does not function and does not hinder the operation of the temperature-sensitive diode 183.

[0190] The housing portion 198 may have the same conductivity type as the contact region 300 of the temperature-sensitive diode 183, and may have a polysilicon with a lower doping concentration than the contact region 300. In this example, the housing portion 198a is in contact with the temperature-sensitive cathode region 181. Therefore, the housing portion 198a may have the same conductivity type as the temperature-sensitive cathode region 181, which is the contact region 300 of the temperature-sensitive diode 183, and may have a polysilicon with a lower doping concentration than the temperature-sensitive cathode region 181. That is, the housing portion 198a may have N-type polysilicon. In this example, the housing portion 198b is in contact with the temperature-sensitive anode region 182. Therefore, the housing portion 198b may have the same conductivity type as the temperature-sensitive anode region 182, which is the contact region 300 of the temperature-sensitive diode 183, and may have a polysilicon with a lower doping concentration than the temperature-sensitive anode region 182. That is, the housing portion 198b may have P-type polysilicon.

[0191] Even if the housing portion 198 has the same conductivity type as the contact area 300 of the temperature-sensing diode 183, the doping concentration of the housing portion 198 is lower than that of the contact area 300, so it has little effect on the operation of the temperature-sensing diode 183. Therefore, the housing portion 198 is unlikely to interfere with the operation of the temperature-sensing diode 183.

[0192] As described above, the housing portion 198a in contact with the temperature-sensitive cathode region 181 of the temperature-sensitive diode 183 may have P-type, undoped, or N-type polysilicon, and the housing portion 198b in contact with the temperature-sensitive anode region 182 of the temperature-sensitive diode 183 may have N-type, undoped, or P-type polysilicon. In the case of a narrow polysilicon width, a portion of the lower end of the temperature-sensitive contact portion 188 may overlap the interlayer insulating film 38. In this case, the housing portion 198 can be considered to consist of a mixture of polysilicon and the first interlayer insulating film 36 and / or the second interlayer insulating film 37.

[0193] Figure 7A shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. This figure shows the region of the temperature-sensing portion 180 above the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 in this example differs from the embodiment in Figure 6A in that the temperature-sensing portion 180 has a temperature-sensing trench contact portion 1885. In this example, the differences from the embodiment in Figure 6A will be explained in particular, and other aspects may be the same as those of the embodiment in Figure 6A.

[0194] The temperature-sensing portion 180 may have a temperature-sensing trench contact portion 1885 that extends in the depth direction of the semiconductor substrate 10 from the upper surface of the interlayer insulating film 38 downward from the upper surface of the temperature-sensing diode 183. The temperature-sensing trench contact portion 1885 is an example of the temperature-sensing contact portion 188. The temperature-sensing trench contact portion 1885 is a portion that is deeper on the back surface 23 side than the surface surface of the temperature-sensing diode 183. In this example, the bottom corner portion 1880 of the temperature-sensing contact portion 188 contacts the temperature-sensing diode 183 on its side surface.

[0195] The sidewall of the temperature-sensing contact portion 188 may be in contact with the temperature-sensing diode 183 and the first interlayer insulating film 36. The temperature-sensing diode 183 may be in contact with the sidewall of the temperature-sensing contact portion 188 from the bottom corner portion 1880 to an area of ​​10% to 90% of the sidewall of the temperature-sensing contact portion. That is, the ratio of the area of ​​the sidewall of the temperature-sensing contact portion 188 that is in contact with the temperature-sensing diode 183 to the area of ​​the sidewall of the temperature-sensing contact portion 188 that is in contact with the temperature-sensing diode 183 may be 10% to 90%. Referring to Figure 6A, length L3 is the length of the sidewall of the temperature-sensing contact portion 188 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10, and length L4 is the length of the sidewall of the temperature-sensing contact portion 188 that is in contact with the temperature-sensing diode 183 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Therefore, the ratio of length L4 to length L3 may be between 10% and 90%. In this example, the temperature-sensitive diode 183 is in contact with the side wall of the temperature-sensitive contact portion 188 from the bottom corner portion 1880 to 36% of the side wall of the temperature-sensitive contact portion 188. That is, the ratio of length L4 to length L3 in this example is 36%.

[0196] Figure 7B shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the temperature sensing portion 180. The semiconductor device 100 in this example differs from the embodiment in Figure 7A in that the housing portion 198 is a second interlayer insulating film 37 provided above the semiconductor substrate 10. Other aspects may be the same as those of the embodiment in Figure 7A.

[0197] Figure 7C shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the temperature sensing portion 180. The semiconductor device 100 in this example differs from the embodiments in Figures 7A and 7B in that the housing portion 198 has polysilicon. Otherwise, it may be the same as the embodiments in Figures 7A and / or 7B.

[0198] Figure 8A shows a cross-section of a modified example of the semiconductor device 100 equipped with a temperature-sensing section 180. The semiconductor device 100 in this example differs from the embodiment in Figure 4C in that, in the depth direction of the semiconductor substrate 10, the extension depth Dd of the temperature-sensing trench contact section 1885 extending from the upper surface of the temperature-sensing diode in the depth direction of the semiconductor substrate 10 may be shallower than the extension depth Dt of the multiple active trench contact sections 1245 extending from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. In this example, the differences from the embodiment in Figure 4C will be explained in particular, and other aspects may be the same as the embodiment in Figure 4C. That is, the contact width of the temperature-sensing contact section 188 may be larger than the contact width of the active contact section 124. The active contact section 124 in this example is an example of the main region contact section 224 provided in the main region 220, which will be described later. The active trench contact section 1245 in this example is an example of the main region trench contact section 2245.

[0199] In the depth direction of the semiconductor substrate 10, the extension depth Dd of the temperature-sensitive trench contact portion 1885 extending from the upper surface of the temperature-sensitive diode in the depth direction of the semiconductor substrate may be shallower than the extension depth Dt of the multiple active trench contact portions 1245 extending from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. By making the extension depth Dd of the temperature-sensitive trench contact portion 1885 shallower than the extension depth Dt of the active trench contact portion 1245, it is possible to suppress the temperature-sensitive contact portion 188 from penetrating the temperature-sensitive diode 183 and extending the second interlayer insulating film 37, thereby preventing the insulation between the temperature-sensitive diode 183 and the semiconductor substrate 10 from being lost. In addition, since the active trench contact portion 1245 extends deeper than the temperature-sensitive trench contact portion 1885, the active contact portion 124 is formed sufficiently deep in the contact region 15, thereby suppressing latch-up. The temperature-sensitive trench contact portion 1885 and the activated trench contact portion 1245 can be formed in the same process. However, the temperature-sensitive trench contact portion 1885 and the activated trench contact portion 1245 may be formed in different processes.

[0200] The contact width Wtd of the temperature-sensitive trench contact portion 1885 in contact with the temperature-sensitive diode 183 may be greater than, the same as, or less than the contact width Wtt1 of the first active contact portion 1241. The contact width Wtd of the temperature-sensitive trench contact portion 1885 may be the width at which the temperature-sensitive trench contact portion 1885 contacts the upper surface of the temperature-sensitive diode 183. The first active contact width Wtt1 may be the width at which the first active contact portion 1241 contacts the upper surface of the mesa portion 71 of the semiconductor substrate 10.

[0201] Figure 8B shows a cross-section of a modified semiconductor device 100 equipped with a temperature-sensing section 180. This example of the semiconductor device 100 differs from the embodiment in Figure 8A in that the contact width of the temperature-sensing contact section 188 and the contact width of the active contact section 124 are the same, or the contact width of the temperature-sensing contact section 188 is narrower than the contact width of the active contact section 124. Otherwise, it may be the same as the embodiment in Figure 8A. That is, the extension depth Dd of the temperature-sensing trench contact section 1885 may be shallower than the extension depth Dt of the active trench contact section 1245. The active contact section 124 in this example is an example of a main region contact section 224 provided in the main region 220, which will be described later. The active trench contact section 1245 in this example is an example of a main region trench contact section 2245.

[0202] Figure 8C shows a cross-section of a modified semiconductor device 100 equipped with a temperature-sensing section 180. This example of the semiconductor device 100 differs from the embodiments in Figures 8A and 8B in that the extension depth Dd of the temperature-sensing trench contact section 1885 is substantially 0. Otherwise, it may be the same as the embodiments in Figures 8A and / or 8B. That is, the temperature-sensing contact section 188 does not extend to the temperature-sensing diode 183, and the active trench contact section 1245 may be extended to a depth Dt. The active contact section 124 in this example is an example of a main region contact section 224 provided in the main region 220, which will be described later. The active trench contact section 1245 in this example is an example of a main region trench contact section 2245.

[0203] The examples shown in Figures 8A, 8B, and 8C were explained using modifications from Figure 4C, but the examples are not limited to these. For example, in Figures 5A, 7A, 7B, or 7C, the extension depth Dd of the temperature-sensitive trench contact portion 1885 may be shallower than the extension depth Dt of the active trench contact portion 1245. Similarly, in the example shown in Figures 5A, 6A, 6B, or 6C, the temperature-sensitive contact portion 188 may not extend to the temperature-sensitive diode 183, and the active trench contact portion 1245 may be extended to a depth of Dt.

[0204] As described above, the semiconductor device 100 of the present invention may satisfy at least one of the following conditions: the contact width of the temperature-sensitive contact portion 188 is greater than the contact width of the active contact portion 124, or the extension depth of the temperature-sensitive contact portion 188 is shallower than the extension depth of the active contact portion 124. For example, the contact width of the temperature-sensitive contact portion 188 may be greater than the contact width of the active contact portion 124, and the extension depth of the temperature-sensitive contact portion 188 may be the same as the extension depth of the active contact portion 124. For yet another example, the contact width of the temperature-sensitive contact portion 188 may be greater than the contact width of the active contact portion 124, and the extension depth of the temperature-sensitive contact portion 188 may be shallower than the extension depth of the active contact portion 124. The temperature-sensitive contact portion 188 does not extend to the temperature-sensitive diode 183, and the active contact portion 124 may extend to the mesa portions 71, 81, 91 and the active trench portion 122.

[0205] Thus, by having different widths and / or depths for the active contact portion 124 and the temperature-sensitive contact portion 188, that is, by having different shapes for the active contact portion 124 and the temperature-sensitive contact portion 188, a stable electrical connection can be ensured at each contact portion.

[0206] Figure 9 shows an example of an enlarged view of the top surface of the semiconductor device 100. The semiconductor device 100 in this example differs from the embodiment in Figure 1A in that a connection portion 25 is provided between the emitter electrode 52 and the dummy conductive portion 34. In this example, the differences from the embodiment in Figure 1A will be explained in particular, and other aspects may be the same as those of the embodiment in Figure 1A.

[0207] The semiconductor device 100 comprises a main region 220, which is the area where the main current flows between the front surface 21 and the back surface 23 of the semiconductor substrate 10, and an outer peripheral region 230 that surrounds the main region 220. For example, the boundary between the main region 220 and the outer peripheral region 230 is the boundary between the base region 14 and the well region 17.

[0208] An interlayer insulating film 38 is provided above the front surface 21 of the semiconductor substrate 10, but the interlayer insulating film 38 is omitted in Figure 9. Contact holes 54, 55, and 56 are provided through the interlayer insulating film 38.

[0209] The contact hole 55 electrically connects the gate metal layer 50 and the gate conductive part 44 in the transistor part 70 via the connecting part 25. The contact hole 56 electrically connects the emitter electrode 52 and the dummy conductive part 34 in the dummy trench part 30 via the connecting part 25. The connecting part 25 is a conductive material such as polysilicon doped with impurities. In this example, the connecting part 25 is polysilicon (N+) doped with N-type impurities. Polysilicon is an example of a polycrystalline semiconductor. The connecting part 25 is an example of a polycrystalline part 232 provided above the semiconductor substrate 10 or on the front surface 21 side of the semiconductor substrate 10. The connecting part 25 is an example of a polycrystalline part 232 in the outer peripheral region 230.

[0210] Figure 10A shows an example of the d-d' cross section in Figure 9. The d-d' cross section is the YZ plane passing through the contact hole 56 in the outer peripheral region 230. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, a collector electrode 24, and a first outer peripheral region contact portion 234 in the d-d' cross section.

[0211] The polycrystalline portion 232 is provided above the semiconductor substrate 10. The polycrystalline portion 232 is provided above the front surface 21 of the semiconductor substrate 10 or on the side of the front surface 21 of the semiconductor substrate 10. In this example, the polycrystalline portion 232 is provided above the front surface 21 of the semiconductor substrate 10. In this example, the polycrystalline portion 232 is a connecting portion 25. The polycrystalline portion 232 may be provided above the third interlayer insulating film 238. The third interlayer insulating film 238 may be made of the same material as, for example, the dummy insulating film 32. The interlayer insulating film 38 is provided above the polycrystalline portion 232.

[0212] The first outer peripheral region contact portion 234 is provided in the interlayer insulating film 38 above the polycrystalline portion 232. The first outer peripheral region contact portion 234 may have a contact hole 56 and a metal layer filled inside the contact hole 56. The detailed configuration of the first outer peripheral region contact portion 234 will be described later.

[0213] The polycrystalline portion 232 may be connected to the emitter electrode 52 via the first outer peripheral region contact portion 234. The polycrystalline portion 232 may also be connected to the dummy conductive portion 34. In this example, the connection portion 25 is connected to the emitter electrode 52 via the first outer peripheral region contact portion 234 and is also connected to the dummy conductive portion 34.

[0214] The main region 220 may have a main region contact portion 224 provided in the interlayer insulating film 38. This figure is a cross-sectional view of the outer region 230, so the main region contact portion 224 is not shown. The main region contact portion 224 is, for example, the active contact portion 124 shown in Figure 4A. The contact width Wo1 of the first outer region contact portion 234 may be larger than the contact width Wt1 of the main region contact portion 224. The contact width Wo1 of the first outer region contact portion 234 may be the width at which the first outer region contact portion 234 contacts the polycrystalline portion 232. The side wall of the first outer region contact portion 234 is connected to the interlayer insulating film 38 from the upper end to the lower end. contact You may do so.

[0215] In the semiconductor device 100 of this example, the contact width of the first outer peripheral region contact portion 234 is greater than the contact width of the main region contact portion 224. By making the contact width of the first outer peripheral region contact portion 234 greater than that of the main region contact portion 224, the semiconductor device 100 can be manufactured stably even when miniaturized, and stable characteristics can be obtained. In this case, the main region contact portion 224 and the first outer peripheral region contact portion 234 may be formed by different processes.

[0216] Figure 10B shows an example of the d-d' cross section in Figure 9. The semiconductor device 100 in this example differs from the embodiment in Figure 10A in that the outer peripheral region 230 has a first outer peripheral region trench contact portion 2345. In this example, the differences from the embodiment in Figure 10A will be explained in particular, and other aspects may be the same as those of the embodiment in Figure 10A.

[0217] The outer peripheral region 230 may have a first outer peripheral region trench contact portion 2345 that extends in the depth direction of the semiconductor substrate 10 from the upper surface of the interlayer insulating film 38 downward from the upper surface of the polycrystalline portion 232. The first outer peripheral region trench contact portion 2345 is an example of the first outer peripheral region contact portion 234. The first outer peripheral region trench contact portion 2345 is a portion that is deeper on the back surface 23 side of the semiconductor substrate 10 than the upper surface of the polycrystalline portion 232.

[0218] The polycrystalline portion 232 may be connected to the emitter electrode 52 via the first outer peripheral trench contact portion 2345. The polycrystalline portion 232 may also be connected to the dummy conductive portion 34. In this example, the connection portion 25 is connected to the emitter electrode 52 via the first outer peripheral trench contact portion 2345 and is also connected to the dummy conductive portion 34.

[0219] The main region 220 may have a main region trench contact portion 2245 that extends downward from the upper surface of the interlayer insulating film 38 to the front surface of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. Since this figure is a cross-sectional view of the outer peripheral region 230, the main region trench contact portion 2245 is not shown. The main region trench contact portion 2245 is, for example, the active trench contact portion 1245 shown in Figure 4C. The main region trench contact portion 2245 is an example of the main region contact portion 224. The main region trench contact portion 2245 is a portion that is deeper on the back surface 23 side than the front surface 21 of the semiconductor substrate 10. The main region 220 may have a plurality of main region trench contact portions 2245 provided on the front surface 21 of the semiconductor substrate 10.

[0220] In the depth direction of the semiconductor substrate 10, the extension depth Do1 of the first outer peripheral region trench contact portion 2345 extending from the upper surface of the polycrystalline portion 232 in the depth direction of the semiconductor substrate 10 is shallower than the extension depth Dt of the multiple main region trench contact portions 2245 extending from the front surface of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The extension depth Do1 of the first outer peripheral region trench contact portion 2345 may be 0, and the extension depth Dt of the main region trench contact portion 2245 may be a value of 0 or more. By making the extension depth Do1 of the first outer peripheral region trench contact portion 2345 shallower than the extension depth Dt of the main region trench contact portion 2245, it is possible to suppress the first outer peripheral region contact portion 2344 penetrating the polycrystalline portion 232 and extending the third interlayer insulating film 238, thereby preventing the insulation between the polycrystalline portion 232 and the semiconductor substrate 10 from being maintained. In this example, insulation from the semiconductor substrate 10 is not required at the connection portion 25 that connects to the dummy conductive portion 34, but it should be noted that this may be a problem at the first outer peripheral region contact portion 234 of other regions formed simultaneously. Also, since the main region trench contact portion 2245 extends deeper than the first outer peripheral region trench contact portion 2345, latch-up can be suppressed by forming the main region contact portion 224 sufficiently deep in the contact region 15. The first outer peripheral region trench contact portion 2345 and the main region trench contact portion 2245 can be formed in the same process. However, the first outer peripheral region trench contact portion 2345 and the main region trench contact portion 2245 may be formed in different processes.

[0221] The contact width Wto1 of the first outer peripheral trench contact portion 2345 in contact with the polycrystalline portion 232 may be larger, the same as, or smaller than the contact width Wtt1 of each of the multiple main region trench contact portions 2245. The contact width Wto1 of the first outer peripheral trench contact portion 2345 may be the width at which the first outer peripheral trench contact portion 2345 contacts the upper surface of the polycrystalline portion 232. The contact width Wtt1 of the main region trench contact portion 2245 may be the width at which the active trench contact portion 1245 contacts the upper surface of the mesa portion 71 of the semiconductor substrate 10, as shown in Figure 4C.

[0222] Figure 11A shows an example of a d-d' cross-section in Figure 9. The semiconductor device 100 in this example differs from the embodiment in Figure 10A in that the outer peripheral region 230 has a recess region 236. In this example, the differences from the embodiment in Figure 10A will be explained in particular, and other aspects may be the same as those in the embodiment in Figure 10A. That is, the contact width Wo1 of the first outer peripheral region contact portion 234 may be larger than the contact width of the main region contact portion 224.

[0223] The outer peripheral region 230 may have a recess region 236 formed by a depression on the upper surface of the semiconductor substrate 10. The polycrystalline portion 232 may be provided in the recess region 236. In this example, the polycrystalline portion 232 is provided on the front surface 21 side of the semiconductor substrate 10. In the depth direction of the semiconductor substrate 10, the height position of the upper surface of the interlayer insulating film 38 in the main region 220 may be the same as the height position of the upper surface of the interlayer insulating film 38 in the recess region 236. The height position being the same may include the height position being substantially the same. The height position being substantially the same may mean that the distance from the front surface 21 of the semiconductor substrate 10 to the upper surface of the interlayer insulating film 38 in the main region 220 and the distance from the front surface 21 of the semiconductor substrate 10 to the upper surface of the interlayer insulating film 38 in the recess region 236 are within 20% of the average value of the two, or they may be within 10% of the average value.

[0224] If the height position of the upper surface of the interlayer insulating film 38 in the main region 220 and the height position of the upper surface of the interlayer insulating film 38 in the recess region 236 are approximately the same, the main region contact portion 224 and the first outer peripheral region contact portion 234 can be formed simultaneously by the same etching process. That is, if the upper surfaces of both the interlayer insulating film 38 in the main region 220 and the interlayer insulating film 38 in the recess region 236 are at the same height from the front surface 21 of the semiconductor substrate 10, there will be no shift in the exposure focus during the photolithography process. Therefore, the dimensional tolerances of the interlayer insulating film 38, emitter electrode 52, etc. can be reduced. Furthermore, the main region contact portion 224 and the first outer peripheral region contact portion 234 can be formed with the same dimensional tolerance. As a result, compared to forming each contact portion in separate processes, manufacturing can be done easily with fewer steps. However, if the contact width of the first outer peripheral region contact portion 234 is to be larger than the contact width of the main region contact portion 224, the main region contact portion 224 and the first outer peripheral region contact portion 234 may be formed by different processes.

[0225] Figure 11B shows an example of the d-d' cross section in Figure 9. The semiconductor device 100 in this example differs from the embodiment in Figure 10B in that the outer peripheral region 230 has a recess region 236, and differs from the embodiment in Figure 11A in that the outer peripheral region 230 has a first outer peripheral region trench contact portion 2345. Otherwise, it may be the same as the embodiment in Figure 10B and / or Figure 11A.

[0226] Figure 12A shows an example of the d-d' cross-section in Figure 9. The semiconductor device 100 in this example differs from the embodiment in Figure 10A in that the outer peripheral region 230 has a housing portion 198. In this example, the differences from the embodiment in Figure 10A will be explained in particular, and other aspects may be the same as those in the embodiment in Figure 10A. That is, the contact width Wo1 of the first outer peripheral region contact portion 234 may be larger than the contact width of the main region contact portion 224.

[0227] The housing portion 198 is provided below the first outer peripheral region contact portion 234. The material of the housing portion 198 may be the same as that of the interlayer insulating film 38.

[0228] Figure 12B shows an example of an enlarged view of the d-d' cross section in Figure 9. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the outer peripheral region 230.

[0229] The bottom corner portion 2340 of the first outer peripheral region contact portion 234 may be in contact with the polycrystalline portion 232. The bottom corner portion 2340 of the first outer peripheral region contact portion 234 may be the intersection of the bottom surface of the first outer peripheral region contact portion 234 and the side surface of the first outer peripheral region contact portion 234. The bottom corner portion 2340 being in contact with the polycrystalline portion 232 may be in contact with the polycrystalline portion 232 on its upper surface, in contact with the polycrystalline portion 232 on its side surface, or in contact with the polycrystalline portion 232 in an internal region of the polycrystalline portion 232. In this example, the bottom corner portion 2340 is in contact with the polycrystalline portion 232 on its upper surface.

[0230] The first outer peripheral region contact portion 234 in this example has two bottom corner portions 2340. One of the two bottom corner portions 2340 may be in contact with the polycrystalline portion 232. The other of the two bottom corner portions 2340 may or may not be in contact with the housing portion 198. In this example, one bottom corner portion 2340a of the first outer peripheral region contact portion 2340 is in contact with the polycrystalline portion 232, and the other bottom corner portion 2340b is in contact with the housing portion 198.

[0231] The bottom surface of the first outer peripheral region contact portion 234 may be in contact with the housing portion 198. The bottom surface of the first outer peripheral region contact portion 234 may be the surface between the two bottom surface corners 2340 of the first outer peripheral region contact portion 234. When the bottom surface of the first outer peripheral region contact portion 234 is in contact with the housing portion 198, it may be the bottom surface in contact with the housing portion 198 on the upper surface of the housing portion 198, or it may be the bottom surface in contact with the housing portion 198 in an area inside the housing portion 198. In this example, the bottom surface of the first outer peripheral region contact portion 234 is in contact with the housing portion 198 on the upper surface of the housing portion 198.

[0232] The bottom surface of the first outer peripheral region contact portion 234 may be in contact with the polycrystalline portion 232 and the housing portion 198. In this example, the bottom surface of the first outer peripheral region contact portion 234 is in contact with the polycrystalline portion 232 and the housing portion 198 because one bottom surface corner 2340a is in contact with the polycrystalline portion 232 and the other bottom surface corner 2340b is in contact with the housing portion 198.

[0233] The polycrystalline portion 232 may be in contact with the bottom surface of the first outer peripheral region contact portion 234 from the bottom surface corner portion 2340 to an area of ​​10% to 40% of the bottom surface of the first outer peripheral region contact portion 234. That is, the ratio of the area of ​​the bottom surface of the first outer peripheral region contact portion 234 that is in contact with the polycrystalline portion 232 to the area of ​​the bottom surface of the first outer peripheral region contact portion 234 may be 10% to 40%. Referring to Figure 12B, length L1 is the length of the bottom surface of the first outer peripheral region contact portion 234 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Length L2 is the length of the bottom surface of the first outer peripheral region contact portion 234 that is in contact with the polycrystalline portion 232 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Therefore, the ratio of length L2 to length L1 may be 10% to 40%. In this example, the polycrystalline portion 232 is in contact with the bottom surface of the first outer peripheral region contact portion 234 from the bottom surface corner portion 2340a to 20% of the bottom surface of the first outer peripheral region contact portion 234. That is, the ratio of length L2 to length L1 in this example is 20%.

[0234] The first outer peripheral region contact portion 234 may have a barrier metal film 2342 and a plug portion 2344. In this example, the barrier metal film 2342 and the plug portion 2344 are formed of different materials, but they may be formed of the same material.

[0235] The barrier metal film 2342 may be provided on the bottom corner portion 2340 of the first outer peripheral region contact portion 234. In this example, the barrier metal film 2342 is provided over the entire side and bottom surface of the first outer peripheral region contact portion 234, but is not limited thereto. The barrier metal film 2342 may be provided covering at least the bottom corner portion 2340, and may not cover the central part of the bottom surface of the first outer peripheral region contact portion 234. The barrier metal film 2342 may extend beyond the contact hole 56 and be provided above the interlayer insulating film 38. The material of the barrier metal film 2342 may be titanium or a titanium compound, etc.

[0236] The plug portion 2344 may be provided in contact with the inside of the barrier metal film 2342. In this example, the plug portion 2344 is provided by filling the first outer peripheral region contact portion 234, but is not limited to this. The plug portion 2344 may be provided in a part of the first outer peripheral region contact portion 234, and may extend beyond the contact hole 56 and above the interlayer insulating film 38. When the plug portion 2344 is provided in a part of the first outer peripheral region contact portion 234, the remaining area of ​​the first outer peripheral region contact portion 234 may be filled with the same material as the emitter electrode 52. The material of the plug portion 2344 may be a plug metal such as tungsten.

[0237] The side surface of the polycrystalline portion 232 may be in contact with the side surface of the housing portion 198. The housing portion 198 may be a region of the interlayer insulating film 38 located below the first outer peripheral region contact portion 234. The housing portion 198 may be formed in the process of providing the interlayer insulating film 38 and may be formed from the same material as the interlayer insulating film 38. When the housing portion 198 is formed as a region of the interlayer insulating film 38 located below the first outer peripheral region contact portion 234, the housing portion 198 is a virtual region, as shown by the dotted line in Figure 12B. That is, the housing portion 198 may be formed integrally as part of the interlayer insulating film 38. In another example, the housing portion 198 may be a third interlayer insulating film 238 located above the semiconductor substrate 10. The housing portion 198 may be formed in the process of providing the third interlayer insulating film 238 and may be formed from the same material as the third interlayer insulating film 238. In other words, the housing portion 198 may be integrally formed as part of the third interlayer insulating film 238. In this case, the polycrystalline portion 232 may be provided in a recess created by etching the upper surface of the thickly provided third interlayer insulating film 238. In yet another example, the housing portion 198 may be polysilicon with a lower impurity concentration than the polycrystalline portion 232, or undoped polysilicon.

[0238] In this example, the first outer peripheral region contact portion 234 is provided such that its bottom corner portion 2340 is in contact with the polycrystalline portion 232 and its bottom surface is in contact with the housing portion 198. This ensures reliable electrical connection between the emitter electrode 52 and the polycrystalline portion 232. If the plug portion 2344 and the barrier metal film 2342 near the center of the bottom surface of the first outer peripheral region contact portion 234 are removed by over-etching during the etch-back process of the plug portion 2344, a void may form inside the first outer peripheral region contact portion 234. Even in that case, the electrical connection can be ensured by the barrier metal film 2342 and / or plug portion 2344 remaining on the bottom corner portion 2340 of the first outer peripheral region contact portion 234.

[0239] In this example, the first outer peripheral region contact portion 234 is provided with its bottom surface in contact with the housing portion 198. Therefore, even if a void occurs inside the area near the center of the bottom surface of the first outer peripheral region contact portion 234, the impact on the electrical connection at the bottom surface corner portion 2340 between the first outer peripheral region contact portion 234 and the polycrystalline portion 232 is suppressed. This makes it possible to improve the yield of semiconductor device 100 having the desired characteristics. In this example, the outer peripheral region 230 ensures the electrical connection between the first outer peripheral region contact portion 234 and the polycrystalline portion 232, not at the bottom surface corner portion 2340 of the first outer peripheral region contact portion 234, but at the bottom surface corner portion 2340. As a result, even if a void is formed in the area near the center of the first outer peripheral region contact portion 234 that is in contact with the housing portion 198, stable quality can be obtained and the yield can be improved.

[0240] Figure 13A shows an example of the d-d' cross section in Figure 9. The semiconductor device 100 in this example differs from the embodiment in Figure 10B in that the outer peripheral region 230 has a housing portion 198, and differs from the embodiment in Figure 12A in that the outer peripheral region 230 has a first outer peripheral region trench contact portion 2345. Otherwise, it may be the same as the embodiment in Figure 10B and / or Figure 12A.

[0241] Figure 13B shows an example of an enlarged view of the d-d' cross section in Figure 9. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the outer peripheral region 230. The semiconductor device 100 in this example differs from the embodiment in Figure 12B in that the outer peripheral region 230 has a first outer peripheral region trench contact portion 2345. In this example, the differences from the embodiment in Figure 12B will be explained in particular, and other aspects may be the same as those in the embodiment in Figure 12B.

[0242] The sidewall of the first outer peripheral region contact portion 234 may be in contact with the polycrystalline portion 232 and the interlayer insulating film 38. The polycrystalline portion 232 may be in contact with the sidewall of the first outer peripheral region contact portion 234 from the bottom corner portion 2340 to an area of ​​10% to 90% of the sidewall of the first outer peripheral region contact portion 234. That is, the ratio of the area of ​​the sidewall of the first outer peripheral region contact portion 234 that is in contact with the polycrystalline portion 232 to the area of ​​the sidewall of the first outer peripheral region contact portion 234 that is in contact with the polycrystalline portion 232 may be 10% to 90%. Referring to Figure 13B, length L3 is the length of the side wall of the first outer peripheral region contact portion 234 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10, and length L4 is the length of the side wall of the first outer peripheral region contact portion 234 that is in contact with the polycrystalline portion 232 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Therefore, the ratio of length L4 to length L3 may be 10% or more and 90% or less. In this example, the polycrystalline portion 232 is in contact with the side wall of the first outer peripheral region contact portion 234 from the bottom corner portion 2340 to 35% of the side wall of the first outer peripheral region contact portion 234. That is, the ratio of length L4 to length L3 in this example is 35%.

[0243] Figure 14A shows an example of the e-e' cross section in Figure 9. The e-e' cross section is the YZ plane passing through the contact hole 55 in the outer peripheral region 230. The semiconductor device 100 in this example has a semiconductor substrate 10, an interlayer insulating film 38, a gate metal layer 50, a collector electrode 24, and a first outer peripheral region contact portion 234 in the e-e' cross section.

[0244] The polycrystalline portion 232 is provided above the semiconductor substrate 10. The polycrystalline portion 232 is provided above the front surface 21 of the semiconductor substrate 10 or on the side of the front surface 21 of the semiconductor substrate 10. In this example, the polycrystalline portion 232 is provided above the front surface 21 of the semiconductor substrate 10. In this example, the polycrystalline portion 232 is a connecting portion 25. The polycrystalline portion 232 may be provided above the third interlayer insulating film 238. The third interlayer insulating film 238 may be made of the same material as, for example, the gate insulating film 42. The interlayer insulating film 38 is provided above the polycrystalline portion 232.

[0245] The first outer peripheral region contact portion 234 is provided in the interlayer insulating film 38 above the polycrystalline portion 232. The first outer peripheral region contact portion 234 may include a contact hole 55 and a metal layer filled inside the contact hole 55.

[0246] The polycrystalline portion 232 may be connected to the gate metal layer 50 via the first outer peripheral region contact portion 234. The polycrystalline portion 232 may be connected to the gate conductive portion 44. The connection portion 25 of this example is connected to the gate metal layer 50 via the first outer peripheral region contact portion 234, and is connected to the gate conductive portion 44.

[0247] The contact width Wo1 of the first outer peripheral region contact portion 234 may be larger than the contact width Wt1 of the main region contact portion 224. The side wall of the first outer peripheral region contact portion 234 is in contact with the interlayer insulating film 38 from the upper end to the lower end contact may be formed.

[0248] In the semiconductor device 100 of this example, the contact width of the first outer peripheral region contact portion 234 is larger than the contact width of the main region contact portion 224. By making the contact width of the first outer peripheral region contact portion 234 larger than the contact width of the main region contact portion 224, the semiconductor device 100 can be stably manufactured even when miniaturized, and stable characteristics can be obtained. In this case, the main region contact portion 224 and the first outer peripheral region contact portion 234 may be formed by different processes.

[0249] FIG. 14B shows an example of the e-e' cross-section in FIG. 9. The semiconductor device 100 of this example differs from the embodiment of FIG. 14A in that the outer peripheral region 230 includes a first outer peripheral region trench contact portion 2345. In this example, only the differences from the embodiment of FIG. 14A will be specifically described, and other configurations may be the same as those of the embodiment of FIG. 14A.

[0250] The peripheral region 230 may include a first peripheral region trench contact portion 2345 provided extending from the upper surface of the interlayer insulating film 38 to a position lower than the upper surface of the polycrystalline portion 232 in the depth direction of the semiconductor substrate 10. The first peripheral region trench contact portion 2345 is an example of the first peripheral region contact portion 234. The first peripheral region trench contact portion 2345 is a portion deeper toward the back surface 23 side of the semiconductor substrate 10 than the upper surface of the polycrystalline portion 232.

[0251] The polycrystalline portion 232 may be connected to the gate metal layer 50 via the first peripheral region trench contact portion 2345. The polycrystalline portion 232 may be connected to the gate conductive portion 44. The connection portion 25 of this example is connected to the gate metal layer 50 via the first peripheral region trench contact portion 2345, and is connected to the gate conductive portion 44.

[0252] In the depth direction of the semiconductor substrate 10, the extension depth Do1 of the first outer peripheral region trench contact portion 2345 extending from the upper surface of the polycrystalline portion 232 in the depth direction of the semiconductor substrate 10 is shallower than the extension depth Dt of the multiple main region trench contact portions 2245 extending from the front surface of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The extension depth Do1 of the first outer peripheral region trench contact portion 2345 may be 0, and the extension depth Dt of the main region trench contact portion 2245 may be a value of 0 or more. By making the extension depth Do1 of the first outer peripheral region trench contact portion 2345 shallower than the extension depth Dt of the main region trench contact portion 2245, it is possible to suppress the first outer peripheral region contact portion 2344 penetrating the polycrystalline portion 232 and extending the third interlayer insulating film 238, thereby preventing the insulation between the polycrystalline portion 232 and the semiconductor substrate 10 from being maintained. Furthermore, since the main region trench contact portion 2245 extends deeper than the first outer region trench contact portion 2345, latch-up can be suppressed by forming the main region contact portion 224 sufficiently deep in the contact region 15. In particular, in this example, insulation between the connection portion 25 and the well region 17 can be maintained. The first outer region trench contact portion 2345 and the main region trench contact portion 2245 can be formed in the same process. However, the first outer region trench contact portion 2345 and the main region trench contact portion 2245 may be formed in different processes.

[0253] The contact width Wto1 of the first outer peripheral trench contact portion 2345 in contact with the polycrystalline portion 232 may be larger, the same as, or smaller than the contact width Wtt1 of each of the multiple main region trench contact portions 2245.

[0254] Figure 15A shows an example of the e-e' cross-section in Figure 9. The semiconductor device 100 in this example differs from the embodiment in Figure 14A in that the outer peripheral region 230 has a recess region 236. In this example, the differences from the embodiment in Figure 14A will be explained in particular, and other aspects may be the same as those in the embodiment in Figure 14A. That is, the contact width Wo1 of the first outer peripheral region contact portion 234 may be larger than the contact width of the main region contact portion 224.

[0255] The outer peripheral region 230 may have a recessed region 236 on the upper surface of the semiconductor substrate 10. The polycrystalline portion 232 may be provided in the recessed region 236. In this example, the polycrystalline portion 232 is provided on the front surface 21 side of the semiconductor substrate 10. In the depth direction of the semiconductor substrate 10, the height position of the upper surface of the interlayer insulating film 38 in the main region 220 may be the same as the height position of the upper surface of the interlayer insulating film 38 in the recessed region 236.

[0256] If the height position of the upper surface of the interlayer insulating film 38 in the main region 220 and the height position of the upper surface of the interlayer insulating film 38 in the recess region 236 are approximately the same, the main region contact portion 224 and the first outer peripheral region contact portion 234 can be formed simultaneously by the same etching process. That is, if the upper surfaces of both the interlayer insulating film 38 in the main region 220 and the interlayer insulating film 38 in the recess region 236 are at the same height from the front surface 21 of the semiconductor substrate 10, there will be no shift in the exposure focus during the photolithography process. As a result, the dimensional tolerances of the interlayer insulating film 38, emitter electrode 52, gate metal layer 50, etc. can be reduced. Furthermore, the main region contact portion 224 and the first outer peripheral region contact portion 234 can be formed with the same dimensional tolerance. This makes it possible to manufacture them easily with fewer steps compared to when each contact portion is formed in separate processes. However, if the contact width of the first outer peripheral region contact portion 234 is to be larger than the contact width of the main region contact portion 224, the main region contact portion 224 and the first outer peripheral region contact portion 234 may be formed by different processes.

[0257] Figure 15B shows an example of the e-e' cross section in Figure 9. The semiconductor device 100 in this example differs from the embodiment in Figure 14B in that the outer peripheral region 230 has a recess region 236, and differs from the embodiment in Figure 15A in that the outer peripheral region 230 has a first outer peripheral region trench contact portion 2345. Otherwise, it may be the same as the embodiment in Figure 14B and / or Figure 15A.

[0258] Figure 16A shows an example of the e-e' cross-section in Figure 9. The semiconductor device 100 in this example differs from the embodiment in Figure 14A in that the outer peripheral region 230 has a housing portion 198. In this example, the differences from the embodiment in Figure 14A will be explained in particular, and other aspects may be the same as those in the embodiment in Figure 14A. That is, the contact width Wo1 of the first outer peripheral region contact portion 234 may be larger than the contact width of the main region contact portion 224.

[0259] The housing portion 198 is provided below the first outer peripheral region contact portion 234. The material of the housing portion 198 may be the same as that of the interlayer insulating film 38.

[0260] Figure 16B shows an example of an enlarged view of the e-e' cross section in Figure 9. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the outer peripheral region 230.

[0261] The bottom corner portion 2340 of the first outer peripheral region contact portion 234 may be in contact with the polycrystalline portion 232. In this example, the bottom corner portion 2340 is in contact with the polycrystalline portion 232 on its upper surface.

[0262] The bottom surface of the first outer peripheral region contact portion 234 may be in contact with the housing portion 198. In this example, the bottom surface of the first outer peripheral region contact portion 234 is in contact with the housing portion 198 at the upper surface of the housing portion 198.

[0263] The bottom surface of the first outer peripheral region contact portion 234 may be in contact with the polycrystalline portion 232 and the housing portion 198. In this example, the bottom surface of the first outer peripheral region contact portion 234 is in contact with the polycrystalline portion 232 and the housing portion 198 because one bottom surface corner 2340a is in contact with the polycrystalline portion 232 and the other bottom surface corner 2340b is in contact with the housing portion 198.

[0264] The polycrystalline portion 232 may be in contact with the bottom surface of the first outer peripheral region contact portion 234 from the bottom surface corner 2340 to an area of ​​10% to 40% of the bottom surface of the first outer peripheral region contact portion 234. In this example, the polycrystalline portion 232 is in contact with the bottom surface of the first outer peripheral region contact portion 234 from the bottom surface corner 2340a to an area of ​​20% of the bottom surface of the first outer peripheral region contact portion 234. That is, the ratio of length L2 to length L1 in this example is 20%.

[0265] The barrier metal film 2342 may be provided on the bottom corner portion 2340 of the first outer peripheral region contact portion 234. In this example, the barrier metal film 2342 is provided over the entire side and bottom surface of the first outer peripheral region contact portion 234, but is not limited thereto. The barrier metal film 2342 may be provided covering at least the bottom corner portion 2340, and may not cover the central part of the bottom surface of the first outer peripheral region contact portion 234. The barrier metal film 2342 may extend beyond the contact hole 55 and be provided above the interlayer insulating film 38. The material of the barrier metal film 2342 may be titanium or a titanium compound, etc.

[0266] The plug portion 2344 may be provided in contact with the inside of the barrier metal film 2342. In this example, the plug portion 2344 is provided by filling the first outer peripheral region contact portion 234, but is not limited to this. The plug portion 2344 may be provided in a part of the first outer peripheral region contact portion 234, and may extend beyond the contact hole 55 and above the interlayer insulating film 38. When the plug portion 2344 is provided in a part of the first outer peripheral region contact portion 234, the remaining area of ​​the first outer peripheral region contact portion 234 may be filled with the same material as the gate metal layer 50. The material of the plug portion 2344 may be a plug metal such as tungsten.

[0267] The side surface of the polycrystalline portion 232 may be in contact with the side surface of the housing portion 198. The housing portion 198 may be a region of the interlayer insulating film 38 located below the first outer peripheral region contact portion 234. The housing portion 198 may be formed in the process of providing the interlayer insulating film 38 and may be formed from the same material as the interlayer insulating film 38. When the housing portion 198 is formed as a region of the interlayer insulating film 38 located below the first outer peripheral region contact portion 234, the housing portion 198 is a virtual region, as shown by the dotted line in Figure 16B. That is, the housing portion 198 may be formed integrally as part of the interlayer insulating film 38. In another example, the housing portion 198 may be a third interlayer insulating film 238 located above the semiconductor substrate 10. The housing portion 198 may be formed in the process of providing the third interlayer insulating film 238 and may be formed from the same material as the third interlayer insulating film 238. In other words, the housing portion 198 may be integrally formed as part of the third interlayer insulating film 238. In yet another example, the housing portion 198 may be polysilicon with a lower impurity concentration than the polycrystalline portion 232 or undoped polysilicon.

[0268] In this example, the first outer peripheral region contact portion 234 is provided such that its bottom corner portion 2340 is in contact with the polycrystalline portion 232 and its bottom surface is in contact with the housing portion 198. This ensures reliable electrical connection between the gate metal layer 50 and the polycrystalline portion 232. If the plug portion 2344 and the barrier metal film 2342 near the center of the bottom surface of the first outer peripheral region contact portion 234 are removed by over-etching during the etch-back process of the plug portion 2344, a void may form inside the first outer peripheral region contact portion 234. Even in that case, the electrical connection can be ensured by the barrier metal film 2342 and / or plug portion 2344 remaining on the bottom corner portion 2340 of the first outer peripheral region contact portion 234.

[0269] In this example, the first outer peripheral region contact portion 234 is provided with its bottom surface in contact with the housing portion 198. Therefore, even if a void occurs inside the area near the center of the bottom surface of the first outer peripheral region contact portion 234, the impact on the electrical connection at the bottom surface corner portion 2340 between the first outer peripheral region contact portion 234 and the polycrystalline portion 232 is suppressed. This makes it possible to improve the yield of semiconductor device 100 having the desired characteristics. In this example, the outer peripheral region 230 ensures the electrical connection between the first outer peripheral region contact portion 234 and the polycrystalline portion 232, not at the bottom surface corner portion 2340 of the first outer peripheral region contact portion 234, but at the bottom surface corner portion 2340. As a result, even if a void is formed in the area near the center of the first outer peripheral region contact portion 234 that is in contact with the housing portion 198, stable quality can be obtained and the yield can be improved.

[0270] Figure 17A shows an example of the e-e' cross section in Figure 9. The semiconductor device 100 in this example differs from the embodiment in Figure 14B in that the outer peripheral region 230 has a housing portion 198, and differs from the embodiment in Figure 16A in that the first outer peripheral region 230 has a first outer peripheral region trench contact portion 2345. Otherwise, it may be the same as the embodiment in Figure 14B and / or Figure 16A.

[0271] Figure 17B shows an example of an enlarged view of the e-e' cross section in Figure 9. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the outer peripheral region 230. The semiconductor device 100 in this example differs from the embodiment in Figure 16B in that the outer peripheral region 230 has a first outer peripheral region trench contact portion 2345. In this example, the differences from the embodiment in Figure 16B will be explained in particular, and other aspects may be the same as those in the embodiment in Figure 16B.

[0272] A side wall of the first outer peripheral region contact portion 234 may be in contact with the polycrystalline portion 232 and the interlayer insulating film 38. The polycrystalline portion 232 may be in contact with the side wall of the first outer peripheral region contact portion 234 from a bottom corner 2340 to a region ranging from 10% to 90% of the side wall of the first outer peripheral region contact portion 234. In the present example, the polycrystalline portion 232 is in contact with the side wall of the first outer peripheral region contact portion 234 from the bottom corner 2340 to a region corresponding to 35% of the side wall of the first outer peripheral region contact portion 234. That is, a ratio of a length L4 to a length L3 in the present example is 35%.

[0273] Fig. 18A shows an example of a top view of a semiconductor device 100. In the present example, the semiconductor device 100 includes a guard ring 142 in an edge termination structure portion 140. The semiconductor device 100 may include a plurality of guard rings 142.

[0274] The guard ring 142 is a second conductivity type region provided between an active portion 120 and an edge 102 of a semiconductor substrate 10 on a front surface 21 of the semiconductor substrate 10. As an example, the guard ring 142 is of P+ type. The guard ring 142 may surround the active portion 120 when viewed from above. An outer guard ring 142 may surround an inner guard ring 142. "Outer" refers to a side closer to the edge 102, and "inner" refers to a side closer to the center of the semiconductor substrate 10 when viewed from above. By providing the guard ring 142, a depletion layer on the front surface 21 side of the active portion 120 can extend toward the edge 102, so that the breakdown voltage of the semiconductor device 100 can be improved. The semiconductor device 100 may further include at least one of a field plate and a RESURF provided surrounding the active portion 120 in the edge termination structure portion 140.

[0275] Figure 18B shows an example of region R in Figure 18A. The semiconductor device 100 in this example includes a guard ring 142 and a field plate 144 in the edge termination structure 140. The edge termination structure 140 is an example of the outer peripheral region 230. The semiconductor device 100 may include an interlayer insulating film 38, an edge metal layer 146, and a field insulating film 148 in the edge termination structure 140. The interlayer insulating film 38, the edge metal layer 146, and the field insulating film 148 are omitted in Figure 13B. Contact holes 57 and 59 are provided through the interlayer insulating film 38.

[0276] The field plate 144 is a conductive member provided above the semiconductor substrate 10. In this example, the field plate 144 is made of polysilicon with impurities added. The field plate 144 is an example of a polycrystalline portion 232. The field plate 144 is provided above the guard ring 142. The field plate 144 may be electrically connected to the corresponding guard ring 142.

[0277] The guard ring 142 has a non-corner region 1420 and a corner region 1422. The non-corner region 1420 is, for example, a region of the guard ring 142 that extends along the edge 102 of the semiconductor substrate 10, and the corner region 1422 is, for example, a portion of the guard ring 142 that connects the regions that extend along the edge 102 of the semiconductor substrate 10.

[0278] The contact hole 57 connects the edge metal layer 146 and the field plate 144. A barrier metal film made of titanium or a titanium compound and / or a plug made of tungsten may be formed inside the contact hole 57.

[0279] The contact hole 59 connects the edge metal layer 146 and the guard ring 142. A barrier metal film made of titanium or a titanium compound and / or a plug made of tungsten may be formed inside the contact hole 59.

[0280] Contact holes 57 and 59 may be located above the corner region 1422 of the guard ring 142. However, at least one of contact holes 57 or 59 may be located above the non-corner region 1420 of the guard ring 142, or both contact holes 57 and 59 may be located above the non-corner region 1420 of the guard ring 142.

[0281] In this example, contact holes 57 and 59 have longitudinal lengths in the direction of the progression of the guard ring 142 and field plate 144, and are arranged side by side from the center to the edge 102. In other examples, contact holes 57 and 59 may be arranged in the direction of the progression of the guard ring 142 and field plate 144, the longitudinal direction of each contact hole may be from the center to the edge 102, and each contact hole may consist of multiple holes.

[0282] The width d2 of the corner region 1422 may be wider than the width d1 of the non-corner region 1420. That is, the radius of curvature r1 on the edge side 102 (outside) may be smaller than the sum of the radius of curvature r2 on the center side (inside) and d1. In this example, r1 is smaller than d2. The edge metal layer 146 may be provided at the widest part of the corner region 1422, or in its vicinity. In other examples, the width d2 of the corner region 1422 may be equal to the width d1 of the non-corner region 1420. In yet another example, the edge metal layer 146 may be provided in the non-corner region 1420, or it may span both the non-corner region 1420 and the corner region 1422.

[0283] Figure 19A shows an example of the f-f' cross-section in Figure 18B. The f-f' cross-section is a plane in the outer peripheral region 230 that passes through the contact holes 57 and 59 and is parallel to the Z-axis direction. The semiconductor device 100 in this example has a semiconductor substrate 10, an interlayer insulating film 38, a field insulating film 148, an edge metal layer 146, a collector electrode 24, a first outer peripheral region contact portion 234, and a second outer peripheral region contact portion 235 in the f-f' cross-section.

[0284] The field insulating film 148 is provided above the semiconductor substrate 10. The field insulating film 148 may be provided so as to cover the drift region 18 exposed on the front surface 21 of the semiconductor substrate 10 between the well region 17 and the guard ring 142, and between the guard rings 142 themselves. The field insulating film 148 may be provided so as to surround the main region 220 along the guard ring 142.

[0285] The field insulating film 148 may have an insulating film obtained by oxidizing or nitriding the semiconductor substrate 10, an insulating film deposited by CVD or the like, or other insulating films. The field insulating film 148 may be a single-layer insulating film, or an insulating film obtained by laminating multiple films formed by different methods.

[0286] The edge metal layer 146 is provided above the semiconductor substrate 10 and is electrically connected to the guard ring 142. The edge metal layer 146 is provided above the semiconductor substrate 10, with the interlayer insulating film 38 in between. The edge metal layer 146 may be electrically connected to the field plate 144. The edge metal layer 146 may be electrically floating. For example, when a voltage V is applied to the collector electrode 24 with the gate of the semiconductor device 100 turned off, a predetermined voltage lower than the voltage V may be applied to the edge metal layer 146.

[0287] The edge metal layer 146 is formed from a metal-containing material. At least a portion of the edge metal layer 146 may be formed from a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). The edge metal layer 146 may have a barrier metal film formed from titanium or a titanium compound or the like in the layer below the region formed from aluminum or the like.

[0288] The polycrystalline portion 232 is provided above the semiconductor substrate 10. The polycrystalline portion 232 is provided above the front surface 21 of the semiconductor substrate 10 or on the side of the front surface 21 of the semiconductor substrate 10. In this example, the polycrystalline portion 232 is provided above the front surface 21 of the semiconductor substrate 10. In this example, the polycrystalline portion 232 is a field plate 144. The polycrystalline portion 232 may be provided above the third interlayer insulating film 238. The third interlayer insulating film 238 may be, for example, the same material as the gate insulating film 42 and / or dummy insulating film 32. The third interlayer insulating film 238 may be a thermal oxide film as an example. The interlayer insulating film 38 is provided above the polycrystalline portion 232.

[0289] The first outer peripheral region contact portion 234 is provided in the interlayer insulating film 38 above the polycrystalline portion 232. The first outer peripheral region contact portion 234 may have a contact hole 57 and a metal layer filled inside the contact hole 57. The second outer peripheral region contact portion 235 is provided in the interlayer insulating film 38 in a region where the polycrystalline portion 232 is not provided. The second outer peripheral region contact portion 235 may have a contact hole 59 and a metal layer filled inside the contact hole 59. The second outer peripheral region contact portion 235 may include a barrier metal film 2352 and a plug portion 2354.

[0290] The polycrystalline portion 232 may be connected to the edge metal layer 146 via the first outer peripheral region contact portion 234. In this example, the field plate 144 is connected to the edge metal layer 146 via the first outer peripheral region contact portion 234. The semiconductor substrate 10 may be connected to the edge metal layer 146 via the second outer peripheral region contact portion 235. In this example, the guard ring 142 is connected to the edge metal layer 146 via the second outer peripheral region contact portion 235.

[0291] The contact width Wo1 of the first outer peripheral region contact portion 234 may be larger than the contact width Wt1 of the main region contact portion 224. The side wall of the first outer peripheral region contact portion 234 is made of an interlayer insulating film 38 from the upper end to the lower end. contact You may do so.

[0292] In the semiconductor device 100 of this example, the contact width of the first outer peripheral region contact portion 234 is greater than the contact width of the main region contact portion 224. By making the contact width of the first outer peripheral region contact portion 234 greater than that of the main region contact portion 224, the semiconductor device 100 can be manufactured stably even when miniaturized, and stable characteristics can be obtained. In this case, the main region contact portion 224 and the first outer peripheral region contact portion 234 may be formed by different processes.

[0293] Figure 19B shows an example of the f-f' cross-section in Figure 18B. The semiconductor device 100 in this example differs from the embodiment in Figure 19A in that the outer peripheral region 230 has a first outer peripheral region trench contact portion 2345 and a second outer peripheral region trench contact portion 2355. In this example, the differences from the embodiment in Figure 19A will be explained in particular, and other aspects may be the same as those of the embodiment in Figure 19A.

[0294] The outer peripheral region 230 may have a first outer peripheral region trench contact portion 2345 that extends downward from the upper surface of the interlayer insulating film 38 to below the upper surface of the polycrystalline portion 232 in the depth direction of the semiconductor substrate 10. The first outer peripheral region trench contact portion 2345 is an example of the first outer peripheral region contact portion 2345. The first outer peripheral region trench contact portion 2345 is a portion that is deeper on the back surface 23 side of the semiconductor substrate 10 than the upper surface of the polycrystalline portion 232. The outer peripheral region 230 may have a second outer peripheral region trench contact portion 2355 that extends downward from the upper surface of the interlayer insulating film 38 to below the upper surface of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The second outer peripheral region trench contact portion 2355 is an example of the second outer peripheral region contact portion 2355. The second outer peripheral region trench contact portion 2355 is a portion that is deeper on the back surface 23 side of the semiconductor substrate 10 than the upper surface of the semiconductor substrate 10.

[0295] The polycrystalline portion 232 may be connected to the edge metal layer 146 via the first outer periphery trench contact portion 2345. In this example, the field plate 144 is connected to the edge metal layer 146 via the first outer periphery trench contact portion 2345. The semiconductor substrate 10 may be connected to the edge metal layer 146 via the second outer periphery trench contact portion 2355. In this example, the guard ring 142 is connected to the edge metal layer 146 via the second outer periphery trench contact portion 2355.

[0296] In the depth direction of the semiconductor substrate 10, the extension depth Do1 of the first outer peripheral region trench contact portion 2345 extending from the upper surface of the polycrystalline portion 232 in the depth direction of the semiconductor substrate 10 is shallower than the extension depth Dt of the multiple main region trench contact portions 2245 extending from the front surface of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The extension depth Do1 of the first outer peripheral region trench contact portion 2345 may be 0, and the extension depth Dt of the main region trench contact portion 2245 may be a value of 0 or more. By making the extension depth Do1 of the first outer peripheral region trench contact portion 2345 shallower than the extension depth Dt of the main region trench contact portion 2245, it is possible to suppress the first outer peripheral region contact portion 2344 penetrating the polycrystalline portion 232 and extending the third interlayer insulating film 238, thereby preventing the insulation between the polycrystalline portion 232 and the semiconductor substrate 10 from being maintained. In this example, while insulation from the guard ring 142 is not required for the field plate 144, it should be noted that this may be a problem in the first outer peripheral region contact portion 234 of other regions formed simultaneously. Also, since the main region trench contact portion 2245 extends deeper than the first outer peripheral region trench contact portion 2345, latch-up can be suppressed by forming the main region contact portion 224 sufficiently deep in the contact region 15. The first outer peripheral region trench contact portion 2345 and the main region trench contact portion 2245 can be formed in the same process. However, the first outer peripheral region trench contact portion 2345 and the main region trench contact portion 2245 may be formed in different processes.

[0297] The extension depth Do1 of the first outer peripheral trench contact portion 2345 and the extension depth Do2 of the second outer peripheral trench contact portion 2355 may both be shallower than the extension depth Dt of the main region trench contact portion 2245. That is, the extension depth Do1 of the first outer peripheral trench contact portion 2345 extending from the upper surface of the polycrystalline portion 232 in the depth direction of the semiconductor substrate 10 and the extension depth Do2 of the second outer peripheral trench contact portion 2355 extending from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10 may both be shallower than the extension depth Dt of the multiple main region trench contact portions 2245 extending from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10.

[0298] If both the extension depth Do1 of the first outer periphery trench contact portion 2345 and the extension depth Do2 of the second outer periphery trench contact portion 2355 are shallower than the extension depth Dt of the main area trench contact portion 2245, then the first outer periphery trench contact portion 2345 and the second outer periphery trench contact portion 2355 can be formed in the same process. For example, if the first outer periphery trench contact portion 2345 and the second outer periphery trench contact portion 2355 are formed in different processes, the opening ratio of the mask in the process of forming the main area trench contact portion 2245 will be different from the opening ratio of the mask in the process of forming the first outer periphery trench contact portion 2345, so the shapes of the first outer periphery trench contact portion 2345 and the second outer periphery trench contact portion 2355 may differ from the design. Since the first outer periphery trench contact portion 2345 and the second outer periphery trench contact portion 2355 are formed in the same process, the opening ratio of the mask in the process of forming the main region trench contact portion 2245 is similar to the opening ratio of the mask in the process of forming the first outer periphery trench contact portion 2345 and the second outer periphery trench contact portion 2355, and the first outer periphery trench contact portion 2345 is formed in the shape as designed. However, the first outer periphery trench contact portion 2345 and the second outer periphery trench contact portion 2355 may be formed in different processes.

[0299] The contact width Wto1 of the first outer peripheral trench contact portion 2345 in contact with the polycrystalline portion 232 may be larger, the same as, or smaller than the contact width Wtt1 of each of the multiple main region trench contact portions 2245. The contact width Wto2 of the second outer peripheral trench contact portion 2355 in contact with the front surface 21 of the semiconductor substrate 10 may be larger, the same as, or smaller than the contact width Wtt1 of each of the multiple main region trench contact portions 2245.

[0300] Figure 19C shows an example of the f-f' cross-section in Figure 18B. The semiconductor device 100 in this example differs from the embodiment in Figure 19B in that the extension depth of the first outer peripheral trench contact portion 2345 and the second outer peripheral trench contact portion 2355 are different. In this example, the differences from the embodiment in Figure 19B will be explained in detail, and other aspects may be the same as those of the embodiment in Figure 19B.

[0301] The extension depth Do1 of the first outer peripheral trench contact portion 2345 extending from the upper surface of the polycrystalline portion 232 in the depth direction of the semiconductor substrate 10 may be shallower than the extension depth Do2 of the second outer peripheral trench contact portion 2355 extending from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. In this case, the first outer peripheral trench contact portion 2345 and the second outer peripheral trench contact portion 2355 may be formed by different processes, and the second outer peripheral trench contact portion 2355 and the main region trench contact portion 2245 may be formed by the same process.

[0302] In the depth direction of the semiconductor substrate 10, the height position of the upper surface of the interlayer insulating film 38 in the main region 220 is approximately the same as the height position of the upper surface of the interlayer insulating film 38 in the portion where the second outer peripheral region trench contact portion 2355 is provided. As a result, the main region trench contact portion 2245 and the second outer peripheral region trench contact portion 2355 can be formed simultaneously by the same etching process. That is, if the upper surfaces of both the interlayer insulating film 38 in the main region 220 and the interlayer insulating film 38 in the portion where the second outer peripheral region trench contact portion 2355 is provided are at the same height from the front surface 21 of the semiconductor substrate 10, there will be no shift in the exposure focus during the photolithography process. Therefore, the dimensional tolerances of the interlayer insulating film 38, emitter electrode 52, edge metal layer 146, etc. can be reduced. Furthermore, the main region trench contact portion 2245 and the second outer peripheral region trench contact portion 2355 can be formed with the same dimensional tolerance.

[0303] Figure 20A shows an example of the f-f' cross-section in Figure 18B. The semiconductor device 100 in this example differs from the embodiment in Figure 19A in that the outer peripheral region 230 has a recess region 236. In this example, the differences from the embodiment in Figure 19A will be explained in particular, and other aspects may be the same as those in the embodiment in Figure 19A. That is, the contact width Wo1 of the first outer peripheral region contact portion 234 may be larger than the contact width of the main region contact portion 224.

[0304] The outer peripheral region 230 may have a recessed region 236 on the upper surface of the semiconductor substrate 10. The polycrystalline portion 232 may be provided in the recessed region 236. In this example, the polycrystalline portion 232 is provided on the front surface 21 side of the semiconductor substrate 10. In the depth direction of the semiconductor substrate 10, the height position of the upper surface of the interlayer insulating film 38 in the main region 220 may be the same as the height position of the upper surface of the interlayer insulating film 38 in the recessed region 236.

[0305] If the height position of the upper surface of the interlayer insulating film 38 in the main region 220 and the height position of the upper surface of the interlayer insulating film 38 in the recess region 236 are approximately the same, the main region contact portion 224 and the first outer peripheral region contact portion 234 can be formed simultaneously by the same etching process. That is, if the upper surfaces of both the interlayer insulating film 38 in the main region 220 and the interlayer insulating film 38 in the recess region 236 are at the same height from the front surface 21 of the semiconductor substrate 10, there will be no shift in the exposure focus during the photolithography process. As a result, the dimensional tolerances of the interlayer insulating film 38, emitter electrode 52, edge metal layer 146, etc. can be reduced. Furthermore, the main region contact portion 224 and the first outer peripheral region contact portion 234 can be formed with the same dimensional tolerance. This makes it possible to manufacture them easily with fewer steps compared to when each contact portion is formed in separate processes. However, if the contact width of the first outer peripheral region contact portion 234 is to be larger than the contact width of the main region contact portion 224, the main region contact portion 224 and the first outer peripheral region contact portion 234 may be formed by different processes.

[0306] Figure 20B shows an example of the f-f' cross-section in Figure 18B. The semiconductor device 100 in this example differs from the embodiment in Figure 19B in that the outer peripheral region 230 has a recess region 236, and differs from the embodiment in Figure 20A in that the outer peripheral region 230 has a first outer peripheral region trench contact portion 2345 and a second outer peripheral region trench contact portion 2355. Otherwise, it may be the same as the embodiment in Figure 19B and / or Figure 20A.

[0307] In this example, the height position of the upper surface of the interlayer insulating film 38 in the main region 220, the height position of the upper surface of the interlayer insulating film 38 in the recess region 236, and the height position of the upper surface of the interlayer insulating film 38 in the portion where the second outer peripheral region trench contact portion 2355 is provided are substantially the same. Therefore, the main region trench contact portion 2245, the first outer peripheral region trench contact portion 2345, and the second outer peripheral region trench contact portion 2355 can be formed simultaneously by the same etching process. This allows for easier manufacturing with fewer steps compared to the case where each contact portion is formed in separate processes. However, each contact portion may be formed in different processes.

[0308] Figure 21A shows an example of the f-f' cross-section in Figure 18B. The semiconductor device 100 in this example differs from the embodiment in Figure 19A in that the outer peripheral region 230 has a housing portion 198. In this example, the differences from the embodiment in Figure 19A will be explained in particular, and other aspects may be the same as those in the embodiment in Figure 19A. That is, the contact width Wo1 of the first outer peripheral region contact portion 234 may be larger than the contact width of the main region contact portion 224.

[0309] The housing portion 198 is provided below the first outer peripheral region contact portion 234. The material of the housing portion 198 may be the same as or different from that of the interlayer insulating film 38.

[0310] Figure 21B shows an example of an enlarged view of the f-f' cross section in Figure 18B. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the outer peripheral region 230.

[0311] The bottom corner portion 2340 of the first outer peripheral region contact portion 234 may be in contact with the polycrystalline portion 232. In this example, the bottom corner portion 2340 is in contact with the polycrystalline portion 232 on its upper surface.

[0312] The bottom surface of the first outer peripheral region contact portion 234 may be in contact with the housing portion 198. In this example, the bottom surface of the first outer peripheral region contact portion 234 is in contact with the housing portion 198 at the upper surface of the housing portion 198.

[0313] The bottom surface of the first outer peripheral region contact portion 234 may be in contact with the polycrystalline portion 232 and the housing portion 198. In this example, the bottom surface of the first outer peripheral region contact portion 234 is in contact with the polycrystalline portion 232 and the housing portion 198 because one bottom surface corner 2340a is in contact with the polycrystalline portion 232 and the other bottom surface corner 2340b is in contact with the housing portion 198.

[0314] The polycrystalline portion 232 may be in contact with the bottom surface of the first outer peripheral region contact portion 234 from the bottom surface corner 2340 to an area of ​​10% to 40% of the bottom surface of the first outer peripheral region contact portion 234. In this example, the polycrystalline portion 232 is in contact with the bottom surface of the first outer peripheral region contact portion 234 from the bottom surface corner 2340a to an area of ​​20% of the bottom surface of the first outer peripheral region contact portion 234. That is, the ratio of length L2 to length L1 in this example is 20%.

[0315] The barrier metal film 2342 may be provided on the bottom corner portion 2340 of the first outer peripheral region contact portion 234. In this example, the barrier metal film 2342 is provided over the entire side and bottom surface of the first outer peripheral region contact portion 234, but is not limited thereto. The barrier metal film 2342 may be provided covering at least the bottom corner portion 2340, and may not cover the central part of the bottom surface of the first outer peripheral region contact portion 234. The barrier metal film 2342 may extend beyond the contact hole 57 and be provided above the interlayer insulating film 38. The material of the barrier metal film 2342 may be titanium or a titanium compound, etc.

[0316] The plug portion 2344 may be provided in contact with the inside of the barrier metal film 2342. In this example, the plug portion 2344 is provided by filling the first outer peripheral region contact portion 234, but is not limited to this. The plug portion 2344 may be provided in a part of the first outer peripheral region contact portion 234, and may extend beyond the contact hole 57 and above the interlayer insulating film 38. When the plug portion 2344 is provided in a part of the first outer peripheral region contact portion 234, the remaining area of ​​the first outer peripheral region contact portion 234 may be filled with the same material as the edge metal layer 146. The material of the plug portion 2344 may be a plug metal such as tungsten.

[0317] The side surface of the polycrystalline portion 232 may be in contact with the side surface of the housing portion 198. The housing portion 198 may be a region of the interlayer insulating film 38 located below the first outer peripheral region contact portion 234. The housing portion 198 may be formed in the process of providing the interlayer insulating film 38 and may be formed from the same material as the interlayer insulating film 38. When the housing portion 198 is formed as a region of the interlayer insulating film 38 located below the first outer peripheral region contact portion 234, the housing portion 198 is a virtual region, as shown by the dotted line in Figure 21B. That is, the housing portion 198 may be formed integrally as part of the interlayer insulating film 38. In another example, the housing portion 198 may be a third interlayer insulating film 238 located above the semiconductor substrate 10. The housing portion 198 may be formed in the process of providing the third interlayer insulating film 238 and may be formed from the same material as the third interlayer insulating film 238. In other words, the housing portion 198 may be integrally formed as part of the third interlayer insulating film 238.

[0318] In this example, the first outer peripheral region contact portion 234 is provided such that its bottom corner portion 2340 is in contact with the polycrystalline portion 232 and its bottom surface is in contact with the housing portion 198. This ensures reliable electrical connection between the edge metal layer 146 and the polycrystalline portion 232. If the plug portion 2344 and the barrier metal film 2342 near the center of the bottom surface of the first outer peripheral region contact portion 234 are removed by over-etching during the etch-back process of the plug portion 2344, a void may be formed inside the first outer peripheral region contact portion 234. Even in that case, the electrical connection can be ensured by the barrier metal film 2342 and / or plug portion 2344 remaining on the bottom corner portion 2340 of the first outer peripheral region contact portion 234.

[0319] In this example, the first outer peripheral region contact portion 234 is provided with its bottom surface in contact with the housing portion 198. Therefore, even if a void occurs inside the area near the center of the bottom surface of the first outer peripheral region contact portion 234, the impact on the electrical connection at the bottom surface corner portion 2340 between the first outer peripheral region contact portion 234 and the polycrystalline portion 232 is suppressed. This makes it possible to improve the yield of semiconductor device 100 having the desired characteristics. In this example, the outer peripheral region 230 ensures the electrical connection between the first outer peripheral region contact portion 234 and the polycrystalline portion 232, not at the bottom surface corner portion 2340 of the first outer peripheral region contact portion 234, but at the bottom surface corner portion 2340. As a result, even if a void is formed in the area near the center of the first outer peripheral region contact portion 234 that is in contact with the housing portion 198, stable quality can be obtained and the yield can be improved.

[0320] Figure 21C shows an example of an enlarged view of the f-f' cross-section in Figure 18B. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the first outer peripheral region 230. The semiconductor device 100 in this example differs from the embodiment in Figure 21B in that the housing portion 198 is located below the first outer peripheral region contact portion 234 of the field insulating film 148. Otherwise, it may be the same as the embodiment in Figure 21B.

[0321] Figure 21D shows an example of an enlarged view of the f-f' cross section in Figure 18B. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the first outer peripheral region 230. The semiconductor device 100 in this example differs from the embodiments in Figures 21B and 21C in that a housing portion 198 is provided separately from the interlayer insulating film 38 and the field insulating film 148. In this example, the differences from the embodiments in Figures 21B and 21C will be explained in particular, and other aspects may be the same as those in Figures 21B and / or 21C.

[0322] The housing portion 198 may have polysilicon with a lower impurity concentration than the contact region 300 of the polycrystalline portion 232. The contact region 300 of the polycrystalline portion 232 may be the region of the polycrystalline portion 232 in contact with the housing portion 198. For example, the housing portion 198 may have polysilicon or undoped polysilicon with a lower impurity concentration than the polycrystalline portion 232.

[0323] Figure 22A shows an example of the f-f' cross-section in Figure 18B. The semiconductor device 100 in this example differs from the embodiment in Figure 19B in that the outer peripheral region 230 has a housing portion 198, and differs from the embodiment in Figure 21A in that the outer peripheral region 230 has a first outer peripheral region trench contact portion 2345 and a second outer peripheral region trench contact portion 2355. Otherwise, it may be the same as the embodiment in Figure 19B and / or Figure 21A.

[0324] Figure 22B shows an example of the f-f' cross-section in Figure 18B. The semiconductor device 100 in this example differs from the embodiment in Figure 19C in that the outer peripheral region 230 has a housing portion 198, and differs from the embodiment in Figure 22A in that the extension depth of the first outer peripheral region trench contact portion 2345 and the second outer peripheral region trench contact portion 2355 are different. Otherwise, it may be the same as the embodiment in Figure 19C and / or Figure 22A.

[0325] Figure 22C shows an example of an enlarged view of the f-f' cross section in Figure 18B. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the outer peripheral region 230. The semiconductor device 100 in this example differs from the embodiment in Figure 21B in that the outer peripheral region 230 has a first outer peripheral region trench contact portion 2345. In this example, the differences from the embodiment in Figure 21B will be explained in particular, and other aspects may be the same as those in the embodiment in Figure 21B.

[0326] The sidewall of the first outer peripheral region contact portion 234 may be in contact with the polycrystalline portion 232 and the interlayer insulating film 38. The polycrystalline portion 232 may be in contact with the sidewall of the first outer peripheral region contact portion 2340 from the bottom corner portion 2340 to a region of 10% to 90% of the sidewall of the first outer peripheral region contact portion 234. In this example, the polycrystalline portion 232 is in contact with the sidewall of the first outer peripheral region contact portion 2340 from the bottom corner portion 2340 to a region of 35% of the sidewall of the first outer peripheral region contact portion 234. That is, the ratio of length L4 to length L3 in this example is 35%.

[0327] Figure 22D shows an example of an enlarged view of the f-f' cross section in Figure 18B. This figure shows the region of the outer peripheral region 230 above the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 in this example differs from the embodiment in Figure 21C in that the outer peripheral region 230 has a first outer peripheral region trench contact portion 2345, and differs from the embodiment in Figure 22C in that the housing portion 198 is a region of the field insulating film 148 located below the first outer peripheral region contact portion 234. Otherwise, it may be the same as the embodiment in Figure 21C and / or Figure 22C.

[0328] Figure 22E shows an example of an enlarged view of the f-f' cross section in Figure 18B. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the outer peripheral region 230. The semiconductor device 100 in this example differs from the embodiment in Figure 21D in that the outer peripheral region 230 has a first outer peripheral region trench contact portion 2345, and differs from the embodiments in Figures 22C and 22D in that a housing portion 198 is provided separately from the interlayer insulating film 38 and the field insulating film 148. Otherwise, it may be the same as the embodiments in Figures 21D, 22C and / or Figure 22D.

[0329] Figure 23A shows an example of the f-f' cross-section in Figure 18B. The semiconductor device 100 in this example differs from the embodiment in Figure 21A in that the first outer peripheral region contact portion 234 is provided above the polycrystalline portion 232 above the field insulating film 148. Otherwise, it may be the same as the embodiment in Figure 21A.

[0330] Figure 23B shows an example of an enlarged view of the f-f' cross-section in Figure 18B. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the outer peripheral region 230. The semiconductor device 100 in this example differs from the embodiment in Figure 21B in that the first outer peripheral region contact portion 234 is provided above the polycrystalline portion 232 above the field insulating film 148. Otherwise, it may be the same as the embodiment in Figure 21B.

[0331] Figure 23C shows an example of an enlarged view of the f-f' cross section in Figure 18B. This figure shows the region above the front surface 21 of the semiconductor substrate 10 in the outer peripheral region 230. The semiconductor device 100 in this example differs from the embodiment in Figure 21D in that the first outer peripheral region contact portion 234 is provided above the polycrystalline portion 232 above the field insulating film 148, and differs from the embodiment in Figure 23B in that a housing portion 198 is provided separately from the interlayer insulating film 38. Otherwise, it may be the same as the embodiment in Figure 21D and / or Figure 23B.

[0332] Figure 24A shows an example of the f-f' cross section in Figure 18B. The semiconductor device 100 in this example differs from the embodiment in Figure 22A in that the first outer peripheral region contact portion 234 is provided above the polycrystalline portion 232 above the field insulating film 148, and differs from the embodiment in Figure 23A in that the outer peripheral region 230 has a first outer peripheral region trench contact portion 2345 and a second outer peripheral region trench contact portion 2355. Otherwise, it may be the same as the embodiment in Figure 22A and / or Figure 23A.

[0333] Figure 24B shows an example of the f-f' cross-section in Figure 18B. The semiconductor device 100 in this example differs from the embodiment in Figure 22B in that the first outer peripheral region contact portion 234 is provided above the polycrystalline portion 232 above the field insulating film 148, and differs from the embodiment in Figure 24A in that the extension depth of the first outer peripheral region trench contact portion 2345 and the second outer peripheral region trench contact portion 2355 are different. Otherwise, it may be the same as the embodiment in Figure 22B and / or Figure 24A.

[0334] Figure 24C shows an example of an enlarged view of the f-f' cross section in Figure 18B. This figure shows the region in the outer peripheral region 230 that is above the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 in this example differs from the embodiment in Figure 22C in that the first outer peripheral region contact portion 234 is provided above the polycrystalline portion 232 above the field insulating film 148, and differs from the embodiment in Figure 23B in that the outer peripheral region 230 has a first outer peripheral region trench contact portion 2345. Otherwise, it may be the same as the embodiment in Figure 22C and / or Figure 23B.

[0335] Figure 24D shows an example of an enlarged view of the f-f' cross section in Figure 18B. This figure shows the region in the outer peripheral region 230 that is above the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 in this example differs from the embodiment in Figure 22E in that the first outer peripheral region contact portion 234 is provided above the polycrystalline portion 232 above the field insulating film 148, and differs from the embodiment in Figure 23C in that the outer peripheral region 230 has a first outer peripheral region trench contact portion 2345. Otherwise, it may be the same as the embodiment in Figure 22E and / or Figure 23C.

[0336] Figure 25 shows an example of a g-g' cross-section in Figure 18A. The g-g' cross-section is the XZ plane passing through the contact hole 53 near the gate pad 112. The gate pad 112 is provided in the pad region 330. The pad region 330 is separated from the main region 220 by a well region 17, etc., and has individual pads. The pad region 330 may be located near the edge 102 of the semiconductor substrate 10. The vicinity of the edge 102 refers to the region between the edge 102 and the emitter electrode 52 in a top view. In other examples, the pad region 330 may be provided in the region between multiple emitter electrodes 52. During mounting or testing of the semiconductor device 100, each pad may be connected to an external circuit via wiring such as wires. The gate pad 112 is an example of a pad. The semiconductor device 100 in this example has a semiconductor substrate 10, an interlayer insulating film 38, a pad electrode 51, a collector electrode 24, and a pad region contact portion 334 in a g-g' cross-section.

[0337] The polycrystalline portion 332 is provided above the semiconductor substrate 10. The polycrystalline portion 332 is provided above the front surface 21 of the semiconductor substrate 10 or on the side of the front surface 21 of the semiconductor substrate 10. In this example, the polycrystalline portion 332 is provided above the front surface 21 of the semiconductor substrate 10. In this example, the polycrystalline portion 332 is the pad connection portion 125. The polycrystalline portion 332 may be provided above the pad region insulating film 338. The pad region insulating film 338 may be made of the same material as the gate insulating film 42, for example. The pad region insulating film 338 may be a thermal oxide film. The interlayer insulating film 38 is provided above the polycrystalline portion 332.

[0338] The pad region contact portion 334 is provided in the interlayer insulating film 38 above the polycrystalline portion 332. The pad region contact portion 334 may have a contact hole 53 and a metal layer filled inside the contact hole 53. The detailed configuration of the pad region contact portion 334 will be described later.

[0339] The polycrystalline portion 332 may be connected to the pad electrode 51 via the pad region contact portion 334. In this example, the pad connection portion 125 is connected to the pad electrode 51 via the pad region contact portion 334.

[0340] The pad area contact portion 334 may include a barrier metal film 3342 provided in the contact hole 53 and a plug portion 3344. The barrier metal film 3342 of the pad area contact portion 334 may contain titanium or a titanium compound. The plug portion 3344 of the pad area contact portion 334 may contain a plug metal such as tungsten. In this example, the barrier metal film 3342 is provided above the interlayer insulating film 38 and is in contact with the pad electrode 51. In the main region 220, the outer peripheral region 230, and / or the temperature sensing portion 180, etc., a barrier metal film 2242, a barrier metal film 2342, and / or a barrier metal film 1882 may also be provided above the interlayer insulating film 38. In this example, the plug portion 3344 is provided inside the contact hole 53. In other examples, the plug portion 3344 may be located outside the contact hole 53, above the barrier metal film 3342, and in contact with the pad electrode 51. In the main region 220, the outer peripheral region 230, and / or the temperature sensing portion 180, the plug portions 2244, 2344, and / or 1884 may be located outside the contact holes 54, 55, 56, 57, 58, and / or 59, above the barrier metal film 2242, 2342, and / or 1882. In yet another example, the barrier metal film 3342 may not be located above the interlayer insulating film 38, but only inside the contact hole 53.

[0341] The pad connection portion 125 may be made of the same polycrystalline material as the gate conductive portion 44 and the dummy conductive portion 34. In other examples, the pad connection portion 125 may be made of polycrystalline material deposited simultaneously with the polycrystalline material constituting the temperature-sensing diode 183, and made conductive by ion implantation or other means as needed. The pad region insulating film 338 below the polycrystalline portion 332 may not have the same configuration as the gate insulating film 42, but may have the same configuration as the second interlayer insulating film 37 of the temperature-sensing portion 180. The pad connection portion 125 does not have to be electrically connected to anything other than the pad electrode 51. In that case, each pad connection portion 125 may or may not be connected to each other at a location different from the cross-section in Figure 25. In this case, the pad electrode 51 may be directly connected to the gate metal layer 50. Also, the pad connection portion 125 does not have to be conductive. In other examples, the pad connection portion 125 may be electrically connected to anything other than the pad electrode 51. In that case, each pad connection portion 125 may be connected at a location different from the cross-section in Figure 25. For example, the pad connection portion 125 may be connected to the connection portion 25. Also, the pad electrode 51 may not be directly connected to the gate metal layer 50 but connected via the pad connection portion 125. In this case, the pad connection portion 125 is conductive and may be connected to the gate metal layer 50 outside the gate pad 112 in a top view, and may be connected to the gate metal layer 50 in the same manner as the connection to the pad electrode 51.

[0342] The barrier metal film 3342 may be provided up to the end of the pad electrode 51. The pad electrode 51 may be provided wider than the end of the pad connection portion 125. In other examples, the pad electrode 51 may not be provided up to the end of the pad connection portion 125.

[0343] The pad region 330 may have a pad region trench contact portion 3345 that extends in the depth direction of the semiconductor substrate 10 from the upper surface of the interlayer insulating film 38 downwards from the upper surface of the polycrystalline portion 332. The pad region trench contact portion 3345 is an example of the pad region contact portion 334. The pad region trench contact portion 3345 is a portion that is deeper on the back surface 23 side of the semiconductor substrate 10 than the upper surface of the polycrystalline portion 332.

[0344] The polycrystalline portion 332 may be connected to the pad electrode 51 via the pad region trench contact portion 3345. In this example, the pad connection portion 125 is connected to the pad electrode 51 via the pad region trench contact portion 3345.

[0345] The main region 220 may have a main region trench contact portion 2245 that extends downward from the upper surface of the interlayer insulating film 38 to the front surface of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. Since this figure is a cross-sectional view of the pad region 330, the main region trench contact portion 2245 is not shown. The main region trench contact portion 2245 is, for example, the active trench contact portion 1245 shown in Figure 4C. The main region trench contact portion 2245 is an example of the main region contact portion 224. The main region trench contact portion 2245 is a portion that is deeper on the back surface 23 side than the front surface 21 of the semiconductor substrate 10. The main region 220 may have a plurality of main region trench contact portions 2245 provided on the front surface 21 of the semiconductor substrate 10.

[0346] In the depth direction of the semiconductor substrate 10, the extension depth Dp of the pad region trench contact portion 3345 extending from the upper surface of the polycrystalline portion 332 in the depth direction of the semiconductor substrate 10 is shallower than the extension depth Dt of the multiple main region trench contact portions 2245 extending from the front surface of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. By making the extension depth Dp of the pad region trench contact portion 3345 shallower than the extension depth Dt of the main region trench contact portion 2245, it is possible to suppress the pad region contact portion 334 penetrating the pad connection portion 125 and the pad region insulating film 338, thereby preventing the insulation between the pad connection portion 125 and the semiconductor substrate 10 from being lost. Furthermore, since the main region trench contact portion 2245 extends deeper than the pad region trench contact portion 3345, latch-up can be suppressed by forming the main region contact portion 224 sufficiently deep in the contact region 15. The pad area trench contact portion 3345 and the main area trench contact portion 2245 may be formed in the same process. However, the pad area trench contact portion 3345 and the main area trench contact portion 2245 may be formed in different processes.

[0347] The contact width Wtp of the pad region trench contact portion 3345 in contact with the polycrystalline portion 332 may be larger, the same as, or smaller than the contact width Wtt1 of each of the multiple main region trench contact portions 2245. The contact width Wtp of the pad region trench contact portion 3345 may be the width at which the pad region trench contact portion 3345 contacts the upper surface of the polycrystalline portion 332. The contact width Wtt1 of the main region trench contact portion 2245 may be the width at which the active trench contact portion 1245 contacts the upper surface of the mesa portion 71 of the semiconductor substrate 10, as shown in Figure 4C.

[0348] In other examples, the extension depth Dp of the pad area trench contact portion 3345 may be substantially zero. The pad area contact portion 334 may not extend to the pad connection portion 125, and the main area trench contact portion 2245 may extend to a depth Dt.

[0349] Although Figure 25 uses the gate pad 112 for explanation, the configuration described for the gate pad 112 may also be applied to other pads. For example, it may be used for the anode pad 116, cathode pad 118, sense electrode 114, and / or any other pad not shown, as depicted in Figure 18A. The pad electrode 51 may be in direct contact with the anode wiring portion 117 or cathode wiring portion 119, etc., or it may be indirectly connected via the polycrystalline portion 332. If the pad is a Kelvin emitter pad (not shown) that takes the same potential as the emitter electrode 52, the pad region contact portion 334 may extend from the upper surface of the pad region insulating film 338 in the depth direction of the semiconductor substrate 10, and the thickness T of the pad region insulating film 338 below the pad region contact portion 334 may become thinner, or the pad region contact portion 334 may penetrate the pad region insulating film 338 and reach the semiconductor substrate 10. Although Figure 25 was used to explain the example of an XZ cross section, the longitudinal direction of the contact hole 53 does not have to be the Y axis direction. For example, the longitudinal direction of the contact hole 53 may be the X-axis direction, or any other direction, and contact holes 53 with different orientations may be used in combination.

[0350] Figure 26 shows an example of a g-g' cross-section in Figure 18A. The semiconductor device 100 in this example differs from the embodiment in Figure 25 in that the pad region 330 has a recess region 336. In this example, the differences from the embodiment in Figure 25 will be explained in particular, and other aspects may be the same as those in the embodiment in Figure 25. That is, the contact depth Dp of the pad region contact portion 334 may be shallower than the contact depth of the main region contact portion 224.

[0351] The pad region 330 may have a recess region 336 formed by a depression on the upper surface of the semiconductor substrate 10. The polycrystalline portion 332 may be provided in the recess region 336. In this example, the polycrystalline portion 332 is provided on the front surface 21 side of the semiconductor substrate 10. In the depth direction of the semiconductor substrate 10, the height position of the upper surface of the interlayer insulating film 38 in the main region 220 may be the same as the height position of the upper surface of the interlayer insulating film 38 in the recess region 336. The height position being the same may include the height position being substantially the same. The height position being substantially the same may mean that the distance from the front surface 21 of the semiconductor substrate 10 to the upper surface of the interlayer insulating film 38 in the main region 220 and the distance from the front surface 21 of the semiconductor substrate 10 to the upper surface of the interlayer insulating film 38 in the recess region 336 are within 20% of the average value of the two, or they may be within 10% of the average value.

[0352] If the height position of the upper surface of the interlayer insulating film 38 in the main region 220 and the height position of the upper surface of the interlayer insulating film 38 in the recess region 336 are approximately the same, the main region contact portion 224 and the pad region contact portion 334 can be formed simultaneously by the same etching process. That is, if the upper surfaces of both the interlayer insulating film 38 in the main region 220 and the interlayer insulating film 38 in the recess region 336 are at the same height from the front surface 21 of the semiconductor substrate 10, there will be no shift in the exposure focus during the photolithography process. Therefore, the dimensional tolerances of the interlayer insulating film 38, emitter electrode 52, etc. can be reduced. Furthermore, the main region contact portion 224 and the pad region contact portion 334 can be formed with the same dimensional tolerance. As a result, they can be easily manufactured with fewer steps compared to when each contact portion is formed in separate processes. However, the main region contact portion 224 and the pad region contact portion 334 may be formed by different processes.

[0353] Figure 27 shows an example of a g-g' cross-section in Figure 18A. The semiconductor device 100 in this example differs from the embodiment in Figure 25 in that the pad region 330 has a housing portion 198. In this example, the differences from the embodiment in Figure 25 will be explained in detail, and other aspects may be the same as those of the embodiment in Figure 25.

[0354] The housing portion 198 is provided below the pad area contact portion 334. The material of the housing portion 198 may be the same as that of the interlayer insulating film 38.

[0355] The bottom corner portion 3340 of the pad area contact portion 334 may be in contact with the polycrystalline portion 332. The bottom corner portion 3340 of the pad area contact portion 334 may be the intersection of the bottom surface of the pad area contact portion 334 and the side surface of the pad area contact portion 334. Contact between the bottom corner portion 3340 and the polycrystalline portion 332 may mean contact with the polycrystalline portion 332 on its upper surface, contact with the polycrystalline portion 332 on its side surface, or contact with the polycrystalline portion 332 in an internal region of the polycrystalline portion 332. In this example, the bottom corner portion 3340 is in contact with the polycrystalline portion 332 on its upper surface.

[0356] The pad area contact portion 334 in this example has two bottom corner portions 3340. One of the two bottom corner portions 3340 may be in contact with the polycrystalline portion 332. The other of the two bottom corner portions 3340 may or may not be in contact with the housing portion 198. In this example, one bottom corner portion 3340a of the pad area contact portion 3340 is in contact with the polycrystalline portion 332, and the other bottom corner portion 3340b is in contact with the housing portion 198.

[0357] The bottom surface of the pad area contact portion 334 may be in contact with the housing portion 198. The bottom surface of the pad area contact portion 334 may be the surface between the two bottom corner portions 3340 of the pad area contact portion 334. When the bottom surface of the pad area contact portion 334 is in contact with the housing portion 198, it may be that the bottom surface is in contact with the housing portion 198 on the upper surface of the housing portion 198, or it may be that the bottom surface is in contact with the housing portion 198 in an area inside the housing portion 198. In this example, the bottom surface of the pad area contact portion 334 is in contact with the housing portion 198 on the upper surface of the housing portion 198.

[0358] The bottom surface of the pad area contact portion 334 may be in contact with the polycrystalline portion 332 and the housing portion 198. In this example, one bottom corner 3340a of the pad area contact portion 334 is in contact with the polycrystalline portion 332, and the other bottom corner 3340b is in contact with the housing portion 198, so the bottom surface of the pad area contact portion 334 is in contact with the polycrystalline portion 332 and the housing portion 198.

[0359] The polycrystalline portion 332 may be in contact with the bottom surface of the pad region contact portion 334 from the bottom surface corner portion 3340 to an area of ​​10% to 40% of the bottom surface of the pad region contact portion 334. That is, the ratio of the area of ​​the bottom surface of the pad region contact portion 334 that is in contact with the polycrystalline portion 332 to the area of ​​the bottom surface of the pad region contact portion 334 may be 10% to 40%. Referring to Figure 27, length L1 is the length of the bottom surface of the pad region contact portion 334 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Length L2 is the length of the bottom surface of the pad region contact portion 334 that is in contact with the polycrystalline portion 332 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Therefore, the ratio of length L2 to length L1 may be 10% to 40%. In this example, the polycrystalline portion 332 is in contact with the bottom surface of the pad region contact portion 334 from the bottom surface corner portion 3340a to 20% of the bottom surface of the pad region contact portion 334. That is, the ratio of length L2 to length L1 in this example is 20%.

[0360] The pad area contact portion 334 may have a barrier metal film 3342 and a plug portion 3344. In this example, the barrier metal film 3342 and the plug portion 3344 are formed of different materials, but they may be formed of the same material.

[0361] The barrier metal film 3342 may be provided on the bottom corner portion 3340 of the pad area contact portion 334. In this example, the barrier metal film 3342 is provided over the entire side and bottom surface of the pad area contact portion 334, but is not limited thereto. The barrier metal film 3342 may be provided covering at least the bottom corner portion 3340, and may not cover the central part of the bottom surface of the pad area contact portion 334. The barrier metal film 3342 may extend beyond the contact hole 53 and be provided above the interlayer insulating film 38. The material of the barrier metal film 3342 may be titanium or a titanium compound, etc.

[0362] The plug portion 3344 may be provided in contact with the inside of the barrier metal film 3342. In this example, the plug portion 3344 is provided by filling the pad area contact portion 334, but is not limited to this. The plug portion 3344 may be provided in a part of the pad area contact portion 334, and may extend beyond the contact hole 56 and above the interlayer insulating film 38. When the plug portion 3344 is provided in a part of the pad area contact portion 334, the remaining area of ​​the pad area contact portion 334 may be filled with the same material as the pad electrode 51. The material of the plug portion 3344 may be a plug metal such as tungsten.

[0363] The side surface of the polycrystalline portion 332 may be in contact with the side surface of the housing portion 198. The housing portion 198 may be a region of the interlayer insulating film 38 located below the pad region contact portion 334. The housing portion 198 may be formed in the process of providing the interlayer insulating film 38 and may be formed from the same material as the interlayer insulating film 38. When the housing portion 198 is formed as a region of the interlayer insulating film 38 located below the pad region contact portion 334, the housing portion 198 may be a virtual region. For example, the housing portion 198 may be integrally formed as part of the interlayer insulating film 38. In another example, the housing portion 198 may be polysilicon with a lower impurity concentration than the polycrystalline portion 332 or undoped polysilicon. In yet another example, the housing portion 198 may be a pad region insulating film 338 located above the semiconductor substrate 10. In this case, the housing portion 198 may be formed in the process of providing the pad region insulating film 338 and may be formed from the same material as the pad region insulating film 338. In other words, the housing portion 198 may be integrally formed as part of the pad region insulating film 338.

[0364] In this example, the pad area contact portion 334 is provided such that its bottom corner portion 3340 is in contact with the polycrystalline portion 332 and its bottom surface is in contact with the housing portion 198. This ensures reliable electrical connection between the pad electrode 51 and the polycrystalline portion 332. If the plug portion 3344 and the barrier metal film 3342 near the center of the bottom surface of the pad area contact portion 334 are removed by over-etching during the etch-back process of the plug portion 3344, a void may form inside the pad area contact portion 334. Even in that case, the electrical connection can be ensured by the barrier metal film 3342 and / or plug portion 3344 remaining on the bottom corner portion 3340 of the pad area contact portion 3340.

[0365] In this example, the pad region contact portion 334 is provided with its bottom surface in contact with the housing portion 198. Therefore, even if a void occurs inside the pad region contact portion 334 near the center of its bottom surface, the impact on the electrical connection at the bottom corner portion 3340 between the pad region contact portion 334 and the polycrystalline portion 332 is suppressed. This makes it possible to improve the yield of semiconductor device 100 having the desired characteristics. In this example, the pad region 330 ensures the electrical connection between the pad region contact portion 334 and the polycrystalline portion 332 at the bottom corner portion 3340 rather than the center of the bottom surface of the pad region contact portion 334. As a result, even if a void is formed in the area near the center of the pad region contact portion 334 that is in contact with the housing portion 198, stable quality can be obtained and the yield can be improved.

[0366] Figure 28 shows an example of a g-g' cross-section in Figure 18A. The semiconductor device 100 in this example differs from the embodiment in Figure 27 in that the pad region 330 has a pad region trench contact portion 3345. Otherwise, it may be the same as the embodiment in Figure 27.

[0367] The sidewall of the pad region contact portion 334 may be in contact with the polycrystalline portion 332 and the interlayer insulating film 38. The polycrystalline portion 332 may be in contact with the sidewall of the pad region contact portion 334 from the bottom corner portion 3340 to an area of ​​10% to 90% of the sidewall of the pad region contact portion 334. That is, the ratio of the area of ​​the sidewall of the pad region contact portion 334 that is in contact with the polycrystalline portion 332 to the area of ​​the sidewall of the pad region contact portion 334 that is in contact with the polycrystalline portion 332 may be 10% to 90%. Referring to Figure 28, length L3 is the length of the sidewall of the pad region contact portion 334 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10, and length L4 is the length of the sidewall of the pad region contact portion 334 that is in contact with the polycrystalline portion 332 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Therefore, the ratio of length L4 to length L3 may be between 10% and 90%. In this example, the polycrystalline portion 232 is in contact with the side wall of the pad region contact portion 334 from the bottom corner portion 3340 to 35% of the side wall of the pad region contact portion 334. That is, the ratio of length L4 to length L3 in this example is 35%.

[0368] Figure 29 shows an example of the electrical connections of each part of the semiconductor device 100. In this example, a Zener diode 170 is provided in antiparallel for voltage withstand protection between the cathode pad 118 and the anode pad 116. The Zener diode 170 may have the same configuration as the temperature-sensing diode 183. In this case, the forward voltage of the Zener diode 170 may be different from the forward voltage of the temperature-sensing diode 183. If the temperature-sensing diode 183 consists of a series connection of multiple temperature-sensing cathode regions 181 and temperature-sensing anode regions 182, the Zener diode 170 may be provided between each temperature-sensing cathode region 181 and temperature-sensing anode region 182. Also, if a Zener diode 170 is provided between the temperature-sensing part 180 and the active part 120 for electric field protection, the Zener diode 170 may have the same configuration as the temperature-sensing diode 183. In this case, the breakdown voltage of the Zener diode 170 may be different from the breakdown voltage of the temperature-sensing diode 183. The Zener diodes 170 may be configured in a series of multiple diodes. In other examples, the Zener diodes 170 may be connected at different positions, or they may not be provided at all.

[0369] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0370] It should be noted that the execution order of operations, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be performed in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, this does not mean that it is mandatory to perform the operations in that order. [Explanation of Symbols]

[0371] 10...Semiconductor substrate, 12...Emitter region, 14...Base region, 15...Contact region, 16...Storage region, 17...Well region, 18...Drift region, 20...Buffer region, 21...Front surface, 22...Collector region, 23...Back surface, 24...Collector electrode, 25...Connection portion, 30...Dummy trench portion, 31...Extended portion, 32...Dummy insulating film, 33...Connection portion, 34...Dummy conductive portion, 36...First interlayer insulating film, 37...Second interlayer insulating film, 38...Interlayer insulating film, 40...Gate trench 41...Extended portion, 42...Gate insulating film, 43...Connection portion, 44...Gate conductive portion, 50...Gate metal layer, 51...Pad electrode, 52...Emitter electrode, 53...Contact hole, 54...Contact hole, 55...Contact hole, 56...Contact hole, 57...Contact hole, 58...Contact hole, 59...Contact hole, 70...Transistor portion, 71...Mesa portion, 80...Diode portion, 81...Mesa portion, 82...Cathode region, 90...Boundary portion, 91...Mesa 100... Semiconductor device, 102... Edge, 112... Gate pad, 114... Sense electrode, 115... Current sense section, 116... Anode pad, 117... Anode wiring section, 118... Cathode pad, 119... Cathode wiring section, 120... Active section, 122... Active trench section, 124... Active contact section, 125... Pad connection section, 140... Edge termination structure section, 142... Guard ring, 144... Field plate, 146... Edge metal layer, 148... Field insulating film, 151... Back Surface-side lifetime control region, 152... Front surface-side lifetime control region, 170... Zener diode, 180... Temperature sensing region, 181... Temperature sensing cathode region, 182... Temperature sensing anode region, 183... Temperature sensing diode, 188... Temperature sensing contact region, 194... Recess region, 196... Insulating film, 198... Housing region, 200... Recess, 220... Main region, 224... Main region contact region, 230... Outer peripheral region, 232... Polycrystalline region, 234... First outer peripheral region contact region, 235... Second outer peripheral region contact region,236...Recess region, 238...Third interlayer insulating film, 300...Contact region, 330...Pad region, 332...Polycrystalline region, 336...Recess region, 334...Pad region contact region, 338...Pad region insulating film, 1241...First active contact region, 1242...Second active contact region, 1243...Barrier metal film, 1244...Plug region, 1245...Active trench contact region, 1420...Non-corner region, 1422...Corner region, 1880...Bottom corner region, 1882...Barrier metal film, 1884... • Plug section, 1885... Temperature-sensitive trench contact section, 2242... Barrier metal film, 2244... Plug section, 2245... Main area trench contact section, 2340... Bottom corner section, 2342... Barrier metal film, 2344... Plug section, 2345... First outer peripheral area trench contact section, 2352... Barrier metal film, 2354... Plug section, 2355... Second outer peripheral area trench contact section, 3340... Bottom corner section, 3342... Barrier metal film, 3344... Plug section, 3345... Pad area trench contact section,

Claims

1. A semiconductor device comprising a main region and an outer peripheral region, The main region has a plurality of main region trench contact portions provided on the front surface of the first conductivity type semiconductor substrate. The aforementioned outer peripheral region is A polycrystalline portion provided above the semiconductor substrate, An interlayer insulating film provided above the polycrystalline portion, In the depth direction of the semiconductor substrate, a first outer peripheral trench contact portion is provided, extending from the upper surface of the interlayer insulating film to below the upper surface of the polycrystalline portion, It has, In the depth direction of the semiconductor substrate, the extension depth of the first outer peripheral trench contact portion from the upper surface of the polycrystalline portion in the depth direction of the semiconductor substrate is shallower than the extension depth of the plurality of main trench contact portions from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate. Semiconductor equipment.

2. The outer peripheral region has a recessed region in which a depression is provided on the upper surface of the semiconductor substrate. The polycrystalline portion is provided in the recess region. The semiconductor device according to claim 1.

3. The contact width of the first outer peripheral trench contact portion in contact with the polycrystalline portion is greater than the contact width of each of the multiple main trench contact portions. The semiconductor device according to claim 1.

4. The contact width of the first outer peripheral trench contact portion in contact with the polycrystalline portion is smaller than the contact width of each of the multiple main trench contact portions. The semiconductor device according to claim 1.

5. A gate trench portion having a gate conductive portion is provided on the front surface of the semiconductor substrate, A gate metal layer provided above the semiconductor substrate and electrically connected to the gate conductive portion, Equipped with, The aforementioned polycrystalline portion is The gate metal layer is connected via the first outer peripheral trench contact portion, The gate conductive part is connected to the gate conductive part. The semiconductor device according to any one of claims 1 to 4.

6. A dummy trench portion having a dummy conductive portion is provided on the front surface of the semiconductor substrate, An emitter electrode provided above the semiconductor substrate and electrically connected to the semiconductor substrate, Equipped with, The aforementioned polycrystalline portion is The emitter electrode is connected via the first outer peripheral trench contact portion, The dummy conductive part is connected to The semiconductor device according to any one of claims 1 to 4.

7. On the front surface of the semiconductor substrate, a second conductive type guard ring is provided between the main region and the edge of the semiconductor substrate, An edge metal layer provided above the semiconductor substrate and electrically connected to the guard ring, Equipped with, The polycrystalline portion is connected to the edge metal layer via the first outer peripheral trench contact portion. The semiconductor device according to any one of claims 1 to 4.

8. The outer peripheral region, in the region where the polycrystalline portion is not provided, has a second outer peripheral region trench contact portion that extends in the depth direction of the semiconductor substrate from the upper surface of the interlayer insulating film to a point below the upper surface of the semiconductor substrate. The extension depth of the first outer peripheral trench contact portion extending from the upper surface of the polycrystalline portion in the depth direction of the semiconductor substrate is shallower than the extension depth of the second outer peripheral trench contact portion extending from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate. The semiconductor device according to claim 7.

9. The outer peripheral region, in the region where the polycrystalline portion is not provided, has a second outer peripheral region trench contact portion that extends in the depth direction of the semiconductor substrate from the upper surface of the interlayer insulating film to a point below the upper surface of the semiconductor substrate. The extension depth of the first outer peripheral trench contact portion extending from the upper surface of the polycrystalline portion in the depth direction of the semiconductor substrate and the extension depth of the second outer peripheral trench contact portion extending from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate are shallower than the extension depth of the plurality of main region trench contact portions extending from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate. The semiconductor device according to claim 7.

10. A semiconductor device comprising a main region and a pad region, The main region has a plurality of main region trench contact portions provided on the front surface of the first conductivity type semiconductor substrate. The aforementioned pad area is Pads for connecting to external circuits, A polycrystalline portion provided above the semiconductor substrate, An interlayer insulating film provided above the polycrystalline portion, In the depth direction of the semiconductor substrate, a pad region trench contact portion is provided extending from the upper surface of the interlayer insulating film downward from the upper surface of the polycrystalline portion, It has, In the depth direction of the semiconductor substrate, the extension depth of the pad region trench contact portion extending from the upper surface of the polycrystalline portion in the depth direction of the semiconductor substrate is shallower than the extension depth of the plurality of main region trench contact portions extending from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate. Semiconductor equipment.

Images