How to rewrite a resistive switching element

Abstract

To provide a method for rewriting a resistance-variable element that solves two failure modes at the same time.SOLUTION: A method for rewriting a resistance-variable element including a first electrode, a second electrode, and an ion conductive layer located between the electrodes in which a state where the resistance-variable element is caused to have a low resistance by forming a metal bridge in the ion conductive layer is defined as an ON-state and a state where the resistance-variable element is caused to have a high resistance by forming no metal bridge or cutting the metal bridge midway is defined as an OFF-state, includes steps of applying a first OFF-voltage when transitioning from the ON-state to the OFF-state, reading and determining a resistance value between the first electrode and the second electrode, applying a second ON-voltage lower than a first ON-voltage to the resistance-variable element in the OFF-state that does not satisfy a determination value in accordance with the determination, and applying a second OFF-voltage.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] The present disclosure relates to a rewriting method for a resistance change element.

Background Art

[0002] In order to diversify the functions of programmable logic and promote its implementation in electronic devices and the like, it is necessary to reduce the size of switches that interconnect logic cells and also reduce their on-resistance. Non-volatile switching elements have been developed that utilize an electrochemical reaction to electrically deposit metal within an ion conductive layer that conducts metal ions, form metal crosslinks within the ion conductive layer, and switch from an off state to an on state. It is known that such non-volatile switching elements are smaller in size and have lower on-resistance than conventional semiconductor switches. Non-volatile switching elements include the "two-terminal switch (Fig. 1A)" disclosed in Patent Document 1 and the "three-terminal switch" disclosed in Patent Document 2.

[0003] The "two-terminal switch" shown in Figure 1A has a structure in which an ion-conducting layer 13 is sandwiched between a lower electrode 11 that supplies metal ions and an upper electrode 12 that does not supply metal ions during the process of switching the switching element from the "off" state to the "on" state. During the process of switching the switching element from the "off" state to the "on" state, the upper electrode 12 is grounded and a positive voltage is applied to the lower electrode 11. On the lower electrode 11 side, the metal is ionized and the generated metal ions are introduced into the ion-conducting layer 13, while on the upper electrode 12 side, the metal ions are reduced and metal is deposited. The deposited metal forms a metal bridge in the ion-conducting layer 13 that reaches from the upper electrode 12 side to the lower electrode 11 side, resulting in switching from the "off" state to the "on" state. This is called the SET operation. Conversely, during the process of switching the switching element from the "on" state to the "off" state, the upper electrode 12 is grounded and a negative voltage is applied to the lower electrode 11. During this process, the deposited metal is reionized, and on the lower electrode 11 side, the reduction of metal ions promotes the redeposition of the metal. As a result, the metal bridge disappears, and the system switches from the "on" state to the "off" state. This is called the RESET operation.

[0004] Because "two-terminal switches" have a simple structure, the manufacturing process is straightforward, and it is possible to fabricate "two-terminal switches" with element sizes on the order of nanometers. "Three-terminal switches," as exemplified in Figure 3 (Figure 1B) in Patent Document 2, have a structure in which the upper electrodes of two "two-terminal switches" are integrated, thus ensuring high reliability.

[0005] A polymer ion conductive layer mainly composed of silicon, oxygen, and carbon is preferable as the ion conductive layer. Polymer ion conductive layers have excellent operational reliability because they can maintain a high dielectric breakdown voltage even when metal crosslinking is formed (Patent Document 3).

[0006] Furthermore, in order to incorporate (apply) non-volatile switching elements as wiring switching switches in programmable logic, it is necessary to reduce the "element size" and simplify the manufacturing process to accommodate the high density of wiring. In state-of-the-art semiconductor devices, copper is mainly used as the wiring material for forming multilayer wiring. There is a need to develop a method for efficiently forming non-volatile switching elements, such as resistive switching elements, within multilayer copper wiring. Non-patent document 1 discloses a technology for integrating switching elements that utilize electrochemical reactions into semiconductor devices. Non-patent document 1 describes a configuration in which the copper wiring on the semiconductor substrate and the lower electrode of the switching element are used interchangeably when the lower electrode of the switching element is made of copper. By adopting this structure, the process of newly forming the lower electrode in addition to the copper wiring can be omitted. Therefore, a mask for the "patterning process" for fabricating the lower electrode becomes unnecessary, and for example, in order to fabricate a resistive switching element with a "two-terminal switch" configuration, only two photomasks (PRs) used in the "ion conduction layer" formation process and the "upper electrode" formation process need to be added.

[0007] When copper wiring on a semiconductor substrate and the lower electrode of a switching element are used interchangeably, if a "polymer ion conducting layer" formed from a porous polymer mainly composed of silicon, oxygen, and carbon is directly deposited on the copper wiring, the surface of the copper wiring will oxidize. To prevent this oxidation of the copper wiring surface, a thin metal film that functions as an oxidation sacrificial layer is provided on the copper wiring surface before the "polymer ion conducting layer" is deposited. During the deposition process of the "polymer ion conducting layer," the thin metal film is oxidized by oxygen and converted into a "thin film of metal oxide exhibiting ion conductivity." For example, as illustrated in Figure 4 (Figure 1C) of Patent Document 3, the "thin film of metal oxide" produced by the oxidation of the "thin metal film that functions as an oxidation sacrificial layer" together with the "polymer ion conducting layer" deposited on its upper surface constitute an ion conducting layer.

[0008] When fabricating the lower electrode of a switching element from copper, the upper electrode, which does not supply metal ions during the process of switching the switching element from the "off" state to the "on" state, is formed using platinum or gold, which are resistant to oxidation, or ruthenium, which remains conductive even after oxidation. Non-patent document 1 describes the fabrication of the upper electrode using ruthenium, which is suitable for processing. The switching element disclosed in Non-patent document 1 will be explained using Figure 2.

[0009] The switching element has a configuration comprising a lower electrode 21, a second ion conductive layer 24 formed at the interface with the lower electrode 21, a first ion conductive layer 23 in contact with the second ion conductive layer 24, a first upper electrode 22 provided via the lower electrode 21, the second ion conductive layer 24, and the first ion conductive layer 23, and a second upper electrode 25 in contact with the upper surface of the first upper electrode 22. The first ion conductive layer 23 and the second ion conductive layer 24 serve as a medium for the conduction of metal ions. Furthermore, it is desirable that the material of the first upper electrode 22 does not supply metal ions to the first ion conductive layer 23 and the second ion conductive layer 24 when the first upper electrode 22 is grounded and a positive voltage is applied to the lower electrode 21 during the switching process from the "off" state to the "on" state.

[0010] The lower electrode 21 is made of copper. For example, copper wiring formed by sputtering or electroplating is used as the lower electrode 21.

[0011] The second ion-conducting layer 24 is formed of a metal oxide. First, a thin film of the metal constituting the metal oxide is deposited on the lower electrode 21. When a SiOCH-based polymer film containing silicon, oxygen, carbon, and hydrogen, which constitutes the first ion-conducting layer 23, is deposited on the surface of the metal thin film by plasma CVD, the oxygen present in the deposition chamber oxidizes the metal thin film, converting it into a metal oxide thin film. Thus, a second ion-conducting layer 24, made of a metal oxide thin film, is formed between the lower electrode 21 and the first ion-conducting layer 23. The metal constituting the metal oxide can be selected from the group consisting of titanium, aluminum, zirconium, hafnium, and tantalum. These metals may also be stacked and used as a thin metal film. The optimal film thickness of the metal thin film is 0.5 nm to 2 nm. If the film thickness is thinner than the optimal thickness, oxidation will extend beyond the metal thin film and reach the copper wiring surface while the SiOCH-based polymer film is deposited by plasma CVD. As a result, slight oxidation of the copper wiring surface occurs. On the other hand, if the film thickness is thicker than the optimal thickness, the oxidation of the metal thin film is not completed during the deposition of the SiOCH-based polymer film by plasma CVD, and it remains as metal on the copper wiring surface.

[0012] The thin metal film used to fabricate the second ion-conducting layer 24 is formed using sputtering, laser ablation, or plasma CVD. The thickness of the fabricated second ion-conducting layer 24 is preferably 50% or less of the thickness of the first ion-conducting layer 23.

[0013] The first ion-conducting layer 23 is formed from a SiOCH-based polymer film containing silicon, oxygen, carbon, and hydrogen, which is deposited by plasma CVD.

[0014] As the metal material for fabricating the first upper electrode 22, a ruthenium alloy with titanium, tantalum, zirconium, hafnium, aluminum, etc., as additives is used. The second upper electrode 25 serves to protect the first upper electrode 21 from etching damage. The second upper electrode 25 is composed of a metallic nitride. Particularly preferred are nitrides of titanium, tantalum, zirconium, hafnium, and aluminum, which function as an etching stop film and have conductivity.

[0015] The method for driving a switching element that employs a "two-terminal switch" configuration will be explained with reference to Figure 3.

[0016] When the first upper electrode 32 and the second upper electrode 37 are grounded and a positive voltage is applied to the lower electrode 31, the metal of the lower electrode 31 becomes metal ions 35 via the second ion conducting layer 36 and dissolves in the first ion conducting layer 33. Then, the metal ions 35 in the second ion conducting layer 36 and the first ion conducting layer 33 deposit on the surface of the first upper electrode 32 as metal bridges 34, and the lower electrode 31 and the first upper electrode 32 are connected by the deposited metal bridges 34. When the lower electrode 31 and the first upper electrode 32 are electrically connected by the metal bridges 34, the "two-terminal switch" is turned "on".

[0017] On the other hand, when the first upper electrode 32 is grounded in the "on" state and a negative voltage is applied to the lower electrode 31, the metal bridge 34 dissolves into metal ions 35 in the second ion conductive layer 36 and the first ion conductive layer 33, and a portion of the metal bridge 34 breaks. At this time, the metal ions 35 are recovered by the metal 34 dispersed in the second ion conductive layer 36 and the first ion conductive layer 33, and by the lower electrode 31. As a result, the electrical connection between the lower electrode 31 and the first upper electrode 32 is broken, and the "two-terminal switch" goes into the "off" state.

[0018] After switching to the "off" state described above, to switch from the "off" state to the "on" state, the first upper electrode 32 and the second upper electrode 37 should be grounded and a positive voltage applied to the lower electrode 31 again. Alternatively, the lower electrode 31 may be grounded and a negative voltage applied to the first upper electrode 32 and the second upper electrode 36 to turn the "two-terminal switch" to the "on" state, or the lower electrode 31 may be grounded and a positive voltage applied to the first upper electrode 32 to turn the "two-terminal switch" to the "off" state.

[0019] Furthermore, during the process of switching the "two-terminal switch" to the "off" state, changes in electrical characteristics occur even before the electrical connection is completely broken, such as an increase in the resistance between the lower electrode 31 and the first upper electrode 32, or a change in the inter-electrode capacitance, until the electrical connection is finally broken.

[0020] The SET / RESET method primarily involves applying voltage pulses to the element. In integrated circuits, if an element does not turn "on" with the SET pulse, a verification method is used in which the SET pulse is applied again. This is also the case for RESET operation. [Prior art documents] [Patent Documents]

[0021] [Patent Document 1] International Publication No. 00 / 48196 [Patent Document 2] International Publication No. 2012 / 043502 [Patent Document 3] International Publication No. 2011 / 058947 [Patent Document 4] Japanese Patent Publication No. 2013-058779 [Non-patent literature]

[0022] [Non-Patent Document 1] IEEE TRANSACTIONS ON ELECTRON DEVICES, Volume 57, pp. 1987-1995, 2010 Summary of the Invention Problems to be Solved by the Invention

[0023] Switching elements have variations in electrical programming. In the rewriting operation of an atomic movement-type switch, when a defect occurs where a desired resistance state is not obtained after applying a predetermined voltage pulse, a verify sequence that repeatedly applies the predetermined voltage pulse is performed. The verify sequence is a technique for reducing defects by repeatedly applying only RESET pulses. Conventionally, for example, a method of programming an element that cannot be reset (defective bit) using a verify method of applying the same RESET pulse again has been common. Similarly, Patent Document 4 proposes a method of reducing defective bits by applying a pre-pulse voltage in advance before switching, but this method has been insufficient as a measure for reducing the number of defective bits. Furthermore, there is also a problem that endurance (rewrite resistance) deteriorates when SET operations and RESET operations are simply repeated to obtain a desired resistance state.

[0024] The present disclosure has been made in view of the above points, and an object of the present disclosure is to provide a rewriting method for a resistance change element that can simultaneously solve failure modes, further suppress endurance degradation, reduce the number of defective bits, and obtain a high-resistance "off" state with high yield. Means for Solving the Problems

[0025] According to this disclosure, a resistance changing element is provided, comprising a first electrode, a second electrode, and an ion conducting layer located between the electrodes, wherein the element is considered to be in an ON state when a voltage pulse is applied to form a metal bridge made of atoms constituting the second electrode within the ion conducting layer, resulting in low resistance, and is considered to be in an OFF state when the metal bridge is not formed or the metal bridge is broken midway, resulting in high resistance, and a first ON voltage is applied to the first electrode to transition to the ON state, and a first OFF voltage is applied to the second electrode to transition to the OFF state, wherein when transitioning from the ON state to the OFF state, a method for rewriting the resistance changing element is provided, comprising the steps of: applying the first OFF voltage; reading the resistance value between the first electrode and the second electrode and determining a first resistance value; applying a second ON voltage to the resistance changing element in the OFF state that is smaller than the determined value of the first resistance value; and repeating the steps of applying the second OFF voltage until the read resistance value is larger than the determined value of the first resistance value.

[0026] The determination of the first resistance value may be based on the fact that the first resistance value is in the range of 1 MΩ to 10 MΩ.

[0027] The second O hmm In the step of applying voltage, a current due to a second on-voltage that is higher than the current due to the first on-voltage may be applied. The current due to the second on-voltage may be in the range of 25 to 50 μA. Alternatively, the current due to the second on-voltage may be increased in steps up to 100 μA. Furthermore, the pulse width of the second on-voltage may be set from 10 ns to 100 ns.

[0028] The first ON voltage may be applied in two stages, with the second applied voltage being lower than the first applied voltage, and the second applied current being higher than the first applied current.

[0029] The current control in the process of applying the off voltage may be controlled by controlling the current when transitioning to the on state using the gate voltage of the matrix transistor located at the end of the crossbar switch connected to the first electrode.

[0030] In the step of applying the second off-voltage, the voltage may be increased in steps and the process may be performed multiple times. [Effects of the Invention]

[0031] According to this disclosure, it is possible to provide a method for rewriting a resistive switching element that simultaneously resolves faulty modes, suppresses degradation of endurance, reduces the number of faulty bits, and yields a high-resistance "off" state. [Brief explanation of the drawing]

[0032] [Figure 1A] This figure shows an example of a two-terminal switch. [Figure 1B] This figure shows an example of a two-terminal switch. [Figure 1C] This figure shows an example of a two-terminal switch. [Figure 2] This figure shows an example of a switching element. [Figure 3] This figure shows a method for driving a switching element that employs a two-terminal switch configuration. [Figure 4A] This diagram shows the normal RESET operation. [Figure 4B] This figure shows the rearrangement of the bridged state by a weak SET sequence. [Figure 4C] This diagram illustrates a defect where the cross-linking was incomplete, resulting in insufficient resistance. [Figure 4D] This diagram shows the rearrangement of the bridged state. [Figure 5] This is a circuit diagram illustrating the control of a 3-terminal switch. [Figure 6] This is a normal distribution chart of resistance during the ON state, before retrying, and after retrying. [Figure 7]This is a normal distribution chart of resistance during the ON state, before retrying, and after retrying. [Figure 8] This is a diagram illustrating the retry sequence using a simple algorithm. [Figure 9] This is a cumulative normal distribution chart of resistance before the ON, OFF, and weak SET sequences, and after the weak SET sequence. [Figure 10] This is a cumulative normal distribution chart of resistance during the ON state, before retrying, and after retrying. [Figure 11] This is a cumulative normal distribution chart of resistance during the ON state, before retrying, and after retrying. [Figure 12A] This is a schematic cross-sectional view showing step 1 of the manufacturing process for a semiconductor device in which a 3-terminal switch is formed inside a multilayer wiring layer. [Figure 12B] This is a schematic cross-sectional view showing step 2 of the manufacturing process for a semiconductor device in which a 3-terminal switch is formed inside a multilayer wiring layer. [Figure 12C] This is a schematic cross-sectional view showing step 3 of the manufacturing process for a semiconductor device in which a 3-terminal switch is formed inside a multilayer wiring layer. [Figure 12D] This is a schematic cross-sectional view showing step 4 of the manufacturing process for a semiconductor device in which a 3-terminal switch is formed inside a multilayer wiring layer. [Figure 12E] This is a schematic cross-sectional view showing step 5 of the manufacturing process for a semiconductor device in which a 3-terminal switch is formed inside a multilayer wiring layer. [Figure 12F] This is a schematic cross-sectional view showing step 6 of the manufacturing process for a semiconductor device in which a 3-terminal switch is formed inside a multilayer wiring layer. [Figure 12G] This is a schematic cross-sectional view showing step 7 of the manufacturing process for a semiconductor device in which a 3-terminal switch is formed inside a multilayer wiring layer. [Figure 12H] This is a schematic cross-sectional view showing step 8 of the manufacturing process for a semiconductor device in which a 3-terminal switch is formed inside a multilayer wiring layer. [Figure 12I] This is a schematic cross-sectional view showing step 9 of the manufacturing process for a semiconductor device in which a 3-terminal switch is formed inside a multilayer wiring layer. [Figure 12J]This is a schematic cross-sectional view showing step 10 of the manufacturing process for a semiconductor device in which a 3-terminal switch is formed inside a multilayer wiring layer. [Figure 12K] This is a schematic cross-sectional view showing step 11 of the manufacturing process for a semiconductor device in which a 3-terminal switch is formed inside a multilayer wiring layer. [Figure 12L] This is a schematic cross-sectional view showing step 12 of the manufacturing process for a semiconductor device in which a 3-terminal switch is formed inside a multilayer wiring layer. [Modes for carrying out the invention]

[0033] Hereinafter, an example of an embodiment of this disclosure will be described with reference to the drawings. In each drawing, identical or equivalent components and parts are given the same reference numerals. Also, the dimensional ratios in the drawings are exaggerated for illustrative purposes and may differ from the actual ratios.

[0034] The inventors of this case diligently investigated the phenomenon of faulty bits occurring in resistive switching elements and found that the faulty modes during RESET can be classified into the following two categories. (1) A malfunction mode in which the bridge is quasi-stabilized with respect to pulses in the RESET direction and does not transition to a high-resistance state. (2) A faulty mode in which the crosslinking is not completely recovered and breaks midway, resulting in no high resistance.

[0035] (1) is a defective bit that is stuck at a low resistance value, and its resistance value does not change even when a RESET pulse is applied. (2) is a defective bit that has a resistance value that is in an intermediate state between low and high resistance values, and does not reach the high resistance region.

[0036] The following are two countermeasures in the present invention for the above-mentioned failure modes. To resolve the faulty mode in retry sequence (2), a SET pulse is applied to the faulty bit that is in an intermediate resistance state, causing it to transition to a low resistance state and rebuilding the bridged state. From here, applying a RESET pulse again allows it to transition to a high resistance state. This sequence will be called the retry sequence.

[0037] Weak SET sequence: To resolve the malfunction mode of (1), a SET pulse is applied to the bits that are not to be RESET. This releases the fixation by rearranging the bridged state through the application of a voltage in the opposite direction to RESET, and then applying a RESET pulse allows the transition to high resistance. This sequence will be called the weak SET sequence. In both the retry sequence and the weak SET sequence, multiple RESETs may occur after a single application of SET voltage.

[0038] The present disclosure aims to provide a method for rewriting a resistive switching element that combines a weak SET sequence and a retry sequence to simultaneously resolve two failure modes, further suppress endurance degradation, reduce the number of faulty bits, and obtain a high-resistance off state with good yield.

[0039] (First Embodiment) First, as a first embodiment of this disclosure, an on / off switching mechanism for a switching element employing a "two-terminal switch" and a "three-terminal switch" configuration will be described.

[0040] Atomic switches, which are resistive switching elements, have a structure in which an ion conductor is sandwiched between an electrode that does not contribute to the reaction (such as Ru) and an electrode that forms a metal bridge within the ion conductor (such as Cu). The ON and OFF states change as the metal bridges are formed and destroyed within the ion conductor, and this state is maintained in a non-volatile state. Figure 4A shows the normal RESET operation.

[0041] Next, we will explain the difference between the weak SET sequence and the retry sequence. First, it was found that two-terminal elements that did not achieve the desired off-resistance had two failure modes, as described above: (1) a failure mode in which the bridge was quasi-stabilized with respect to the pulse in the RESET direction and therefore did not operate at high resistance, and (2) a failure mode in which the bridge was not fully recovered and broke midway, resulting in no high resistance. For the failure mode (1) in which the bridge was quasi-stabilized with respect to the application of the pulse in the RESET direction, it was found that a weak SET sequence, in which a SET pulse was applied once and then multiple RESET pulses were applied again, rearranged the bridge state (Figure 4B), resolved the quasi-stabilization of the bridge, and allowed the resistance to be increased above the on-resistance. For the failure mode (2) in which the bridge was only partially connected and therefore did not become high resistance (Figure 4C), it was found that a retry sequence, in which a SET pulse was applied once to rearrange the bridge state (Figure 4D) and then another RESET pulse was applied, allowed the bridge to be fully recovered and the resistance to be increased.

[0042] Next, the control of the 3-terminal switch will be explained. Figure 5 is a circuit diagram illustrating the control of the 3-terminal switch. The 3-terminal switch 100 is connected in series with the source of the cell transistor and has a 1T2R structure consisting of one transistor and two resistors. The current that turns it ON can be controlled by the gate voltage. The 3-terminal switch 100 is placed at each crossover point, and the programming voltage is applied via the transistor selected by the programming driver (PX, PY, and C). These drivers and decoders are located around the logic cell array. The unit cell has a 1T2R type structure by sharing the final stage of the selected transistor. Therefore, the area of ​​the logic cell can be saved by 25% compared to the 2T2R type consisting of two transistors and two resistors. In this circuit, the control point of the target element of the 3-terminal switch 100 is uniquely determined by the DX and DY decode signals, so the immunity to SET interference is much higher compared to the programming method that applies 1 / 2 voltage to the non-selected control line.

[0043] First, when controlling the current applied to the 3-terminal switch 100 with a cell transistor, the current is controlled by the cell transistor directly connected to the 3-terminal switch 100. On the other hand, the current applied to the 3-terminal switch 100 can also be controlled by the matrix transistors at the end of the matrix of the crossbar switch.

[0044] (Example 1) (Verify sequence) First, an example of a conventional verification sequence is shown. After 100 rewrite cycles, elements that did not reach 10 MΩ were considered faulty bits.

[0045] First, a pulse with a current of 500 μA, a voltage of 4 V, and a pulse width of 10 μs was applied to the lower electrode 31 in Figure 3 to turn it on, and then a pulse with a current of 500 μA, a voltage of 2.4 V, and a pulse width of 100 ns was applied to the upper electrode 37 to turn it off. Here, bits that could not be completely reset were detected and extracted, and the number of defective bits was reduced by a simple verification sequence in which the same RESET pulse was applied. However, the resistance distribution at the time of off did not become high off-resistance even after 100 repetitions of the verification using the same RESET pulse, and there was almost no difference from the off-resistance distribution of the first time. Also, bits with a resistance of 10 MΩ or less are shown as defective bits, but saturation occurred at around 550 defective bits.

[0046] (Example 2) (Retry sequence, no increase in current) Next, an example of a retry sequence will be described. First, a pulse with a current of 770 μA, a voltage of 4 V, and a pulse width of 10 μs is applied to the lower electrode 31 in the SET direction to turn the element ON, and a voltage of 2.45 V in the RESET direction is applied to turn it OFF. For elements that were not determined to be OFF, a pulse of 770 μA, 4 V, and 10 μs in the SET direction is input to rebuild the bridge, and then the RESET voltage is applied again, showing an example of a retry sequence that recovers a large amount of metal during RESET. Here, the SET voltage applied again is called the "second ON voltage". The RESET voltage applied again is called the "second OFF voltage". Here, the pulse width of the current of 770 μA on the RESET side is 2.45 V and 100 ns. If the RESET voltage is too high, it will set the element in reverse, so 1.5 V to 2.7 V is desirable. Figure 7 shows the normal distribution of ON, OFF, and initial resistances, and the OFF distribution is 1 MΩ or more, showing the effect of the retry sequence. For the OFF detection, a resistance value of 1MΩ to 10MΩ is preferable.

[0047] However, as shown in Figure 6, when SET / RESET was repeated in the retry sequence with the same SET voltage as the initial SET, there was a problem in that the Program / Erase endurance deteriorated due to physical stress on the areas where crosslinks were formed in the ion conduction layer. Simply applying the SET voltage could lead to the formation of thick crosslinks, making RESET impossible or degrading the endurance. On the other hand, when the SET pulse current during retry was reduced to 100 μA, it did not reach the judgment off resistor, resulting in a failure to reach the judgment even in the retry sequence.

[0048] (Example 3) Figure 7 shows the normal distribution of on, off, and initial resistance values ​​when the pulse was set to 4V, 1.05mA, and 10μs pulse width, followed by 5 retries of 20 each. The current at the time of setting for each retry was increased by 20 times each to 150μA, 200μA, 250μA, 300μA, and 350μA. With the retry sequence of this embodiment, the number of defective bits converged to 0. In this embodiment, the metal crosslinking within the ion conductive layer is as shown in the left diagram of Figure 4D, and the endurance does not deteriorate even with repeated Program / Erase operations.

[0049] Figure 8 shows a simplified algorithm diagram of the retry sequence. After the program starts, all bits are set with SET pulse 1 (step S101), and all bits are reset with RESET pulse 1 (step S102). If the RESET is successful (step S103; Yes), the sequence ends. If the RESET is unsuccessful (step S103; No), 20 retries are performed with retry SET pulse 2 (step S104), and if the RESET is successful (step S105; Yes), the retry sequence ends. If the RESET is unsuccessful (step S105; No), 20 retries are performed with retry SET pulse 2 (step S104), and if the RESET is successful (step S105; Yes), the retry sequence ends. If the RESET is unsuccessful (step S105; No), the retry SET pulse is increased every n tries.

[0050] (Example 4) (Pulse width, current dependence) Next, we will describe another example of the retry sequence. In a retry sequence using a pulse with a current of 770 μA, a voltage of 4 V, and a pulse width of 100 μs, one bad bit remained, and this bad bit did not disappear because its resistance was lower than the on resistance. Next, when the pulse width of the SET voltage was set to 10 μs, the bad bits converged to 0. This suggests that by lengthening the SET pulse, some bits became lower in resistance than the on state. On the other hand, when a retry was performed with a pulse width of 10 ns for the SET voltage, the bad bits converged to 0, but in the element where the retry was performed with a pulse width of 5 ns, the bad bits did not converge to 0. From this, it can be concluded that a pulse width of 10 ns to 10 μs is desirable for the SET voltage in the retry sequence. Furthermore, the current applied to the element was changed with a second on voltage. As a result, the bad bits did not converge to 0 at 10 μA, whereas they did converge to 0 at 25 μA. The upper limit of the current was 200 μA.

[0051] (Example 5) (Weak SET sequence) Next, an example of the weak SET sequence will be described. First, for a faulty bit in the ON state that does not transition to the OFF state despite the application of the RESET voltage, a SET voltage is applied with a voltage and current lower than the first ON voltage to encourage the rearrangement of the bit that is stuck at a resistance value near the ON state, and then the reset voltage is applied again to enable the transition to the OFF state. At this time, the current when applying the reset voltage is set to flow 150 μA through the column transistor, and the RESET voltage is increased stepwise from 1.5 V to 2.6 V in 0.1 V steps, with a pulse width of 100 ns each time. By gradually increasing the voltage, it is possible to suppress defects in which low-resistance bits suddenly occur. In addition, by applying the RESET voltage multiple times each time the weak SET voltage is applied, it is possible to suppress characteristic degradation (endurance degradation) due to rewriting. Figure 9 is a figure showing the cumulative normal distribution of the resistance value after the SET operation on an 8 kΩ resistor, after RESET before weak SET application, and after RESET after weak SET application. It can be seen that applying a weak SET eliminates faulty bits that get stuck in the ON position, resulting in a high OFF-resistance state.

[0052] (Example 6) If a large voltage and current are applied during SET, a low-resistance bit that cannot be RESET will occur. To prevent this defect, a method of dividing the initial ON process into two steps is effective. In the first step, SET is performed with high voltage and low current, and in the second step, ON is performed with low voltage and high current. This suppresses over-SET, which causes low-resistance bits. The voltage in the first step should be higher than the voltage in the second step. For example, the first step voltage should be 4V and the second step voltage should be around 2V or 3V. Conversely, the current in the second step should be higher than the current in the first step. For example, if the ON resistance is around 5kΩ, it is preferable to set the first step current to 110μA or less and the second step current to 160μA or more. The ON resistance is determined by the second step current.

[0053] (Example 7) Figure 10 shows the cumulative normal distribution of resistance values: initial off-resistance, resistance after SET operation to a 10kΩ resistor, and resistance after RESET verification operation. SET was performed using a 2-step SET with 4V current 110μA and 2V current 120μA. The current during RESET was set to 150μA, and the RESET voltage was 2.4V for 100ns. Verification was performed by re-running the RESET operation for bits where the off-resistance was determined to be 10MΩ or less. The resistance distribution after RESET verification shifted to approximately half an order of magnitude higher resistance compared to the resistance distribution before verification.

[0054] Figure 11 shows the cumulative normal distribution of resistance values ​​to illustrate the retry operation according to this embodiment. After performing SET and RESET operations under the same conditions as described above, a pulse of 25 μA, 2 V, and 100 ns in the SET direction was applied as a second ON voltage to the bits whose off-resistance was determined to be 10 MΩ or less to perform bridge rearrangement, and then the RESET voltage was applied to those bits again. With the application of retries, a resistance increase of one order of magnitude was observed near the median and 1.5 orders of magnitude near -3σ.

[0055] (Second embodiment) Next, as a second embodiment, a manufacturing process for a semiconductor device in which a "three-terminal switch" with electrically connected upper electrodes is formed inside a multilayer wiring layer, particularly the process of forming the "three-terminal switch" inside the multilayer wiring layer, will be explained with reference to the drawings. The "three-terminal switch" is a switch configuration formed within the multilayer wiring, and the retry sequence of this embodiment can reduce the off-resistance without reducing the endurance. Therefore, the process of forming the "three-terminal switch" inside the multilayer wiring layer will be explained as the form in which the effects of this embodiment can be most effectively utilized.

[0056] Figures 12A to 12L are schematic cross-sectional views showing steps 1 to 12 of the manufacturing process for a semiconductor device in which a "3-terminal switch" is formed inside a multilayer wiring layer according to the second embodiment.

[0057] (Process 1) Step 1 is shown in Figure 12A. First, an interlayer insulating film 142 (e.g., silicon oxide film, thickness 300 nm) is deposited on a semiconductor substrate 141 (e.g., a substrate on which a semiconductor device is formed). Next, a barrier insulating film 143 (e.g., silicon nitride film, thickness 30 nm) is deposited on the interlayer insulating film 142. Next, an interlayer insulating film 144 (e.g., silicon oxide film, thickness 200 nm) is deposited on the barrier insulating film 143. Subsequently, wiring grooves are formed in the interlayer insulating film 144 and the barrier insulating film 143 using a lithography method (including photoresist formation, dry etching, and photoresist removal). Next, first wiring A145a and first wiring B145b (e.g., copper) are embedded in the wiring grooves via a barrier metal A146a (e.g., tantalum nitride / tantalum, thickness 5 nm / 5 nm). In Step 1, the interlayer insulating films 142 and 144 can be formed by plasma CVD (Chemical Vapor Deposition). Here, plasma CVD is a method in which, for example, a gaseous or liquid raw material is vaporized and continuously supplied to a reaction chamber under reduced pressure, and molecules are excited by plasma energy, forming a continuous film on a substrate by gas-phase reaction or substrate surface reaction. Furthermore, in step 1, the first wiring A145a and the first wiring B145b can be formed by, for example, forming a barrier metal 146 (for example, a tantalum nitride / tantalum laminated film) by PVD, embedding copper in the wiring groove by electroplating after the formation of copper seeds by PVD, heat treatment at a temperature of 200°C or higher, and then removing excess copper outside the wiring groove by CMP.

[0058] Such a series of copper wiring formation methods can utilize general techniques in the relevant field. Here, the CMP (Chemical Mechanical Polishing) method is a method of planarizing wafer surface irregularities that occur during the multilayer wiring formation process by polishing them with a rotating polishing pad while flowing a polishing solution onto the wafer surface. Planarization is achieved by forming embedded wiring (damascene wiring) by polishing excess copper embedded in grooves, or by polishing the interlayer insulating film.

[0059] (Process 2) Step 2 is shown in Figure 12B. Next, a barrier insulating film 147 (for example, a silicon carbonitride film, thickness 30 nm) is formed on the interlayer insulating film 144 including the first wiring A145a and the first wiring B145b. The barrier insulating film 147 can be formed by plasma CVD. The thickness of the barrier insulating film 147 is preferably about 10 nm to 50 nm.

[0060] (Step 3) Step 3 is shown in Figure 12C. Next, a hard mask film 148 (for example, a silicon oxide film) is formed on the barrier insulating film 147. From the viewpoint of maintaining a high etching selectivity ratio in dry etching, the hard mask film 148 is preferably made of a different material from the barrier insulating film 147, and may be an insulating film or a conductive film. For example, a silicon oxide film, silicon nitride film, TiN, Ti, tantalum, tantalum nitride, etc. can be used for the hard mask film 148, and a silicon nitride / SiO2 laminate can be used.

[0061] (Step 4) Step 4 is shown in Figure 12D. Next, the openings are patterned on the hard mask film 148 using a photoresist (not shown), and the opening pattern is formed on the hard mask film 148 by dry etching using the photoresist as a mask. After that, the photoresist is removed by oxygen plasma ashing or the like. At this time, the dry etching does not necessarily have to stop at the upper surface of the barrier insulating film 147, and may reach the interior of the barrier insulating film 147.

[0062] (Step 5) Step 5 is shown in Figure 12E. Next, using the hard mask film 148 as a mask, the barrier insulating film 147 exposed through the openings in the hard mask film 148 is etched back (dry etched) to form openings in the barrier insulating film 147, exposing the first wiring A145a and the first wiring B145b through these openings. The openings formed in the barrier insulating film 147 may extend into the interior of the interlayer insulating film. Subsequently, an organic stripping treatment using an amine-based stripping solution is performed to remove copper oxide formed on the exposed surfaces of the first wiring A145a and the first wiring B145b, as well as to remove etching duplicate products generated during the etch-back process. In step 5, it is preferable that the hard mask film 148 is completely removed during the etch-back process, but if it is an insulating material, it may remain. The shape of the openings in the barrier insulating film 147 can be circular, square, or quadrilateral, and the diameter of the circle or the length of one side of the quadrilateral can be between 20 nm and 500 nm. Furthermore, in step 5, by using reactive dry etching for the etch-back of the barrier insulating film 147, the walls of the openings in the barrier insulating film 147 can be made tapered. In reactive dry etching, a gas containing fluorocarbons can be used as the etching gas.

[0063] (Step 6) Step 6 is shown in Figure 12F. Next, a SiOCH-based polymer film containing silicon, oxygen, carbon, and hydrogen is formed on the barrier insulating film 147, which includes the first wiring A145a and the first wiring B145b, as an ion conductive layer 149b constituting the resistive change layer 149, with a thickness of 6 nm by plasma CVD. In step 6, the raw materials for the cyclic organic siloxane and helium, which is the carrier gas, are introduced into the reaction chamber. Once the supply of both is stabilized and the pressure in the reaction chamber becomes constant, the application of RF power is started. The raw material is supplied at a rate of 10-200 sccm, and helium is supplied at a rate of 500 sccm via the raw material vaporizer and at a rate of 500 sccm directly to the reaction chamber via a separate line.

[0064] In step 6, since moisture and other substances adhere to the openings of the barrier insulating film 147 due to the organic stripping treatment in step 5, it is preferable to degass them by applying heat treatment under reduced pressure at a temperature of about 250°C to 350°C before depositing the resistive change layer 149. At that time, it is desirable to do so under vacuum or in a nitrogen atmosphere to prevent the copper surface from being oxidized again. In addition, in step 6, before depositing the resistive change layer 149, gas cleaning using H2 gas or plasma cleaning treatment may be performed on the first wiring A145a and first wiring B145b exposed from the openings of the barrier insulating film 147. Gas cleaning or plasma cleaning treatment can suppress the oxidation of copper in the first wiring A145a and first wiring B145b when forming the resistive change layer 149, and can suppress thermal diffusion (mass transfer) of copper during the process.

[0065] Furthermore, in step 6, before depositing the ion-conducting layer 149b, an anti-oxidation film 149a is deposited using PVD, consisting of a thin film of titanium with a thickness of 0.5 nm and an aluminum film with a thickness of 0.5 nm, thereby suppressing oxidation of the copper wiring surface of the first wiring A145a and the first wiring B145b. The titanium and aluminum layers of the anti-oxidation film 149a are oxidized during the formation of the ion-conducting layer 149b to form an oxide film. In step 6, it is necessary to embed the resistance-changing layer 149 in the stepped opening with good coverage, so it is preferable to use the plasma CVD method.

[0066] (Step 7) Step 7 is shown in Figure 12G. A ruthenium-titanium alloy is formed on the resistive change layer 149 as the first upper electrode 150 with a film thickness of 10 nm using the CO-sputtering method. In this process, the ruthenium target and the titanium target are located in the same chamber, and the alloy film is deposited by sputtering simultaneously. At this time, the power applied to the ruthenium target is set to 150 W and the power applied to the titanium target is set to 75 W, so that the ruthenium content in the "ruthenium-titanium alloy" is 83 atm%. Alternatively, 15 sccm of nitrogen may be introduced and nitriding may be performed. In this case, the titanium content will be 9% and the nitrogen content will be 8%. Next, a second upper electrode 151 is formed on the first upper electrode 150. As the second upper electrode 151, titanium nitride is formed with a film thickness of 25 nm using the reactive sputtering method. At this time, the power applied to the titanium target is set to 1800 W, and nitrogen gas and argon gas are introduced into the chamber for sputtering. In this process, the nitrogen flow rate and argon flow rate are set to 1:1, thereby achieving a titanium content of 30 atm% in titanium nitride.

[0067] (Step 8) Step 8 is shown in Figure 12H. Next, a hard mask film 152 (e.g., a silicon nitride film, thickness 30 nm) and a hard mask film 153 (e.g., a silicon oxide film, thickness 200 nm) are laminated on the second upper electrode 151 in this order. In step 8, the hard mask films 152 and 153 can be formed using plasma CVD. The hard mask films 152 and 153 can be formed using plasma CVD, which is common in the art. Furthermore, it is preferable that the hard mask films 152 and 153 are of different types; for example, the hard mask film 152 can be a silicon nitride film and the hard mask film 153 can be an SiO2 film. In this case, it is preferable that the hard mask film 152 is made of the same material as the protective insulating film 154 and the barrier insulating film 147, which will be described later. That is, surrounding the resistive switching element entirely with the same material integrates the material interfaces, preventing the intrusion of moisture from the outside and preventing detachment from the resistive switching element itself. Furthermore, the hard mask film 152 can be formed by plasma CVD, but it is necessary to maintain a reduced pressure in the reaction chamber before film formation. During this reduced pressure period, oxygen is desorbed from the resistive layer 149, and the leakage current of the ion conduction layer increases due to oxygen vacancies. To suppress these, it is preferable to set the film formation temperature to 350°C or lower, preferably 250°C or lower. In addition, since the film is exposed to the film formation gas under reduced pressure before film formation, it is preferable not to use a reducing gas. For example, it is preferable to use a silicon nitride film formed by high-density plasma using a SiH4 / N2 mixed gas as a raw material.

[0068] (Step 9) Step 9 is shown in Figure 12I. Next, a photoresist (not shown) for patterning the resistive element portion is formed on the hard mask film 153. Subsequently, the hard mask film 153 is dry-etched using the photoresist as a mask until the hard mask film 152 is exposed. Subsequently, the photoresist is removed using oxygen plasma ashing and organic exfoliation.

[0069] (Step 10) Step 10 is shown in Figure 12J. Next, the hard mask film 152, the second upper electrode 151, the first upper electrode 150, and the resistive transition layer 149 are continuously dry-etched using the hard mask film 153 as a mask. At this time, it is preferable that the hard mask film 153 is completely removed during etch-back, but it may remain as is. In step 10, for example, if the second upper electrode 151 is titanium nitride, it can be processed with a Cl2-based RIE, and if the first upper electrode 150 is a ruthenium-titanium alloy, it can be processed with a Cl2 / O2 mixed gas using RIE. Also, when etching the resistive transition layer 149, it is necessary to stop the dry etching on the lower barrier insulating film 147. If the resistive transition layer 149 is an SiOCH-based polymer film containing silicon, oxygen, carbon, and hydrogen, and the barrier insulating film 147 is a silicon nitride film or a silicon carbonitride film, RIE processing can be performed by adjusting the etching conditions with a mixed gas such as a CF4 system, a CF4 / Cl2 system, or a CF4 / Cl2 / Ar system. By using this hard mask RIE method, the resistive switching layer 149 can be processed without exposing the resistive switching element portion to oxygen plasma ashing for resist removal. Furthermore, if oxidation treatment with oxygen plasma is performed after processing, the oxidation plasma treatment can be irradiated without depending on the resist stripping time.

[0070] (Step 11) Step 11 is shown in Figure 12K. Next, a protective insulating film 154 (for example, a silicon nitride film, thickness 30 nm) is deposited on a barrier insulating film 147 which includes a hard mask film 152, a second upper electrode 151, a first upper electrode 150, and a resistance change layer 149. In step 11, the protective insulating film 154 can be formed by plasma CVD, but it is necessary to maintain a reduced pressure in the reaction chamber before film formation. At this time, oxygen is desorbed from the side surface of the resistance change layer 149, and the leakage current of the ion conduction layer increases. To suppress these, it is preferable to set the film formation temperature of the protective insulating film 154 to 250°C or lower. Furthermore, since it is exposed to a film formation gas under reduced pressure before film formation, it is preferable not to use a reducing gas. For example, it is preferable to use a silicon nitride film formed at a substrate temperature of 200°C using a high-density plasma with a SiH4 / N2 mixed gas as the raw material.

[0071] (Step 12) Step 12 is shown in Figure 12L. Next, an interlayer insulating film 155 (e.g., a SiOC film) and an interlayer insulating film 157 (e.g., a silicon oxide film) are deposited on the protective insulating film 154 in that order. Then, a wiring groove for the second wiring 158 and a pilot hole for the plug 159 are formed. The second wiring 158 (e.g., copper) and the plug 159 (e.g., copper) are simultaneously formed in the wiring groove and pilot hole via a barrier metal 160 (e.g., tantalum nitride / tantalum) using a copper dual damascene wiring process. Then, a barrier insulating film 161 (e.g., a silicon nitride film) is deposited on the interlayer insulating film 157 containing the second wiring 158. In step 12, the formation of the second wiring 158 can be carried out using the same process as the formation of the lower layer wiring. At this time, by using the same material for the barrier metal 160 and the second upper electrode 151, the contact resistance between the plug 159 and the second upper electrode 151 can be reduced, improving the performance of the device (reducing the resistance of the 3-terminal switch 162 when it is ON). Furthermore, in step 12, the interlayer insulating film 155 and the interlayer insulating film 157 can be formed by plasma CVD. Also, in step 12, in order to eliminate the step formed by the "3-terminal switch" 162, the interlayer insulating film 155 may be deposited thickly, and then the interlayer insulating film 155 may be planarized by CMP to achieve the desired thickness of the interlayer insulating film 155.

[0072] The three-terminal switch created by steps 1 to 12 above has a switch configuration formed within multilayer wiring, and the retry sequence of this embodiment can reduce the off-resistance without reducing the endurance.

[0073] While embodiments of the present disclosure have been described in detail above with reference to the attached drawings, the technical scope of the present disclosure is not limited to these examples. It is clear that a person with ordinary skill in the art of the present disclosure may conceive of various modifications or alterations within the scope of the technical idea set forth in the claims, and these modifications or alterations are also understood to fall within the technical scope of the present disclosure.

[0074] Furthermore, the effects described in the above embodiments are descriptive or illustrative, and are not limited to those described in the above embodiments. In other words, the technology relating to this disclosure may produce other effects that would be obvious to a person of ordinary skill in the art of this disclosure from the descriptions in the above embodiments, in addition to or in lieu of the effects described in the above embodiments. [Explanation of Symbols]

[0075] 100 3-terminal switch 141 Semiconductor substrates 142 Interlayer insulating film 143 Barrier insulating film 144 Interlayer insulating film 145a First Wiring A 145b 1st wiring B 146 Barrier Metal 147 Barrier insulating film 148 Hard mask film 149 Resistivity change layer 149a Antioxidant film 149b Ion Conducting Layer 150 1st upper electrode 151 2nd upper electrode 152 Hard mask film 153 Hard mask film 154 Protective insulating film 155 Interlayer insulating film 157 Interlayer insulating film 158 2nd wiring 159 plug 160 Barrier Metal 161 Barrier insulating film 162 Terminal Switch

Claims

1. It consists of a first electrode, a second electrode, and an ion-conducting layer located between the electrodes. The ON state is defined as the case where a metal bridge made of atoms constituting the second electrode is formed in the ion conductive layer by applying a voltage pulse, resulting in low resistance, and the OFF state is defined as the case where the metal bridge is not formed or the metal bridge is broken midway, resulting in high resistance. In a resistive switching element, a first on-voltage is applied to the first electrode to transition to the ON state, and a first off-voltage is applied to the second electrode to transition to the OFF state, When transitioning from the ON state to the OFF state, The steps include applying the first off-voltage and A step of reading the resistance value between the first electrode and the second electrode and determining the first resistance value, The resistance changing element in the off state, which is smaller than the determination value of the first resistance value, A step of applying a second ON voltage, A step of applying a second off-voltage, The process includes repeating the steps until the read resistance value becomes larger than the first resistance value determination value, In the step of applying the second ON voltage, A current based on the second on-voltage, which is higher than the current based on the first on-voltage, is applied. The current due to the second on-voltage is in the range of 25 to 50 μA. A method for rewriting a resistive switching element, wherein the current due to the second on-voltage is gradually increased up to 100 μA.

2. The first ON voltage is applied in two separate steps. The second applied voltage is lower than the first applied voltage. The second current applied is higher than the first current applied. A method for rewriting a resistive switching element as described in claim 1.

3. The method for rewriting a resistance change element according to claim 1, wherein the step of applying the second off voltage is performed multiple times by gradually increasing the voltage.

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