Hybrid multilayer field-effect transistor

Abstract

The hybrid laminated semiconductor device includes a nanosheet stack on a substrate and an all-around gate. The nanosheet stack includes a first stack portion and a second stack portion. The first stack portion includes a first channel. The second stack portion is laminated on the first stack portion and includes a second channel. The all-around gate includes a first gate portion surrounding the first channel and a second gate portion surrounding the second channel. A first gate extension contacts the first gate portion and a second gate extension contacts the second gate portion. At least one gate contact contacts the first gate extension to establish electrical conductivity with the first gate portion and contacts the second gate extension to establish electrical conductivity with the second gate portion.

Description

Technical Field

[0001] The present invention generally relates to a fabrication method for semiconductor devices and the resulting structure. More specifically, the present invention relates to a fabrication method for hybrid stacked field effect transistors and the resulting structure.

Background Art

[0002] In modern semiconductor device fabrication processes, a large number of semiconductor devices such as n-type field effect transistors (NFETs) and p-type field effect transistors (PFETs) are fabricated on a single wafer. Non-planar transistor device architectures, for example, fin-type FETs (FinFETs) and nanosheet FETs, can provide improved device density and improved performance compared to planar transistors. Unlike conventional planar FETs, non-planar FETs utilize gate-all-around (GAA) technology to achieve a gate stack that surrounds the entire perimeter of the channel region. The resulting GAA FET has a reduced device footprint and improved control of channel current flow.

[0003] One type of recently developed non-planar FET is referred to as complementary field effect transistor (CFET). A CFET comprises a PFET stacked vertically over an NFET, or vice versa. CFET can utilize GAA technology when stacking PFET and NFET transistors on top of each other to enable smaller scale devices, which meets the continuous trend of reducing the footprint of semiconductor devices. However, since not all circuit components consist of CMOS pairs, CFET devices (PFET on NFET or NFET on PFET) that provide a pair of devices with different polarities do not offer sufficient flexibility in circuit design. Therefore, hybrid stacked FET solutions with flexible gate control are attractive for various types of circuits.

Summary of the Invention

[0004] Embodiments of the present invention relate to a method for performing fabrication operations to form a hybrid multilayer semiconductor device. The fabrication operation includes forming a nanosheet stack (NS stack) on a substrate, the nanosheet stack comprising a first stack portion including a first channel, a second stack portion stacked on the first stack portion and including a second channel, and a dielectric spacer inserted between the first and second stack portions. The operation further includes forming an all-around gate including a first gate portion surrounding the first channel and a second gate portion surrounding the second channel. The operation further includes forming a first gate extension on a first side of the nanosheet stack so as to be in contact with the first gate portion, and forming a second gate extension on a second side of the nanosheet stack so as to be in contact with the second gate portion. The second side is different from the first side. The process further includes forming a first gate contact that contacts a first gate extension to establish conductivity with a first gate portion, and forming a second gate contact that contacts a second gate extension to establish conductivity with a second gate portion.

[0005] Embodiments of the present invention are directed to a method for performing a fabrication step to form a hybrid multilayer semiconductor device. The fabrication step includes forming a nanosheet stack on a substrate. The nanosheet stack comprises a first stack portion including a first channel, a second stack portion stacked on the first stack portion and including a second channel, and a dielectric spacer inserted between the first and second stack portions. The step further includes forming an all-around gate including a first gate portion wrapped around the first channel and a second gate portion surrounding the second channel. The step further includes forming a first gate extension on a first side of the nanosheet stack so as to be in contact with the first gate portion, and forming a second gate extension on the same first side of the nanosheet stack so as to be in contact with the second gate portion. The process further includes forming gate contacts that contact both the first gate extension and the second gate extension in order to establish conductivity with the first gate portion and the second gate portion.

[0006] Embodiments of the present invention are directed toward a hybrid multilayer semiconductor device. The hybrid multilayer semiconductor device comprises a nanosheet stack on a substrate and an all-around gate. The nanosheet stack includes a first stack portion and a second stack portion. The first stack portion includes a first channel. The second stack portion is stacked on top of the first stack portion and includes a second channel. The all-around gate includes a first gate portion surrounding the first channel and a second gate portion surrounding the second channel. A first gate extension contacts the first gate portion, and a second gate extension contacts the second gate portion. At least one gate contact contacts the first gate extension to establish conductivity with the first gate portion and contacts the second gate extension to establish conductivity with the second gate portion.

[0007] Additional features and advantages are realized through the techniques described herein. Other embodiments and aspects are described in detail herein. For a better understanding, please refer to the specification and drawings.

[0008] Subject matter considered to be embodiments is specifically pointed out and explicitly claimed in the claims at the end of this specification. The above and other features and advantages of the embodiments will become apparent by referring to the following detailed description together with the accompanying drawings. [Brief explanation of the drawing]

[0009] [Figure 1] These are schematic diagrams of various hybrid stacked semiconductor devices according to embodiments of the present invention. [Figure 2] These are multiple cross-sectional views after various fabrication steps for forming a hybrid multilayer semiconductor device comprising two stacked FETs of the same type having independently controlled gates, and are cross-sectional views of the hybrid multilayer semiconductor device after performing various intermediate fabrication steps according to aspects of the present invention. [Figure 3] These are multiple cross-sectional views after various fabrication steps for forming a hybrid multilayer semiconductor device comprising two stacked FETs of the same type having independently controlled gates, and are cross-sectional views of the hybrid multilayer semiconductor device after performing additional fabrication steps according to embodiments of the present invention. [Figure 4] These are multiple cross-sectional views after various fabrication steps for forming a hybrid multilayer semiconductor device comprising two stacked FETs of the same type having independently controlled gates, and are cross-sectional views of the hybrid multilayer semiconductor device after additional fabrication steps according to embodiments of the present invention. [Figure 5] These are multiple cross-sectional views after various fabrication steps for forming a hybrid multilayer semiconductor device comprising two stacked FETs of the same type having independently controlled gates, and are cross-sectional views of the hybrid multilayer semiconductor device after additional fabrication steps according to embodiments of the present invention. [Figure 6]These are multiple cross-sectional views after various fabrication steps for forming a hybrid multilayer semiconductor device comprising two stacked FETs of the same type having independently controlled gates, and are cross-sectional views of the hybrid multilayer semiconductor device after additional fabrication steps according to embodiments of the present invention. [Figure 7] These are multiple cross-sectional views after various fabrication steps for forming a hybrid multilayer semiconductor device comprising two stacked FETs of the same type having independently controlled gates, and are cross-sectional views of the hybrid multilayer semiconductor device after additional fabrication steps according to embodiments of the present invention. [Figure 8] These are multiple cross-sectional views after various fabrication steps for forming a hybrid multilayer semiconductor device comprising two stacked FETs of the same type having independently controlled gates, and are cross-sectional views of the hybrid multilayer semiconductor device after additional fabrication steps according to embodiments of the present invention. [Figure 9] These are multiple cross-sectional views after various fabrication steps for forming a hybrid multilayer semiconductor device comprising two stacked FETs of the same type having independently controlled gates, and are cross-sectional views of the hybrid multilayer semiconductor device after additional fabrication steps according to embodiments of the present invention. [Figure 10] These are multiple cross-sectional views after various fabrication steps for forming a hybrid multilayer semiconductor device comprising two stacked FETs of the same type having independently controlled gates, and are cross-sectional views of the hybrid multilayer semiconductor device after additional fabrication steps according to embodiments of the present invention. [Figure 11] These are multiple cross-sectional views after various fabrication steps for forming a hybrid multilayer semiconductor device comprising two stacked FETs of the same type having independently controlled gates, and are cross-sectional views of the hybrid multilayer semiconductor device after additional fabrication steps according to embodiments of the present invention. [Figure 12] These are multiple cross-sectional views after various fabrication steps for forming a hybrid multilayer semiconductor device comprising two stacked FETs of the same type having independently controlled gates, and are cross-sectional views of the hybrid multilayer semiconductor device after additional fabrication steps according to embodiments of the present invention. [Figure 13]These are multiple cross-sectional views after various fabrication steps for forming a hybrid multilayer semiconductor device comprising two stacked FETs of the same type having independently controlled gates, and are cross-sectional views of the hybrid multilayer semiconductor device after additional fabrication steps according to embodiments of the present invention. [Figure 14] These are multiple cross-sectional views after various fabrication steps for forming a hybrid multilayer semiconductor device comprising two stacked FETs of the same type having independently controlled gates, and are cross-sectional views of the hybrid multilayer semiconductor device after additional fabrication steps according to embodiments of the present invention. [Figure 15] These are multiple cross-sectional views after various fabrication steps for forming a hybrid semiconductor device including a stacked CMOS FET having a shared gate, and are cross-sectional views of the hybrid stacked semiconductor device after performing various intermediate fabrication steps according to aspects of the present invention. [Figure 16] These are multiple cross-sectional views after various fabrication steps for forming a hybrid semiconductor device including a stacked CMOS FET having a shared gate, and are cross-sectional views of the hybrid stacked semiconductor device after additional fabrication steps according to an aspect of the present invention. [Figure 17] These are multiple cross-sectional views after various fabrication steps for forming a hybrid semiconductor device including a stacked CMOS FET having a shared gate, and are cross-sectional views of the hybrid stacked semiconductor device after additional fabrication steps according to an aspect of the present invention. [Figure 18] These are multiple cross-sectional views after various fabrication steps for forming a hybrid semiconductor device including a stacked CMOS FET having a shared gate, and are cross-sectional views of the hybrid stacked semiconductor device after additional fabrication steps according to an aspect of the present invention. [Figure 19] These are multiple cross-sectional views after various fabrication steps for forming a hybrid semiconductor device including a stacked CMOS FET having a shared gate, and are cross-sectional views of the hybrid stacked semiconductor device after additional fabrication steps according to an aspect of the present invention. [Figure 20]1 is a schematic diagram of an integrated circuit (IC) including different types of hybrid stacked semiconductor devices according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] This detailed description includes examples of how aspects of the present invention may be implemented to form a wraparound lower insulating region in an exemplary gate-all-around (GAA) nanosheet FET architecture having silicon (Si) channel nanosheets and SiGe sacrificial nanosheets, but implementation of the teachings described herein is not limited to any specific type of FET structure or combination of materials. Rather, embodiments of the present invention may be practiced with any other type of transistor device or materials now known or later developed where it is desirable to improve the electrical insulation of source / drain regions and gates from an underlying substrate.

[0011] For the sake of brevity, conventional techniques related to the fabrication of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Furthermore, the various tasks and process steps described herein may be incorporated into more comprehensive procedures or processes that include additional steps or functionality not described in detail herein. In particular, since various steps in the manufacturing of semiconductor devices and semiconductor-based ICs are well known, many conventional steps are only briefly mentioned herein or omitted entirely without providing details of well-known processes for the sake of brevity.

[0012] Turning next to a more specific description of the technology related to the present invention, transistors are semiconductor devices commonly found in a wide variety of ICs. Transistors are essentially switches. When a voltage higher than the threshold voltage is applied to the gate of the transistor, the switch turns on and current flows through the transistor. When the voltage at the gate is lower than the threshold voltage, the switch is off and no current flows through the transistor.

[0013] A typical semiconductor device is formed using an active region of a wafer. The active region is defined by insulating regions that are used to separate adjacent semiconductor devices and provide electrical isolation therebetween. For example, in an integrated circuit (IC) comprising a plurality of metal oxide semiconductor field effect transistors (MOSFETs), each MOSFET has a source and a drain formed in an active region of a semiconductor layer by implanting n-type or p-type impurities into the layer of semiconductor material. A channel (or body) region is disposed between the source and the drain. A gate electrode is disposed above the body region. The gate electrode and the body are separated by a gate dielectric layer.

[0014] MOSFET-based ICs are fabricated using so-called complementary metal oxide semiconductor (CMOS) fabrication technology. In general, CMOS is a technology that uses complementary and symmetrical pairs of p-type and n-type MOSFETs to implement logic functions. The channel region connects the source and the drain, and current flows from the source to the drain through the channel region. The current is induced in the channel region by a voltage applied to the gate electrode.

[0015] The wafer footprint of an FET is related to the electrical conductivity of the channel material. If the channel is under better electrostatic control, the FET can be fabricated with a correspondingly smaller wafer footprint. A known method to improve channel electrostatic control and reduce FET size is to form the channel using gate-all-around techniques. For example, FinFETs or nanosheet devices form a gate that surrounds the channel to improve gate control. Also to reduce the device footprint, so-called multilayer field-effect transistors (FETs) are a next-generation device structure that offers scaling gains beyond previous nanosheet and fin-type transistor architectures. Multilayer FETs include a first device defining a first type of transistor (e.g., n-type NS FET) stacked vertically on top of a second device defining a different type of NS transistor (e.g., p-type NS FET). In this way, the two transistors can share the same device footprint, requiring only the space of a single transistor so that the device density is doubled.

[0016] Conventional multilayer FETs achieve the goal of reducing the device footprint, but they exhibit problems with reduced application flexibility. For example, the two multilayer transistors in a conventional multilayer FET are controlled using the same gate. Therefore, the multilayer transistors are said to be complementary to each other. Consequently, conventional multilayer FETs are often referred to as complementary field-effect transistors (CFETs).

[0017] Conventional CFETs can efficiently support CMOS logic circuits due to their inherent reduction in device footprint, along with their complementary and symmetric transistor relationships; however, their shared gates limit the applications for which the device can be used. For example, artificial intelligence (AI) applications utilize AI hardware accelerators that use local register files (LRFs). These register files typically contain an unbalanced number of different types of semiconductor devices (e.g., a greater number of NFET pairs compared to the total number of CMOS FETs) to implement high-speed static RAM with dedicated read and write ports. Thus, the complementary and symmetric architectural characteristics of conventional CFETs (e.g., always including stacked arrangements of NFETs and PFETs) can result in inefficiencies in terms of the overall IC footprint. Furthermore, transistors with independently controlled gates are required to select separate ports in the register file. As a result, CFETs with shared gates are generally impractical for use in many AI applications.

[0018] Next, moving to an overview of aspects of the present invention, one or more embodiments of the present invention solve the above-mentioned drawbacks of known multilayer FET architectures and fabrication techniques by providing a hybrid multilayer semiconductor device comprising different types of multilayer FETs. However, unlike conventional CFETs, the hybrid multilayer semiconductor devices described herein can have independently controlled gates for each multilayer FET or shared gates (i.e., commonly controlled gates) shared by the multilayer FETs in different types of multilayer transistors.

[0019] Referring to Figure 1, for example, an unlimiting embodiment of the present invention provides a hybrid multilayer semiconductor device 10 comprising a pair of stacked NFETs having independently controlled gates. According to another unlimiting embodiment of the present invention, a hybrid multilayer semiconductor device 20 may comprise a pair of stacked PFETs having independently controlled gates. According to yet another unlimiting embodiment of the present invention, a hybrid multilayer semiconductor device 30 may comprise a pair of stacked NFETs having a shared gate. According to yet another unlimiting embodiment of the present invention, a hybrid multilayer semiconductor device 40 may comprise a pair of stacked PFETs having a shared gate. According to yet another unlimiting embodiment of the present invention, a hybrid multilayer semiconductor device 50 may comprise a stacked CMOS FET (e.g., an NFET stacked on top of a PFET, and vice versa) having independently controlled gates. According to yet another unlimiting embodiment of the present invention, a hybrid multilayer semiconductor device 60 may comprise a stacked CMOS FET (e.g., an NFET stacked on top of a PFET, and vice versa) having a shared gate. Accordingly, various non-limiting embodiments of the hybrid stacked semiconductor devices described herein can be used in a wide range of applications, such as AI applications, while satisfying the ongoing trend of reducing the footprint of semiconductor devices.

[0020] According to non-limiting embodiments of the present invention, the steps described herein for fabricating a hybrid multilayer semiconductor device include forming dielectric insulators between stacked channels to form either independent gate regions or shared gate regions. Accordingly, gate extensions can be formed in independent gate regions to facilitate the formation of independently controlled gates, or in a shared gate region to facilitate the formation of a shared gate.

[0021] Next, moving on to a more detailed description of the fabrication process and the resulting structure according to aspects of the present invention, Figures 2 to 19 show the hybrid stacked semiconductor device 100 after various fabrication processes have been performed. The cross-sectional views shown in Figures 2 to 19 are two-dimensional, but the figures shown in Figures 2 to 19 are understood to represent a three-dimensional structure. The top-down reference diagram 101 shown in Figure 2 provides a reference point for the various cross-sectional views (X view, Y1A view, and Y1B view) shown in Figures 2 to 19. The X view along the line X is a side view across the gate region 103 (i.e., the region where the gate is formed), the Y1A view along the line Y1A is a side view across the active region 105 between the gates (also referred to as the "S / D region," where one or more source / drains are formed), and the Y1B view along the line Y1B is a side view across the active region 107 below the gates (also referred to as the "channel region," located below the gates, where one or more types of NS stacks are formed).

[0022] Referring to Figure 2, a hybrid multilayer semiconductor device 100 is shown after performing various known intermediate fabrication steps according to embodiments of the present invention. At this stage, the hybrid multilayer semiconductor device 100 includes a nanosheet stack (NS stack) 102 formed on a substrate 104. The substrate 104 may consist of any suitable substrate material, such as single crystal Si, silicon germanium (SiGe), III-V compound semiconductor, II-VI compound semiconductor, or semiconductor-on-insulator (SOI). For example, III-V compound semiconductors include materials having at least one group III element and at least one group V element, such as aluminum gallium arsenide (AlGaAs), aluminum gallium nitride (AlGaN), aluminum arsenide (AlAs), aluminum indium arsenide (AlInAs), aluminum nitride (AlN), gallium antimonide (GaSb), aluminum gallium antimonide (GaAlSb), gallium arsenide (GaAs), gallium antimonide (GaAsSb), gallium nitride (GaN), indium antimonide (InSb), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium phosphide arsenide (InGaAsP), indium gallium nitride (InGaN), indium nitride (InN), indium phosphide (InP), and one or more alloy combinations containing at least one of the above materials. Alloy combinations may include binary (two elements, e.g., gallium(III) arsenide (GaAs)), ternary (three elements, e.g., InGaAs) and quaternary (four elements, e.g., aluminum-gallium-indium phosphide (AlInGaP)) alloys.

[0023] In some embodiments of the present invention, the substrate 104 may include a buried oxide layer 106 to provide a silicon-on-insulator (SOI) configuration. The buried oxide layer 106 may consist of any suitable dielectric material, such as silicon oxide. In some embodiments of the present invention, the buried oxide layer 106 is formed to a thickness of about 145 nm, but other thicknesses are within the scope of the present invention.

[0024] In some embodiments of the present invention, the NS stack 102 may include one or more semiconductor layers 108 alternating with one or more sacrificial layers 110. In some embodiments of the present invention, the semiconductor layers 108 and the sacrificial layers 110 are epitaxially grown layers. In some embodiments of the present invention, the upper stack portion 113 (also referred herein as the upper NS stack 113) of the NS stack 102 is separated from the lower stack portion 115 (also referred herein as the lower NS stack 115) of the NS stack 102 by a sacrificial spacer layer 112. The upper portion 113 and the lower portion 115 of the NS stack 102 may define their respective channel types. For example, in some embodiments of the present invention, the semiconductor layers 108 in the upper portion 113 of the NS stack 102 define a first stack of channels (e.g., n-type channels) in the final device, while the semiconductor layers 108 in the lower portion 115 of the NS stack 102 define a second stack of the same type of channel (e.g., n-type channels) in the final device. In another embodiment of the present invention, the semiconductor layer 108 in the upper portion 113 of the NS stack 102 defines a first type of stacked channel (e.g., a p-type channel stack) in the final device, while the semiconductor layer 108 in the lower portion 115 of the NS stack 102 defines a second type of stacked channel (e.g., a p-type channel) in the final device.

[0025] For simplicity, we will refer to the process performed on an NS stack 102 having 4 nanosheets (e.g., 4 semiconductor layers 108 shown in Figure 2) alternating with 6 sacrificial layers 110. However, it is understood that the NS stack 102 may include any number of nanosheets alternating with a corresponding number of sacrificial layers. For example, the NS stack 102 may include 2 nanosheets, 5 nanosheets, 8 nanosheets, or any number of nanosheets, along with a corresponding number of sacrificial layers (i.e., as appropriate to form a nanosheet stack having a bottom sacrificial layer below the bottom nanosheet and sacrificial layers between each pair of adjacent nanosheets). Furthermore, although the NS stack 102 is illustrated to have the same number of channels (semiconductor layers 108) above and below the sacrificial spacer layer 112, the shown configuration is not required. In some embodiments of the present invention, the upper portion 113 of the NS stack 102 may have more or fewer channels (e.g., semiconductor layers 108) than the lower portion 115 of the NS stack 102.

[0026] The semiconductor layer 108 may consist of any suitable material, such as single-crystal silicon or silicon-germanium. In some embodiments of the present invention, the semiconductor layer 108 is a silicon nanosheet. In some embodiments of the present invention, the semiconductor layer 108 has a thickness of about 4 nm to about 10 nm, for example, 6 nm, but other thicknesses are within the range assumed by the present invention. In some embodiments of the present invention, the substrate 104 and the semiconductor layer 108 may consist of the same semiconductor material. In other embodiments of the present invention, the substrate 104 may consist of a first semiconductor material and the semiconductor layer 108 may consist of a second semiconductor material.

[0027] The sacrificial layer 110 may be a silicon or silicon-germanium layer, depending on the material of the semiconductor layer 108, in order to satisfy the etching selectivity requirement. For example, in embodiments of the present invention where the semiconductor layer 108 is a silicon nanosheet, the sacrificial layer 110 may be a silicon-germanium layer. In embodiments of the present invention where the semiconductor layer 108 is a silicon-germanium nanosheet, the sacrificial layer 110 may be a silicon-germanium layer having a higher germanium concentration than the germanium concentration in the semiconductor layer 108. For example, if the semiconductor layer 108 is silicon-germanium (sometimes referred to as SiGe5) with a germanium concentration of 5 percent, the sacrificial layer 110 may be a silicon-germanium layer (SiGe25) with a germanium concentration of about 25 percent, but other germanium concentrations are within the scope of the present invention. In some embodiments of the present invention, the sacrificial layer 110 has a thickness of about 8 nm to about 15 nm, for example 10 nm, but other thicknesses are within the scope of the present invention.

[0028] The sacrificial spacer layer 112 may consist of a silicon-germanium layer having a germanium concentration selected to provide etching selectivity for both the semiconductor layer 108 and the sacrificial layer 110. For example, in embodiments of the present invention where the semiconductor layer 108 is a SiGe 5 nanosheet and the sacrificial layer 110 is a SiGe 25 layer, the sacrificial spacer layer 112 may be SiGe 60, but other germanium concentrations are within the scope of the present invention. As shown with respect to Figure 9, the sacrificial spacer layer 112 is replaced by a dielectric spacer 126 that separates the upper portion 113 of the NS stack 102 from the lower portion 115 of the NS stack 102. As a result, the thickness of the sacrificial spacer layer 112 defines the final dielectric separation between the upper portion 113 and the lower portion 115 of the NS stack 102. In some embodiments of the present invention, the sacrificial spacer layer 112 may have a thickness of about 5 nm to about 35 nm, for example, 15 nm, but other thicknesses are within the scope of the present invention.

[0029] Continuing to refer to Figure 2, a hard mask 114 is formed on the NS stack 102. The portion of the NS stack 102 on which the hard mask 114 is formed is referred to as the active regions (105 and 107). In some embodiments of the present invention, the hard mask 114 may consist of any suitable material, such as silicon nitride. The hard mask is used to define the dimensions of the active regions 105 and 107. For example, the hard mask 114 may be patterned to achieve a target length and width. A wet or dry etching process may then be performed to selectively remove portions of the NS stack not covered by the patterned hard mask. Accordingly, the portions of the NS stack 102 that remain beneath the hard mask define the active regions 105 and 107. In some embodiments of the present invention, the hard mask 114 is further used to protect the active regions 105 and 107 from various subsequent fabrication processes performed to obtain the finished hybrid multilayer semiconductor device 100, for example, shown in Figures 14 and 19.

[0030] Referring further to Figure 2, the hybrid multilayer semiconductor device 100 after the deposition of the gate extension layer 116 is shown. The gate extension layer 116 is conformally deposited along the surface of the substrate 104 (e.g., the upper surface of the oxide layer 106) together with the sidewalls of the NS stack 102. Accordingly, the gate extension layer 116 is formed in both the S / D region 105 (as shown in Figure Y1A) and the channel region 107 (as shown in Figure Y1B).

[0031] The gate extension layer 116 can be deposited, for example, using a chemical vapor deposition (CVD) process, and may have a thickness in the range of approximately 8 nm to approximately 20 nm. In one or more embodiments of the present invention, the gate extension layer 116 is made of the same material as the sacrificial layer 110. For example, if the sacrificial layer 110 is a SiGe25 layer, then the gate extension layer 116 is also a SiGe25 layer.

[0032] Referring next to Figure 3, the hybrid multilayer semiconductor device 100 is shown after the gate extension layer 116 has been recessed and patterned. According to one embodiment of the present invention, the gate extension layer 116 located in the active regions 105 and 107 may first be recessed up to the interface between the sacrificial spacer layer 112 and the lower NS stack 115 or just above the interface between the sacrificial spacer layer 112 and the lower NS stack 115. A directional RIE process that attacks the material of the gate extension layer 116 without substantially reacting with the rest of the hybrid multilayer semiconductor device 100 may be performed to recess the gate extension layer 116. The lower horizontal portion of the gate extension layer above the dielectric layer 106 may be protected by a soft mask such as a recessed OPL (organic layer).

[0033] The recessed gate extension layers 116 located in active regions 105 and 107 can then be patterned by depositing a soft mask layer formed from OPL material (not shown) covering the recessed gate extension layers 116, and removing a portion of the soft mask layer formed in contact with one side of the lower NS stack 115 while retaining a portion of the soft mask layer formed on the opposite side of the NS stack 115. Accordingly, a first portion of the recessed gate extension layer 116 (e.g., the left portion of the recessed gate extension layer 116) is exposed, while a second portion of the recessed gate extension layer 117 (e.g., the right portion of the recessed gate extension layer 117) remains covered by the remaining soft mask.

[0034] Subsequently, another directional RIE process may be performed to remove the exposed portion of the gate extension layer 116, which attacks the material of the gate extension layer 116 without substantially reacting with the remaining material of the hybrid stacked semiconductor device 100. Then, the soft mask layer may be removed to expose the remaining portion of the gate extension layer 117 formed on one side of the lower NS stack 115, as shown in Figure 3.

[0035] Next, the remaining portion of the gate extension layer 117 is simply referred to as the first gate extension 117 (i.e., the lower gate extension 117). As shown in Figure 3, the lower gate extension 117 is present in the active regions 105 (as shown in Figure Y1A) and 107 (as shown in Figure Y1B). The lower gate extension 117 includes a base portion 119 and a side portion 121. The base portion 119 is formed on the substrate 104 (e.g., the upper surface of the oxide layer 106) and extends in a first direction from the side wall of the lower NS stack 115. The side portion 121 extends upward from the base portion 119 and runs along the side of the lower NS stack 115. In the above example, the lower gate extension 117 is formed on the right side of the lower NS stack 115, but it should be understood that the lower gate extension 117 may also be formed on the left side of the lower NS stack 115 without departing from the scope of the present invention.

[0036] Referring to Figure 4, a hybrid multilayer semiconductor device 100 is shown after a first interlayer dielectric (ILD) 118 has been deposited on a wafer. The first ILD 118 can be formed from a variety of dielectric materials, including, but not limited to, silicon dioxide (SiO2), SiN, SiOC, SiCN, SiC, or a combination of several layers. The first ILD 118 can then be recessed to the interface between the sacrificial spacer layer 112 and the lower NS stack 115, or just above the interface between the sacrificial spacer layer 112 and the lower NS stack 115. A RIE or wet etching process that attacks the material of the first ILD 118 without substantially reacting with the rest of the hybrid multilayer semiconductor device 100 may be performed to recess the first ILD 118. Accordingly, the portion of the lower gate extension 117 located in the active regions 105 and 107 remains covered by the recessed ILD 118.

[0037] Moving to Figure 5, the hybrid multilayer semiconductor device 100 is shown after a second gate extension 120 (e.g., an upper gate extension 120) has been formed on the active regions 105 and 107. The upper gate extension 120 is formed using a technique similar to that used to form the lower gate extension 117. Therefore, for simplicity's sake, details regarding the formation of the upper gate extension 120 are not repeated. As shown in Figure 5, the upper gate extension 120 is formed adjacent to the upper NS stack 113, but on the side opposite to the lower gate extension 117. Accordingly, the upper gate extension 120 includes a base portion 123 formed on the upper surface of the ILD 118 and extending from the sidewall of the upper NS stack 113 in a second direction opposite to the first direction of the lower base portion 119. The side portion 125 extends upward from the base portion 123 and runs along the side of the upper NS stack 113.

[0038] Referring to Figure 6, the hybrid multilayer semiconductor device 100 is shown after a second ILD 122 is deposited on a first ILD 118. Similar to the first ILD 118, the second ILD 122 may be formed from a dielectric material including, but not limited to, silicon dioxide (SiO2), SiN, SiOC, SiOCN, SiC, or a combination of several layers. In some embodiments of the present invention, an etching process may be performed to reduce the height of the hard mask layer 114 before depositing the ILD 122. As shown in Figure 6, the lower and upper gate extensions 117 and 120 located in the active regions 105 (as shown in Figure Y1A) and 107 (as shown in Figure Y1B) are covered and sealed by the first and second ILDs 118 and 122.

[0039] Moving to Figure 7, the hybrid stacked semiconductor device 100 is shown after removing portions of the first and second ILDs 118 and 122 from the region not covered by the gate mask (as shown in Figure Y1A), while retaining portions of the first and second ILDs 118 and 122 in the channel region 107 protected by the gate mask (not shown) (as shown in Figure Y1B). Accordingly, portions of the lower and upper gate extensions 117 and 120 located in the S / D region 105 (as shown in Figure Y1A) are exposed, while portions of the lower and upper gate extensions 117 and 120 located in the channel region 107 (as shown in Figure Y1B) remain covered.

[0040] After removing the portions of the first and second ILDs 118 and 122 from the S / D region 105 (as shown in Figure Y1A), a directional RIE process may be performed to remove the portions of the lower and upper gate extensions 117 and 120 from the S / D region 105 (as shown in Figure Y1A), attacking the material of the lower and upper gate extensions 117 and 120 without substantially reacting with the remaining material of the hybrid stacked semiconductor device 100 (including the first and second ILDs 118 and 122).

[0041] The ILD 122 maintained in the channel region 107 (as shown in Figure Y1B) protects the lower and upper gate extensions 117 and 120 when etching them from the S / D region 105 (as shown in Figure Y1A). Accordingly, the lower and upper gate extensions 117 and 120 maintained in the channel region 107 (as shown in Figure Y1B) facilitate the formation of independently controlled gates corresponding to the lower NS stack 115 and the upper NS stack 113, respectively.

[0042] For example, the base portion 119 of the lower gate extension 117 extends laterally from the sidewall of the lower NS stack 115 in a first direction, while the base portion 123 of the upper gate extension 120 extends laterally from the sidewall of the upper NS stack 113 in a second direction opposite to the first direction of the lower base portion 119. The lower base portion 119 provides a first contact area for a first gate contact that can be used to control the lower NS stack 115, while the upper base portion 123 provides a second contact area for a second gate contact that can be used to control the upper NS stack 113. The opposing orientations of the lower and upper base portions 119 and 123 allow for the formation of a first gate contact that is isolated (i.e., electrically isolated) from the second gate contact. In this way, a hybrid multilayer semiconductor device 100 including a multilayer FET having independently controlled gates can be fabricated by embodiments of the present invention described herein.

[0043] Next, moving to Figure 8, the hybrid multilayer semiconductor device 100 is shown after the removal of the sacrificial spacer layer 112. In one or more embodiments of the present invention, an etching process utilizing an etchant chemical action that attacks the material of the sacrificial spacer layer 112 without substantially reacting with the remaining material of the hybrid multilayer semiconductor device 100 may be applied to the sacrificial spacer layer 112 exposed to openings formed when the first and second ILDs 118 and 122 are removed. For example, SiGe 60 can be selectively removed from silicon and SiGe 25 using gas-phase HCl etching. Accordingly, a spacer gap 124 is formed between the upper NS stack 113 and the lower NS stack 115.

[0044] Next, referring to Figure 9, the hybrid multilayer semiconductor device 100 is shown after the spacer gap 124 has been filled with dielectric material 126. In one or more embodiments of the present invention, the dielectric material 126 forms a dielectric spacer 126 that separates (i.e., electrically insulates) the rest of the upper NS stack 113 from the rest of the lower NS stack 115.

[0045] Continuing to refer to Figure 9, a sidewall spacer 128 (sometimes referred to as a gate spacer) is formed on the sidewall of the gate (which is a pillar defined by the remaining ILDs 122 and 118). In some embodiments of the present invention, the sidewall spacer 128 and dielectric material 126 are formed using chemical vapor deposition (CVD), plasma CVD (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermochemical vapor deposition (RTCVD), metal-organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), rate-limiting reaction-treated CVD (LRPCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), chemical solution deposition, molecular beam epitaxy (MBE), or other similar processes in combination with a wet or dry etching process. For example, the spacer material may be conformally deposited and selectively removed using RIE to form the sidewall spacer 128.

[0046] In some embodiments of the present invention, the dielectric spacer 126 is formed simultaneously with the sidewall spacer 128 when the spacer material is deposited. In other words, the spacer material 128 deposited on the sidewall of the gate can also fill the spacer gap 124.

[0047] The sidewall spacer 128 may consist of any suitable material, such as a low dielectric constant dielectric, nitride, silicon nitride, silicon oxide, SiON, SiC, SiOCn, or SiBCN. In some embodiments of the present invention, the sidewall spacer 128 contains silicon nitride. The sidewall spacer 128 may be formed to a thickness of about 5 to 40 nm, but other thicknesses are within the scope of the present invention.

[0048] Continuing to refer to Figure 9, a portion of the NS stack 102 located in the S / D region 105 (as shown in Figure Y1A) is removed from the active region void 109, exposing the channel region 107 and the surface of the embedded oxide layer 106 (or the substrate 104 if the embedded oxide layer 106 is absent) (this is sometimes referred to as a stack recess). The NS stack 102 can be recessed using, for example, wet etching, dry etching, or a combination of wet and / or dry etching. In some embodiments of the present invention, the NS stack 102 is recessed using a RIE process. In some embodiments of the present invention, the NS stack 102 is selectively recessed relative to the sidewall spacer 128 and ILD 122.

[0049] Next, referring to Figure 10, the hybrid multilayer semiconductor device 100 is shown after a portion of the sacrificial layer 110 has been recessed to form a cavity (not shown) in the NS stack 102. The cavity is then filled with dielectric material to form an inner spacer 130. In some embodiments of the present invention, portions of the inner spacer 130 that extend beyond the sidewalls of the NS stack 102 are removed, for example, using an isotropic etching process. In this way, the sidewalls of the inner spacer 130 become coplane (i.e., "flush") with the sidewalls of the semiconductor layer 108.

[0050] In some embodiments of the present invention, the inner spacer 130 is formed using CVD, PECVD, ALD, PVD, chemical solution deposition, or other similar processes in combination with a wet or dry etching process. The inner spacer 130 may consist of any suitable material such as low dielectric constant dielectrics, nitrides, silicon nitride, silicon dioxide, SiON, SiC, SiOCn, or SiBCN.

[0051] Moving to Figure 11, the hybrid multilayer semiconductor device 100 is shown after forming a first source / drain 132 (e.g., lower S / D132) that contacts the lower NS stack 115 and a second S / D134 (e.g., upper S / D134) that contacts the upper NS stack 113. In some embodiments of the present invention, the lower S / D132 is made of the same semiconductor type material as the upper S / D134. For example, the lower S / D132 and upper S / D134 are made of n-type semiconductor material. In this way, a hybrid multilayer semiconductor device 100 including a pair of stacked NFETs can be fabricated as described herein.

[0052] In some embodiments of the present invention, both the lower S / D132 and the upper S / D134 may be formed from a p-type semiconductor material. In this way, a hybrid multilayer semiconductor device 100 comprising a pair of multilayer PFETs can be fabricated as described herein.

[0053] In some embodiments of the present invention, the lower S / D132 may be formed from a first type semiconductor material, while the upper S / D134 may be formed from a second type semiconductor material different from the first semiconductor material of the lower S / D132. For example, the lower S / D132 may be formed from an n-type semiconductor material, while the upper S / D134 may be formed from a p-type semiconductor material, or vice versa. In this way, a hybrid multilayer semiconductor device 100 including a multilayer CMOS FET can be fabricated as described herein.

[0054] Continuing to refer to Figure 11, the lower S / D132 and upper S / D134 can be epitaxially grown from the exposed sidewalls of the lower NS stack 115 and upper NS stack 113, respectively, using, for example, gas-phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid-phase epitaxy (LPE), or other suitable processes. In some embodiments of the present invention, the gas source for epitaxial deposition of semiconductor material includes a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, a Si layer can be epitaxially deposited (or grown) from a silicon gas source selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane, and combinations thereof. Germanium layers can be epitaxially deposited from a germanium gas source selected from the group consisting of germanine, digermanine, halogermanine, dichlorogermanine, trichlorogermanine, tetrachlorogermanine, and combinations thereof. Silicon-germanium alloy layers can be epitaxially formed using combinations of such gas sources. Carrier gases such as hydrogen, nitrogen, helium, and argon may be used. In some embodiments of the present invention, the epitaxial semiconductor material includes carbon-doped silicon (Si:C). This Si:C layer can be grown in the same chamber used for other epitaxy steps, or in a dedicated Si:C epitaxy chamber. Si:C may contain carbon in the range of about 0.2 percent to about 3.0 percent.

[0055] In some embodiments of the present invention, epitaxially grown silicon and silicon-germanium can be doped by adding an n-type dopant (e.g., P or As) or a p-type dopant (e.g., Ga, B, BF2, or Al). In some embodiments of the present invention, the first S / D132 and the second S / D134 are epitaxially formed and can be doped by various methods, such as in-situ doped epitaxy (doping during deposition), post-epitaxy doping, or by injection and plasma doping. The dopant concentration in the doped region is 1 × 10⁻⁶ 19 cm -3 ~2×10 21 cm -3 , or 1 × 10 20 cm -3 ~1 × 10 21 cm -3 It could be within the range.

[0056] In some embodiments of the present invention, the lower S / D132 and upper S / D134 are made of silicon or silicon-germanium. In some embodiments of the present invention, the lower S / D132 and upper S / D134 are made of silicon-germanium doped with boron to a boron concentration of about 1 to about 15 percent, for example, 2 percent, but other boron concentrations are within the range assumed by the present invention.

[0057] Continuing to refer to Figure 11, an insulating dielectric 136 is formed between the lower S / D 132 and the upper S / D 134. The insulating dielectric 136 may consist of any suitable dielectric material, such as oxides, low dielectric constant dielectrics, nitrides, silicon nitride, silicon oxide, SiON, SiC, SiOCN, and SiBCN. In some embodiments of the present invention, the insulating dielectric 136 is deposited on the substrate 104 (e.g., the upper surface of the oxide layer 106) to cover the lower S / D 132 before forming the upper S / D 134. In some embodiments of the present invention, the insulating dielectric 136 may then be etched and recessed to the height of the uppermost surface of the dielectric spacer 126 or above. The upper S / D 134 may then be formed on the upper surface of the insulating dielectric 136 as described herein. In this way, the insulating dielectric 136 provides dielectric insulation between the lower S / D 132 and the upper S / D 134.

[0058] Next, moving to Figure 12, the hybrid multilayer semiconductor device 100 is shown after the deposition of the third ILD 138. The third ILD 138 can consist of any suitable dielectric material, such as porous silicate, carbon-doped oxide, silicon dioxide, silicon nitride, silicon oxynitride, or other dielectric materials. Any known method for forming the interlayer dielectric 138, such as CVD, PECVD, ALD, fluid CVD, spin-on dielectric, or PVD, can be utilized. In some embodiments of the present invention, the hybrid semiconductor device 100 is planarized and stopped at the top surface of the sidewall spacer 128 and the second ILD 122. The third ILD 138 can be planarized, for example, using a chemical mechanical planarization (CMP) process.

[0059] Continuing to refer to Figure 12, the first gate contact trench 140 and the second gate contact trench 141 are formed on the gate extension layer (as shown in Figure Y1B). In some embodiments of the present invention, the gate contact trenches 140 and 141 may be patterned by etching after lithography to expose the base portion 119 of the lower gate extension 117 and the base portion 123 of the upper gate extension 120. Any known method for etching the patterns of the gate contact trenches 140 and 141 within the second ILD 122, such as wet etching, dry etching, or a combination of sequential wet or dry etching or both, may be used. In some embodiments of the present invention, etching using a chemical etchant that attacks the material of the second ILD 122 without substantially reacting with the remaining material of the hybrid multilayer semiconductor device 100 may be performed to form the gate contact trenches 140 and 141.

[0060] Next, moving to Figure 13, the hybrid multilayer semiconductor device 100 is shown after the sacrificial layer 110 has been removed from the NS stack 102. In one or more embodiments of the present invention, the sacrificial layer 110 can be selectively removed using a wet or dry etching process that uses a chemical etchant that attacks the material of the sacrificial layer 110 without substantially reacting with the remaining material of the hybrid multilayer semiconductor device 100. Accordingly, the nanosheet channels of the upper and lower NS stacks 113 and 115 (e.g., the semiconductor layer 108 in the channel region 107) are "released" and channel voids 142 are formed in the NS stack 102.

[0061] In some embodiments of the present invention, selective removal of the sacrificial layer 110 also includes removing the upper gate extension 117 and the lower gate extension 120 if they are formed from the same material as the sacrificial layer 110. Accordingly, the lower contact extension trench 143 and the upper contact extension trench 145 are formed in the second ILD 122. The lower contact extension trench 143 extends laterally from the first contact trench 140, exposing the sidewall of the lower NS stack 115. Similarly, the upper contact extension trench 145 extends laterally from the second contact trench 141, exposing the sidewall of the upper NS stack 113.

[0062] Referring to Figure 14, a hybrid multilayer semiconductor device 100 is shown after filling the channel void 142 with a high dielectric constant metal gate material to form an all-around gate 144 surrounding a semiconductor layer 108 (e.g., channel 108) contained in the NS stack 102. The gate 144 may be formed according to a known substitution gate (RMG) process, or so-called gate-last process. For example, the gate 144 may be formed by selectively removing the sacrificial layer 110 to free up the semiconductor layer 108 as described above, and then depositing a high dielectric constant metal gate material in the channel void 142.

[0063] In one or more embodiments of the present invention, the high dielectric constant metal gate material may include a layer of high dielectric constant dielectric material and a work function metal (WFM) layer. Examples of high dielectric constant dielectrics include, but are not limited to, metal oxides such as hafnium oxide, hafnium oxide-silicon, hafnium oxynitride-silicon, lanthanum oxide, lanthanum oxide-aluminum, zirconium oxide, zirconium oxide-silicon, zirconium oxynitride-silicon, tantalum oxide, titanium oxide, barium oxide-strontium oxide-titanium, barium oxide-titanium, strontium oxide-titanium, yttrium oxide, aluminum oxide, lead scandium oxide-tantalum, and lead zinc niobate. The high dielectric constant dielectric may further include dopants such as lanthanum and aluminum.

[0064] In some embodiments of the present invention, the high dielectric film may have a thickness of about 0.5 nm to about 4 nm. In some embodiments of the present invention, the high dielectric film contains hafnium oxide and has a thickness of about 1 nm, but other thicknesses are within the range assumed by the present invention.

[0065] In some embodiments of the present invention, the gate 144 includes one or more work function layers (sometimes referred to as work function metal stacks) formed between a high dielectric constant dielectric film and a bulk gate material. In some embodiments of the present invention, the gate 144 includes one or more work function layers but does not include a bulk gate material.

[0066] If present, the work function layer may consist of, for example, aluminum, strontium titanate, strontium oxide, titanium nitride, tantalum nitride, hafnium nitride, tungsten nitride, molybdenum nitride, niobium nitride, titanium-aluminum nitride, tantalum-silicon nitride, titanium-aluminum carbide, tantalum carbide, titanium carbide, and combinations thereof. The work function layer can act to change the work function of gate 144, enabling adjustment of the device threshold voltage. The work function layer may be formed to a thickness of about 0.5 to 6 nm, but other thicknesses are within the scope of the invention. In some embodiments of the invention, each of the work function layers may be formed to a different thickness. In some embodiments of the invention, the work function layer includes a TiN / TiC / TiCAl stack.

[0067] In some embodiments of the present invention, the gate 144 includes a body formed from a bulk conductive gate material deposited on a work function layer or a gate dielectric or both. The bulk gate material may include any suitable conductive material such as metals (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, gold), conductive metallic compound materials (e.g., tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, titanium-aluminum carbide, tungsten silide, tungsten nitride, ruthenium oxide, cobalt silide, nickel silide), conductive carbon, graphene, or any suitable combination of these materials. The conductive gate material may further include dopants incorporated during or after deposition.

[0068] Continuing to refer to Figure 14, the first and second gate contact trenches 140 and 141, along with the lower and upper gate extension trenches 143 and 145, are filled with an electrically conductive material to form the first gate contact 146 and the corresponding lower gate extension 147, and the second gate contact 148 and the corresponding upper gate extension 149. The electrically conductive material may be the same material used to form the all-around gate 144. In some embodiments of the present invention, the gate contact material overfills the gate contact trenches 140 and 141, which forms an overburden that can be removed, for example, by a CMP process.

[0069] As shown in Figure 14, the lower gate extension 147 includes a base portion 151 and a side portion 153. The base portion 151 is formed on the substrate 104 (e.g., the upper surface of the oxide layer 106) and extends in a first direction from the side wall of the lower NS stack 115. The side portion 153 extends upward from the base portion 151 and, by running along the side of the lower NS stack 115, establishes contact with the portion of the gate 144 located in the lower NS stack 115. The upper gate extension 149 includes a base portion 155 that extends from the side wall of the upper NS stack 113 in a second direction opposite to the first direction of the lower base portion 151. The side portion 157 extends upward from the base portion 155 and, by running along the side of the upper NS stack 113, establishes contact with the portion of the gate 144 contained in the upper NS stack 113.

[0070] As described herein, the opposing orientation of the lower and upper base portions 151 and 155 of the lower and upper gate extensions 147 and 149, respectively, facilitates the separation and isolation of the first gate contact 146 from the second gate contact 148. For example, the first gate contact 146 extends through the ILD 122 and contacts the base portion 151. Accordingly, the lower gate extension 147 can be used to establish conductivity between the first gate contact 146 and the gate 144, and thus control the lower NS stack 115. Similarly, the second gate contact 148 extends through the ILD 122 and contacts the upper base portion 155. Accordingly, the upper gate extension can be used to establish conductivity between the second gate contact 148 and the gate 144, and thus control the upper NS stack 113 independently of the lower NS stack 115.

[0071] Referring further to Figure 14, the first and second S / D contacts 152 and 154 are formed to establish conductivity to the first and second S / Ds 132 and 134. The first and second S / D contacts 152 and 154 can be formed by performing known patterning and etching techniques. For example, an S / D gate contact trench (not shown) can be patterned by etching to expose the upper surfaces of the first and second S / Ds 132 and 134 after lithography. Any known method for etching the pattern of the trenches for the S / D contacts 152 and 154 within the ILDs 138 and 136, such as wet etching, dry etching, or a combination of sequential wet or dry etching or both, can be used. In some embodiments of the present invention, a RIE process that attacks the material of the ILDs 136 and 138 without substantially reacting with the remaining material of the hybrid multilayer semiconductor device 100 can be performed to form the S / D contact trenches. The S / D contact trenches can then be filled with a conductive material such as copper (Cu) or tungsten (W), Co, or Ru to establish contact with the first S / D 132 and the second S / D 134. Prior to contact metal filling, a silicide liner such as Ti, Ni, or NiPt is deposited on the S / D epitaxial layer, followed by the deposition of an adhesive metal layer such as TiN. In some embodiments of the present invention, a CMP process may then be performed so that the first and second S / D contacts 152 and 154 are coplane (i.e., flush) with the sidewall spacers 128 and ILD 122.

[0072] As shown in Figure 14, a completed hybrid multilayer semiconductor device 100 is provided. The hybrid multilayer semiconductor device 100 includes an upper NS stack 113 positioned (i.e., stacked) above a lower NS stack 115, the lower NS stack 115 being controllable using a first gate contact 146, and the upper NS stack 113 being controllable using a second gate contact 148 independently of the first gate contact 146. Although the completed hybrid multilayer semiconductor device 100 is shown to include a pair of stacked NFETs having independently controlled gates, it should be understood that the above fabrication process may be used to provide hybrid multilayer semiconductor devices 100 having different transistor stack configurations, including, but not limited to, a pair of stacked PFETs having independently controlled gates or stacked CMOS FETs having independently controlled gates (e.g., NFETs stacked on top of PFETs, and vice versa).

[0073] Next, referring to Figures 15 to 19, a series of fabrication steps for forming a hybrid multilayer semiconductor device including a multilayer FET having a shared gate (i.e., a commonly controlled gate) shared by the multilayer FETs is shown. It should be understood that one or more of the fabrication steps described with reference to Figures 2 to 14 may also be applicable when forming a hybrid multilayer semiconductor device including a multilayer FET having a shared gate. Therefore, these details will not be repeated for the sake of brevity.

[0074] Referring to Figure 15, a hybrid multilayer semiconductor device 100 is shown after performing various known intermediate fabrication steps according to embodiments of the present invention. At this stage of the process flow, the hybrid multilayer semiconductor device 100 is shown after the formation of the first gate extension 117 (i.e., the lower gate extension 117). As shown in Figure 15, the lower gate extension 117 is located in the active regions 105 (as shown in Figure Y1A) and 107 (as shown in Figure Y1B). The lower gate extension 117 includes a base portion 119 and a side portion 121. The base portion 119 is formed on the substrate 104 (e.g., the upper surface of the oxide layer 106) and extends in a first direction from the sidewall of the lower NS stack 115. The side portion 121 extends upward from the base portion 119 and runs along the side of the lower NS stack 115. In the above example, the lower gate extension 117 is formed on the right side of the lower NS stack 115, but it should be understood that the lower gate extension 117 may also be formed on the left side of the lower NS stack 115 without departing from the scope of the present invention.

[0075] Moving to Figure 16, the hybrid multilayer semiconductor device 100 is shown after the formation of the second gate extension 120 (i.e., the upper gate extension 120). Unlike the hybrid multilayer semiconductor device 100 described above with reference to Figures 2 to 14, the upper gate extension 120 shown in Figure 16 is formed on the same side as the lower gate extension 117 of the NS stack 102, rather than on the opposite side of the NS stack 102, and has an orientation that substantially coincides with the orientation of the lower gate extension, rather than the opposite orientation (as shown in, for example, Figure 3). Accordingly, the lower and upper gate extensions 117 and 120 can facilitate the formation of a shared gate (i.e., a commonly controlled gate) shared by the multilayer FETs included in the completed hybrid multilayer semiconductor device 100 (see Figure 19).

[0076] As shown in Figure 16, the upper gate extension 120 is located in the active regions 105 (as shown in Figure Y1A) and 107 (as shown in Figure Y1B). The upper gate extension 120 includes a base portion 123 formed on the upper surface of the ILD 118 and extending from the side wall of the upper NS stack 113 in a first direction, i.e., in the same direction as the lower base portion 119. The side portion 125 extends upward from the upper base portion 123 and runs along the side of the upper NS stack 113. Accordingly, the upper base portion 123 is positioned directly above the lower base portion 119.

[0077] Next, referring to Figure 17, the hybrid multilayer semiconductor device 100 is shown after forming a first source / drain 132 (e.g., lower S / D132) corresponding to the lower NS stack 115 and a second S / D134 (e.g., upper S / D134) corresponding to the upper NS stack 113. The insulating dielectric 136 separates the lower S / D132 from the upper S / D134, providing electrical isolation.

[0078] In this example, the lower NS stack 115 is formed from an n-type semiconductor material, while the upper S / D 134 is formed from a p-type semiconductor material, to facilitate a completed hybrid multilayer semiconductor device 100 (see Figure 19) including a multilayer CMOS having a shared gate contact 170 (e.g., a PFET stacked on top of an NFET). However, it should be understood that other stack configurations may be provided according to the fabrication methods of the present invention described herein. In some embodiments of the present invention, for example, the lower NS stack 115 is formed from a p-type semiconductor material, while the upper S / D 134 is formed from an n-type semiconductor material, to facilitate a completed hybrid multilayer semiconductor device 100 including a multilayer CMOS with a different arrangement having a shared gate contact 170. In some embodiments of the present invention, the lower S / D 132 and upper S / D 134 may be formed from the same material to provide a hybrid multilayer semiconductor device 100 having FETs of the same type that share a gate.

[0079] Moving to Figure 18, the hybrid multilayer semiconductor device 100 is shown after the formation of a shared gate contact trench 180 in the ILD 122. As described herein, the shared gate contact trench 180 can be patterned by etching a pattern through the ILD 122 and the base portion 123 of the upper gate extension 120 until the base portion 119 of the lower gate extension 117 is exposed, after lithography. Any known method for etching the patterns of the gate contact trenches 140 and 141 within the second ILD 122, such as wet etching, dry etching, or a combination of sequential wet or dry etching or both, may be used.

[0080] Referring to Figure 19, the hybrid multilayer semiconductor device 100 is shown after the sacrificial layer 110 has been replaced and the shared gate contact trench 180 has been filled with a high dielectric constant metal gate material to form upper and lower gate extensions 147 and 149 that establish a connection with the shared gate contact 182.

[0081] The lower gate extension 147 includes a base portion 151 and a side portion 153. The base portion 151 is formed on the substrate 104 (e.g., the upper surface of the oxide layer 106) and extends in a first direction from the side of the NS stack 102 corresponding to the lower NS stack 115. The side portion 153 extends upward from the base portion 151 and, by running along the sidewall of the lower NS stack 115, establishes contact with the portion of the metal all-around gate 144 contained in the lower NS stack 115. The upper gate extension 149 includes a base portion 155 that extends in the same first direction as the lower base portion 151 from the same side of the NS stack 102 corresponding to the upper NS stack 113. The side portion 157 extends upward from the base portion 155 and, by running along the side of the upper NS stack 113, establishes contact with the portion of the metal all-around gate 144 contained in the upper NS stack 113.

[0082] The matching orientation of the lower and upper base portions 151 and 155 of the lower and upper gate extensions 147 and 149, respectively, facilitates the formation of a shared gate contact 182 that establishes a shared or common connection between a portion of the gate 144 located in the lower NS stack 115 and a portion of the gate 144 included in the upper NS stack 113. In this way, a hybrid multilayer semiconductor device 100 can be provided that includes a multilayer CMOS FET having a shared gate (e.g., an NFET stacked on top of a PFET, and vice versa), or a hybrid multilayer semiconductor device 40 can be provided that may include a pair of stacked FETs of the same type having a shared gate (e.g., a multilayer NFET or a multilayer PFET).

[0083] As shown in Figure 19, a completed hybrid multilayer semiconductor device 100 is provided after forming first and second S / D contacts 152 and 154 that contact the lower S / D 132 and upper S / D 134, respectively. The hybrid multilayer semiconductor device 100 includes an upper NS stack 113 positioned (i.e., stacked) above a lower NS stack 115, and the lower NS stack 115 and upper NS stack 113 may be controlled using a shared gate contact 170. Although a completed hybrid multilayer semiconductor device 100 including a stacked CMOS (e.g., a PFET stacked on top of an NFET) having a shared gate contact 170 is shown, it should be understood that the above fabrication steps may be used to provide hybrid multilayer semiconductor devices 100 having different transistor stack configurations, including, but not limited to, a pair of stacked NFETs with a shared gate, a pair of stacked PFETs with a shared gate, or an NFET stacked on top of a PFET with a shared gate.

[0084] Next, moving to Figure 20, an IC200 is shown that includes different types of hybrid multilayer semiconductor devices according to one embodiment of the present invention. As described herein, the fabrication steps described herein enable the provision of different types of hybrid multilayer semiconductor devices. For example, returning to Figure 1, several embodiments of the present invention provide a hybrid semiconductor device 10 which may include a pair of stacked NFETs having independently controlled gates. According to another non-limiting embodiment of the present invention, the hybrid multilayer semiconductor device 20 may include a pair of stacked PFETs having independently controlled gates. According to yet another non-limiting embodiment of the present invention, the hybrid multilayer semiconductor device 30 may include a pair of stacked NFETs having a shared gate. According to yet another non-limiting embodiment of the present invention, the hybrid multilayer semiconductor device 40 may include a pair of stacked PFETs having a shared gate. According to yet another non-limiting embodiment of the present invention, the hybrid multilayer semiconductor device 50 may include stacked CMOS FETs having independently controlled gates (e.g., NFETs stacked on top of PFETs, and vice versa). According to yet another non-limiting embodiment of the present invention, the hybrid stacked semiconductor device 60 may include stacked CMOS FETs having a shared gate (e.g., NFETs stacked on top of PFETs, and vice versa).

[0085] As shown in Figure 20, IC200 may include, for example, a local register file (LRF) implemented in an AI hardware accelerator. IC200 includes several hybrid multilayer semiconductor devices having different types of multilayer FETs and gate arrangements. For example, IC200 includes a group of hybrid multilayer semiconductor devices 10, each containing a pair of multilayer NFETs with independently controlled gates, along with a group of hybrid multilayer semiconductor devices 60, each containing multilayer CMOS FETs with shared gates (e.g., NFETs stacked on top of PFETs, and vice versa). Accordingly, hybrid multilayer semiconductor devices according to embodiments of the present invention can be used in a wider range of applications compared to conventional CFEs.

[0086] The methods and resulting structures described herein may be used in the fabrication of IC chips. The resulting IC chips may be distributed by the fabricator in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packaged form. In the latter case, the chips are mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other higher carrier) or in a multi-chip package (such as a ceramic carrier with either or both surface-mounted or embedded-mounted wiring). In either case, the chips are then integrated with other chips, discrete circuit elements, or other signal processing devices or combinations thereof as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product may be any product containing an IC chip, ranging from toys and other low-cost applications to displays, keyboards or other input devices, and advanced computer products with a central processor.

[0087] Various embodiments of the present invention are described herein with reference to the relevant drawings. Alternative embodiments may be devised without departing from the scope of the invention. Various connections and positional relationships between elements (e.g., top, bottom, adjacent, etc.) are described in the detailed description and in the drawings, but those skilled in the art will recognize that many of the positional relationships described herein are independent of orientation, in that the described function is maintained even if the orientation is changed. These connections or positional relationships, or both, may be direct or indirect unless otherwise specified, and the invention is not intended to be limited in this respect. Similarly, the term “joined” and its variations describe having a communication path between two elements and do not imply a direct connection between elements without an intervening element / connection between them. All of these variations are considered part of this specification. Accordingly, the joining of entities may refer to either a direct or indirect joining, and the positional relationships between entities may be direct or indirect positional relationships. As an example of an indirect positional relationship, any reference herein to forming layer "A" on layer "B" includes a situation in which one or more intermediate layers (e.g., layer "C") are located between layer "A" and layer "B," provided that the relevant properties and functions of layers "A" and "B" are not substantially altered by the intermediate layers.

[0088] The following definitions and abbreviations shall be used for interpretation of the claims and specification. As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains,” or “containing,” or any other variant thereof, are intended to encompass non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus comprising an enumeration of elements is not necessarily limited to those elements alone and may include other elements not expressly enumerated or that are inherent to such composition, mixture, process, method, article, or apparatus.

[0089] Furthermore, the term “exemplary” is used herein to mean “acting as an example, illustration, or demonstration.” Any embodiment or design described herein as “exemplary” should not necessarily be construed as being preferable or advantageous to other embodiments or designs. The terms “at least one” and “one or more” are understood to include one or more any integers, i.e., 1, 2, 3, 4, etc. The term “multiple” is understood to include two or more any integers, i.e., 2, 3, 4, 5, etc. The term “connection” may include indirect “connection” and direct “connection.”

[0090] In this specification, references to “one embodiment,” “embodiment,” and “exemplary embodiment” indicate that the embodiments described may include certain features, structures, or characteristics, but each individual embodiment may or may not include those specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Also, if certain features, structures, or characteristics are described in relation to one embodiment, it is assumed that the influence of such features, structures, or characteristics in relation to other embodiments, whether explicitly stated or not, is within the knowledge of those skilled in the art.

[0091] For the purposes of the following explanation, the terms “up,” “down,” “right,” “left,” “vertical,” “horizontal,” “upper side,” “lower side,” and their derivatives shall be in relation to the described structures and methods as they are oriented in the drawings. The terms “overlying,” “atop,” “on top,” “positioned on,” or “positioned atop” mean that a first element, such as a first structure, is located on a second element, such as a second structure, and that an intervening element, such as an interface structure, may be located between the first and second elements. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected at the interface between the two elements without any intervening conductive, insulating, or semiconductor layer.

[0092] Spatially relative terms, such as “down,” “below,” “subordinate,” “up,” and “superior,” may be used herein for the ease of describing the relationship between one element or feature and another, as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or process, in addition to the orientation shown in the figures. For example, if the device in the figure is turned upside down, an element described as “below” or “below” another element or feature will be oriented “up” the other element or feature. Thus, the term “below” may encompass both upward and downward orientations. The device may also be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein may be interpreted accordingly.

[0093] The terms “about,” “substantially,” “approximately,” and their variations are intended to include the degree of error associated with the measurement of a particular quantity based on the equipment available at the time of filing this application. For example, “about” may include a range of ±8%, ±5%, or ±2% of a given value.

[0094] For example, the phrase "selective to" in "a first element selective to a second element" means that the first element can be etched and the second element can act as an etch stop.

[0095] The term "conformal" (e.g., conformal layer) means that the thickness of a layer is substantially the same on all surfaces, or that the variation in thickness is less than 15% of the nominal thickness of the layer.

[0096] As previously stated herein, for the sake of simplicity, prior art relating to the fabrication of semiconductor devices and ICs may or may not be described in detail herein. However, for background purposes, a more general description of semiconductor device fabrication processes that may be used when carrying out one or more embodiments of the present invention is provided below. While specific fabrication steps used when carrying out one or more embodiments of the present invention may be individually known, the described combinations of steps or resulting structures or both of the present invention are unique. Thus, the unique combinations of steps described in relation to the fabrication of semiconductor devices according to the present invention utilize a variety of individual known physical and chemical processes performed on a semiconductor (e.g., silicon) substrate, some of which are described in the paragraphs immediately following.

[0097] Generally, the various processes used to form microchips packaged within ICs are divided into four comprehensive categories: deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process of growing, coating, or otherwise transferring material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). Removal / etching is any process of removing material from a wafer. Examples include etching processes (either wet or dry), chemical mechanical planarization (CMP), etc. For example, reactive ion etching (RIE) is a type of dry etching that uses chemically reactive plasma to remove material, such as a mask pattern on a semiconductor material, by exposing the material to ion bombardment, where the ions remove portions of the material from the exposed surface. Plasma is typically generated by an electromagnetic field under low pressure (vacuum). Semiconductor doping is the modification of electrical properties by doping, for example, the source and drain of a transistor, generally by diffusion, ion implantation, or both. Following these doping processes, furnace annealing or rapid thermal annealing (RTA) is performed. Annealing acts to activate the implanted dopants. Both conductive (e.g., polysilicon, aluminum, copper, etc.) and insulating (e.g., various forms of silicon dioxide, silicon nitride, etc.) films are used to connect and insulate transistors and their components. Selective doping of different areas of a semiconductor substrate allows the conductivity of the substrate to change with the application of voltage. By creating structures of these various components, millions of transistors can be constructed and wired to form the complex circuits of modern microelectronic devices. Semiconductor lithography is the process of forming a three-dimensional relief image or pattern on a semiconductor substrate for later transfer to a substrate. In semiconductor lithography, the pattern is formed by a photosensitive polymer called a photoresist.The complex structure and circuitry that make up a transistor require numerous repetitions of lithography and etching pattern transfer steps to build the many wires connecting millions of transistors. Each pattern printed on the wafer is aligned with a previously formed pattern, gradually building conductors, insulators, and selectively doped areas to form the final device.

[0098] The flowcharts and diagrams in the figures illustrate possible embodiments of a manufacturing method or process method, or both, according to various embodiments of the present invention. Various functions / processes of the method are represented by blocks in the flowcharts. In some alternative embodiments, the functions described within the blocks may occur in a different order than that shown in the figures. For example, two blocks shown consecutively may actually be executed substantially concurrently, or they may sometimes be executed in reverse order depending on the related functions.

[0099] The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to be exhaustive or limit the scope of the embodiments described. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the embodiments described. The terminology used herein has been selected to best describe the principles of the embodiments, practical applications, or technical improvements beyond the art found in the market, or to enable others skilled in the art to understand the embodiments described herein.

Claims

1. A method for fabricating a hybrid stacked semiconductor device, The method involves forming a nanosheet stack on a substrate, wherein the nanosheet stack comprises a first stack portion including a first channel, a second stack portion stacked on the first stack portion and including a second channel, and a dielectric spacer inserted between the first stack portion and the second stack portion. To form an all-around gate including a first gate portion surrounding the first channel and a second gate portion surrounding the second channel, Forming a first gate extension on a first side of the nanosheet stack so as to contact the first gate portion, comprising forming a first sidewall portion that contacts the first gate portion, and forming a first base portion that extends from the first sidewall portion in a first direction so as to define the first gate extension, Forming a second gate extension on a second side of the nanosheet stack so as to contact the second gate portion, comprising forming a second sidewall portion that contacts the second gate portion, and forming a second base portion that extends from the second sidewall portion along a second direction different from the first direction, wherein the second side is different from the first side. To establish conductivity with the first gate portion, a first gate contact is formed that contacts the first base portion, To establish conductivity with the second gate portion, a second gate contact is formed that contacts the second base portion. Methods that include...

2. The method according to claim 1, further comprising forming a first source / drain so as to contact the first stack portion and forming a second source / drain so as to contact the second stack portion.

3. The method according to claim 2, further comprising doping the first source / drain with a first dopant and doping the second source / drain with a second dopant which is the same as the first dopant.

4. The method according to claim 2, further comprising doping the first source / drain with a first dopant and doping the second source / drain with a second dopant different from the first dopant.

5. Forming the first and second gate extensions is The first gate extension layer is formed on a first dielectric material, wherein the first gate extension layer includes a first base portion formed directly on the substrate and a first sidewall portion formed directly in contact with the first stack portion. The method involves forming a second gate extension layer on a second dielectric material, wherein the second gate extension layer includes a second base portion formed on the upper surface of the second dielectric material and a second sidewall portion formed directly in contact with the second stack portion. In order to form the first gate extension, the first gate extension layer is replaced with an electrically conductive material, In order to form the second gate extension, the second gate extension layer is replaced with an electrically conductive material. The method according to claim 1, further comprising:

6. Removing a portion of the first and second gate extensions from the active region of the substrate, In order to expose a portion of the substrate, a portion of the nanosheet stack is removed from the active region, The first source / drain is formed directly on the exposed portion of the substrate, wherein the first source / drain is in contact with the first channel included in the first stack portion of the nanosheet stack, The first source / drain is covered with an insulating dielectric, The process involves forming a second source / drain on the insulating dielectric, wherein the second source / drain contacts the second channel included in the second stack portion of the nanosheet stack. The method according to claim 5, further comprising:

7. A method for fabricating a hybrid stacked semiconductor device, The method involves forming a nanosheet stack on a substrate, wherein the nanosheet stack comprises a first stack portion including a first channel, a second stack portion stacked on the first stack portion and including a second channel, and a dielectric spacer inserted between the first stack portion and the second stack portion. To form an all-around gate including a first gate portion surrounding the first channel and a second gate portion surrounding the second channel, A first gate extension is formed on the first side of the nanosheet stack so as to contact the first gate portion, A second gate extension is formed on the same first side of the nanosheet stack so as to contact the second gate portion, To establish conductivity between the first gate portion and the second gate portion, a gate contact is formed that contacts both the first gate extension and the second gate extension. Methods that include...

8. The method according to claim 7, further comprising forming a first source / drain so as to contact the first stack portion and forming a second source / drain so as to contact the second stack portion.

9. The method according to claim 8, further comprising doping the first source / drain with a first dopant and doping the second source / drain with a second dopant which is the same as the first dopant.

10. Doping the first source / drain with the first dopant, and the second The method according to claim 8, further comprising doping the source / drain with a second dopant different from the first dopant.

11. Forming the first and second gate extensions is A first side wall portion is formed that contacts the first gate portion, and a first base portion is formed that extends from the first side wall portion along a first direction so as to define the extension of the first gate portion. A second side wall portion is formed that contacts the second gate portion, and a second base portion is formed that extends from the second side wall portion along the same first direction as the first base portion. The method according to claim 7, including the method described in claim 7.

12. Forming the first and second gate extensions is The method involves forming a first gate extension layer on a first dielectric material, wherein the first gate extension layer includes a first base portion formed directly on the substrate and a first sidewall portion formed directly in contact with the first side of the nanosheet stack so as to contact the first stack portion. The method involves forming a second gate extension layer on a second dielectric material, wherein the second gate extension layer includes a second base portion formed on the upper surface of the second dielectric material and a second sidewall portion formed directly in contact with the same first side of the nanosheet stack so as to be in contact with the second stack portion. In order to form the first gate extension, the first gate extension layer is replaced with an electrically conductive material, In order to form the second gate extension, the second gate extension layer is replaced with an electrically conductive material. The method according to claim 11, further comprising:

13. Removing a portion of the first and second gate extensions from the active region of the substrate, In order to expose a portion of the substrate, a portion of the nanosheet stack is removed from the active region, The first source / drain is formed directly on the exposed portion of the substrate, wherein the first source / drain is in contact with the first channel included in the first stack portion of the nanosheet stack, The first source / drain is covered with an insulating dielectric, The process involves forming a second source / drain on the insulating dielectric, wherein the second source / drain contacts the second channel included in the second stack portion of the nanosheet stack. The method according to claim 12, further comprising:

14. A hybrid stacked semiconductor device, A nanosheet stack on a substrate comprising: a first stack portion including a first channel; a second stack portion stacked on the first stack portion, the second stack portion including a second channel; and a dielectric spacer inserted between the first stack portion and the second stack portion; An all-around gate including a first gate portion surrounding the first channel and a second gate portion surrounding the second channel, A first gate extension that contacts the first gate portion at the first side of the nanosheet stack, comprising a first base portion extending in a first direction from the side wall of the first stack portion, and a first side portion extending upward from the first base portion and contacting the first gate portion, A second gate extension that contacts the second gate portion at a second side of the nanosheet stack opposite to the first side, the second gate extension includes a second base portion located above the first gate extension and extending from the side wall of the second stack portion in a second direction different from the first direction, and a second side portion extending upward from the second base portion and contacting the second gate portion, A first gate contact that contacts the first base portion to establish conductivity with the first gate portion, and a second gate contact that contacts the second base portion to establish conductivity with the second gate portion. A hybrid stacked semiconductor device equipped with the following features.

15. A hybrid stacked semiconductor device, A nanosheet stack on a substrate comprising: a first stack portion including a first channel; a second stack portion stacked on the first stack portion, the second stack portion including a second channel; and a dielectric spacer inserted between the first stack portion and the second stack portion; An all-around gate including a first gate portion surrounding the first channel and a second gate portion surrounding the second channel, A first gate extension that contacts the first gate portion at the first side of the nanosheet stack, The nanosheet stack has a second gate extension that contacts the second gate portion at the first side, A single gate contact that contacts both the first gate extension to establish conductivity with the first gate portion and the second gate extension to establish conductivity with the second gate portion. A hybrid stacked semiconductor device equipped with the following features.

16. The hybrid stacked semiconductor device according to claim 14 or 15, wherein the first stack portion includes a first channel doped with a first dopant to form a first type of transistor, and the second stack portion includes a second channel doped with a second dopant different from the first type of transistor to form a second type of transistor different from the first type of transistor.

17. The hybrid stacked semiconductor device according to claim 14 or 15, wherein the first stack portion includes a first channel doped with a first dopant to form a first type of transistor, and the second stack portion includes a second channel doped with a second dopant identical to the first dopant to form a second type of transistor which is identical to the first type of transistor.

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