Multilayer work function metal in nanosheet stack using sacrificial oxide material

Abstract

A semiconductor structure is formed using the nanosheet stack on a semiconductor substrate. The semiconductor structure includes multiple layers of work function metal surrounding each channel of the multiple channels in the nanosheet stack and on the semiconductor substrate below the nanosheet stack. Adjacent layers of work function metal in the semiconductor structure are separated by oxide material. The oxide material is a very thin oxide layer having a thickness of a few angstroms or less. The semiconductor structure includes an n-type work function metal on an outer layer of the multiple layers of work function metal. The n-type work function metal can be an aluminum-containing metal covered by a capping material below the gate electrode material.

Description

Technical Field

[0001] The present invention generally relates to the field of semiconductor device fabrication for forming complementary metal oxide semiconductor (CMOS) devices using nanosheet stacks having a plurality of layers of work function metals. More specifically, it relates to forming n-type and p-type field effect transistors having one or more layers of work function metals that provide different threshold voltages. Background Art

[0002] Continuous innovation in semiconductor process technology has enabled higher integration density and device scaling to achieve both increased circuit density and required electrical performance. As the semiconductor industry moves beyond the 10 nanometer (nm) technology node and progresses further, there is a need to scale planar and non-planar semiconductor device structures, such as field effect transistors formed using CMOS device processes, to smaller dimensions. One approach to achieving both increased circuit density and improved electrical performance involves the use of very thin vertically stacked nanosheet layers, which can be patterned and etched to form nanosheet stacks. Nanosheet stacks typically form nanosheet field effect transistor (FET) devices, which are considered a viable option for continued scaling. In general, a nanosheet FET device comprises a device channel having a nanosheet stack composed of one or more nanosheet layers, each nanosheet layer having a vertical thickness substantially smaller than the width of the nanosheet layer. Summary of the Invention

[0003] Embodiments of the present invention disclose a semiconductor structure for a field-effect transistor formed using a nanosheet stack and a multilayer of work function metal surrounding a plurality of channels within the nanosheet stack. Embodiments of the present invention disclose that the plurality of layers of work function metal are on each of the plurality of channels within the nanosheet stack and on a semiconductor substrate beneath the nanosheet stack. In embodiments of the present invention, adjacent layers of work function metal are separated by an oxide material. Embodiments of the present invention include an n-type work function metal on the outer layer of the plurality of work function metal layers. The n-type work function metal is covered by a capping material beneath the gate electrode material.

[0004] Embodiments of the present invention disclose a semiconductor substrate beneath the nanosheet stack, where a first layer of work function metal is located around each of a plurality of channels within the nanosheet stack. A first sacrificial oxide material layer is located on top of the first work function metal. The first sacrificial oxide material has a thickness in the range of a few angstroms or less after the etching process. Embodiments of the present invention include a semiconductor structure having a second work function metal layer on top of the first sacrificial oxide material layer. The second sacrificial oxide material layer is located on top of the second work function metal. The second sacrificial oxide material is a very thin layer of sacrificial oxide material remaining after the etching process. Embodiments of the present invention include a semiconductor structure having a third work function metal layer on top of the second sacrificial oxide material. The third work function metal fills the gaps between the surfaces of the second sacrificial oxide within and beneath the nanosheet stack. Embodiments of the present invention provide a third sacrificial oxide material layer on the exposed surface of the third work function metal. The third oxide layer is very thin, with a thickness in the range of a few angstroms. Embodiments of the present invention disclose a fourth work function metal layer on top of the third sacrificial oxide. Furthermore, embodiments of the present invention provide a fifth work function metal on top of a fourth work function metal. The fifth work function metal is an n-type work function metal. A cap material covers the fifth work function metal, and a gate electrode material is placed on top of the cap material.

[0005] Embodiments of the present invention provide a method for forming a field-effect transistor from a nanosheet stack having multiple layers of work function metal on a semiconductor substrate around each channel of the nanosheet stack and beneath the nanosheet stack. The method includes depositing a first work function metal on multiple channels within each of the multiple nanosheet stacks and on the semiconductor substrate. The method includes depositing a first oxide material on the first work function metal. The method includes depositing a first soft mask on the multiple nanosheet stacks, patterning the first soft mask, and removing the first soft mask from at least one of the multiple nanosheet stacks. The method includes removing the first oxide material and the first work function metal from at least one of the nanosheet stacks. The method includes removing the remaining first soft mask on one or more nanosheet stacks. The method includes removing the upper part of the first oxide material from one or more nanosheet stacks, leaving the lower part of the first oxide material on the first work function metal.

[0006] Furthermore, embodiments of the present invention include depositing a second work function metal on multiple channels of multiple nanosheet stacks on a semiconductor substrate and beneath each of the multiple nanosheet stacks. This method includes depositing a second oxide material on the second work function metal. This method includes depositing and patterning a second soft mask on the multiple nanosheet stacks. This method includes removing the second soft mask from at least two of the multiple nanosheet stacks, and then removing the second oxide material and the second work function metal from at least two of the multiple nanosheet stacks. This method includes removing the second soft mask from nanosheet stacks that are still covered by the remainder of the second soft mask. After removing the remainder of the soft mask, this method includes removing the upper part of the second oxide material from two or more of the multiple nanosheet stacks. The lower part of the second oxide material remains on the work function metal. Embodiments of the present invention include depositing a third work function metal on the remaining lower part of the second oxide material, where the remainder of the second oxide is several angstroms thick. Furthermore, embodiments of the present invention include depositing an n-type work function metal on a third work function metal. The n-type work function metal fills the gaps between adjacent surfaces of the third work function metal. This method includes depositing a metal nitride capping layer on the n-type work function metal and depositing a gate electrode material on the capping layer.

[0007] The above and other aspects, features, and advantages of various embodiments of the present invention will become more apparent from the following description made in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0008] [Figure 1] This diagram shows a cross-sectional view of a semiconductor structure having four nanosheet stacks on a portion of a semiconductor substrate, according to one embodiment of the present invention. [Figure 2] This image shows a cross-sectional view of a semiconductor structure after a layer of work function metal (WFM) has been deposited on the exposed surface of the semiconductor structure, according to one embodiment of the present invention. [Figure 3] This image shows a cross-sectional view of a semiconductor structure after a layer of sacrificial oxide material has been deposited on the exposed surface of the semiconductor structure, according to one embodiment of the present invention. [Figure 4] This shows a cross-sectional view of a semiconductor structure after a layer of soft mask material has been deposited on each semiconductor structure, according to one embodiment of the present invention. [Figure 5] This image shows a cross-sectional view of the semiconductor structure after each of the four nanosheet stacks has been unblocked, according to one embodiment of the present invention. [Figure 6] This image shows a cross-sectional view of the semiconductor structure after removing sacrificial oxides and WFMs from three of the four nanosheet stacks according to one embodiment of the present invention. [Figure 7] This image shows a top view of the semiconductor structure after removing the soft mask from the fourth nanosheet stack, according to one embodiment of the present invention. [Figure 8] This shows a cross-sectional view of the semiconductor structure after the sacrificial oxide top layer has been removed from WFM21 on a fourth nanosheet stack, according to one embodiment of the present invention. [Figure 9] This shows a cross-sectional view of a semiconductor structure after depositing WFMs on the sacrificial oxide of the fourth or rightmost nanosheet stack and on the first three dielectric materials of the nanosheet stack, according to one embodiment of the present invention. [Figure 10] Figure 9 shows a cross-sectional view of the semiconductor structure and another deposited sacrificial oxide material layer according to one embodiment of the present invention. [Figure 11] Figure 10 shows a cross-sectional view of a semiconductor structure after another soft mask has been deposited on each of the semiconductor structures according to one embodiment of the present invention. [Figure 12] This shows a cross-sectional view of a semiconductor structure according to one embodiment of the present invention, after the exposed soft mask, sacrificial oxide, and a portion of the upper WFM have been patterned and removed. [Figure 13] This shows a cross-sectional view of the semiconductor structure after the remaining exposed portion of the soft mask has been removed, according to one embodiment of the present invention. [Figure 14]The image shows a cross-sectional view of the semiconductor structure after removing the exposed sacrificial oxide on the upper WFM of the third and fourth nanosheet stacks according to one embodiment of the present invention. [Figure 15] This shows a cross-sectional view of a semiconductor structure after a third WFM has been deposited on the semiconductor structure, according to one embodiment of the present invention. [Figure 16] This shows a cross-sectional view of a semiconductor structure after another layer of sacrificial oxide has been deposited on a third WFM according to one embodiment of the present invention. [Figure 17] This image shows a cross-sectional view of a semiconductor structure after another soft mask has been deposited according to one embodiment of the present invention, and a portion of the deposited soft mask on the first nanosheet stack has been removed. [Figure 18] This shows a cross-sectional view of the semiconductor structure after removing the sacrificial oxide and the third WFM from the first nanosheet stack according to one embodiment of the present invention. [Figure 19] This shows a cross-sectional view of the semiconductor structure after the soft mask has been removed, according to one embodiment of the present invention. [Figure 20] This shows a cross-sectional view of the semiconductor structure after removing the top layer of sacrificial oxide from the exposed portion of the third WFM on the last three nanosheet stack, according to one embodiment of the present invention. [Figure 21] The image shows a cross-sectional view of the semiconductor structure after depositing another WFM around and beneath each of the first three nanosheet stacks and on the fourth nanosheet stack, according to one embodiment of the present invention. [Figure 22] The image shows a cross-sectional view of the semiconductor structure after depositing n-type WFMs under and around each channel portion of the first three nanosheet stacks and on the fourth nanosheet stack according to one embodiment of the present invention, depositing cap material on the exposed surface of the n-type WFMs of each nanosheet stack, and then depositing gate electrode material on each nanosheet stack and on the semiconductor substrate. [Modes for carrying out the invention]

[0009] Nanosheet (NS) transistors are being pursued as a viable device architecture for scaling CMOS devices with advanced technologies beyond the 10nm node. One challenge in manufacturing NS transistors is the difficulty in removing the soft mask material between channels in the NS stack that forms the NS transistor. After depositing a layer of work function metal, also known as work function metal, on top of the portion of channel material in the NS stack that forms the NS transistor, a layer of soft mask material is deposited on and around the channels of the NS stack. To form an NS transistor with multiple work function metal (WFM) layers, it is necessary to remove the soft mask material between channels in the NS stack. The soft mask material can be patterned, and a portion of the soft mask material can be removed on one or more NS stacks to unblock or expose selected NS stacks. Conventional etching processes for soft mask removal leave a considerable amount of soft mask material between adjacent channels in the NS stack, limiting the number of WFM layers that can be deposited around the channels of the NS stack. Element mapping of the NS stack after soft mask removal identifies a large amount of soft mask between adjacent channels in the NS stack.

[0010] To provide a higher effective work function for an NS transistor, it is desirable to be able to deposit multiple layers of work function metal around the channel in the NS stack. Providing a different number of WFM layers allows for a range of effective work function values ​​and associated threshold voltages for the completed NS transistor. To provide a variety of effective work functions for the NS stack forming an NS transistor, such as a field-effect (FET) device, it is desirable to provide clean, open regions between adjacent channel portions in the NS stack, allowing for the deposition of multiple WFM layers within the NS stack.

[0011] Embodiments of the present invention provide numerous semiconductor structures that can be used in either n-type FETS (NFET) or p-type FET (PFET) formed from a nanosheet stack comprising a plurality of WFM layers each having a thin sacrificial oxide layer on each channel of the nanosheet stack. A method of forming various semiconductor structures for an FET device (i.e., an NS transistor) provides a method of forming an FET device having one or more WFM layers over a channel portion of a nanosheet stack. In this method, a semiconductor structure is provided comprising a thin layer of sacrificial oxide material between each layer of WFM of the nanosheet stack. The method produces semiconductor structures for FET devices that can have one, two, three or more layers of WFM to provide a range of desired effective work functions for various FET devices. Embodiments of the present invention provide both methods of forming an FET device having a desired effective work function and forming a semiconductor structure having a desired number of WFM layers to provide each FET device with the desired effective work function.

[0012] Embodiments of the present invention provide a method of forming an FET device using an NS stack having an interface layer (IL) on each channel of the NS stack on a semiconductor substrate. A layer of high-k dielectric material, such as hafnium oxide, is deposited on the IL over the channel and on the semiconductor substrate. The method includes depositing a WFM such as a metal nitride material over the high-k dielectric material. The sacrificial oxide is conformally deposited on the WFM and pinches off the space between adjacent channels in the NS stack. Sacrificial oxide materials, such as lanthanum oxide, yttrium oxide, or other similar oxide materials, are easier to remove from the gap between adjacent channels than conventionally used soft mask materials. The larger space between adjacent channels in the nanosheet stack provides more space for depositing additional layers of WFM between adjacent channels in the NS stack.

[0013] This method involves depositing a soft mask material onto a sacrificial oxide that is patterned and selectively removed to expose one or more nanosheet stacks. After exposing one or more nanosheet stacks, the sacrificial oxide and WFM metal are removed using one or more isotropic etching processes or wet etching processes. The remaining soft mask is removed from the protected or blocked nanosheet stacks, and the top layer of sacrificial oxide is removed from each of the protected or blocked nanosheet stacks, for example, using a wet etching process. A thin layer of some of the sacrificial oxide material remains on the WFM of the previously blocked nanosheet stacks. Another layer of WFM can be deposited on top of the nanosheet stacks. A second layer of soft mask can be deposited on a semiconductor substrate, and the above process can be repeated to leave a second layer of WFM with a very thin underlayer of the sacrificial oxide layer remaining on the second WFM. These processes can be repeated any number of times, as long as space remains between adjacent channels in the nanosheet stacks. In various embodiments, a third WFM can be deposited on the remainder of a second sacrificial oxide layer, and then layers of n-type WFM, capping metal nitride material, and gate electrode material can be deposited to form an FET device. Known back-end-of-line processes can be used to form the FET contacts and interconnects. Embodiments of the present invention provide a method for fabricating an FET device using a sacrificial oxide material having nanosheet stacks and multiple WFM layers, where increasing the number of WFM layers generates a higher effective work function in the FET device.

[0014] The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of the exemplary embodiments of the invention defined by the claims and their equivalents. The description of various embodiments of the invention is presented for illustrative purposes, and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. Accordingly, those skilled in the art will recognize that various changes and modifications to the embodiments described herein can be made without departing from the scope of the present invention. Some of the illustrated process steps may be combined as an integrated process step. In addition, descriptions of well-known functions and configurations may be omitted for clarity and conciseness.

[0015] The terms and words used in the following description and claims are not limited to bibliographic meanings, and are merely used to enable a clear and consistent understanding of the present invention. Therefore, it will be apparent to those skilled in the art that the following description of exemplary embodiments of the present invention is provided for illustrative purposes only, and not for the purpose of limiting the present invention defined by the appended claims and their equivalents.

[0016] It should be understood that unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" include plural referents. Therefore, for example, a reference to "a component surface" includes a reference to one or more such surfaces, unless the context clearly indicates otherwise.

[0017] For the purposes of the following description, terms such as “up,” “down,” “right,” “left,” “vertical,” “horizontal,” “upper,” “lower,” and their derivatives shall be those of the structures and methods disclosed as shown in the drawings. Terms such as “on top,” “overlapping,” “on top,” “on top,” “located on top,” or “located on top” mean that a first element, such as a first structure, is present on a second element (such as a second structure), and there may be intervening elements, such as an interface structure, between the first and second elements. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected at the interface of the two elements without an intermediate conductive, insulating, or semiconductor layer.

[0018] To avoid ambiguity in the presentation of embodiments of the present invention, some processing steps or operations known in the art may be combined for presentation and explanatory purposes in the following detailed description, and in some cases may not be described in detail. In other examples, some processing steps or operations known in the art may not be described at all. It should be understood that the following description focuses rather on the specific features or elements of various embodiments of the present invention.

[0019] Detailed embodiments of the claimed structures and methods are disclosed herein. The method steps described below do not constitute a complete process flow for manufacturing an integrated circuit on a semiconductor chip. The methods described herein can be used to manufacture integrated circuit chips or semiconductor chips. These embodiments can be implemented in combination with integrated circuit manufacturing techniques for semiconductor chips and devices currently used in the art, and include only the parts of commonly implemented process steps necessary for understanding the embodiments described. These figures represent cross-sectional portions of a semiconductor chip or substrate such as a semiconductor wafer during manufacturing, are not drawn to a fixed scale, and are drawn to illustrate the features of the embodiments described. Details of specific structures and functions disclosed herein should not be construed as limitations, but only as representative grounds for teaching those skilled in the art how to use the methods and structures of this disclosure in various ways. In the description, well-known features and technical details may be omitted to avoid unnecessarily obscuring the embodiments presented.

[0020] References in this specification to “one embodiment,” “another embodiment,” “another embodiment,” and “one embodiment” indicate that the embodiments described may include certain features, structures, or characteristics, but not all embodiments necessarily include certain features, structures, or characteristics. Furthermore, such expressions do not necessarily refer to the same embodiment. Moreover, if certain features, structures, or characteristics are described in relation to an embodiment, it is understood that the influence of such features, structures, or characteristics in relation to other embodiments, whether explicitly stated or not, is within the knowledge of those skilled in the art. In this specification, various elements may be described using terms such as “first,” “second,” etc., but it will be understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. Accordingly, the first element described below may be called the second element without departing from the scope of the concept of the present invention.

[0021] The deposition processes for materials used below, such as metallic materials, work function materials, dielectric materials, and sacrificial materials, include, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or gas cluster ion beam (GCIB) deposition. CVD is a deposition process in which deposition species are formed as a result of chemical reactions between gaseous reactants at temperatures above room temperature (e.g., from about 25°C to about 900°C). The solid products of the reaction are deposited on a surface on which a film, coating, or layer of the solid products is formed. Variations of the CVD process include, but are not limited to, atmospheric pressure CVD (APCVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), and metal-organic CVD (MOCVD), and combinations thereof may also be used. In alternative embodiments using PVD, the sputtering apparatus may include a DC diode system, high-frequency sputtering, magnetron sputtering, or ionized metal plasma sputtering. In alternative embodiments using ALD, chemical precursors react with the material surface one at a time to deposit a thin film on the surface.

[0022] The removal or selective etching of materials as used herein includes, but is not limited to, patterning a soft mask material using, for example, lithography, photolithography, extreme ultraviolet (EUV) lithography processes, or any other known semiconductor patterning processes followed by one or more etching processes. The terms “blocked” or “unblocked” as used herein generally refer to areas of a semiconductor structure or nanosheet stack that are covered or “blocked” by the rest of the patterned and etched soft mask material, or protected from subsequent etching processes, or to areas of semiconductor that are uncovered or “unblocked” and can be etched by an etching process. While various materials are referred to as being removed or “etched” herein, etching generally refers to one or more processes that implement the removal of one or more materials. Examples of etching processes include, but are not limited to, dry etching processes using reactive ion etching (RIE) or ion beam etching (IBE), wet chemical etching processes, or combinations thereof. Dry etching may be performed using plasma.

[0023] Next, refer to the figures. These figures provide schematic cross-sectional views of semiconductor devices at an intermediate stage of manufacturing according to one or more embodiments of the present invention. The schematic diagrams of the devices of the present invention are not intended to be accurate or limited with respect to the scale of the device elements.

[0024] Figure 1 shows a cross-sectional view of a semiconductor structure according to one embodiment of the present invention, having four nanosheet stacks on a portion of a substrate 1. As shown, Figure 1 includes the substrate 1, an insulating layer 2, channels 4, an interface layer (IL) 5 surrounding each of the channels 4, and dielectric 6 on and around the IL 5 and the insulating layer 2, respectively. Each of the nanosheet stacks (NS) 101, 102, 103, and 104 contains three portions of the channel 4 surrounded by the IL 5 and the dielectric 6. Each of the NS 101, 102, 103, and 104 resides on the dielectric 6 on the insulating layer 2 of the substrate 1. Each of the NS 101, 102, 103, and 104 is formed using a known nanosheet stack formation process and is not limited to nanosheet stacks having three channel layers, as shown in Figure 1 as three portions of the channel 4.

[0025] In various embodiments, channel 4 is composed of silicon, but is not limited to this semiconductor material. Channel 4 may be any semiconductor material used as a channel nanosheet layer in a nanosheet stack. Each of the channels 4 may have a thickness in the range of 2 to 20 nanometers, but is not limited to these thicknesses.

[0026] IL5 can be a layer of oxide dielectric material such as SiOx or SiNOx, but is not limited to these materials. The suffix x here can be any number or integer, such as 2 for SiO2. IL5 is covered with a layer of high-k dielectric material or higher-k gate dielectric material, which includes, but is not limited to, HfO2, La2O3, Zr2O3, etc., which can be deposited by PVD, CVD, or ALD. In various embodiments, IL5 is formed by chemical treatment, annealing processes, or deposition processes such as ALD, and IL5 may have a thickness of 0.5 nm to 1.5 nm, but is not limited to these thicknesses.

[0027] The dielectric 6 exists on the IL5 surrounding the adjacent channel 4 in each of NS101, 102, 103, and 104, and on the isolation functional layer 2 on the substrate 1. In some embodiments, the dielectric 6 is composed of a high-k dielectric material (i.e., having a dielectric constant greater than 4). In one embodiment, the dielectric 6 is a dielectric material with a dielectric constant of 4 or less. For example, the dielectric 6 can be composed of one of the following: hafnium oxide (e.g., HfO2), hafnium silicon oxide, hafnium silicon nitride (e.g., HfSiON), lanthanum oxide (e.g., La2O3), tantalum oxide (e.g., TaO), titanium oxide (e.g., TiO), silicon dioxide, etc., but is not limited to these. The dielectric 6 can be deposited by ALD, CVD, or PVD. The typical distance between dielectrics 6 on adjacent channels 4 can be 4 nm to 12 nm, but is not limited to these distances.

[0028] NS101, 102, 103, and 104 are precursors to either an NFET or a PFET device semiconductor structure. In various embodiments, once the NS transistors described later in Figure 22 are completed, a pair of NS transistors having an NFET and a PFET (not shown) cannot share a gate electrode. The two transistors can be formed from any of the resulting FET structures created from NS101, 102, 103, and 104 after processing is complete (for example, as shown in Figure 22). As is known to those skilled in the art, the type of material used for each NS (e.g., n-type or p-type material in the FET junction) determines whether the nanosheet stack forms an NFET or a PFET.

[0029] The substrate 1 may be a semiconductor substrate composed of any known semiconductor substrate material used in CMOS processes. For example, the substrate 1 may be composed of a silicon semiconductor material, another group IV semiconductor material (e.g., Ge), a group III-V semiconductor material (e.g., gallium arsenide), a group II-VI semiconductor material, or any other known semiconductor material used in semiconductor circuits or a compound of any known semiconductor material, where the group is a column or group of elements in the periodic table. In some embodiments, the substrate 1 may include one or more doped regions and undoped regions, or doped regions, undoped regions, stress regions, or defect-prone regions. In some examples, the substrate 1 may include one or more other devices or transistors (not shown). In one embodiment, the substrate 10 is one of a layered semiconductor substrate such as a semiconductor-on-insulator substrate (SOI), a Ge-on-insulator (GeOI), or a silicon-on-replacement insulator (SRI). The dielectric layer 6 is located on the insulating layer 2 on the substrate 1.

[0030] In various embodiments, the substrate 1 is shown as four distinct parts of a semiconductor substrate, with each part of the substrate 1 being under one of NS101, 102, 103, and 104, but the substrate 1 is a single semiconductor substrate having one or more nanosheet stacks. In other examples (not shown), the substrate 1 may have fewer or more nanosheet stacks than NS101, 102, 103, and 104. For example, the substrate 1 may have 20 nanosheet stacks.

[0031] Figure 2 shows a cross-sectional view of a semiconductor structure after a work function metal (WFM) layer 21 has been deposited on the exposed surface of the semiconductor structure according to one embodiment of the present invention. As shown in the figure, Figure 2 includes NS201, 202, 203, and 204, a substrate 1, an insulating layer 2, channels 4, an interface layer (IL) 5 around each channel 4, a dielectric 6, and WFM21. In various embodiments, the WFM21 is composed of a metal nitride material. For example, the WFM21 can be titanium nitride (TiN), but is not limited to this material. The WFM21 can be deposited to a thickness ranging from 0.5 nm to 5 nm by ALD, PVD, or CVD, but is limited to this thickness range. The WFM21 is a first layer of work function metal deposited on each of NS201, 202, 203, and 204, as shown in Figure 2.

[0032] Figure 3 shows a cross-sectional view of a semiconductor structure after a layer of sacrificial oxide 33 has been deposited on the exposed surface of the semiconductor structure according to one embodiment of the present invention. As shown, Figure 3 includes NS301, 302, 303, and 304 having WFM21 covered with sacrificial oxide 33. Each of NS301, 302, 303, and 304 is located on a portion of the substrate 1. The sacrificial oxide 33 can be deposited on the WFM21 by one of PVD, CVD, or ALD. In various embodiments, the sacrificial oxide 33 is one of lanthanum oxide or yttrium oxide, but is not limited to these oxide materials. For example, the sacrificial oxide 33 may be La2O3 or Y2O3. The sacrificial oxide 33 is deposited conformally, filling the regions or spaces between adjacent WFM21 on the channels 4, and the spaces between the WFM21 on the lower part of the channels 4 and the WFM21 on the dielectric 6 on the insulating layer 2 on the substrate 1.

[0033] Figure 4 shows a cross-sectional view of a semiconductor structure after a soft mask layer 42 has been deposited on each semiconductor structure according to one embodiment of the present invention. As shown, Figure 4 includes the elements of Figure 3 and a soft mask 42 that covers the top of the sacrificial oxide 33 and extends thereon. The soft mask 42 can be any soft mask material used for forming FETs using nanosheet stacks. For example, the soft mask 42 can be an organic planarization layer (OPL) deposited on each of the four semiconductor structures. The soft mask 42 can function as a resist.

[0034] Figure 5 shows a cross-sectional view of the semiconductor structure after unblocking NS501, 502, and 503 according to one embodiment of the present invention. As shown, Figure 5 includes unblocked NS501, 502, and 503 and blocked NS504. The soft mask 42 is patterned and removed on the sacrificial oxide 33 on each of NS501, 502, and 503. The soft mask 42 can be patterned and portions of the soft mask 42 removed to selectively remove the soft mask 42 from NS501, 502, and 503. The uncovered portions of the semiconductor structure (e.g., NS501, 502, and 503) are not blocked. The remaining portion of the soft mask 42 remains on NS504 or blocks NS504.

[0035] Figure 6 shows a cross-sectional view of the semiconductor structure after the removal of sacrificial oxides 33 and WFM21 from NS601, 602, and 603 according to one embodiment of the present invention. As shown, Figure 6 includes each of NS604 covered by a soft mask 42 and each of NS601, 602, and 603 without sacrificial oxides 33 and WFM21. As shown, the sacrificial oxides 33 and WFM21 remain under the soft mask 42 in NS604.

[0036] One or more etching processes are used to remove the sacrificial oxide 33, followed by the removal of WFM 21 from NS 601, 602, and 603, such as one or more wet etching processes, or a combination of a dry etching process and one or more wet etching processes. For example, a wet etching process using hydrogen chloride (HCl) removes the sacrificial oxide 33. Using an etching process, the sacrificial oxide 33 is effectively removed from the gaps between adjacent surfaces of the dielectric 6. In some embodiments, depending on the specific composition of these materials, other etching processes can be used to remove WFM 21 or sacrificial oxide 33. The sacrificial oxide 33 can be completely removed between adjacent portions of the channels 4 covered by the dielectric 6 in NS 601, 602, and 603.

[0037] As mentioned above, in conventional nanosheet stacks formed using soft mask material between adjacent surfaces of the material, such as soft mask material between WFM21 on channel 4, it is difficult to remove the soft mask material between the dielectric 6 on the WFM21 and on channel 4. In conventionally formed nanosheet stacks, if soft mask material is present between channels 4 instead of sacrificial oxide 43, the gaps between adjacent channels 4 may not be completely open. If the gaps between adjacent channels 4 are not open in conventional nanosheet stacks, the deposition of additional WFM layers in later process steps is limited.

[0038] Figure 7 shows a top view of the semiconductor structure after the soft mask 42 has been removed from NS704 according to one embodiment of the present invention. As shown, Figure 7 includes NS601, 602, and 603 unchanged from Figure 6, and the unblocked NS704. The soft mask 42 is removed from the sacrificial oxide 33 on NS704.

[0039] Figure 8 shows a cross-sectional view of a semiconductor structure after the upper layer of sacrificial oxide 33 has been removed from a WFM21 on NS804 according to one embodiment of the present invention. After the upper layer of sacrificial oxide 33 is removed, the lower layer of the sacrificial oxide remains. The upper layer of sacrificial oxide 33 can be removed by HCl or DICO2, but is not limited to these etching treatments. The remaining lower layer of sacrificial oxide 33 is shown by a dashed line and is labeled as sacrificial oxide 33 in Figure 8.

[0040] In various embodiments, the sacrificial oxide 33 may be a very thin layer of oxide material containing either La or Y. For example, the sacrificial oxide 33 may be a single layer of sacrificial oxide material. In other cases, the sacrificial oxide 33 may be several atomic layers of sacrificial oxide material. For example, the thickness of the sacrificial oxide 33 may be 2-3 atomic thicknesses, or 2 or 3 atomic layers thickness. In some embodiments, the sacrificial oxide 33 is, for example, a mixture of La and Ti, or Y and Ti, several angstroms thick. In other cases, the sacrificial oxide 33 forms a discontinuous metal oxide layer on the WFM 21. After removing the top of the sacrificial oxide 33, one of the La or Y in the sacrificial oxide 33 remains and is detectable using elemental surface analysis. As illustrated, the sacrificial oxide 33 is also present on the WFM 21 on the dielectric 6 on the substrate 1. The very thin layer of sacrificial oxide 33 leaves most of the space between the WFM 21 on each channel 4 (for example, the sacrificial oxide 33 does not significantly block or reduce the suspension region between the WFM 21 on adjacent channels 4 of NS804).

[0041] As shown in Figure 8, NS804 includes WFM21 on each surface of the dielectric 6 (e.g., on the substrate 1 and surrounding the dielectric 6 on the IL5 on each channel 4), and has a very thin layer of sacrificial oxide 33 on the WFM21 (e.g., a few angstroms for a single layer of sacrificial oxide 33, as described above). NS801, 802, and 803 each include only the elements shown and described above with respect to Figure 1 (e.g., in NS101, NS102, and NS103).

[0042] Figure 9 shows a cross-sectional view of a semiconductor structure after depositing WFM22 on the sacrificial oxide 33 of NS904 and on the dielectric 6 of NS901, 902, and 903 according to one embodiment of the present invention. As shown, Figure 9 shows the elements shown in Figure 8 with the WFM layer 22 deposited on the exposed surface of the semiconductor structure. A thin layer of WFM22 is deposited and covers the exposed surface using one of ALD, PVD, or CVD. For example, the thickness of WFM22 can be in the range between 0.5 nm and 5 nm, but is not limited to these thicknesses. WFM22 can be any metal nitride. For example, WFM22 can be made of TiN. In some embodiments, WFM22 is the same metal nitride material as WFM21. In other embodiments, WFM22 is made of a different material than WFM21. As shown, WFM22 is deposited on the sacrificial oxide 33 of NS904 and is a second WFM on the channel 4 of NS904. WFM22 is located on the dielectric 6 of NS901, 902, and 903, and on the dielectric 6 on each portion of the substrate 1.

[0043] Figure 10 shows a cross-sectional view of the semiconductor structure and sacrificial oxide 43 of Figure 9 according to one embodiment of the present invention. Using one of the known oxide deposition processes, such as ALD, CVD, or PVD, a layer of sacrificial oxide 43 is deposited on NS1001, 1002, 1003, and 1004 and on the upper surface of the WFM22 on each portion of the substrate 1. In various embodiments, the sacrificial oxide 43 is conformally deposited by ALD, filling the gaps on the WFM22 between the adjacent surfaces of the WFM22 on each channel 4 of the four nanosheet stacks shown and the sacrificial oxide 33 on the WFM21 on the dielectric 6 on the insulating layer 2. In various embodiments, the sacrificial oxide 43 is the same or similar oxide material as the sacrificial oxide 33. For example, the sacrificial oxide 43 is an oxide formed of either La or Y. In some cases, the sacrificial oxide 43 is a different oxide material from the sacrificial oxide 43.

[0044] Figure 11 shows a cross-sectional view of a semiconductor structure after a soft mask 52 has been deposited on each of the semiconductor structures in Figure 10, according to one embodiment of the present invention. As shown, Figure 11 includes the elements of Figure 10 and the soft mask 52. The soft mask 52 may be the same or similar soft mask material as the soft mask 42. For example, the soft mask 52 is OPL. The soft mask 52 covers each of the nanosheet stacks (e.g., on NS1101, 1102, 1103, and 1104).

[0045] Figure 12 shows a cross-sectional view of the semiconductor structure after patterning and removing a portion of the soft mask 52 and removing the exposed portions of the sacrificial oxide 43 and WFM 22 according to one embodiment of the present invention. As shown, Figure 12 shows the removal of the soft mask 52 from blocks NS1203 and NS1204, and from NS1201 and NS1202. After the removal of the soft mask 52, the exposed portions of the sacrificial oxide 43 and WFM 22 of NS1201 and NS1202 are removed using, for example, a wet etching process or other processes described with respect to Figure 6. As shown, NS1201 and NS1202 consist of a channel 4, an IL 5, and a dielectric 6 on the dielectric 6 on the insulating layer 2.

[0046] Figure 13 shows a cross-sectional view of the semiconductor structure after the remaining portion of the soft mask 52 has been removed, according to one embodiment of the present invention. As shown, Figure 13 includes the elements of Figure 12 without the soft mask 52. NS1301, 1302, 1303, and 1304 are unblocked or exposed, respectively. NS1303 and NS1304 enclose the channel 4 (e.g., on the sacrificial oxide 33) and include the sacrificial oxide 43 on the sacrificial oxide 33 on the substrate 1.

[0047] Figure 14 shows a cross-sectional view of the semiconductor structures of NS1403 and NS1404 after the top layer of sacrificial oxide 43 on the WFM22 has been removed, according to one embodiment of the present invention. The top layer of sacrificial oxide 43 is removed from the surface of the remaining WFM22 of NS1403 and NS1404 using one or more oxide removal processes, such as a wet chemical etching process. A very thin layer of sacrificial oxide 43 remains on the WFM22, as described in detail earlier with reference to Figure 8, and is shown by a dashed line. In some cases, the remaining sacrificial oxide 43 may be a compound or mixture of La and Ti, with a thickness of several angstroms (e.g., 2-5 angstroms). In other cases, the sacrificial oxide 43 may have a single-layer thickness, or there may be several atomic layers of sacrificial oxide 43 on the WFM22. For example, the thickness of the sacrificial oxide 43 may be 2-3 atoms or 2-5 atomic layers. In other cases, the sacrificial oxide 43 forms a discontinuous metal oxide layer on the WFM22. The sacrificial oxide 43 surrounds the WFM 22 on each channel 4 and is present on the WFM 22 on the substrate 1. The sacrificial oxide 43 is the second sacrificial oxide material remaining within NS1404. The sacrificial oxide 43 is the first and only sacrificial oxide material on NS1403.

[0048] As shown in the figure, NS1404 includes the remaining portion of sacrificial oxide 43 on the WFM22 surrounding the sacrificial oxide 33 around the channel 4 and on the substrate 1, and the remaining portion of sacrificial oxide 33 on the WFM21 on the dielectric 6 (for example, on each channel 4 and on the dielectric 6 surrounding the IL5 on the substrate 1).

[0049] NS1403 includes the remaining portion of the sacrificial oxide 43 on the WFM22 surrounding the dielectric 6 (for example, the WFM22 surrounds each of the channels 4 and the IL5 on the substrate 1).

[0050] NS1402 and NS1401 include the elements shown in NS101 and NS102 in Figure 1.

[0051] Figure 15 shows a cross-sectional view of a semiconductor structure after WFM23 has been deposited on the semiconductor structure according to one embodiment of the present invention. As shown, Figure 15 shows NS1501 and 1502, each having a single WFM layer (e.g., WFM23), NS1503, having WFM22 and WFM23 in a nanosheet stack, and NS1504, having three layers of WFM (e.g., WFM23, 22, and 21). As shown in Figure 15, the deposition of WFM23 pinches off the gaps between sacrificial oxides 43 on adjacent channels 4 of NS1504 and the gap between the lower channel portion of channel 4 and the substrate 1 (e.g., pinching off the sacrificial oxides 43 on channel 4 and any region on the substrate 1). As illustrated, Figure 15 includes the elements of Figure 14 and WFM23. WFM23 can be deposited using the WFM deposition process described above. WFM23 can be the same metal nitride material as WFM22 and WFM21 or both, and can have similar thicknesses. In some embodiments, WFM23 is a different metal nitride material from WFM22 or WFM21.

[0052] Figure 16 shows a cross-sectional view of a semiconductor structure after sacrificial oxide 53 has been deposited on a WFM 23 according to one embodiment of the present invention. As shown, Figure 16 includes the elements of Figure 15 and the sacrificial oxide 53. As shown, the sacrificial oxide 53 is not deposited between the channels 4 of NS1604 as previously described, and the WFM 23 pinches off the gap between the sacrificial oxide 43 on the WFM 22 of NS1504 in Figure 15 and NS1604 in Figure 16. In various embodiments, the sacrificial oxide 53 can be made of the same or similar material as the sacrificial oxide 33 described with respect to Figure 3. For example, the sacrificial oxide 53 is one of the following: a lanthanum oxide material or a yttrium oxide material, but is not limited to these oxide materials, and is conformally deposited on each of the semiconductor structures (e.g., on each of NS1601, 1602, 1603, and 1604, and between the WFM23 on the channels 4 of NS1601, 1602, and 1603 and the surface of the WFM23 on the substrate 1 of NS1601, 1602, and 1603).

[0053] Figure 17 shows a cross-sectional view of a semiconductor structure after depositing a soft mask 62 and removing a portion of the soft mask 62 on NS1701, according to one embodiment of the present invention. As shown, Figure 17 shows NS1702, 1703, and 1704 covered by the soft mask 62, and NS1701 without the soft mask 62. NS1701 is essentially the same as NS1601. NS1702, 1703, and 1704 contain elements of NS1602, 1603, and 1604, respectively, but are blocked by the soft mask 62.

[0054] Figure 18 shows a cross-sectional view of the semiconductor structure after the removal of sacrificial oxide 53 and WFM23 from NS1801 according to one embodiment of the present invention. As shown, Figure 18 includes NS1702, 1703, and 1704, which are unchanged from Figure 17 and NS1801, without the sacrificial oxide 53 or WFM23. As shown, NS1801 includes a channel 4, IL5, and dielectric 6 on the dielectric 6 on the insulating layer 2. The sacrificial oxide 53 and WFM23 are removed using the etching process described with respect to Figure 6. The surface of the dielectric 6 inside and beneath NS1801 is exposed after the etching process.

[0055] Figure 19 shows a cross-sectional view of the semiconductor structure after the soft mask 62 has been removed, according to one embodiment of the present invention. As shown, Figure 19 includes the elements of Figure 18 with the soft mask 62 removed. NS1901 is essentially the same as NS1801. In Figure 19, all nanosheet stacks (e.g., NS1901, 1902, 1903, and 1904) are either unblocked or exposed.

[0056] Figure 20 shows a cross-sectional view of the semiconductor structure after the top layer of sacrificial oxide 53 has been removed from the WFM23 on NS2002, 2003, and NS2004 according to one embodiment of the present invention. As shown, Figure 20 includes NS2001, which is the same as NS1901, and NS2002, NS2003, and NS2004, which have the bottom layer of sacrificial oxide 53, and is a dashed line labeled as sacrificial oxide 53 covering the WFM23 on the exposed surfaces of the middle and lower WFM23 of NS2001, 2002, and 2003, and the WFM23 on the outer surface of NS2004. In various embodiments, sacrificial oxide 53 is the same as sacrificial oxide 33. In some embodiments, the remaining sacrificial oxide 53 is an oxide material different from either or both of sacrificial oxide 43 and sacrificial oxide 33. As previously mentioned with respect to Figure 8, a very thin layer of sacrificial oxide 53 is present on each surface of the WFM23 present in Figure 19. As mentioned above, the sacrificial oxide 53 may be discontinuous in some cases, or it may be a compound material containing, for example, a mixture of La or Y and Ti, but is not limited to this mixture of materials (for example, the mixture of the material with either La or Y may vary depending on the metal nitride deposited for the WFM 23). In some cases, the remainder of the sacrificial oxide 53 may have a thickness of 1 to 3 angstroms or a few atoms. For example, the thickness of the sacrificial oxide 53 may be 2 to 3 atoms or an atomic layer.

[0057] As illustrated, Figure 20 shows NS2004 with the remaining sacrificial oxide 53 on the WFM23 outside NS2004. In NS2004, the sacrificial oxide 53 is not present between adjacent surfaces of WFM23. This is because, as previously mentioned, WFM23 fills the gaps between the sacrificial oxide 43 around each channel 4, is below the sacrificial oxide 43 on the lower channel of channel 4, and fills the gaps above the sacrificial oxide 43 on WFM22 above the sacrificial oxide 33 on WFM21 on the dielectric 6 on the substrate 1. NS2004 also includes the remaining sacrificial oxide 43 around each channel 4 and on WFM22 on the substrate 1 (as previously mentioned with reference to, for example, Figure 15). NS2004 also includes the remaining sacrificial oxide 33 on WFM21 surrounding the dielectric 6 around IL5 on channel 4 and the dielectric 6 on the substrate 1 (as previously mentioned, for example, in Figures 8 and 14).

[0058] As illustrated, NS2003 includes the remaining portion of the sacrificial oxide 53 around channel 4 and on WFM23 on substrate 1 (for example, as previously mentioned with respect to Figure 14, the sacrificial oxide 53 is located between the sacrificial oxide 43 on WFM22 on dielectric 6 surrounding IL5 and on substrate 1, on each channel 4 and on substrate 1).

[0059] NS2002 includes the channel 4 and the remaining portion of the sacrificial oxide 53 on the WFM23 on the dielectric 6 on the IL5 on the substrate 1. NS2001 includes the elements described above with respect to Figure 1 (e.g., within NS101).

[0060] Figure 21 shows a cross-sectional view of a semiconductor structure after WFM24 is deposited on and below NS2101, 2102, and 2103, respectively, and on NS2104, according to one embodiment of the present invention. As shown, Figure 21 includes the elements of Figure 20 and the WFM24. The WFM24 is deposited on NS2104, on and around the dielectric 6 in NS2101, on and around the sacrificial oxide 53 in NS2102 and NS2103. Because there are no gaps between adjacent portions of the sacrificial oxide 53 on the channels 4 of NS2104 (for example, no gaps between adjacent 53 on adjacent channels 4), the WFM24 cannot be deposited between the channels 4 of NS2104 or between the surrounding channels 4. However, gaps between the sacrificial oxide 53 remain within NS2101, 2102, and 2103, which are sufficient for conformal deposition of the WFM24. The WFM24 may be the same WFM as the WFM21 described with respect to Figure 2, or it may be a different WFM. WFM24 can be made from the same or different WFM material as WFM22 or WFM23.

[0061] Figure 22 shows a cross-sectional view of the semiconductor structure after depositing WFM 102 under and around each channel portion of NS2201, 2202, and 2203 and on NS2204 according to one embodiment of the present invention, depositing caps 103 on the exposed surfaces of each WFM 102 of NS2201, 2202, 2203, and 2204, and depositing gate electrode material 104 on the caps 103 on each of NS2201, 2202, 2203, and 2204. As shown, Figure 22 includes the elements of Figure 21, comprising WFM 102, caps 103, and gate electrode material 104. The WFM 102, caps 103, and gate electrode material 104 each extend onto the substrate 1 adjacent to NS2201, NS2202, NS2203, and NS2204.

[0062] In various embodiments, WFM102 is an n-type work function metal. For example, WFM102 may be an aluminum-containing WFM such as TiAl, TiAlC, or AlC, or in one embodiment, WFM102 is TiN, but is not limited to these materials. In another embodiment, WFM102 is a stack composed of multiple layers of material, one of which is an aluminum-containing metal. In one embodiment, WFM102 is aluminum containing a metal as the work function metal.

[0063] As illustrated, WFM102 is located adjacent to and in contact with each of NS2201, 2202, 2203, and 2204, and is present on a portion of WFM24 on the substrate 1. Furthermore, WFM102 is located around the outside of NS2204, and is deposited above, below, around, and on the upper portion of each channel 4 of NS2201, NS2202, and NS2203, and on the upper part of the substrate 1. In NS2201, NS2202, 2203, and 2204, WFM102 is deposited on the exposed surface of WFM24. As illustrated, WFM102 is deposited on NS2204, but not between the channels 4 of NS2204, on the substrate 1, or below the lower channels of channel 4 (for example, as illustrated and described above with respect to Figure 20, there are no gaps or spaces between the channels 4 of NS2204 and between the layers of WFM23 on the substrate 1).

[0064] WFM102 fills the gaps between WFM24 surrounding adjacent channels 4 in NS2201, 2202, and 2203, respectively, and fills the gaps between WFM24 on the substrate 1 and WFM24 on the lower channel of channel 4. For example, in NS2201, WFM102 is deposited on the dielectric 6 around channel 4 and on WFM24 on the dielectric 6 on the insulating layer 2 on substrate 1. WFM102 fills the gaps between the exposed surfaces of WFM24. For example, WFM102 fills the gaps between WFM24 on the dielectric 6 on IL5 around adjacent channels 4, and the gaps between WFM24 on the dielectric 6 on substrate 1 and WFM24 around the dielectric 6 surrounding the lower channel 4.

[0065] In NS2202, WFM102 fills the gaps between adjacent surfaces of WFM24. WFM24 is on sacrificial oxide 53, which is on WFM22 on dielectric 6. In other words, WFM102 is between WFM24 surrounding each channel 4 covered by IL5, dielectric 6, WFM22, sacrificial oxide 53, and WFM24 on the lower channel of channel 4, and between WFM24 on sacrificial oxide 53 on sacrificial oxide 43 on WFM22 on dielectric 6 on insulating layer 2 on substrate 1.

[0066] In NS2203, WFM102 is located on the WFM24 that is below the sacrificial oxide 53 on the WFM23 around the channel 4 and below the WFM23. For example, the WFM24 around the channel 4, surrounding the WFM23, is on the sacrificial oxide 43 on the WFM22 that surrounds the dielectric 6 on the IL5 around each channel 4. WFM102 is also located on the WFM24 between the lower channel 4 and the substrate 1. WFM102 fills the gap between WFM24 near the lower channel of channel 4, it is on the sacrificial oxide 53, the sacrificial oxide 53 is on WFM23, it is on the sacrificial oxide 43 on WFM22, and it is on the dielectric 6 on the insulating layer 2 on the substrate 1. WFM102 fills the gap between WFM24 around channel 4 and fills the gap between WFM24 around the lower channel of channel 4 and WFM24 on the substrate 1. WFM102 fills the gaps between adjacent surfaces of WFM24 on NS2203.

[0067] In NS2204, WFM102 surrounds the WFM24 that is on the outside of NS2204 (for example, WFM102 is not between or below channels 4). In NS2201, 2202, and 2203, WFM102 fills the gaps between adjacent surfaces of WFM24. In other words, in NS2201, 2202, and 2203, WFM102 fills the gaps between the WFM24 around adjacent channels 4 and between the WFM24 below the lower channels of channel 4 and the WFM24 on substrate 1.

[0068] The cap 103 can be a cap layer made of a metal nitride material such as TiN. The WFM 102, cap 103, and gate electrode material 104 can be deposited using known deposition processes (e.g., CVD, PVD, ALD, etc.). The cap 103 is deposited on the WFM 102 around the outside of NS2201, 2202, 2203, and 2204, and on the WFM 102 on the substrate 1.

[0069] The gate electrode material 104 can be any known gate electrode material suitable for forming an NFET or PFET device. The gate electrode material 104 can be deposited around any of NS2201, NS2202, NS2203, or NS2204. The gate electrode material 104 can be W, Al, Co, Ru, or one of the other known gate electrode materials used for forming FET devices. As is known to those skilled in the art, each of NS2201, 2202, 2203, or 2204 can form one of an NFET or PFET device depending on the doping and material selection in NS2201, 2202, 2203, or 2204.

[0070] As illustrated, NS2204 contains three layers of work function metal covered with the remainder of the sacrificial oxide material (e.g., WFM21, 22, and 23 with sacrificial oxides 33, 43, and 53). There is no layer of sacrificial oxide 53 or WFM24 on WFM23 between channels 4 of NS2204 or between WFM23 on substrate 1. As shown in Figure 22, a fourth layer of work function metal (e.g., WFM24) surrounds the outer surface of WFM24 on NS2204. A fifth layer of work function metal (i.e., WFM102) is above WFM24 and below cap 103.

[0071] In other examples, the sacrificial oxide layer 53 or 43 may or may not be present in the nanosheet stack, depending on the thickness of the deposited material and the spacing between adjacent channels 4 in the NS2204. Furthermore, if the gaps between adjacent channels 4 in a nanosheet stack such as NS2204 are sufficiently large, three or more layers of work function metal may be deposited around the channels 4 of the NS2204, and three or more layers of sacrificial oxide material may be present around each channel 4 and on the substrate 1.

[0072] In various embodiments, WFM21, 22, 23, and 24 are composed of metals having the same work function. In some embodiments, WFM21, 22, 23, and 24 are not composed of metals having the same work function (for example, WFM21 may be different from each of WFM22, 23, and 24, or WFM22 may be the same as WFM23 or WFM24, etc.). Similarly, each of the sacrificial oxides 33, 43, and 53 may be the same oxide material or different oxide materials.

[0073] As shown in Figure 22, NS2204 includes a gate electrode material 104 on the cap 103 and a WFM 102 on the cap 103. WFM 102 is on top of WFM 24 with the remainder on the sacrificial oxide 53 surrounding the outside of NS2204. WFM 23 is on top of the sacrificial oxide 43 surrounding the channel 4 and fills the gaps between the channels 4 and between the channels 4 and the substrate 1, as previously described (for example, WFM 24, sacrificial oxide 53, WFM 102, cap 103, and gate electrode material 104 are not under or between each channel 4). NS2204 includes the remainder of sacrificial oxide 43 around and under each channel 4 and on WFM 22 on the substrate 1. NS2204 also includes the remainder of sacrificial oxide 33 on WFM 21 surrounding the IL 5 on the channel 4 and the dielectric 6 on the substrate 1 (for example, as previously described with reference to Figure 8).

[0074] In one embodiment, the process discussed with respect to Figures 1-22 is performed on a single nanosheet stack to form NS2204. In this embodiment, the process steps shown in Figures 1-22 for blocking and unblocking additional nanosheet stacks (e.g., nanosheet stacks 2201, 2202, and 2203 are not present) are not performed. The process in this case includes the deposition of a work function metal, the deposition of an oxide, the removal of the oxide top surface using an etching process, the deposition of a cap, and the deposition of a gate electrode.

[0075] NS2203 includes a gate electrode material 104 on cap 103 and cap 103 on WFM 102 on outer surface WFM 24, but the gate electrode material 104 and cap 103 are not present on WFM 24 between or below channels 4. In NS2203, WFM 24 may be on the remainder of sacrificial oxide 53 on WFM 23 which is on the remainder of sacrificial oxide 43, as described above. The remainder of sacrificial oxide 43 is on WFM 22. As shown in Figure 22, WFM 22 is on dielectric 6 (e.g., on IL 5 and on substrate 1).

[0076] NS2202 includes a gate electrode material 104 on the cap 103 and a cap 103 on the WFM 102 on the outer surface WFM 24, but the gate electrode material 104 and cap 103 are not present on the WFM 24 between or below the channels 4. NS2202 includes the remaining portion on the sacrificial oxide 53 around and below each channel 4, and on the WFM 23 on the substrate 1, where the WFM 23 is present on the dielectric 6 (e.g., on the IL 5 and on the substrate 1).

[0077] NS2201 includes a gate electrode material 104 on cap 103 and cap 103 on WFM 102 on outer surface WFM 24, but the gate electrode material 104 and cap 103 are not between or under the dielectric 6 above and around channel 4 (for example, as shown, WFM 102 is between the dielectric 6 on IL 5 and WFM 24 on substrate 1).

[0078] The structure and material layers of NS2204 (e.g., four WFM layers including WFM21, 22, 23, and 24) result in FET devices formed using NS2204 having a high effective work function. Comparing the effective work function of FET devices formed with NS2204 to those formed with NS2201, NS2202, and NS2203, FETs formed with NS2204 have the highest effective work function. Similarly, NS2203 forms an FET device with three layers of work function metal, each with a very thin oxide material layer from one of the sacrificial oxides 33 and 43 between WFM212 and WFM22, and between WFM23 and WFM24, each having a relatively high effective work function value. The effective work function of NS2203 is lower than that provided by NS2204, but higher than that of NS2202 and NS2201.

[0079] In other words, when comparing the effective work functions of NS2201, 2202, 2203, and 2204, the following comparison is possible: the effective work function of NS2204 is greater than that of NS2203, the effective work function of NS2203 is greater than that of NS2202, and the effective work function of NS2202 is greater than that of NS2201.

[0080] Using sacrificial oxide materials (e.g., La2O3, Y2O3, or other similar oxide materials) instead of soft mask materials between channel portions of a nanosheet stack during FET device formation allows for more effective removal of residual material between adjacent channel portions of the nanosheet stack. This ability to effectively remove residual material between adjacent channel portions of the nanosheet stack widens the gaps between adjacent channels. This increased gap allows for the deposition of additional WFM layers above, below, and around portions of the channel material, thereby improving the effective work function of the FET device.

Claims

1. A semiconductor structure comprising a nanosheet stack forming a field-effect transistor device, wherein the semiconductor structure is Multiple channels within a nanosheet stack on a semiconductor substrate, A plurality of work function metal layers on each of the plurality of channels of the nanosheet stack and on the semiconductor substrate, wherein adjacent plurality of work function metal layers are separated by an oxide material, An n-type work function metal located on the outer layer of a plurality of layers of the work function metal, wherein the n-type work function metal fills the gaps between the surfaces of the outer work function metal on each of the plurality of channels in the nanosheet stack and on the semiconductor substrate, and the plurality of layers of the work function metal are at least two layers of work function metal located beneath the n-type work function metal, The cap layer on the n-type work function metal, The gate electrode material on the cap layer and A semiconductor structure that includes this.

2. The semiconductor structure according to claim 1, wherein the more layers of the work function metal on each channel among the plurality of channels in the nanosheet stack, the higher the effective work function is provided compared to the case where the number of layers of the work function metal on each channel of the plurality of channels in the nanosheet stack is small.

3. A layer of a first work function metal on each of the plurality of channels in the nanosheet stack and on the semiconductor substrate, A layer of the first oxide material on the layer of the first work function metal, A layer of a second work function metal on the layer of the first oxide material, A layer of second oxide material on the layer of the second work function metal, A layer of a third work function metal on the layer of the second oxide material, wherein the layer of the third work function metal fills the gaps between adjacent surfaces of the layer of the second oxide material, A layer of third oxide material on the exposed surface of the third work function metal layer, A fourth work function metal layer on top of the third work function metal layer, A fifth work function metal on the layer of the fourth work function metal, The cap layer on the metal layer with the fourth work function, The gate electrode material on the cap layer and The semiconductor structure according to claim 1, including the above.

4. The semiconductor structure according to claim 3, wherein the first oxide material and the second oxide material are one of lanthanum oxide or yttrium oxide.

5. The semiconductor structure according to claim 3, wherein the first work function metal is a metal nitride material.

6. The semiconductor structure according to claim 3, wherein the first oxide material layer, the second oxide material layer, and the third oxide material layer each have the thickness of a single layer or several atomic layers of each oxide material.

7. The semiconductor structure according to claim 3, wherein the layers of the first oxide material are discontinuous.

8. The semiconductor structure according to claim 3, wherein the second oxide material layer has a lanthanum-titanium mixed interface layer.

9. The semiconductor structure according to claim 4, wherein the third oxide material layer is one of lanthanum oxide having a composition of La2O3 or yttrium oxide having a composition of Y2O3.

10. The semiconductor structure according to claim 3, wherein the fifth work function metal is an aluminum-containing work function material.

11. The semiconductor structure according to claim 3, wherein the fifth work function metal is a multilayer work function metal.

12. The semiconductor structure according to claim 3, wherein the first work function metal layer, the second work function metal layer, the third work function metal layer, and the fourth work function metal layer are made of the same material.

13. A method for forming multiple field-effect devices having multiple work function metal layers, wherein the method is A first work function metal is deposited on multiple channels within each nanosheet stack and beneath each nanosheet stack of multiple nanosheet stacks on a semiconductor substrate. Depositing a first oxide material on the first work function metal, The process involves depositing and patterning a first soft mask onto the aforementioned nanosheet stacks, Removing the first soft mask from at least one of the plurality of nanosheet stacks, Removing the first oxide material and the first work function metal from at least one of the plurality of nanosheet stacks, To remove the first soft mask remaining on one or more of the plurality of nanosheet stacks, The removal involves removing the upper part of the first oxide material from one or more of the plurality of nanosheet stacks, wherein the lower part of the first oxide material remains on the first work function metal. Depositing a second work function metal on the first oxide material remaining on the first work function metal and Methods that include...

14. The process involves depositing an n-type work function metal on the second work function metal and filling one or more gaps between adjacent surfaces of the second work function metal, Depositing a cap layer on the aforementioned n-type work function metal, Depositing gate electrode material on the aforementioned n-type work function metal and The method according to claim 13, further comprising:

15. Depositing a second oxide material on the second work function metal, Depositing a second soft mask on the aforementioned plurality of nanosheet stacks, Removing the second soft mask from at least two of the plurality of nanosheet stacks, Removing the second oxide material and the second work function metal from at least two of the plurality of nanosheet stacks, Removing the second soft mask from at least one of the plurality of nanosheet stacks covered by the second soft mask, The removal involves removing the upper part of the second oxide material from at least one of the plurality of nanosheet stacks, wherein the lower part of the second oxide material remains on the second work function metal. The deposition of a third work function metal on the second oxide material, wherein the third work function metal fills the gaps between adjacent surfaces of the second oxide material, Depositing a fourth work function metal on the exposed surface of the third work function metal, Depositing a fifth work function metal on top of the fourth work function metal, Depositing a cap layer on the metal with the fifth work function, Depositing gate electrode material on the aforementioned cap layer The method according to claim 13, further comprising:

16. The method according to claim 15, wherein the first work function metal, the second work function metal, the third work function metal, and the fourth work function metal are all the same work function metal.

17. The method according to claim 15, wherein the first oxide material and the second oxide material are each one of a lanthanum oxide material or a yttrium oxide material.

18. The method according to claim 17, wherein the lower portion of the first oxide material remaining on the first work function metal is a single layer of one of the lanthanum oxide material or the yttrium oxide material.

19. The method according to claim 15, wherein the fifth work function metal is an aluminum-containing work function metal.

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