Formation of magnetic tunnel junction pillars for MRAM devices

Abstract

A method of manufacturing an MRAM device includes forming an MTJ stack on a substrate, forming a hard mask layer on the MTJ stack, forming an etch pattern pad on the hard mask, forming spacers on sides of the etch pattern pad to form first openings exposing the hard mask, patterning the MTJ stack by a first etch using the first openings to form a plurality of first MTJ pillars separated by first vias, filling the first vias with a first dielectric, removing the spacers from the etch pattern pad to form a plurality of second openings between the first dielectric and the etch pattern pad, patterning the plurality of first MTJ pillars by a second etch using the second openings to form a plurality of second MTJ pillars separated by second vias, and filling the second vias with a second dielectric to encapsulate the plurality of second MTJ pillars.

Description

TECHNICAL FIELD

[0001] The present invention relates to magnetoresistive random access memory ("MRAM") device cells comprising a magnetic tunnel junction ("MTJ") stack, and methods of manufacturing MRAM devices. BACKGROUND ART

[0002] Current MTJ pillar formation for MRAM requires aggressive ion beam etching (IBE) to remove metal residues on the sidewalls of the MTJ that cause short circuits. Overly aggressive IBE etches away NBLOK, comes into contact with the bottom Cu contact, and can cause Cu exposure, migration, and oxidation. A large IBE opening during pillar formation causes NBLOK loss due to the loading effect. Therefore, prior solutions require low-intensity IBE to avoid excessive NBLOK loss. However, when post-etching oxidation is performed after reducing the IBE budget, and metal residues are oxidized, significant damage is caused to the sidewalls of the MTJ. SUMMARY OF THE INVENTION

[0003] Embodiments of the present invention relate to a method for manufacturing an MRAM device having magnetic tunnel junction (MTJ) pillars, comprising: forming a plurality of layers defining an MTJ stack on a substrate; forming a metal hard mask layer on the MTJ stack; forming a plurality of etching pattern pads on the metal hard mask layer; forming spacers on the sides of the plurality of etching pattern pads for forming a plurality of first openings that expose the hard mask layer; patterning the MTJ stack by first etching using the first openings so that a plurality of first MTJ pillars separated by first vias are formed; filling the first vias with a first dielectric; removing spacers from the plurality of etching pattern pads so that a plurality of second openings are formed between the first dielectric and the plurality of etching pattern pads; patterning the plurality of first MTJ pillars by second etching using the second openings so that a plurality of second MTJ pillars separated by second vias are formed; and filling the second vias with a second dielectric to encapsulate the plurality of second MTJ pillars.

[0004] Embodiments of the present invention relate to an MRAM device having magnetic tunnel junction (MTJ) pillars, comprising a plurality of MTJ pillars on a substrate, a first dielectric between pairs of MTJ pillars with two vias defined between each pair of MTJ pillars, and a second dielectric filling the via pairs and encapsulating the plurality of MTJ pillars.

[0005] The further features, structure, and operation of various embodiments will be described in detail below with reference to the attached drawings. In the drawings, similar reference numerals indicate identical or functionally similar elements. [Brief explanation of the drawing]

[0006] [Figure 1] This is a cross-sectional view of the back-end-of-line base layer formed beneath the magnetic tunnel junction (MTJ) stack of an MRAM device according to multiple embodiments. [Figure 2]This is a cross-sectional view of the MRAM device shown in Figure 1 after an additional manufacturing process, according to multiple embodiments. [Figure 3] This is a cross-sectional view of the MRAM device shown in Figure 2 after an additional manufacturing process, according to multiple embodiments. [Figure 4] Figure 3 is a cross-sectional view of an MRAM device after an additional manufacturing process, according to multiple embodiments. [Figure 5] Figure 4 is a cross-sectional view of an MRAM device after an additional manufacturing process, according to multiple embodiments. [Figure 6] Figure 5 is a cross-sectional view of an MRAM device after an additional manufacturing process, according to multiple embodiments. [Figure 7] Figure 6 is a cross-sectional view of an MRAM device after an additional manufacturing process, according to multiple embodiments. [Figure 8] Figure 7 is a cross-sectional view of an MRAM device after an additional manufacturing process, according to multiple embodiments. [Figure 9] Figure 8 is a cross-sectional view of an MRAM device after an additional manufacturing process, according to multiple embodiments. [Modes for carrying out the invention]

[0007] This disclosure describes an MRAM device including a magnetic tunnel junction ("MTJ") stack, and a method for manufacturing an MRAM device. In particular, this disclosure describes a two-step etching process consisting of one etching process for removing the MTJ stack material in the field region and a second etching process with a small etching opening. This disclosure describes an MRAM device comprising an MTJ stack pillar having two different underlying dielectric layers adjacent to the MTJ stack pillar, each having a different cross-sectional profile in the same direction.

[0008] Various embodiments of the present invention are described herein with reference to the relevant drawings. Alternative embodiments can be devised without departing from the scope of the present invention. It should be noted that various connections and positional relationships between elements (e.g., above, below, adjacent, etc.) are described in the following description and drawings. These connections or positional relationships, or both, may be direct or indirect unless otherwise specified, and this disclosure is not intended to be limiting in this respect. Thus, the joining of entities may refer to either direct or indirect joining, and the positional relationships between entities may be direct or indirect. As an example of an indirect positional relationship, when this specification refers to layer "A" covering layer "B", it includes a situation in which there is one or more intermediate layers (e.g., layer "C") between layer "A" and layer "B" to the extent that the relevant properties and functionality of layer "A" and layer "B" are not substantially altered by the intermediate layer.

[0009] The following definitions and abbreviations are for use in interpreting the claims and specification. As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “have,” “having,” “contains,” or “containing,” or any other variation thereof, are intended to include non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus containing the enumerated elements is not necessarily limited to those elements alone and may include other elements not expressly enumerated or specific to such composition, mixture, process, method, article, or apparatus.

[0010] For the purposes of the following explanation, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives are assumed to relate to the structure and method described and to the orientation in the drawings. The terms “overlying,” “atop,” “on top,” “positioned on,” or “positioned atop” mean that a first element, e.g., a first structure, is located on a second element, e.g., a second structure, in which case there may be intervening elements, such as a junction surface structure, between the first and second elements. The term “direct contact” means that a first element, e.g., a first structure, and a second element, e.g., a second structure, are connected without any intermediate conductive, insulating, or semiconductor layers at the junction surface of the two elements. For example, the phrase "selective to ~," such as "a first element selective to a second element," should be noted as meaning that the first element can be etched and the second element can function as an etch stop.

[0011] For the sake of brevity, conventional techniques related to the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Furthermore, various tasks and process steps described herein may be incorporated into more comprehensive procedures or processes that have additional steps or functionalities not described in detail herein. In particular, various processes for the manufacture of semiconductor devices and semiconductor-based ICs are well known, and therefore, for the sake of brevity, many conventional processes are only briefly mentioned herein or omitted entirely, and details of well known processes are not provided.

[0012] Generally, the various processes used to form microchips that are packaged into ICs are classified into four common categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography.

[0013] Deposition is any process that involves depositing, coating, or otherwise transferring a material onto a wafer. Available techniques include, among others, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). Another deposition technique is plasma-enhanced chemical vapor deposition ("PECVD"), which uses the energy in a plasma to induce reactions on the wafer surface that would normally require higher temperatures associated with conventional CVD. Energetic ion bombardment can also be used during PECVD deposition to improve the electrical and mechanical properties of the film.

[0014] Removal / etching is any process that removes material from a wafer. Examples include etching processes (wet or dry) and chemical mechanical planarization ("CMP"). One example of a removal process is ion beam etching ("IBE"). Generally, IBE (or milling) refers to a dry plasma etching method that uses a remote broad-beam ion / plasma source to remove a substrate by physical inert gas means, chemical reactive gas means, or both. Like other dry plasma etching techniques, IBE offers advantages such as etching rate, anisotropy, selectivity, uniformity, aspect ratio, and minimization of substrate damage. Another example of a dry removal process is reactive ion etching ("RIE"). Generally, RIE uses chemically reactive plasma to remove material deposited on a wafer. In RIE, the plasma is generated under low pressure (vacuum) by an electromagnetic field. High-energy ions from the RIE plasma aggressively act on the wafer surface, reacting with it to remove the material.

[0015] Semiconductor doping is the modification of electrical properties by doping, for example, the source and drain of a transistor, typically by diffusion, ion implantation, or both. These doping processes are followed by furnace annealing or fast thermal annealing ("RTA"). Annealing activates the implanted dopants. To connect and insulate the transistor and its components, films of conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used. By selectively doping different areas of a semiconductor substrate, it becomes possible to change the conductivity of the substrate by applying a voltage. By creating the structures of these various components, millions of transistors can be constructed and wired together to form the complex circuit configurations of modern microelectronic devices.

[0016] Semiconductor lithography is the process of forming a three-dimensional relief image or pattern on a semiconductor substrate and then transferring that pattern to the substrate. In semiconductor lithography, patterns are formed using a photosensitive polymer called photoresist. The lithography process and etching / pattern transfer process are repeated multiple times to construct the complex structures that make up transistors and the numerous wires that connect millions of transistors in a circuit. Each pattern printed on the wafer is aligned with a pre-formed pattern, and conductors, insulators, and selectively doped areas are built over time to form the final device.

[0017] Turning now to an overview of technologies more specifically related to aspects of the present invention, embedded DRAM ("eDRAM") is dynamic random access memory ("DRAM") integrated on the same die or multi-chip module ("MCM") of an application-specific integrated circuit ("ASIC") or a microprocessor. eDRAM is implemented with silicon-on-insulator ("SOI") technology, which refers to the use of a layered silicon-insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing. eDRAM technology has met with varying degrees of success, and demand for SOI technology as a server memory option has declined in recent years.

[0018] Magnetoresistive random access memory (MRAM) devices that use magnetic tunnel junctions (MTJs) are one alternative that can replace existing eDRAM technology. MRAM is a non-volatile memory, and this advantage is the driving force that accelerates the development of this memory technology.

[0019] Referring now to the drawings, wherein like numerals refer to like or similar elements, and initially referring to FIG. 1, there is shown an exemplary structure 10 to which embodiments of the present invention can be applied. The structure 10 includes a back-end-of-line ("BEOL") substrate 12 formed of a plurality of layers. In general, the BEOL substrate 12 is the second part of IC manufacturing, where individual devices (transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer. As shown in FIG. 1, the BEOL substrate 12 includes a BEOL metal layer 14 and a BEOL dielectric layer 16. The BEOL metal layer 14 may include, for example, Cu, TaN, Ta, Ti, TiN, or combinations thereof. The BEOL dielectric layer 16 may include, for example, SiO x , SiN x , SiBCN, low-k NBLOK, or any other suitable dielectric material.

[0020] A micro-stud layer 18 is formed on the BEOL metal layer 14. First, the micro-stud layer 18 can be formed by patterning the dielectric layer 16 by lithography. Then, vias are formed in the via dielectric layer 16, for example by RIE, to remove spaces for filling by the subsequent micro-stud layer 18. In certain embodiments, the micro-stud layer 18 may include a material such as W, Cu, TaN, Ta, Ti, TiN, TiOCN, TaOCN, or a combination of these materials. The micro-stud layer 18 may be formed by CVD, PVD, ALD, or a combination of these. After the micro-stud layer 18 is formed, the structure is subjected to, for example, CMP to planarize the surface for further processing. The structure including the BEOL layer shown in FIG. 1 is a starting structure on which an MTJ stack will be formed on the surface.

[0021] An MTJ stack 20 is formed on the via dielectric 16 and the micro-stud layer 18. In some embodiments, the MTJ stack layer 20 includes a seed layer 22 formed on the via dielectric layer 16. The seed layer 22 has a crystal lattice and grain structure suitable as a growth surface for the free layer of the MTJ stack 20. The seed layer 22 can be, for example, a metal seed layer made of Ru, Ta, NiCr, or a combination of these materials.

[0022] Generally, an MTJ stack 20 may include a magnetic free layer 24, a tunnel barrier layer 26, and a reference layer 28 having a fixed magnetic polarity. Generally, the magnetic free layer 24 has a reversible magnetic moment or magnetization. In certain embodiments, the tunnel barrier layer 26 is a barrier, such as a thin insulating layer between two conductive materials. Electrons pass through the tunnel barrier 26 by the process of quantum tunneling. In certain embodiments, the tunnel barrier layer 26 is composed of MgO. In certain embodiments, each layer of the MTJ stack 20 may have a thickness ranging from less than an angstrom to several angstroms or nanometers. Typical material examples for an MTJ stack 20 include MgO for the tunnel barrier layer 26, CoFeB for the free layer 24, and multiple layers composed of different materials for the reference layer 28. It should be understood that the MRAM materials forming the MTJ stack 20 are not limited to these materials or layers described above. That is, an MRAM material stack may consist of a stack of any known materials used in MRAM devices. Furthermore, it should be understood that any of the MTJ stacks 20 may include additional layers, certain layers may be omitted, and each layer may include any number of sub-layers.

[0023] A hard mask stack 30 is deposited on the MTJ stack 20. In some embodiments, the hard mask stack 30 consists of a layer of Ta or Ru and a layer of TaN. The hard mask stack 30 is then patterned by lithography and RIE. As shown in Figure 2, in certain embodiments, the etching pattern layer is made of organic planarization layer ("OPL") material, SiN x SiO x The material is patterned to form an etching pattern pad 32, which consists of oxides such as SiARC, photoresist, or a combination thereof. First, the material for the etching pattern pad 32 is deposited on the hard mask 30 and then etched by RIE or IBE to form the pattern of the pad 32 shown in Figure 2.

[0024] Next, referring to Figure 3, a spacer 34 is formed on the side wall of the etching pattern lattice 32, forming a first opening 35. The spacer 34 can be made of, for example, SiN, SiBCN, or SiCN, and is generally selected to have etching selectivity with respect to the etching pattern pad 32.

[0025] Next, referring to Figure 4, the MTJ stack 20 is patterned with a first IBE, utilizing an etching pattern pad 32 with pattern spacers 34, to form a first MTJ pillar 21. As shown in Figure 4, etching is stopped inside (or near the top) of the dielectric layer 16. In some embodiments, the MTJ stack 20 is patterned with IBE or RIE or a combination thereof at multiple angles. Thus, after the etching procedure, multiple first MTJ pillars 21 are formed, separated by vias 36. Considering that this IBE is not for final MTJ pillar formation, a non-aggressive or low-intensity IBE may be used at the opening 35. In some embodiments, the IBE may use a low bias voltage for a short time.

[0026] Next, referring to Figure 5, a first dielectric layer 38 is deposited to fill the vias 36. This first dielectric layer 38 can be composed of any suitable ILD oxide, a low-k flowable oxide. In some embodiments, the first dielectric layer 38 has a very low adhesion coefficient to the MTJ pillar so that it can be easily removed from the surface of the first MTJ pillar 21. In some embodiments, the dielectric material is low-quality SiN, SiBCN, SiON, SiO x It may consist of , SiCON, or a combination thereof, in which case the dielectric material may be susceptible to damage by IBE etching. The first dielectric layer 38 is deposited to a height sufficient to cover the sidewalls of the spacer 34 and the upper surface of the spacer 34 and the etching pattern pad 32. CMP is performed following dielectric filling of the vias 36 to expose the upper surface of the etching pattern pad 32 together with the spacer 34.

[0027] Referring next to Figure 6, the spacer 34 is removed, leaving etching openings 40 on both sides of the etching pattern pad 32. The etching openings 40 are smaller than the first opening 35. The spacer is removed using selective RIE or a suitable wet or dry etching process. In some embodiments, removal of the spacer defines the etching openings 40 to have a substantially vertical etch slope or a substantially vertical contact angle. The use of the terms “substantially vertical etch slope” or “substantially vertical contact angle” means the angle determined by the sidewalls of the opening being formed at at least 80 degrees, preferably about 90 degrees, with respect to the top plane of the etching pattern 32.

[0028] As shown in Figure 7, a second IBE is performed to etch the first MTJ pillar 21 using an etching pattern pad 32 without a pattern spacer 34, thereby forming a second MTJ pillar 41. As shown in Figure 7, the etching is stopped inside (or near the top of) the dielectric layer 16, forming vias 42 between the MTJ pillar 41 and the first dielectric 38. The smaller the etching opening 40, the less gauging into the dielectric 16, allowing for a much higher IBE budget. The second IBE can therefore be performed more aggressively than the first IBE etching, with a more linear etching angle and using a higher bias voltage for a longer period of time. No additional lithography process is required. The pre-filled sacrificial dielectric 38 will be eroded during the second IBE etching so that two second vias 42 are formed between the pair of second pillars 41 of the MTJ. The dielectric 38 also acts as a protective layer for the underlying NBLOK layer 16. Thus, due to the small size of the opening 40, the NBLOK loss during this second IBE step is minimized compared to conventional MTJ stack patterning performed at much larger openings. The top 44 of the opening 40 widens due to erosion of the first dielectric 38, which is beneficial for the subsequent angled IBE cleaning etching.

[0029] A dielectric encapsulation layer 46 is formed by filling vias 42 to cover the exposed surfaces of the second pillar 41 and etching pattern pad 32 of the MTJ, followed by a CMP planarization process. As shown in Figure 8, CMP exposes the upper surfaces of the second MTJ pillar 41 and the dielectric encapsulation layer 46. For example, the dielectric encapsulation layer 46 can be made of PVD, ALD, PECVD, AlO x , TiO x It includes at least one of BN, SiN, and SiBCN.

[0030] Next, referring to Figure 9, following the CMP planarization process, a metal contact layer 48 is formed on the exposed surfaces of the encapsulation layer 46 and the second MTJ pillar 41 by conventional lithography. In some embodiments, following the formation of the metal contact layer 48, a second ILD layer or NBLOK layer 50 is formed to cover the upper surface of the metal contact layer 48. In certain embodiments, the metal contact layer 48 is composed of Ta, TaN, Cu, or any suitable combination thereof. In some embodiments, as shown in Figure 9, a portion of the encapsulation layer 46 is removed using selective RIE or other suitable wet or dry etching to form a metal contact layer on multiple surfaces of the metal hard mask layer 30 of the second MTJ pillar 41.

[0031] The final MRAM device 52 shown in Figure 9 consists of a second MTJ stack pillar 41 and two different underlying dielectric layers 38 and 46 adjacent to the second MTJ stack pillar 41, each having a different cross-sectional profile. The MRAM device 52 is formed using a two-step etching process: one etching process that removes the MTJ stack material in the field region using the etching opening 36 shown in Figure 4, and a second etching process that uses a smaller etching opening 40 shown in Figure 6. The two different dielectric fillers 38 and 46 adjacent to the MTJ pillars better retain the underlying NBLOK 16. Dielectric layer 38 is an eroded intermediate sacrificial dielectric between the second MTJ pillars 41.

[0032] The descriptions of various embodiments are presented for illustrative purposes only and are not intended to be exhaustive or limit the scope of the embodiments disclosed. Many changes and modifications will be apparent to those skilled in the art without departing from the scope of the embodiments described. The terminology used herein has been selected to best describe the principles of the embodiments, their practical applications, or technical improvements to the technology available on the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for manufacturing an MRAM device having a magnetic tunnel junction (MTJ) pillar, Forming multiple layers that define the MTJ stack on the substrate, Forming a metal hard mask layer on the MTJ stack, Forming multiple etching pattern pads on the aforementioned metal hard mask layer, Spacers are formed on the sides of the plurality of etching pattern pads to form a plurality of first openings that expose the metal hard mask layer, Patterning the MTJ stack by a first etching using the first opening such that a plurality of first MTJ pillars separated by the first via are formed, Filling the first via with the first dielectric, The spacers are removed from the plurality of etching pattern pads so that a plurality of second openings are formed between the first dielectric and the plurality of etching pattern pads, Patterning the plurality of first MTJ pillars by a second etching using the second opening such that a plurality of second MTJ pillars separated by a second via are formed, A method comprising filling the second vias with a second dielectric in order to encapsulate the plurality of second MTJ pillars.

2. The method according to claim 1, wherein the second opening has a smaller width than the first opening.

3. The method according to claim 2, wherein the first etching is performed by IBE using a first bias voltage for a first time, and the second etching is performed by IBE using a second bias voltage for a second time, wherein the second bias voltage is higher than the first bias voltage and the second time is longer than the first time.

4. The method according to claim 1, wherein during the second etching, the second dielectric is eroded such that two second vias are formed between the second pillar pair of the MTJ.

5. The method according to claim 1, wherein during the second etching, the second dielectric is eroded such that the width of the second via is wider at the top than at the bottom.

6. The method according to claim 1, wherein the cross-sectional profile of the first dielectric in the first direction is different from the cross-sectional profile of the second dielectric in the first direction.

7. The method according to claim 1, wherein the first dielectric and the second dielectric are made of different materials.

8. The method according to claim 1, wherein the plurality of second MTJ pillars are sealed with the second dielectric, then CMP planarization is performed to deposit a metal contact layer on the second MTJ pillars.

9. The method according to claim 1, wherein the plurality of layers defining the MTJ stack comprises a magnetically free layer on one side of the tunnel barrier layer and a reference layer having a fixed magnetic polarity on the opposite side of the tunnel barrier layer.

10. The method according to claim 1, further comprising forming a seed layer on the substrate before forming the plurality of layers defining the MTJ stack.

11. An MRAM device having a magnetic tunnel junction (MTJ) pillar, Multiple MTJ pillars on the substrate, A first dielectric is positioned between pairs of MTJ pillars, with two vias in between each pair of MTJ pillars, A second dielectric is provided which fills the pair of vias and encapsulates the plurality of MTJ pillars, The second dielectric is in contact with the pair of side walls of the MTJ pillar, surrounding the top of the first dielectric and above it, MRAM device.

12. The MRAM device according to claim 11, wherein the width of the two vias between each pair of MTJ pillars is wider at the top than at the bottom.

13. The MRAM device according to claim 11, wherein the cross-sectional profile of the first dielectric in the first direction is different from the cross-sectional profile of the second dielectric in the first direction.

14. The MRAM device according to claim 11, wherein the first dielectric and the second dielectric are made of different materials.

15. The MRAM device according to claim 11, further comprising a metal contact layer on the plurality of MTJ pillars.

16. The MRAM device according to claim 11, wherein the plurality of MTJ pillars each comprises a magnetically free layer on one side of the tunnel barrier layer and a reference layer having a fixed magnetic polarity on the opposite side of the tunnel barrier layer.

17. The MRAM device according to claim 16, wherein the MTJ pillar further comprises a seed layer between the substrate and the plurality of MTJ pillars.

18. The MRAM device according to claim 17, wherein the MTJ pillar further comprises a metal hard mask layer on the magnetic free layer.

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