An amplifier in which vertically stacked transconductance cells are coupled in parallel and / or cascaded "current mode".

Abstract

To provide a method, a system, and an apparatus, for an amplifier with stacked transconducting cells in parallel and / or cascade "current mode" combining.SOLUTION: A method for operation of a current mode amplifier comprises: inputting, into each transconducting cell of a plurality of transconducting cells, a direct current supply current (Idc), an alternating current radio frequency (RF) input current (IRF_IN), and an RF input signal (RFIN); and outputting, by each of the transconducting cells of the plurality of transconducting cells, the direct current supply current (Idc) and an alternating current RF output current (IRF_OUT). The plurality of transconducting cells are connected together in cascode for the direct current supply current (Idc), are connected together in parallel or in cascade for the RF input signal (RFIN), and are connected together in parallel or in cascade for the alternating current RF output current (IRF_OUT).SELECTED DRAWING: Figure 14A

Description

[Technical Field]

[0001] This disclosure relates to an amplifier. Specifically, this disclosure relates to an amplifier in which vertically stacked transconductance cells are coupled in parallel and / or cascaded "current-mode" coupling. [Background technology]

[0002] Signal amplifiers targeting the high-frequency millimeter-wave band operate from tens of gigahertz (GHz) to hundreds of GHz, and these amplifiers are often required to be implemented using semiconductor technology with high-frequency performance indicated by the unity-gain frequency figure of merit (Ft). Typically, devices with high Ft have smaller feature sizes fabricated on the device, which reduces voltage handling and device voltage breakdown, thereby limiting the output power that can be obtained from a single device. For systems requiring more output power than is available from a single device, or for systems with limited high-voltage supply, device stacking techniques are employed, in which a common current is shared among cascode-like devices and the power supply voltage is distributed among each device. However, this conventional stacked device approach has known limitations on placement size when using power coupling techniques, and further, there are reliability concerns when using "voltage mode" coupling techniques.

[0003] In light of the above, an improved design for high-voltage signal amplifiers is needed. [Overview of the Initiative]

[0004] This disclosure relates to methods, systems, and apparatus for amplifiers in which vertically stacked transconductance cells are current-mode coupled. In one or more embodiments, a method for operating a high-voltage signal amplifier comprises supplying each transconductance cell of a plurality of transconductance cells with a direct current (DC) supply current (Idc) and an alternating current (AC) radio frequency (RF) input current (Idc). RF_IN ), and RF input signal (RF IN This method includes inputting a DC supply current (Idc) and an AC RF output current (Idc) through each of the transconductance cells among the multiple transconductance cells. RF_OUT This further includes outputting an RF input signal (RF). In one or more embodiments, the transconductance cells are cascoded to each other for a DC supply current (Idc) and an RF input signal (RF IN They are cascaded (or connected in parallel) to each other for the purpose of AC RF output current (I RF_OUT They are cascaded (or connected in parallel) to each other for the purpose of )

[0005] In at least one embodiment, the method uses an input signal source (Vin) to input an RF input signal (RF IN The method further includes providing the RF input signal (RF) to the input matching network (M1). In some embodiments, the input matching network (M1) is a single-input single-output matching network. In one or more embodiments, the method uses the input matching network (M1) to provide the RF input signal (RF) to the input matching network (M1). IN This further includes converting the values ​​to provide power matching to each input of the transconductance cell.

[0006] In one or more embodiments, the transconductance cell receives an RF input signal (RF IN When cascaded together for this purpose, the input matching network (M1) is connected to one of the input junctions of the transconductance cells.

[0007] In at least one embodiment, the method outputs an AC RF output current (I RF_OUT ) output from a transconductance cell among the plurality of transconductance cells is input to an output matching network (M2) to transfer power to a load impedance (R L ). The method further comprises transferring power to R). In some embodiments, the output matching network (M2) is a single-input single-output matching network.

[0008] In one or more embodiments, when the transconductance cells are cascaded with each other for AC RF output current, the output matching network (M2) is connected to an input junction of one of the transconductance cells.

[0009] In at least one embodiment, in the method, each of the transconductance cells comprises a metal oxide silicon field effect transistor (MOSFET). In some embodiments, each of the transconductance cells comprises a bipolar junction transistor (BJT).

[0010] In one or more embodiments, the method further comprises evenly distributing a power supply voltage (Vdd) among the transconductance cells to supply power to the transconductance cells. In some embodiments, the DC supply voltage drop across each of the transconductance cells is Vdd / N, where N is the number of transconductance cells.

[0011] In at least one embodiment, a method for operating a high-voltage multi-stage signal amplifier comprises providing, to each transconductance cell of a plurality of transconductance cells in a first stage, a direct current (DC) supply current (Idc), an alternating current (AC) radio frequency (RF) input current (I RF_IN ), and an RF input signal (RF INThis method includes inputting a DC supply current (Idc) and an AC RF input current (Idc) to each of the multiple transconductance cells in the second stage. RF_IN ), and RF input signal (RF IN The method further includes inputting ). The method also includes inputting a DC supply current (Idc) and an AC RF output current (Idc) through each of the transconductance cells among the multiple transconductance cells of the first stage. RF_OUT This method includes outputting a DC supply current (Idc) and an AC RF output current (Idc) through each of the transconductance cells among the multiple transconductance cells of the second stage. RF_OUT This includes outputting an RF input signal (RF). In one or more embodiments, the transconductance cells of the first stage are cascoded to each other for a DC supply current (Idc) and an RF input signal (RF IN They are connected in parallel (or cascaded) to each other for the purpose of AC RF output current (I RF_OUT They are connected in parallel (or cascaded) to each other for the RF input signal (RF). In at least one embodiment, the transconductance cells of the second stage are cascoded to each other for the DC supply current (Idc) and the RF input signal (RF IN They are connected in parallel (or cascaded) to each other for the purpose of AC RF output current (I RF_OUT They are connected in parallel (or cascaded) to each other for the purpose of supplying DC current. In some embodiments, the first stage and the second stage are cascoded to each other for the purpose of supplying DC current.

[0012] In one or more embodiments, the method further includes distributing the power supply voltage (Vdd) equally among the first and second stage transconductance cells to supply power to the first and second stage transconductances. In some embodiments, the DC supply voltage drop across each of the first and second stage transconductance cells is Vdd / N, where N is the number of first and second stage transconductance cells.

[0013] In at least one embodiment, the method uses an input signal source (Vin) to input an RF input signal (RF IN The method further includes providing the RF input signal (RF) to the input matching network (M1). In some embodiments, the input matching network (M1) is a single-input single-output matching network. In one or more embodiments, the method uses the input matching network (M1) to provide the RF input signal (RF) to the input matching network (M1). IN The method further includes converting the values ​​to provide power matching to each input of the transconductance cell of the first stage.

[0014] In one or more embodiments, the AC RF output current (I) is output from at least one transconductance cell of the plurality of transconductance cells of the first stage. RF_OUT This further includes inputting the power to an internal stage matching network (M2) to transfer power to the transconductance cells of the second stage. In some embodiments, the internal stage matching network (M2) is a single-input, single-output matching network.

[0015] In at least one embodiment, the method uses the AC RF output current (I) output from at least one transconductance cell of the plurality of transconductance cells of the second stage. RF_OUT ) is input to the output matching network (M3) and the load (R L This further includes transmitting power to the ). In some embodiments, the output matching network (M3) is a single-input single-output matching network.

[0016] In one or more embodiments, the high-voltage signal amplifier comprises a plurality of transconductance cells, each of which receives a direct current (DC) supply current (Idc) and an alternating current (AC) radio frequency (RF) input current (Idc). RF_IN ), and RF input signal (RF IN ) are configured to receive a DC supply current (Idc) and an AC RF output current (Idc), respectively. RF_OUTIt includes a plurality of transconductance cells configured to output an RF input signal (RF). In at least one embodiment, the transconductance cells are cascoded to each other for a DC supply current (Idc) and an RF input signal (RF). IN They are connected in parallel (or cascaded) to each other for the purpose of AC RF output current (I RF_OUT They are connected in parallel (or cascaded) to each other for the purpose of [something].

[0017] In at least one embodiment, the amplifier receives an RF input signal (RF IN The system further includes an input signal source (Vin) that provides an RF input signal (RF) to the input matching network (M1). In some embodiments, the input matching network (M1) provides an RF input signal (RF) IN ) converts to provide power matching to each input of the transconductance cell. In one or more embodiments, the transconductance cell converts the RF input signal (RF IN When cascaded together for this purpose, the input matching network (M1) is connected to one of the input junctions of the transconductance cells.

[0018] In one or more embodiments, the AC RF output current (I) output from one of the transconductance cells among the plurality of transconductance cells RF_OUT ) is input to the output matching network (M2), and the load impedance (R L Power is transmitted to the transconductance cells. In some embodiments, when the transconductance cells are cascaded together for the AC RF output current, the output matching network (M2) is connected to the input junction of one of the transconductance cells.

[0019] In at least one embodiment, the power supply voltage (Vdd) is evenly distributed among the transconductance cells to power them. In some embodiments, the DC supply voltage drop across each of the transconductance cells is Vdd / N, where N is the number of transconductance cells.

[0020] In one or more embodiments, a high-voltage multistage signal amplifier comprises a plurality of transconductance cells in the first stage, each of which receives a direct current (DC) supply current (Idc) and an alternating current (AC) radio frequency (RF) input current (Idc). RF_IN ), and RF input signal (RF IN ) are configured to receive a DC supply current (Idc) and an AC RF output current (Idc), respectively. RF_OUT The amplifier includes a plurality of transconductance cells in the first stage, each configured to output a direct current (DC) supply current (Idc) and an alternating current (AC) radio frequency (RF) input current (Idc). RF_IN ), and RF input signal (RF IN ) are configured to receive a DC supply current (Idc) and an AC RF output current (Idc), respectively. RF_OUT The system includes a plurality of transconductance cells in the second stage, configured to output an RF input signal (RF). In one or more embodiments, the transconductance cells in the first stage are cascoded to each other for a DC supply current (Idc) and an RF input signal (RF). IN They are connected in parallel (or cascaded) to each other for the purpose of AC RF output current (I RF_OUT They are connected in parallel (or cascaded) to each other for the RF input signal (RF). In at least one embodiment, the transconductance cells of the second stage are cascoded to each other for the DC supply current (Idc) and the RF input signal (RF IN They are connected in parallel (or cascaded) to each other for the purpose of AC RF output current (I RF_OUT They are connected in parallel (or cascaded) to each other for the purpose of supplying DC current. In some embodiments, the first stage and the second stage are cascoded to each other for the purpose of supplying DC current.

[0021] In one or more embodiments, the power supply voltage (Vdd) is evenly distributed among the transconductance cells of the first and second stages to power the transconductance of the first and second stages. In one or more embodiments, the DC supply voltage drop across each of the transconductance cells of the first and second stages is Vdd / N, where N is the number of transconductance cells of the first and second stages.

[0022] In at least one embodiment, the amplifier receives an RF input signal (RF IN The system further includes an input signal source (Vin) that provides an RF input signal (RF) to the input matching network (M1). In at least one embodiment, the input matching network (M1) is a single-input single-output matching network. In some embodiments, the input matching network (M1) is an RF input signal (RF IN ) is converted to provide power matching to each input of the first stage transconductance cell.

[0023] In at least one embodiment, the AC RF output current (I) is output from at least one transconductance cell among the plurality of transconductance cells of the first stage. RF_OUT The AC RF output current (I) is input to the internal stage matching network (M2) and power is transferred to the transconductance cells of the second stage. In one or more embodiments, the AC RF output current (I) is output from at least one transconductance cell among the plurality of transconductance cells of the second stage. RF_OUT ) is input to the output matching network (M3), and the load (R L Power is transmitted to the ). In some embodiments, the output matching network (M3) is a single-input single-output matching network.

[0024] In one or more embodiments, a method for operating a high-voltage signal amplifier involves supplying each transconductance cell with a direct current (DC) supply current (Idc) and an alternating current (AC) radio frequency (RF) input current (Idc) to each transconductance cell of a plurality of transconductance cells. RF_IN ), and RF input signal (RF INThis method includes inputting a DC supply current (Idc) and an AC RF output current (Idc) through each of the transconductance cells among the multiple transconductance cells. RF_OUT This further includes outputting a DC RF output. In one or more embodiments, transconductance cells are cascoded to each other for DC supply current and cascaded to each other for AC input signal and AC RF output current.

[0025] In one or more embodiments, the method further includes supplying power to the transconductance cells by equally distributing the power supply voltage (Vdd) among the transconductance cells. In at least one embodiment, the DC supply voltage drop across each of the transconductance cells is Vdd / N, where N is the number of transconductance cells.

[0026] In at least one embodiment, the method uses an input signal source (Vin) to input an RF input signal (RF IN This further includes providing the RF input signal (RF) to the input matching network (M1). In some embodiments, the input matching network (M1) is a single-input single-output matching network. In one or more embodiments, the input matching network (M1) provides the RF input signal (RF) to the input matching network (M1). IN This further includes converting the values ​​to provide power matching to each input of the transconductance cell.

[0027] In one or more embodiments, the method uses the AC RF output current (I) output from the last transconductance cell of a plurality of transconductance cells. RF_OUT ) is input to the output matching network (M2), and the load impedance (R L This further includes transmitting power to the ). In some embodiments, the output matching network (M2) is a single-input single-output matching network.

[0028] In at least one embodiment, each of the transconductance cells includes a metal-oxide-silicon field-effect transistor (MOSFET). In several embodiments, each of the transconductance cells includes a bipolar junction transistor (BJT).

[0029] In one or more embodiments, the high-voltage signal amplifier comprises a plurality of transconductance cells, each of which receives a direct current (DC) supply current (Idc) and an alternating current (AC) radio frequency (RF) input current (Idc). RF_IN ), and RF input signal (RF IN ) are configured to receive a DC supply current (Idc) and an AC RF output current (Idc), respectively. RF_OUT The system includes a plurality of transconductance cells configured to output a DC supply current. In at least one embodiment, the transconductance cells are cascoded to each other for the DC supply current and cascaded to each other for the AC RF input current and the AC RF output current.

[0030] In at least one embodiment, each of the transconductance cells is further configured to receive a power supply voltage (Vdd), which is evenly distributed among the transconductance cells to power them. In some embodiments, the DC supply voltage drop across each of the transconductance cells is Vdd / N, where N is the number of transconductance cells.

[0031] In one or more embodiments, the amplifier further includes an input matching network (M1). In some embodiments, the amplifier receives an RF input signal (RF IN The system further includes an input signal source (Vin) that provides an RF input signal (RF) to the input matching network (M1). In at least one embodiment, the input matching network (M1) provides an RF input signal (RF IN ) is configured to convert and provide power matching to each input of the transconductance cell.

[0032] In at least one embodiment, the amplifier outputs an AC RF output current (I) from the last transconductance cell of a plurality of transconductance cells. RF_OUT ) receives the load impedance (R L The system further includes an output matching network (M2) configured to transmit power to the ).

[0033] In one or more embodiments, a method for operating a high-voltage multistage signal amplifier involves supplying each transconductance cell of a plurality of transconductance cells in the first stage with a DC supply current (Idc) and an AC RF input current (Idc). RF_IN ), and RF input signal (RF IN This method includes inputting a DC supply current (Idc) and an AC RF input current (Idc) to each of the multiple transconductance cells in the second stage. RF_IN ), and RF input signal (RF IN The method further includes inputting ). The method also includes inputting a DC supply current (Idc) and an AC RF output current (Idc) through each of the transconductance cells among the multiple transconductance cells of the first stage. RF_OUT This method includes outputting a DC supply current (Idc) and an AC RF output current (Idc) through each of the transconductance cells among the multiple transconductance cells of the second stage. RF_OUT This includes outputting a DC supply current. In one or more embodiments, the transconductance cells of the first stage are cascoded with each other for the DC supply current and cascaded with each other for the AC RF input current and AC RF output current. In at least one embodiment, the transconductance cells of the second stage are cascoded with each other for the DC supply current and cascaded with each other for the AC RF input current and AC RF output current. In some embodiments, the first stage and the second stage are cascoded with each other for the DC supply current and cascaded with each other for the AC RF input current and AC RF output current.

[0034] In at least one embodiment, the method further includes distributing the power supply voltage (Vdd) equally among the first and second stage transconductance cells to supply power to the first and second stage transconductances. In some embodiments, the DC supply voltage drop across each of the first and second stage transconductance cells is Vdd / N, where N is the number of first and second stage transconductance cells.

[0035] In one or more embodiments, the method uses an input signal source (Vin) to input an RF input signal (RF IN The method further includes providing the RF input signal (RF) to an input matching network (M1). In some embodiments, the input matching network (M1) is a single-input single-output matching network. In at least one embodiment, the method uses the input matching network (M1) to provide the RF input signal (RF) to an input matching network (M1). IN The method further includes converting the values ​​to provide power matching to each input of the transconductance cell of the first stage.

[0036] In at least one embodiment, the method outputs an AC RF output current (I) from the last conductance cell of a plurality of transconductance cells in the first stage. RF_OUT This further includes inputting the power to an internal stage matching network (M2) to transfer power to the transconductance cells of the second stage. In some embodiments, the internal stage matching network (M2) is a single-input, single-output matching network.

[0037] In one or more embodiments, the method uses the AC RF output current (I) output from the last transconductance cell of the plurality of transconductance cells in the second stage. RF_OUT ) is input to the output matching network (M3) and the load (R L This further includes transmitting power to the ). In some embodiments, the output matching network (M3) is a single-input single-output matching network.

[0038] In at least one embodiment, the high-voltage multistage signal amplifier comprises a plurality of transconductance cells in the first stage, each of which has a direct current (DC) supply current (Idc) and an alternating current (AC) radio frequency (RF) input current (Idc). RF_IN ), and RF input signal (RF IN ) are configured to receive a DC supply current (Idc) and an AC RF output current (Idc), respectively. RF_OUT The amplifier includes a plurality of transconductance cells in the first stage, configured to output a DC supply current (Idc) and an AC RF input current (Idc). In one or more embodiments, the transconductance cells in the first stage are cascoded to each other for the DC supply current and cascaded to each other for the AC RF input current and the AC RF output current. The amplifier includes a plurality of transconductance cells in the second stage, each configured to output a DC supply current (Idc) and an AC RF input current (Idc). RF_IN ), and RF input signal (RF IN ) are configured to receive a DC supply current (Idc) and an AC RF output current (Idc), respectively. RF_OUT The system includes a plurality of transconductance cells in the second stage configured to output ). In one or more embodiments, the transconductance cells in the second stage are cascoded to each other for the DC supply current and cascaded to each other for the AC RF input current and AC RF output current. In some embodiments, the first stage and the second stage are cascoded to each other for the DC supply current and cascaded to each other for the AC RF input current and AC RF output current.

[0039] In one or more embodiments, each of the first and second stage transconductance cells is configured to receive a supply voltage (Vdd), which is evenly distributed among the first and second stage transconductance cells to power them. In some embodiments, the DC supply voltage drop across each of the first and second stage transconductance cells is Vdd / N, where N is the number of first and second stage transconductance cells.

[0040] In at least one embodiment, the amplifier further includes an input matching network (M1). In some embodiments, the amplifier receives an RF input signal (RF IN The system further includes an input signal source (Vin) that provides an RF input signal (RF) to the input matching network (M1). In at least one embodiment, the input matching network (M1) provides an RF input signal (RF IN It is configured to convert the signal to provide power matching to each input of the first stage transconductance cell.

[0041] In one or more embodiments, the amplifier outputs an AC RF output current (I) from the last transconductance cell of the first stage transconductance cell. RF_OUT The system further includes an internal stage matching network (M2) configured to receive the power and transfer it to the transconductance cells of the second stage.

[0042] In at least one embodiment, the amplifier outputs an AC RF output current (I) from the last transconductance cell of the second stage transconductance cell. RF_OUT ) receives the load (R L It further includes an internal stage matching network (M3) configured to transmit power to the ).

[0043] Features, functions, and benefits can be realized individually in various embodiments of this disclosure, or combined in yet another embodiment.

[0044] The above and other features, aspects, and advantages of this disclosure will be better understood by the following description, claims, and accompanying drawings. [Brief explanation of the drawing]

[0045] [Figure 1] This is a schematic circuit diagram of a conventional two-stage amplifier, in which the second stage utilizes vertically stacked devices and includes a parallel input and parallel output power coupling network. [Figure 2] Figure 1 shows an example of a conventional two-stage amplifier, with a layout diagram of the fabricated integrated circuit (IC). [Figure 3] This is a schematic circuit diagram of a conventional single-stage amplifier, which utilizes vertically stacked devices that perform "voltage-mode coupling" and includes a single-input single-output input matching network and a single-input single-output output matching network. [Figure 4] Figure 3 shows the Class A bias of a conventional single-stage amplifier with "voltage mode coupling". [Figure 5A] This is a schematic circuit diagram of a disclosed single-ended, single-stage "current-mode" amplifier according to at least one embodiment of the present disclosure. [Figure 5B] This is a schematic circuit diagram of a disclosed single-ended, single-stage "current-mode" amplifier according to at least one embodiment of the present disclosure. [Figure 5C] Figure 5A is a schematic circuit diagram of the single-stage "current-mode" amplifier disclosed in at least one embodiment of the present disclosure, showing a cascode connection of transconductance cells for DC supply current. [Figure 5D] Figure 5A is a schematic circuit diagram of the single-stage "current-mode" amplifier disclosed in at least one embodiment of the present disclosure, showing a cascaded connection of transconductance cells for AC RF input current and AC RF output current. [Figure 5E] Figure 5A is a schematic circuit diagram of the single-stage "current-mode" amplifier disclosed in at least one embodiment of the present disclosure, showing an input matching network (M1) that drives the RF input signals (RFIN) of each transconductance cell in parallel. [Figure 5F] This flowchart shows a disclosed method for the operation of a disclosed single-ended, single-stage "current-mode" amplifier according to at least one embodiment of the present disclosure. [Figure 6A]A schematic circuit diagram of a disclosed single-ended, single-stage "current-mode" amplifier according to at least one embodiment of the present disclosure, wherein the transconductance cell is implemented as a common source cell including an RF unit device, in particular an n-channel MOSFET (NMOS), as a metal-oxide-semiconductor field-effect transistor (MOSFET). [Figure 6B] A schematic circuit diagram of a disclosed single-ended, single-stage "current-mode" amplifier according to at least one embodiment of the present disclosure, wherein the transconductance cell is implemented as a common source cell including an RF unit device, in particular an n-channel MOSFET (NMOS), as a metal-oxide-semiconductor field-effect transistor (MOSFET). [Figure 7A] A schematic circuit diagram of a disclosed single-ended, single-stage "current-mode" amplifier according to at least one embodiment of the present disclosure, in which the transconductance cell is implemented as a common source cell including an RF unit element device, in particular as an n-channel MOSFET (NMOS). [Figure 7B] A schematic circuit diagram of a disclosed single-ended, single-stage "current-mode" amplifier according to at least one embodiment of the present disclosure, in which the transconductance cell is implemented as a common source cell including an RF unit element device, in particular as an n-channel MOSFET (NMOS). [Figure 8] Figures 5A and 5B, 6A and 6B, and 7A and 7B show the Class A bias of a "current-mode" amplifier according to at least one embodiment of the present disclosure. [Figure 9A] This is a schematic circuit diagram of a disclosed single-ended "current-mode" differential amplifier according to at least one embodiment of the present disclosure. [Figure 9B] This is a schematic circuit diagram of a disclosed single-ended "current-mode" differential amplifier according to at least one embodiment of the present disclosure. [Figure 10A]A schematic circuit diagram of a disclosed single-stage "current-mode" differential amplifier according to at least one embodiment of the present disclosure is shown, in which the transconductance cell is implemented as a common source cell including an RF unit element device as a MOSFET, in particular as an n-channel MOSFET (NMOS). [Figure 10B] A schematic circuit diagram of a disclosed single-stage "current-mode" differential amplifier according to at least one embodiment of the present disclosure is shown, in which the transconductance cell is implemented as a common source cell including an RF unit element device as a MOSFET, in particular as an n-channel MOSFET (NMOS). [Figure 10C] A schematic circuit diagram of a disclosed single-stage "current-mode" differential amplifier according to at least one embodiment of the present disclosure is shown, in which the transconductance cell is implemented as a common source cell including an RF unit element device as a MOSFET, in particular as an n-channel MOSFET (NMOS). [Figure 11A] A schematic circuit diagram of a disclosed multistage "current-mode" amplifier according to at least one embodiment of the present disclosure, where M is the number of transconductance cells in the first stage, N is the number of transconductance cells in the second stage, and a power supply voltage (Vdd) is applied to the first transconductance cells. [Figure 11B] A schematic circuit diagram of a disclosed multistage "current-mode" amplifier according to at least one embodiment of the present disclosure, where M is the number of transconductance cells in the first stage, N is the number of transconductance cells in the second stage, and a power supply voltage (Vdd) is applied to the first transconductance cells. [Figure 11C] A schematic circuit diagram of a disclosed multistage "current-mode" amplifier according to at least one embodiment of the present disclosure, where M is the number of transconductance cells in the first stage, N is the number of transconductance cells in the second stage, and a power supply voltage (Vdd) is applied to the first transconductance cells. [Figure 12A]A schematic circuit diagram of a disclosed multistage "current-mode" amplifier according to at least one embodiment of the present disclosure, where M is the number of transconductance cells in the first stage, N is the number of transconductance cells in the second stage, and the power supply voltage (Vdd) is applied to transconductance cells different from the first transconductance cells. [Figure 12B] A schematic circuit diagram of a disclosed multistage "current-mode" amplifier according to at least one embodiment of the present disclosure, where M is the number of transconductance cells in the first stage, N is the number of transconductance cells in the second stage, and the power supply voltage (Vdd) is applied to transconductance cells different from the first transconductance cells. [Figure 12C] A schematic circuit diagram of a disclosed multistage "current-mode" amplifier according to at least one embodiment of the present disclosure, where M is the number of transconductance cells in the first stage, N is the number of transconductance cells in the second stage, and the power supply voltage (Vdd) is applied to transconductance cells different from the first transconductance cells. [Figure 13] A schematic circuit diagram of a disclosed single-ended, single-stage "current-mode" amplifier according to at least one embodiment of the present disclosure, wherein transconductance cells are connected in parallel to each other for a high-frequency (RF) input signal (RFIN) and for an alternating-frequency (AC) RF output current (IRF_OUT). [Figure 14A] A schematic circuit diagram of a disclosed single-ended, single-stage "current-mode" amplifier according to at least one embodiment of the present disclosure, wherein transconductance cells are connected in parallel to each other for an RF input signal (RFIN) and cascaded to each other for an AC RF output current (IRF_OUT), and an output matching network (M2) is connected to the output junction of the first transconductance cell 1310a. [Figure 14B]A schematic circuit diagram of a disclosed single-ended, single-stage "current-mode" amplifier according to at least one embodiment of the present disclosure, wherein transconductance cells are connected in parallel to each other for an RF input signal (RFIN) and cascaded to each other for an AC RF output current (IRF_OUT), and an output matching network (M2) is connected to the output junction of a second transconductance cell 1310b. [Figure 14C] A schematic circuit diagram of a disclosed single-ended, single-stage "current-mode" amplifier according to at least one embodiment of the present disclosure, wherein transconductance cells are connected in parallel to each other for an RF input signal (RFIN) and cascaded to each other for an AC RF output current (IRF_OUT), and an output matching network (M2) is connected to the output junction of a third transconductance cell 1310c. [Figure 14D] A schematic circuit diagram of a disclosed single-ended, single-stage "current-mode" amplifier according to at least one embodiment of the present disclosure, wherein transconductance cells are connected in parallel to each other for an RF input signal (RFIN) and cascaded to each other for an AC RF output current (IRF_OUT), and an output matching network (M2) is connected to the output junction of the last transconductance cell 1310d. [Figure 14E] Figure 14D is an illustrative detailed circuit diagram of the amplifier shown, according to at least one embodiment of the present disclosure. [Figure 15A] A schematic circuit diagram of a disclosed single-ended, single-stage "current-mode" amplifier according to at least one embodiment of the present disclosure, wherein transconductance cells are cascaded to one another for an RF input signal (RFIN) and connected in parallel to one another for an AC RF output current (IRF_OUT), and an input matching network (M1) is connected to the input junction of a first transconductance cell 1310a. [Figure 15B]A schematic circuit diagram of a disclosed single-ended, single-stage "current-mode" amplifier according to at least one embodiment of the present disclosure, wherein transconductance cells are cascaded to one another for an RF input signal (RFIN) and connected in parallel to one another for an AC RF output current (IRF_OUT), and an input matching network (M1) is connected to the input junction of a second transconductance cell 1310b. [Figure 15C] A schematic circuit diagram of a disclosed single-ended, single-stage "current-mode" amplifier according to at least one embodiment of the present disclosure, wherein transconductance cells are cascaded to one another for an RF input signal (RFIN) and connected in parallel to one another for an AC RF output current (IRF_OUT), and an input matching network (M1) is connected to the input junction of a third transconductance cell 1310c. [Figure 15D] A schematic circuit diagram of a disclosed single-ended, single-stage "current-mode" amplifier according to at least one embodiment of the present disclosure, wherein transconductance cells are cascaded to one another for an RF input signal (RFIN) and connected in parallel to one another for an AC RF output current (IRF_OUT), and an input matching network (M1) is connected to the input junction of the last transconductance cell 1310d. [Figure 16A] A schematic circuit diagram of a disclosed single-ended, single-stage "current-mode" amplifier according to at least one embodiment of the present disclosure, wherein transconductance cells are cascaded to each other for an RF input signal (RFIN) and cascaded to each other for an AC RF output current (IRF_OUT), an input matching network (M1) is connected to the input junction of a first transconductance cell 1310a, and an output matching network (M2) is connected to the output junction of a last transconductance cell 1310d. [Figure 16B]A schematic circuit diagram of a disclosed single-ended, single-stage "current-mode" amplifier according to at least one embodiment of the present disclosure, wherein transconductance cells are cascaded to each other for an RF input signal (RFIN) and cascaded to each other for an AC RF output current (IRF_OUT), an input matching network (M1) is connected to the input junction of a second transconductance cell 1310b, and an output matching network (M2) is connected to the output junction of the second transconductance cell 1310b. [Figure 16C] A schematic circuit diagram of a disclosed single-ended, single-stage "current-mode" amplifier according to at least one embodiment of the present disclosure, wherein transconductance cells are cascaded to each other for an RF input signal (RFIN) and cascaded to each other for an AC RF output current (IRF_OUT), an input matching network (M1) is connected to the input junction of the last transconductance cell 1310d, and an output matching network (M2) is connected to the output junction of the first transconductance cell 1310a. [Figure 17] Figures 13 to 16C show schematic schematics illustrating exemplary transconductance cells that may be used for the transconductance cells of the single-ended, single-stage "current-mode" amplifier disclosed in at least one embodiment of the present disclosure, where the transconductance cell is implemented as a common source cell including an RF unit element device as a MOSFET, particularly as an n-channel MOSFET (NMOS). [Figure 18] This flowchart shows a disclosed method for the operation of the single-ended, single-stage "current-mode" amplifier disclosed in Figures 13 to 16C, according to at least one embodiment of the present disclosure. [Figure 19]A schematic circuit diagram of a disclosed multistage "current-mode" amplifier according to at least one embodiment of the present disclosure is shown, where M is the number of transconductance cells in the first stage, N is the number of transconductance cells in the second stage, and the transconductance cells in the first stage and the transconductance cells in the second stage are connected in parallel (or cascaded) with respect to an RF input signal (RFIN) and are connected in parallel (or cascaded) with respect to an AC RF output current (IRF_OUT). [Figure 20A] This flowchart shows a disclosed method for the operation of the multistage "current-mode" amplifier disclosed in Figure 19, according to at least one embodiment of the present disclosure. [Figure 20B] This flowchart shows a disclosed method for the operation of the multistage "current-mode" amplifier disclosed in Figure 19, according to at least one embodiment of the present disclosure. [Figure 21] This schematic circuit diagram shows an exemplary circuit that may be used for a disclosed multistage "current-mode" amplifier according to at least one embodiment of the present disclosure. [Figure 22A] This graph shows the simulation results of the collector current (Ic)-collector-emitter voltage (Vce) of the first stage transistor T1 of the multistage "current-mode" amplifier shown in Figure 21, according to at least one embodiment of the present disclosure. [Figure 22B] This graph shows the simulation results of the Ic / Vce-time (in picoseconds (psec)) of the first stage transistor T1 of the multistage "current-mode" amplifier shown in Figure 21, according to at least one embodiment of the present disclosure. [Figure 23A] This graph shows the simulation results of Ic-Vce of the top transistor T2 of the second stage of the multistage "current-mode" amplifier shown in Figure 21, according to at least one embodiment of the present disclosure. [Figure 23B] This graph shows the simulation results of the Ic / Vce-time (picoseconds) of the top transistor T2 of the second stage of the multi-stage "current-mode" amplifier shown in Figure 21, according to at least one embodiment of the present disclosure. [Figure 24A] This graph shows the simulation results of Ic-Vce of the bottom transistor T3 of the second stage of the multi-stage "current-mode" amplifier shown in Figure 21, according to at least one embodiment of the present disclosure. [Figure 24B] This graph shows the simulation results of the Ic / Vce-time (picoseconds) of the bottom transistor T3 of the second stage of the multi-stage "current-mode" amplifier shown in Figure 21, according to at least one embodiment of the present disclosure. [Figure 25] This graph shows the simulation results of the output current density (Ice)-Vce-input power (Pin) of the second stage transistors T2 and T3 of the multistage "current mode" amplifier shown in Figure 21, according to at least one embodiment of the present disclosure. [Modes for carrying out the invention]

[0046] The methods and apparatus disclosed herein provide an operative system for an amplifier in which vertically stacked transconductance cells are "current mode combining". In one or more embodiments, the system disclosed provides a more compact power amplifier compared to a similar type of conventional parallel input / output structure (see, for example, amplifier 100 in Figure 1) (by including, for example, a single input matching network and a single output matching network (see, for example, (M1) 520 in Figure 5A and (M2) 530 in Figure 5B)). Thus, the disclosed amplifier structure enables a more compact device arrangement, thereby reducing chip area and cost. Furthermore, the disclosed amplifier structure reduces the gate / base loss mechanism of the vertically stacked device (compared to a conventional "voltage mode" vertically stacked device), thereby improving output power and efficiency. Finally, the disclosed amplifier topology can be extended to multi-stage power amplifiers.

[0047] Currently, power amplifiers with power sharing of a series of vertically stacked transistor devices in a "voltage mode combining" state have been proposed to fabricate amplifiers using low breakdown voltage technology for high-voltage fixed supply systems. In the above structure, the total number of vertically stacked devices is limited due to the gate / base resistance losses of the vertically stacked devices, thereby limiting efficiency. Furthermore, in the realization of parallel input / output coupling, a large die area is used by the coupling network. The disclosed approach is a "current mode" realization of the vertically stacked devices, which simplifies the structure to a single input and single output matched / coupled network, thereby reducing the placement size and reducing the losses of the gate / base vertically stacked devices, thereby improving die size, output power, and efficiency.

[0048] Previous solutions proposed a topology of vertically stacked field-effect transistors (FETs), where the gates of the stacked devices are impedance-dependent (i.e., capacitively divided), allowing the gate voltage to follow the source / drain voltage such that the voltage amplitude at each device is below the device's critical breakdown voltage. This approach has the limitation that gate / base resistance losses provide a leakage path for RF current, thereby limiting efficiency. This limitation generally restricts this amplifier approach to FET technology, which can have base resistance losses (as opposed to BJT technology). Furthermore, realizing parallel inputs and outputs in this topology requires a large die area because the coupling network is implemented as a Wilkinson power coupler / distributor (see, e.g., 220 and 230 in Figure 2). Finally, conventional topologies of voltage-mode vertically stacked FETs are entirely dependent on performance related to the absolute value of the gate capacitance, and therefore process changes are not permitted in this topology.

[0049] The systems disclosed herein offer a unique way of coupling the RF currents of devices in a cascaded manner (see, for example, Figure 5D) or in a cascode (see, for example, Figure 5C), i.e., a power-sharing DC (DC) configuration. Note that the term “cascode” is defined herein as “a group of units in which a successive group of units is connected in a series, stacked on top of a first unit,” and is used in that sense throughout this specification. Similarly, the term “cascade” is defined herein as “a group of units in which a successive group of other units is connected in a series, following a first unit,” and is used in that sense throughout this specification. Thus, the configuration obtained for the disclosed systems in this case requires only a single input matching network and a single output matching network. Due to the parallel coupling of devices by the single input matching network, gate / base resistive losses can be ignored by a well-designed matching network. Furthermore, the simplification of the matched network allows for savings in die area due to the simpler matched network. Finally, the disclosed structure reduces the performance dependence on gate / base capacitance values ​​(for example, only a large DC cutoff capacitance is required for the disclosed structure, which allows for process changes).

[0050] The following description includes numerous details to provide a more thorough explanation of the system. However, it will be apparent to those skilled in the art that the disclosed system can be implemented even without these specific details. In other cases, well-known features are not described in detail to avoid unnecessarily complicating the system.

[0051] Embodiments of the Disclosure may be described herein in terms of functional and / or logical components and various processing steps. Such components can be realized by any number of hardware, software, and / or firmware components configured to perform specific functions. For example, embodiments of the Disclosure may utilize various integrated circuit components (e.g., memory elements, digital signal processing elements, logic elements, lookup tables, etc.), which can perform various functions under the control of one or more processors, microprocessors, or other control devices. Furthermore, those skilled in the art will understand that embodiments of the Disclosure can be implemented in combination with other components, and that the systems described herein are merely exemplary embodiments of the Disclosure.

[0052] For the sake of brevity, prior art and components relating to signal amplifiers, as well as other functional aspects of the overall system, may not be described in detail herein. Furthermore, the connecting lines shown in the various drawings contained herein are intended to illustrate exemplary functional relationships and / or physical connections between various elements. Note that many alternative or additional functional relationships or physical connections may exist in one or more embodiments of this disclosure.

[0053] Figure 1 is a schematic circuit diagram of a conventional two-stage amplifier 100, in which the second stage (i.e., stage 2) utilizes vertically stacked devices (e.g., unit element FET devices 110a, 110b, 110c, 110d) and includes a parallel input power coupling network and a parallel output power coupling network (e.g., an interstage power distribution network 120 and an output matching / coupling network 130). Specifically, the conventional two-stage amplifier 100 in Figure 1 utilizes a current-sharing vertically stacked device structure, in which a high voltage supply (Vs) is distributed across a cascode of common source cells, each containing unit element FET devices 110a, 110b, 110c, and 110d. The power supply voltage (Vs) (e.g., 24 volts) is distributed across the drain and source of each unit element FET device 110a, 110b, 110c, and 110d, mitigating voltage breakdown in the unit element FET devices 110a, 110b, 110c, and 110d. A shared DC drain-source current (i.e., "current sharing") exists through each shared source cell and the unit element FET devices 110a, 110b, 110c, and 110d. Specifically, this structure exhibits a two-stage (i.e., stage 1 and stage 2) configuration, where the fan-out of the devices from stage to stage is 1-4. The second stage of amplifier 100 (i.e., Stage 2) utilizes a 1-input, 4-output power splitter (i.e., interstage power distribution network 120) and a power coupler (i.e., output matching / coupling network 130) to distribute the input power and couple the output power of the four unit element FET devices 110a, 110b, 110c, and 110d of the second stage. Note that in amplifier 100 in Figure 1, the FET devices 110a, 110b, 110c, and 110d are cascoded for the DC supply current (flowing down through the devices) and in parallel (not cascaded) for the AC RF signals (e.g., AC RF input current and AC RF output current) (flowing through the devices).

[0054] Figure 2 shows an exemplary fabricated IC arrangement 200 of the conventional two-stage amplifier 100 of Figure 1. In Figure 2, the power splitter (i.e., interstage power distribution network 120) and power coupler (i.e., output matching / coupling network 130) of the amplifier 100 of Figure 1 are implemented by a Wilkinson-type splitter 220 and a Wilkinson-type coupler 230, respectively. While this structure demonstrates an approach to achieving a low-failure device in high-voltage systems using power-sharing vertical stacking FET technology, it has the disadvantage of requiring a large IC area due to the use of large power splitters and couplers.

[0055] Figure 3 is a schematic circuit diagram of a conventional single-stage amplifier 300, which utilizes voltage-mode coupled vertically stacked devices (i.e., unit element FET devices 310a, 310b, 310c, 310d) and includes a single-input single-output input matching network (M1) 320 and a single-input single-output output matching network (2) 330. The amplifier 300 in Figure 3 has a similar structure to the amplifier 100 in Figure 1, where the high voltage supply is distributed through the drain and source of the cascode-connected unit element FET devices 310a, 310b, 310c, and 310d, thereby reducing device failure and sharing a shared DC current (Idc) through each unit element FET device 310a, 310b, 310c, and 310d.

[0056] Specifically, Figure 3 shows a single-stage amplifier 300, in which a single-input single-output input matching network (M1) 320 drives a single unit element transconductance device, which generates a shared alternating current (AC) current (irf) through each unit element FET device 310a, 310b, 310c, and 310d. Following the bottom transconductance unit element FET device 310d is a cascode-connected unit element FET device 310c, where an optionally adjustable gate capacitance (C1) forms a voltage divider between the drain-gate capacitance and gate-source capacitance of the cascode-connected unit element FET device 310c, thereby ensuring that the device breakdown voltage is never exceeded over the RF cycle.

[0057] Note that in amplifier 300 in Figure 3, the FET devices 310a, 310b, 310c, and 310d are cascode-connected for the DC supply current (Idc) (flowing down through the device) and cascode-connected (not cascaded) for the AC RF signal (irf) (flowing down through the device).

[0058] To achieve the desired output power, the gate capacitance (Cn) of each cascode unit element FET device is scaled up with each additional cascode, and the source impedance of that cascode unit element FET device is scaled up accordingly (Ropt is a function of Cn), thereby scaling up the voltage amplitude at the unit element FET devices 310a, 310b, and 310c, because the cascode source voltage amplitude is proportional to Ropt·irf. As each additional cascode unit element FET device 310a, 310b, and 310c is added, Cn is scaled up accordingly, increasing the drain, gate, and source voltage amplitudes of each cascode unit element FET device 310a, 310b, and 310c. A single-input single-output output matching network (M2) 330 is used to provide NRopt to the drain of the last cascode unit element FET device 310a. This structure allows amplifier 300 to be said to be driven in "voltage-mode coupling" because the voltage amplitude is scaled by each additional cascode, thereby ensuring that the drain-gate and gate-source of each unit element FET device 310a, 310b, and 310c never exceed Vdd / N (set as the device breakdown voltage) while simultaneously generating a large output voltage amplitude.

[0059] For Class A operation of the "voltage mode" amplifier 300, and when driving a peak input signal, the AC current amplitude of IRF is Idc, where the peak current 2·Idc is transmitted to the output matching network (M2) 330. The AC voltage amplitude of VRF is Vdd, and the peak voltage amplitude is 2·Vdd.

[0060] Figure 4 shows the voltage-mode coupled Class A bias of the conventional single-stage amplifier 300 from Figure 3. For ideal Class A operation of the amplifier 300 from Figure 3, as shown in Figure 4, the efficiency of this structure approaches 50 percent (%), neglecting non-ideal losses. As shown in Figure 4, the peak drain voltage of the last Nth cascode unit element FET device 310a is 2·Vdd, providing a large output voltage amplitude.

[0061] Referring back to Figure 3, the voltage mode structure of the conventional amplifier 300 has the advantage of having a single-input single-output input matching network (M1) 320 and a single-input single-output output matching network (M2) 330, and since these each contain only a single input and a single output, it is possible to reduce the IC placement area.

[0062] However, this structure has several drawbacks. The first drawback of amplifier 300 is that the capacitance division of the "floating gate" described earlier is only possible in FET technology that does not have a resistive gate / base with high losses. For example, BJT bipolar unit element devices that include a resistive base are not feasible for this structure. Therefore, this topology is limited to complementary metal-oxide-semiconductor (CMOS) FET type unit element devices (e.g., 310a, 310b, 310c, 310d).

[0063] The second drawback of amplifier 300 is that, due to the Cn path to ground, any resistive losses from the gate allow for power loss from the floating gate signal, which reduces the output power efficiency. Again, this limitation prevents the use of other resistive gate / base unit element devices.

[0064] A third drawback of amplifier 300 is that the voltage breakdown reliability of this structure for each unit element FET device (e.g., 310a, 310b, 310c, 310d) depends on the precise adjustment of the gate capacitance (Cn), which raises concerns regarding reliability in the event of process manufacturing changes.

[0065] A fourth disadvantage of amplifier 300 is that the "voltage mode" mechanism of this structure further limits the reliability of unit element FET devices (e.g., 310a, 310b, 310c, 310d) because the voltage amplitude can be 2·Vdd. Specifically, for bulk CMOS devices, the drain and source-body junction diodes for large voltage amplitudes can generate nonlinear distortion, limiting the linear performance of the power amplifier (PA). In extreme cases of large voltage amplitudes, the junction may fail, damaging the device. This mechanism often limits the technology to complementary metal-oxide-semiconductor (CMOS-SOI), which reduces the need for parasitic body junction diodes for unit element FET devices (e.g., 310a, 310b, 310c, 310d). Therefore, conventional amplifiers 100, 300 that utilize vertically stacked devices including power coupling networks, or "voltage-mode" coupling, are severely limited in terms of IC placement area or reliability, which incentivizes the design of the systems of this disclosure that alleviate the aforementioned limitations.

[0066] Figures 5A and 5B are schematic circuit diagrams of the disclosed single-ended, single-stage "current-mode" amplifier 500 according to at least one embodiment of the present disclosure. The disclosed amplifier 500 utilizes a DC cascode of transconductance cells 510a, 510b, 510c, and 510d, which share a common current (Idc) and distribute a power supply voltage (Vdd) across the transconductance cells 510a, 510b, 510c, and 510d, thereby reducing concerns regarding voltage reliability. The amplifier 500 receives parallel RF input signals (RF IN ) has control, while each of the transconductance cells 510a, 510b, 510c, and 510d has cascade output RF current (I RF_OUT), whereby the amplifier 500 is defined as operating in "current mode". Since a single input / output matching network (e.g., a single-input single-output input matching network (M1) 520, and a single-input single-output output matching network (M2) 530) can be used, the disclosed amplifier 500 reduces the aforementioned concerns regarding the large integrated circuit layout area occupied by power distribution / combining networks, and further alleviates concerns regarding voltage amplitude reliability because large voltage amplitudes are not present.

[0067] The disclosed amplifier 500 utilizes a cascode stack of "N" unit transconductance cells 510a, 510b, 510c, 510d, each of which receives as inputs a supply current (Idc), an AC RF input current (I RF_IN ), and an RF input signal (RFIN), and outputs as outputs a DC current (Idc) and an AC RF output current (I RF_OUT ) respectively. In terms of DC input current and DC output current, the transconductance cells 510a, 510b, 510c, 510d are connected in cascode, whereby a common current (Idc) is shared between each of the transconductance cells 510a, 510b, 510c, 510d, and the DC supply voltage drop across each of the transconductance cells 510a, 510b, 510c, 510d is Vdd / N. The transconductance cells 510a, 510b, 510c, 510d are connected such that the output current (I RF_OUT ) of each transconductance cell serves as the input to the input current (I RF_IN ) of a subsequent cascaded transconductance cell. An input signal source (Vin) (with a source resistance (Rs)) is followed by an input matching network (M1) 520, which drives the RF input signals (RF IN ) of each transconductance cell in parallel. The final output current (I RF_OUT ) of the last transconductance cell 510d is applied to the output matching network (M2) 520 to a load impedance (RL ) electric power is transmitted.

[0068] FIG. 5C is a schematic circuit diagram of the disclosed single-stage "current mode" amplifier 500 of FIG. 5A, according to at least one embodiment of the present disclosure, showing a cascode connection of transconductance cells 510a, 510b, 510c for a DC supply current (Idc). Note that, as mentioned previously, the term "cascode" is defined herein as "a plurality of units (e.g., transconductance cells), wherein subsequent plurality of units are consecutively connected in "stacked" arrangement stacked on top of a first unit", and is used throughout this specification to have this meaning.

[0069] FIG. 5D is a schematic circuit diagram of the disclosed single-stage "current mode" amplifier 500 of FIG. 5A, according to at least one embodiment of the present disclosure, showing a cascade connection of transconductance cells 510a, 510b, 510c for an AC RF input current (I RF_IN ) and an AC RF output current (I RF_OUT ). As mentioned previously, the term "cascade" is defined herein as "a plurality of units (e.g., transconductance cells), wherein a plurality of other units are consecutively connected "in series" subsequent to a first unit", and is used throughout this specification to have this meaning.

[0070] FIG. 5E is a schematic circuit diagram of the disclosed single-stage "current mode" amplifier 500 of FIG. 5A, according to at least one embodiment of the present disclosure, showing an input matching network (M1) 520 that drives an input signal (RF IN ) of each of the transconductance cells 510a, 510b, 510c in parallel.

[0071] Figure 5F is a flowchart illustrating a disclosed method for the operation 505 of a disclosed single-ended single-stage "current-mode" amplifier (e.g., amplifier 500 in Figures 5A and 5B) according to at least one embodiment of the present disclosure. In the start 515 of the disclosed method 505, the DC supply current (Idc) and the AC RF input current (Idc) are used. RF_IN ), and RF input signal (RF IN All of the above is input to each transconductance cell of the multiple transconductance cells (525). In addition, each transconductance cell of the multiple transconductance cells receives the DC supply current (Idc) and the AC RF output current (I RF_OUT ) outputs. In one or more embodiments, the transconductance cells are cascoded to each other for the DC supply current (Idc) (see Figure 5C) and cascaded to each other for the AC RF input current and AC RF output current (see Figure 5D) (535). Method 505 then ends (545).

[0072] Note that in one or more embodiments of this disclosure, the disclosed amplifiers (e.g., 500 in Figures 5A and 5B, 600 in Figures 6A and 6B, and 700 in Figures 7A and 7B) implement each transconductance cell as a common source unit / common emitter unit. Each common source unit stage / common emitter unit stage has an RF unit device, which can be implemented using any device technology (e.g., as an FET device in amplifier 600 in Figures 6A and 6B, or as a BJT device in amplifier 700 in Figures 7A and 7B). For example, Figures 6A and 6B are schematic circuit diagrams of the disclosed single-ended single-stage "current-mode" amplifier 600 according to at least one embodiment of this disclosure, where the transconductance cells 610a, 610b, 610c, and 610d are implemented as a common source cell including an RF unit device as a MOSFET, particularly as an NMOS. Furthermore, Figures 7A and 7B are schematic circuit diagrams of the disclosed single-ended, single-stage "current-mode" amplifier 700 according to at least one embodiment of the present disclosure, in which the transconductance cells 710a, 710b, 710c, and 710d are realized by a shared emitter cell and an RF unit element device as a BJT.

[0073] For the disclosed amplifiers 500, 600, and 700, each RF unit element device (e.g., NMOS or BJT) within a common source / common emitter element (e.g., transconductance cells 510a, 510b, 510c, 510d) has a drain-source (or collector-emitter) DC voltage Vdd / N, and this drain-source (or collector-emitter) DC voltage Vdd / N is equal to the power supply Vdd and the N inductors (L ∞ The DC current (Idc) is provided by a DC series connection consisting of a power supply (Vdd) and N unit element common source / emitter cells (e.g., transconductance cells 510a, 510b, 510c, 510d) containing RF unit element devices (e.g., NMOS or BJT). The common DC current (Idc) is provided by the power supply (Vdd) and the N inductive elements (L ∞) is shared through a series connection consisting of N unit element common source / emitter stages (e.g., transconductance cells 510a, 510b, 510c, 510d) containing RF unit element devices (e.g., NMOS or BJT). The DC bias of each RF unit element device (e.g., NMOS or BJT) is provided by a voltage (VbiasN) and a large gate / base bias resistor (Rb), thereby allowing each unit element device (e.g., NMOS or BJT) to be biased individually, and ensuring the current Idc and the nominal distribution of the Vdd voltage at each unit element drain / source or collector / emitter.

[0074] The input RF signal after the single-input single-output input matching network (M1) 520 passes through the gate / base of each unit element device (e.g., NMOS or BJT) to a large capacitance capacitor (C) that allows RF to pass through the gate / base of each unit element in a common source / emitter cell. ∞ They are driven in parallel via a common source / emitter cell (e.g., transconductance cells 510a, 510b, 510c, 510d). Within a common source / emitter cell (e.g., transconductance cells 510a, 510b, 510c, 510d), each unit element device (e.g., NMOS or BJT) acts as a common source / emitter transconductor and a large source / emitter capacitor (C) to ground. ∞ ) and drain / collector RF induction choke (L ∞ ) and, including, the input RF signal from the input source (Vin) is transformed through a single-input single-output input matching network (M1) 520 to drive the gate / base of each common source / emitter unit element in parallel, generating an AC current irf from the drain / collector of each unit element device. The output AC current of each unit element device (e.g., NMOS or BJT) is then used to power a large-capacity RF capacitor (C ∞ The RFs are combined through a series connection of the 530, thereby generating the total AC output current N·irf. The total AC output current (N·irf) is supplied by the load impedance R through the single input single output output matching network (M2) 530. LThe impedance Ropt / N (e.g., a resistance value selected to optimize power and efficiency) converted from is presented. In the peak input power drive of the amplifier, the total AC output current has an amplitude swing N·Idc, where the peak current amount transmitted to Ropt / N is (N+1)·Idc, thereby generating an amplitude swing Vdd / N of the AC voltage and a peak amount of 2Vdd / N.

[0075] Figure 8 shows the Class A bias of the "current-mode" amplifiers 500, 600, and 700 of Figures 5A and 5B, 6A and 6B, and 7A and 7B, according to at least one embodiment of the present disclosure. For ideal Class A operation of amplifiers 500, 600, and 700, the efficiency of the structure approaches 500, 600, and 700, neglecting non-ideal losses, as shown in Figure 8. Due to the nature of summing the output currents of a common source / emitter cell in RF series (e.g., transconductance cells 510a, 510b, 510c, and 510d), the amplifier structure is in "current mode," which is clearly distinguishable from conventional vertically stacked "voltage-mode" amplifiers (e.g., amplifier 100 in Figure 1 and amplifier 300 in Figure 3).

[0076] The design of the matched input network (M1) 520 and the matched output network (M2) 530 may follow conventional matched network designs, including lumped elements or transmit line stubs. For example, L matched networks can be used to form a compact IC area. For applications requiring increased efficiency, the current-mode amplifiers 500, 600, and 700 can be adapted from Class A bias to non-Class A bias by appropriately adjusting Vbias for a given class of operation following conventional amplifier designs. In addition, harmonic termination for waveform shaping may be absorbed in the output matched network (M2) 530.

[0077] Accordingly, Figures 5A and 5B, 6A and 6B, and 7A and 7B illustrate embodiments for the disclosed single-stage amplifiers 500, 600, and 700, having a single-stage power gain indicated in decibels (dB) by "G". The disclosed amplifiers 500, 600, and 700 offer several advantages over conventional amplifier designs (e.g., amplifier 100 in Figure 1 and amplifier 300 in Figure 3). The first advantage of the disclosed amplifiers 500, 600, and 700 is the use of a single-input single-output input matching network (M1) 520 and a single-input single-output output matching network (M2) 530, which significantly reduce the chip area occupied on the IC compared to the conventional amplifier 100 in Figure 1.

[0078] A second advantage of the disclosed amplifiers 500, 600, and 700 is that their structures can be realized using any unit element device technology, such as FETs or BJTs. A third advantage of the disclosed amplifiers 500, 600, and 700 is that they do not rely strictly on gate capacitance matching to maintain voltage amplitude reliability in the event of device failure, as is the case with the conventional amplifier 300 in Figure 3.

[0079] A fourth advantage of the disclosed amplifiers 500, 600, and 700 is that the cascode-connected devices do not have a gate / base leakage path to ground, which reduces efficiency, as seen in the conventional amplifier 300 in Figure 3. Finally, a fifth advantage of the disclosed amplifiers 500, 600, and 700 is that current-mode operation does not result in large voltage amplitudes on the devices, which improves reliability and linearity against body junction failures.

[0080] Different embodiments for the disclosed amplifier 900 may be adapted as shown in Figures 9A and 9B. Both Figures 9A and 9B are schematic circuit diagrams of the disclosed single-ended single-stage "current-mode" differential amplifier 900 according to at least one embodiment of the present disclosure.

[0081] The disclosed single-stage "current-mode" differential amplifier 900, shown in Figures 9A and 9B, utilizes a cascode stack of N differential unit element transconductance cells 910a, 910b, 910c, and 910d, each of which takes a supply current Idc and an AC RF differential current (I) as inputs. RF_IN ), and RF input differential signal (RF IN ) is obtained, and the DC current (Idc) and AC RF differential current (Idc) are output. RF_OUT The transconductance cells 910a, 910b, 910c, and 910d are cascode-connected in terms of DC input current and DC output current, so that a common current (Idc) is shared among each transconductance cell 910a, 910b, 910c, and 910d, and the DC supply voltage drop across each transconductance cell 910a, 910b, 910c, and 910d is Vdd / N. The transconductance cells 910a, 910b, 910c, and 910d generate the output differential current (Idc) of each transconductance cell. RF_OUT ) is the input differential current (I) of the subsequent cascaded transconductance cell. RF_IN The input signal source (Vin) (with source resistor (Rs)) is followed by an input matching network (M1) 920, which is connected in a cascaded manner to serve as the input to the RF of each transconductance cell. IN These are driven in parallel. The final output current I of the last transconductance cell 910d RF_OUT However, when applied to a single-input single-output output matching network (M2) 930, the load impedance R L Power is transmitted to it. Differential RF is used with a differential single-ended balun. IN Converts to a single-ended input, and differential I RF_OUT It can be converted to a single-ended output.

[0082] In one or more embodiments of the present disclosure, the disclosed amplifiers (e.g., 900 in Figures 9A and 9B, 1000 in Figures 10A, 10B, and 10C) implement each transconductance cell as a differential common-source / emitter unit element. Each common-source unit element stage / common-emitter unit element stage has an RF unit element device, which can be implemented in any device technology (e.g., as an FET device, as in amplifier 1000 in Figures 10A, 10B, and 10C, or as a BJT device). Figures 10A, 10B, and 10C all show schematic circuit diagrams of the disclosed single-stage "current-mode" differential amplifier 1000 according to at least one embodiment of the present disclosure, where the transconductance cells 1010a, 1010b, 1010c, and 1010d are implemented as common-source cells including RF unit element devices as MOSFETs, particularly as NMOS.

[0083] For the disclosed amplifiers 900 and 1000, each RF unit element device (e.g., NMOS or BJT) within a common source / emitter element (e.g., transconductance cells 1010a, 1010b, 1010c, 1010d) has a drain-source (or collector-emitter) DC voltage Vdd / N, and this drain-source (or collector-emitter) DC voltage Vdd / N is equal to the power supply Vdd and the N inductive elements (L ∞ The DC current (Idc) is provided by a DC series connection consisting of a power supply (Vdd) and N unit element common source / emitter cells (e.g., transconductance cells 1010a, 1010b, 1010c, 1010d) including RF unit element devices (e.g., NMOS or BJT). The common DC current (Idc) is provided by the power supply (Vdd) and the N inductors (L ∞The RF unit element is shared through a series connection consisting of N unit element common source / emitter stages (e.g., transconductance cells 1010a, 1010b, 1010c, 1010d) containing RF unit element devices (e.g., NMOS or BJT). The DC bias of each RF unit element device (e.g., NMOS or BJT) is provided by a voltage (VbiasN) and a large gate / base bias resistor (Rb), thereby allowing each unit element device to be biased individually and ensuring the current Idc and the nominal distribution of the Vdd voltage at each unit element drain / source or collector / emitter.

[0084] Similarly, the differential versions of the disclosed amplifiers (e.g., amplifier 900 in Figures 9A and 9B, and amplifier 1000 in Figures 10A, 10B, and 10C) can be designed in Class A or non-Class A bias, including the corresponding matched network designs as described above. For Class A bias, the efficiency of the differential structures of amplifiers 900 and 1000 ideally approaches 50%, while maintaining the structural advantages and reliability of compact and simple matched networks (e.g., single-input single-output input matched network (M1) 920 and single-input single-output output matched network (M2) 930).

[0085] A multistage embodiment of the disclosed amplifier (e.g., amplifier 500 in Figures 5A and 5B) may be adapted as shown in Figures 11A, 11B, and 11C. Specifically, Figures 11A, 11B, and 11C are schematic circuit diagrams of the disclosed multistage "current-mode" amplifier 1100 according to at least one embodiment of the present disclosure, where M is the number of first-stage transconductance cells 1110a, 1110b, and 1110c (in this example, 3(3)), N is the number of second-stage transconductance cells 1110d, 1110e, and 1110f (in this example, 3(3)), and a power supply voltage (Vdd) is applied to the first transconductance cell 1110a.

[0086] The disclosed single-ended multistage "current-mode" amplifier 1100, shown in Figures 11A, 11B, and 11C, utilizes a cascode stack of M unit-element transconductance cells 1110a, 1110b, and 1110c as its first stage, and a cascode stack of N unit-element transconductance cells 1110d, 1110e, and 1110f as its second stage. Each of the transconductance cells 1110a, 1110b, 1110c, 1110d, 1110e, and 1110f receives a DC supply current (Idc) and an AC RF input current (Idc) as inputs. RF_IN ), and RF input signal (RF IN ) is obtained, and the DC current (Idc) and AC RF output current (Idc) are output. RF_OUT The transconductance cells 1110a, 1110b, 1110c, 1110d, 1110e, and 1110f are cascode-connected in terms of DC input current and DC output current, so that a common current (Idc) is shared among each of the transconductance cells 1110a, 1110b, 1110c, 1110d, 1110e, and 1110f, and the DC supply voltage drop across each of the transconductance cells 1110a, 1110b, 1110c, 1110d, 1110e, and 1110f is Vdd / (M+N). The transconductance cells 1110a, 1110c, 1110d, 1110d, 1110e, and 1110f within each stage (for example, Stage 1 and Stage 2) have an output current (I RF_OUT ) is the input current (I) of the subsequent cascaded transconductance cell. RF_IN They are cascaded together so that they become inputs to ).

[0087] Following the input signal source (Vin) (with source resistance (Rs)) is an input matching network (M1) 1120, which controls the RF input signal (RF) of each transconductance cell (RF) of the first stage transconductance cells 1110a, 1110b, and 1110c. IN ) are driven in parallel. The final output current I of the last transconductance cell 1110c of the first stage RF_OUTHowever, this is applied to the single-input single-output output matching network (M2) 1125, and power is transferred to the second stage. The output current (I) of the last stage of amplifier 1100 RF_OUT ) is followed by a single-input single-output output matching network (M3) 1130, with a load resistor or (R L Power is transmitted to ). In one or more embodiments, it should be clear that the description of the preceding embodiments can be extended to a multistage amplifier having more than two stages, wherein each stage has a number of transconductance cells that are individually determined.

[0088] Note that in one or more embodiments, each of the transconductance cells 1110a, 1110b, 1110c, 1110d, 1110e, and 1110f of the amplifier 1100 may include a MOSFET device (see, for example, transconductance cell 610a in Figure 6A) or a BJT device (see, for example, transconductance cell 710a in Figure 7A). In some embodiments, in one or more embodiments, the amplifier 1100 in Figures 11A, 11B, and 11C may be configured to be a differential amplifier (see, for example, amplifier 900 in Figures 9A and 9B).

[0089] Figures 12A, 12B, and 12C are schematic circuit diagrams of the disclosed multistage "current-mode" amplifier 1200 according to at least one embodiment of the present disclosure, where M is the number of first-stage transconductance cells 1210a, 1210b, and 1210c (in this example, 3(3)), and N is the number of second-stage transconductance cells 1210d, 1210e, and 1210f (in this example, 3(3)), and the power supply voltage (Vdd) is applied to the transconductance cell 1210d, which is different from the first transconductance cell 1210a.

[0090] In this example as well, the input signal source (Vin) (with source register (Rs)) is followed by an input matching network (M1) 1220, which matches the RF input signals (RF) of each transconductance cell (RF) of the first stage transconductance cells 1210a, 1210b, and 1210c. IN ) are driven in parallel. Output current I of the last transconductance cell 1210c of the first stage RF_OUT However, this is applied to the single-input single-output output matching network (M2) 1225, and power is transferred to the second stage. The output current (I) of the last stage amplifier 1200 RF_OUT Following this is a single-input single-output output matching network (M3) 1230, with a load resistor (R L It transmits power to ).

[0091] The amplifiers 1200 in Figures 12A, 12B, and 12C maintain the same DC current (Idc) and RF signal flow as the amplifiers 1100 in Figures 11A, 11B, and 11C, except for the position of the supply voltage (Vdd). The supply voltage (Vdd) does not necessarily have to start from the first transconductance unit cell 1210a of the first stage, but may start from any transconductance cell 1210a, 1210b, 1210c, 1210d, 1210e, or 1210f of any stage (e.g., Stage 1 or Stage 2). For illustrative purposes, the amplifier 1200 in Figures 12A, 12B, and 12C is a two-stage amplifier 1200 in which the power supply voltage (Vdd) originates from the first transconductance cell 1210d of the second stage, and the DC current from the second stage supplies the DC current to the first stage.

[0092] Note that in one or more embodiments, each of the transconductance cells 1210a, 1210b, 1210c, 1210d, 1210e, and 1210f of amplifier 1200 may include a MOSFET device (see, for example, transconductance cell 610a in Figure 6A) or a BJT device (see, for example, transconductance cell 710a in Figure 7A). In some embodiments, in one or more embodiments, amplifier 1200 in Figures 12A, 12B, and 12C may be configured to be a differential amplifier (see, for example, amplifier 900 in Figures 9A and 9B).

[0093] Figures 13 to 16C are schematic circuit diagrams of the disclosed single-ended single-stage "current-mode" amplifiers 1300, 1400, 1410, 1420, 1430, 1500, 1510, 1520, 1530, 1600, 1610, and 1620 according to various embodiments of the present disclosure. Specifically, the schematic circuit diagrams of Figures 13 to 16C show various different connection configurations (e.g., in parallel and / or cascaded) that may be used for the disclosed single-ended single-stage "current-mode" amplifiers 1300, 1400, 1410, 1420, 1430, 1500, 1510, 1520, 1530, 1600, 1610, and 1620.

[0094] Figure 13 is a schematic circuit diagram of a disclosed single-ended single-stage "current-mode" amplifier 1300 according to at least one embodiment of the present disclosure, in which transconductance cells 1310a, 1310b, 1310c, and 1310d are connected to a high-frequency (RF) input signal (RF IN They are connected in parallel to each other (i.e., "parallel connection"), and the alternating current (AC) RF output current (I RF_OUT They are connected in parallel to each other (i.e., "parallel connection") for the purpose of ).

[0095] Figure 13 shows that amplifier 1300 includes N transconductance cells 1310a, 1310b, 1310c, and 1310d. An exemplary transconductance cell 1310 that may be used for the transconductance cells 1310a, 1310b, 1310c, and 1310d of amplifier 1300 is shown in Figure 17. Note that in one or more embodiments, each of the transconductance cells 1310a, 1310b, 1310c, and 1310d of amplifier 1300 may include a MOSFET device (see, for example, transconductance cell 1310 in Figure 17) or a BJT device (see, for example, transconductance cell 710a in Figure 7A).

[0096] During the operation of amplifier 1300, the power supply voltage (Vdd) is evenly distributed among the transconductance cells 1310a, 1310b, 1310c, and 1310d to supply power to them. The DC supply voltage drop across each of the transconductance cells 1310a, 1310b, 1310c, and 1310d is Vdd / N (where N is the number of transconductance cells 1310a, 1310b, 1310c, and 1310d). The transconductance cells 1310a, 1310b, 1310c, and 1310d are DC cascode-connected to each other and share a common DC supply current (Idc).

[0097] The input signal source (Vin) sends an RF input signal (RF) to the input matching network (M1) 1320. IN ) supplies. In one or more embodiments, the input matching network (M1) 1320 is a single-input single-output matching network. The input matching network (M1) 1320 supplies the RF input signal (RF IN ) is converted to provide power matching to the respective inputs of transconductance cells 1310a, 1310b, 1310c, and 1310d.

[0098] In this way, the DC supply current (Idc) and the RF input signal (RF) are obtained. IN), and AC RF input current (I RF_IN The following are inputs to the transconductance cells 1310a, 1310b, 1310c, and 1310d, respectively. Each of the transconductance cells 1310a, 1310b, 1310c, and 1310d receives the DC supply current (Idc) and the AC RF output current (Idc). RF_OUT It outputs ) (i.e., IRF). AC RF output current (I RF_OUT The (irf) currents combine to generate a combined current (N·irf).

[0099] AC RF output current (I) from the transconductance cell RF_OUT ) (irf) is input to the output matching network (M2) 1330 (i.e., as coupled current (N·irf) and load impedance (R L The output matching network (M2) transmits power to the load impedance (R) through the coupled current (N·irf). L Converts to ). In one or more embodiments, the output matching network (M2) 1330 is a single-input single-output matching network.

[0100] In Figure 13, a DC blocking capacitor (C) allows the RF signal to pass through. ∞ This DC cutoff capacitor (C) is located at the RF input and RF output of the transconductance cells 1310a, 1310b, 1310c, and 1310d, respectively. ∞ This provides DC isolation between the input and output of the connections of transconductance cells 1310a, 1310b, 1310c, and 1310d.

[0101] Figures 14A to 14E are schematic circuit diagrams of the disclosed single-ended single-stage "current-mode" amplifiers 1400, 1410, 1420, and 1430 according to various embodiments of the present disclosure, where transconductance cells 1310a, 1310b, 1310c, and 1310d are connected to the RF input signal (RF IN They are connected in parallel to each other for the purpose of ACRF output current (I RF_OUTThey are cascaded to each other for the purpose of ) the amplifiers 1400, 1410, 1420, and 1430 in Figures 14A to 14E, and the transconductance cells 1310a, 1310b, 1310c, and 1310d are AC RF output current (I RF_OUT Note that amplifiers 1400, 1410, 1420, and 1430 shown in Figures 14A to 14E are basically the same as amplifier 1300 in Figure 13, except that they are cascaded to one another (instead of being connected in parallel to each other, as in amplifier 1300 in Figure 13). Regarding the cascaded connection in Figures 14A to 14E, the AC RF output current (I) of each transconductance cell 1310a, 1310b, 1310c, and 1310d RF_OUT The (irf) currents are added together in the cascade to form a combined current (N·irf).

[0102] Specifically, the schematic circuit diagrams in Figures 14A to 14E show various different connection configurations for connecting the output matching network (M2) 1330 to one of the output junctions of the transconductance cells 1310a, 1310b, 1310c, and 1310d. Thus, the output matching network (M2) 1330 can be placed at any position in the “cascaded connection” of the outputs of the cascaded network. For example, Figure 14A is a schematic circuit diagram of the disclosed single-ended single-stage “current-mode” amplifier 1400 according to at least one embodiment of the present disclosure, in which the transconductance cells 1310a, 1310b, 1310c, and 1310d are connected to an RF input signal (RF IN They are connected in parallel to each other for the purpose of ) and AC RF output current (I RF_OUTThe output matching network (M2) 1330 is connected to the output junction of the first transconductance cell 1310a, as opposed to the RF output junction of the last transconductance cell (e.g., transconductance cell 510d in Figure 5B, or transconductance cell 1310d in Figure 14A). Note that the amplifier 1400 in Figure 14A is equivalent to the amplifier 500 in Figures 5A and 5B, provided that the output matching network (M2) (see, for example, 1330 in Figure 14A) can be positioned at the RF output junction of the first transconductance cell (e.g., transconductance cell 1310a in Figure 14A), as opposed to the RF output junction of the last transconductance cell (e.g., transconductance cell 510d in Figure 5B, or transconductance cell 1310d in Figure 14A).

[0103] Figures 14B to 14D show an output matching network (M2) 1330 connected to the output junctions of various transconductance cells 1310b, 1310c, and 1310d, which are different from the output junction of the first transconductance cell 1310a shown in Figure 14A. For example, Figure 14B shows a schematic circuit diagram of a disclosed single-ended single-stage "current-mode" amplifier according to at least one embodiment of the present disclosure, in which the transconductance cells 1310a, 1310b, 1310c, and 1310d are connected to an RF input signal (RF IN They are connected in parallel to each other for the purpose of ) and AC RF output current (I RF_OUT They are cascaded to each other for the purpose of ), and the output matching network (M2) 1330 is connected to the output junction of the second transconductance cell 1310b. Furthermore, Figure 14C is a schematic circuit diagram of the disclosed single-ended single-stage "current-mode" amplifier according to at least one embodiment of the present disclosure, in which the transconductance cells 1310a, 1310b, 1310c, and 1310d are connected to the RF input signal (RF IN They are connected in parallel to each other for the purpose of ) and AC RF output current (I RF_OUTThey are cascaded to each other for the purpose of ), and the output matching network (M2) 1330 is connected to the output junction of the third transconductance cell 1310c. Also, Figure 14D is a schematic circuit diagram of the disclosed single-ended single-stage "current-mode" amplifier according to at least one embodiment of the present disclosure, in which the transconductance cells 1310a, 1310b, 1310c, and 1310d are connected to the RF input signal (RF IN They are connected in parallel to each other for the purpose of ) and AC RF output current (I RF_OUT They are cascaded to each other for the purpose of output matching network (M2) 1330, which is connected to the output junction of the last transconductance cell 1310d.

[0104] Figure 14E is an exemplary detailed schematic diagram 1440 of the amplifier 1430 shown in Figure 14D, according to at least one embodiment of the present disclosure. Specifically, Figure 14E is one implementation of a cascaded current-mode amplifier 1430 including transconductance cells 1310a, 1310b, and 1310c utilizing NMOS devices.

[0105] Figures 15A to 15D are schematic circuit diagrams of the disclosed single-ended single-stage "current-mode" amplifiers 1500, 1510, 1520, and 1530 according to various embodiments of the present disclosure, where transconductance cells 1310a, 1310b, 1310c, and 1310d are connected to the RF input signal (RF IN They are cascaded to each other for the purpose of AC RF output current (I RF_OUT They are connected in parallel to each other for the purpose of ) . For amplifiers 1500, 1510, 1520, and 1530 in Figures 15A to 15D, the transconductance cells 1310a, 1310b, 1310c, and 1310d are connected in parallel to each other for the purpose of RF input current (RF IN Note that amplifiers 1500, 1510, 1520, and 1530 shown in Figures 15A to 15D are essentially the same as amplifier 1300 in Figure 13, except that they are cascaded to one another (instead of being connected in parallel to each other, as in amplifier 1300 in Figure 13).

[0106] Specifically, the schematic circuit diagrams in Figures 15A to 15D show various different connection configurations for connecting the input matching network (M1) 1320 to one of the input junctions of the transconductance cells 1310a, 1310b, 1310c, and 1310d. Thus, the input matching network (M1) 1320 can be placed at any position in the “cascaded connection” of the inputs of the cascaded network. For example, Figure 15A is a schematic circuit diagram of the disclosed single-ended single-stage “current-mode” amplifier 1500 according to at least one embodiment of the present disclosure, in which the transconductance cells 1310a, 1310b, 1310c, and 1310d are connected to an RF input signal (RF IN They are cascaded to each other for the purpose of ) and AC RF output current (I RF_OUT They are connected in parallel to each other for the purpose of output matching, and the output matching network (M1) 1320 is connected to the input junction of the first transconductance cell 1310a.

[0107] Figures 15B to 15D show an input matching network (M1) 1320 connected to the input junctions of various transconductance cells 1310b, 1310c, and 1310d, which are different from the input junction of the first transconductance cell 1310a shown in Figure 15A. For example, Figure 15B shows a schematic circuit diagram of a disclosed single-ended single-stage "current-mode" amplifier 1510 according to at least one embodiment of the present disclosure, in which the transconductance cells 1310a, 1310b, 1310c, and 1310d are connected to an RF input signal (RF IN They are cascaded to each other for the purpose of AC RF output current (I RF_OUT The output matching network (M1) 1320 is connected in parallel to each other for the RF input signal (RF). Figure 15C is a schematic circuit diagram of the disclosed single-ended single-stage "current-mode" amplifier 1520 according to at least one embodiment of the present disclosure, where the transconductance cells 1310a, 1310b, 1310c, and 1310d are connected in parallel to each other for the RF input signal (RF). INThey are cascaded to each other for the purpose of AC RF output current (I RF_OUT They are connected in parallel to each other for the purpose of ), and the output matching network (M1) 1320 is connected to the input junction of the third transconductance cell 1310c. Furthermore, Figure 15D is a schematic circuit diagram of the disclosed single-ended single-stage "current-mode" amplifier 1530 according to at least one embodiment of the present disclosure, in which the transconductance cells 1310a, 1310b, 1310c, and 1310d are connected in parallel to each other for the RF input signal (RF IN They are cascaded to each other for the purpose of AC RF output current (I RF_OUT They are connected in parallel to each other for the purpose of output matching network (M1) 1320, and the output matching network (M1) 1320 is connected to the input junction of the last transconductance cell 1310d.

[0108] Figures 16A to 16C are schematic circuit diagrams of the disclosed single-ended single-stage "current-mode" amplifiers 1600, 1610, and 1620 according to various embodiments of the present disclosure, where transconductance cells 1310a, 1310b, 1310c, and 1310d are connected to the RF input signal (RF IN They are cascaded to each other for the purpose of AC RF output current (I RF_OUT They are cascaded to each other for the purpose of ) the amplifiers 1600, 1610, and 1620 in Figures 16A to 16C, and the transconductance cells 1310a, 1310b, 1310c, and 1310d are connected to the RF input current (RF IN For this reason, (instead of being connected in parallel with each other as in the amplifier 1300 in Figure 13) they are cascaded with each other, and the AC RF output current (I RF_OUT Note that amplifiers 1600, 1610, and 1620 shown in Figures 16A to 16C are basically the same as amplifier 1300 in Figure 13, except that they are cascaded to one another (instead of being connected in parallel to each other as amplifier 1300 in Figure 13). For the output cascade connection in Figures 16A to 16C, the AC RF output current (I) of each transconductance cell 1310a, 1310b, 1310c, and 1310d RF_OUTThe (irf) currents are added together in the cascade to form a combined current (N·irf).

[0109] Specifically, the schematic circuit diagrams in Figures 16A to 16C show various connection configurations of the input matching network (M1) 1320 to one input junction of the transconductance cells 1310a, 1310b, 1310c, and 1310d, and various connection configurations of the output matching network (M2) 1330 to one output junction of the transconductance cells 1310a, 1310b, 1310c, and 1310d. Note that Figures 16A to 16C only show some (but not all) of the possible connection configurations. Thus, the input matching network (M1) 1320 can be placed at any position in the "cascaded connection" of the inputs of the cascaded network. Furthermore, the output matching network (M2) 1330 can be placed at any position in the "cascaded connection" of the outputs of the cascaded network. For example, Figure 16A is a schematic circuit diagram of a disclosed single-ended single-stage "current-mode" amplifier 1600 according to at least one embodiment of the present disclosure, in which transconductance cells 1310a, 1310b, 1310c, and 1310d are connected to an RF input signal (RF IN They are cascaded to each other for the purpose of AC RF output current (I RF_OUT They are cascaded to each other for the purpose of matching inputs, with input matching network (M1) 1320 connected to the input junction of the first transconductance cell 1310a and output matching network (M2) 1330 connected to the output junction of the last transconductance cell 1310d.

[0110] Figures 16B to 16C show an input matching network (M1) 1320 connected to various input junctions of transconductance cells 1310b and 1310d, which are different from the input junction of the first transconductance cell 1310a shown in Figure 16A. Figures 16B to 16C also show an output matching network (M2) 1330 connected to various output junctions of transconductance cells 1310a and 1310b, which are different from the output junction of the last transconductance cell 1310d shown in Figure 16A. For example, Figure 16B shows a schematic circuit diagram of a disclosed single-ended single-stage "current-mode" amplifier 1610 according to at least one embodiment of the present disclosure, where transconductance cells 1310a, 1310b, 1310c, and 1310d are connected to an RF input signal (RF IN They are cascaded to each other for the purpose of AC RF output current (I RF_OUT The input matching network (M1) 1320 is connected to the input junction of the second transconductance cell 1310b, and the output matching network (M2) 1330 is connected to the output junction of the second transinductance cell 1310b. Figure 16C also shows a schematic circuit diagram of the disclosed single-ended single-stage "current-mode" amplifier 1620 according to at least one embodiment of the present disclosure, in which the transconductance cells 1310a, 1310b, 1310c, and 1310d are cascaded to the RF input signal (RF IN They are cascaded to each other for the purpose of AC RF output current (I RF_OUT They are cascaded to each other for the purpose of matching inputs, with input matching network (M1) 1320 connected to the input junction of the last transconductance cell 1310d and output matching network (M2) 1330 connected to the output junction of the first transconductance cell 1310a.

[0111] Figure 17 is a schematic circuit diagram showing an exemplary transconductance cell 1310 that may be used for the transconductance cells 1310a, 1310b, 1310c, and 1310d of the single-ended, single-stage "current-mode" amplifiers 1300, 1400, 1410, 1420, 1430, 1500, 1510, 1520, 1530, 1600, 1610, and 1620 disclosed in Figures 13 to 16C, according to at least one embodiment of the present disclosure, where the transconductance cell is implemented as a common source cell including an RF unit element device as a MOSFET, particularly as an n-channel MOSFET (NMOS). Although the transconductance cell 1310 is shown as utilizing the NMOS device T1, it should be noted that the transconductance cell 1310 can be realized using any transconductance transistor technology, for example, CMOS, silicon germanium (SiGe), or other III-V semiconductor device technologies.

[0112] In Figure 17, the drain of device T1 is an RF choke element (L) which can be realized by an inductor or a transmit line. ∞ ) includes the input RF port and output RF port (which happen to be on the same node). The drain also includes the input RF port and output RF port (which happen to be on the same node). The DC gate bias is provided by the bias resistor (Rb). The source of device T1 is the shunt large capacitance capacitor (C ∞ This is an RF short circuit generated by ). A DC supply current of value Idc flows through the drain and source.

[0113] Figure 18 is a flowchart of the disclosed method 1800 for the operation of the single-ended single-stage "current-mode" amplifiers 1300, 1400, 1410, 1420, 1430, 1500, 1510, 1520, 1530, 1600, 1610, and 1620 disclosed in Figures 13 to 16C, according to at least one embodiment of the present disclosure. In the beginning 1810 of method 1800, an input signal source (Vin) is fed an RF input signal (RF) to an input matching network (M1). IN ) supplies (1820). Input matching network (M1) receives the RF input signal (RF IN) is converted to provide power matching to the input of each transconductance cell of multiple transconductance cells (1830).

[0114] The power supply voltage (Vdd) is evenly distributed among the transconductance cells to supply power to them, where the DC supply voltage drop across each transconductance cell is Vdd / N, and N is the number of transconductance cells (1840).

[0115] DC supply current (Idc), AC (alternating current) RF (radio frequency) input current (Idc) RF_IN ), and RF input signal (RF IN ) is input to each of the transconductance cells (1850). DC supply current (Idc), and AC RF output current (I RF_OUT ) is output by each of the transconductance cells, where each of the transconductance cells is cascoded to one another for the DC supply current (Idc), and the RF input signal (RF IN They are connected in parallel (or cascaded) to each other for the purpose of AC RF output current (I RF_OUT They are connected in parallel (or cascaded) to each other for the purpose of (1860).

[0116] AC RF output current (I) from the transconductance cell RF_OUT ) is input to the output matching network (M2), and the load impedance (R L Power is transmitted to (1870). Then, method 1800 ends (1880).

[0117] Figure 19 shows a schematic circuit diagram of the disclosed multistage "current-mode" amplifier 1900 according to at least one embodiment of the present disclosure, where M is the number of transconductance cells 1970a, 1970b, 1970c, and 1970d of the first stage, and N is the number of transconductance cells 1970e, 1970f, 1970g, and 1970h of the second stage, wherein the transconductance cells 1970a, 1970b, 1970c, and 1970d in the first stage and the transconductance cells 1970e, 1970f, 1970g, and 1970h in the second stage are connected to an RF input signal (RF IN They are connected in parallel (or cascaded) to each other (1950a, 1950b), and the AC RF output current (I RF_OUT The stages are connected in parallel (or cascaded) for the purpose of (1960a, 1960b). Specifically, Figure 19 shows a multistage (e.g., two-stage) current-mode amplifier 1900, where the DC bias current (Idc) is shared between the two stages (i.e., between the first and second stages). The power supply voltage (Vdd) is supplied to the first stage. The input distribution networks 1950a, 1950b and output coupling networks 1960a, 1960b for each stage may be connected in cascaded or parallel. An internal stage matching network (M2) 1930 is used between multiple stages (i.e., between the first and second stages). Although Figure 19 shows a multistage "current-mode" amplifier 1900 with a total of two stages, it should be noted that in one or more embodiments, the disclosed multistage "current-mode" amplifier may have more stages than the two stages shown in Figure 19.

[0118] In the multi-stage "current-mode" amplifier 1900 shown in Figure 19, the first and second stages can each be implemented by one of the exemplary single-stage amplifiers 1300, 1400, 1410, 1420, 1430, 1500, 1510, 1520, 1530, 1600, 1610, and 1620 shown in Figures 13 to 16C. Furthermore, in one or more embodiments, the transconductance cells 1970a, 1970b, 1970c, 1970d, 1970e, 1970f, 1970g, and 1970h of the multistage amplifier 1900 may each be realized by the exemplary transconductance cell 1310 shown in Figure 17, or alternatively, any other transconductance transistor technology different from the NMOS device technology shown in Figure 17 may be used, including but not limited to CMOS, silicon-germanium (SiGe), or other III-V semiconductor device technologies. Note that in one or more embodiments, each of the transconductance cells 1970a, 1970b, 1970c, 1970d, 1970e, 1970f, 1970g, and 1970h of amplifier 1900 may include a MOSFET device (see, for example, transconductance cell 1310 in Figure 17) or a BJT device (see, for example, transconductance cell 710a in Figure 7A).

[0119] During the operation of amplifier 1900, the power supply voltage (Vdd) (see, for example, Figure 13) is evenly distributed among the transconductance cells 1970a, 1970b, 1970c, 1970d, 1970e, 1970f, 1970g, and 1970h of the first and second stages, supplying power to these transconductance cells 1970a, 1970b, 1970c, 1970d, 1970e, 1970f, 1970g, and 1970h of the first and second stages. The DC supply voltage drop across each of the transconductance cells 1970a, 1970b, 1970c, 1970d, 1970e, 1970f, 1970g, and 1970h of the first and second stages is Vdd / N (where N is the number of transconductance cells 1970a, 1970b, 1970c, 1970d, 1970e, 1970f, 1970g, and 1970h of the first and second stages). The transconductance cells 1970a, 1970b, 1970c, 1970d, 1970e, 1970f, 1970g, and 1970h of the first and second stages are connected to each other in a DC cascode and share a common DC supply current (Idc).

[0120] The input signal source (Vin) sends an RF input signal (RF) to the input matching network (M1) 1920. IN ) supplies. In one or more embodiments, the input matching network (M1) 1920 is a single-input single-output matching network. The input matching network (M1) 1920 supplies the RF input signal (RF IN ) is converted to provide power matching to the respective inputs of the first stage transconductance cells 1970a, 1970b, 1970c, and 1970d.

[0121] In this way, the DC supply current (Idc) and the RF input signal (RF) are obtained. IN ), and AC RF input current (I RF_IN The following are inputs to the transconductance cells 1970a, 1970b, 1970c, and 1970d of the first stage. Each of the transconductance cells 1970a, 1970b, 1970c, and 1970d of the first stage receives the DC supply current (Idc) and the AC RF output current (Idc). RF_OUTIt outputs ) (i.e., IRF). AC RF output current (I RF_OUT The (irf) currents combine to generate a combined current (N·irf).

[0122] AC RF output current (I) from at least one of the transconductance cells 1970a, 1970b, 1970c, and 1970d of the first stage RF_OUT The current (N·irf) is input to the internal stage matching network (M2) 1930 (i.e., as a coupled current (N·irf)) to power the second stage transconductance cells 1970e, 1970f, 1970g, and 1970h. In one or more embodiments, the internal stage matching network (M2) 1930 is a single-input, single-output matching network. The internal stage matching network (M2) 1930 converts the coupled current (N·irf) to provide power matching to the respective inputs of the second stage transconductance cells 1970e, 1970f, 1970g, and 1970h.

[0123] In this way, the DC supply current (Idc), the RF input signal (RFIN), and the AC RF input current (I RF_IN The following are inputs to the second stage transconductance cells 1970e, 1970f, 1970g, and 1970h. Each of the second stage transconductance cells 1970e, 1970f, 1970g, and 1970h receives the DC supply current (Idc) and the AC RF output current (Idc). RF_OUT It outputs ) (i.e., IRF). AC RF output current (I RF_OUT The (irf) currents combine to generate a combined current (N·irf).

[0124] The AC RF output current (I) from at least one of the transconductance cells 1970e, 1970f, 1970g, and 1970h of the second stage RF_OUT )(irf) is input to the external stage matching network (M3) 1940 (i.e., as coupled current (N·irf)) and load (R LPower is transmitted to the ). In one or more embodiments, the external stage matching network (M3) 1940 is a single-input single-output matching network.

[0125] Figures 20A and 20B are flowcharts of the disclosed method 2000 for the operation of the multistage "current-mode" amplifier 1900 disclosed in Figure 19, according to at least one embodiment of the present disclosure. In the beginning of method 2000, an input signal source (Vin) is fed an RF input signal (RF) to an input matching network (M1). IN ) supplies (2020). Input matching network (M1) receives the RF input signal (RF IN ) is converted to provide power matching to the input of each transconductance cell of the multiple transconductance cells of the first stage (2030).

[0126] The power supply voltage (Vdd) is evenly distributed between the transconductance cells of the first stage and the transconductance cells of the second stage, supplying power to the transconductance cells of the first stage and the transconductance cells of the second stage, where the DC supply voltage drop across each of the transconductance cells in the first stage and the transconductance cells in the second stage is Vdd / N, where N is the number of transconductance cells in the first stage and the transconductance cells in the second stage (2040).

[0127] DC supply current (Idc), AC (alternating current) RF (radio frequency) input current (Idc) RF_IN ), and RF input signal (RF IN ) is input to each of the transconductance cells of the first stage (2050). DC supply current (Idc), AC RF input current (I RF_IN ), and RF input signal (RF IN ) is entered into each of the transconductance cells in the second row (2060).

[0128] DC supply current (Idc), and AC RF output current (I RF_OUT) is output by each of the transconductance cells of the first stage, where each of the transconductance cells of the first stage is cascoded with one another for the DC supply current (Idc), and the RF input signal (RF IN They are connected in parallel (or cascaded) to each other for the purpose of AC RF output current (I RF_OUT They are connected in parallel (or cascaded) to each other for the purpose of (2070).

[0129] DC supply current (Idc), and AC RF output current (I RF_OUT ) is output by each of the second stage transconductance cells, where each of the second stage transconductance cells is cascoded with one another for the DC supply current (Idc), and the RF input signal (RF IN They are connected in parallel (or cascaded) to each other for the purpose of AC RF output current (I RF_OUT They are connected in parallel (or cascaded) to each other for the purpose of (2080).

[0130] AC RF output current (I) from at least one of the transconductance cells of the first stage RF_OUT The AC RF output current (I) is input to the internal stage matching network (M2) and power is transferred to the transconductance cells of the second stage (2090). RF_OUT ) is input to the output matching network (M3), and the load impedance (R L Power is transmitted to (2095). Then, method 2000 ends (2098).

[0131] Figure 21 is a schematic schematic diagram showing an exemplary circuit 2100 that may be used for a disclosed multistage "current-mode" amplifier according to at least one embodiment of the present disclosure. Specifically, the circuit 2100 of Figure 21 is an implementation of a multistage power amplifier, wherein the first stage includes a common-emitter amplifier and the second stage includes a parallel-input / parallel-output current-mode amplifier (see, for example, amplifier 1300 in Figure 13). The circuit 2100 is shown to include an input matching network (M1) 2120, an internal stage matching network (M2) 2130, and an output matching network (M3) 2140. The first stage is also shown to include one transconductance device T1 (for example, in the form of a BJT transistor), and the second stage is shown to include two transconductance devices T2 and T3 (for example, in the form of BJT transistors). As shown in the amplifier 1900 in Figure 19, the DC supply current (Idc) is shared between multiple stages (i.e., between the first stage and the second stage), and the internal matching network 2130 is used between these multiple stages.

[0132] Figure 22A is a graph 2200 showing the simulation results of the collector current (Ic)-collector-emitter voltage (Vce) of the first stage transistor T1 of the multistage "current-mode" amplifier of Figure 21, according to at least one embodiment of the present disclosure. Graph 2200 shows a load line plot of the swept input power (Pin) of Ic-Vce for the T1 device. The curve shows that the output voltage at the T1 device remains below the unsafe operating region (i.e., the device failure region) 2205.

[0133] Figure 22B is graph 2210 showing the simulation results of the Ic / Vce-time (in picoseconds (psec)) of the first stage transistor T1 of the multistage "current-mode" amplifier of Figure 21 according to at least one embodiment of the present disclosure. Graph 2210 is a time-domain plot of the Vce voltage and Ic current at the T1 device. Graph 2210 shows that the voltage at the T1 device remains below the unsafe operating region 2215.

[0134] Figure 23A is a graph 2300 showing the simulation results of the Ic-Vce of the top transistor T2 of the second stage of the multistage "current-mode" amplifier of Figure 21, according to at least one embodiment of the present disclosure. Graph 2300 shows a load line plot of the swept input power (Pin) of the Ic-Vce of the T2 device. The curve shows that the output voltage at the T2 device remains below the unsafe operating region (i.e., the device failure region) 2305.

[0135] Figure 23B is graph 2310 showing the simulation results of the Ic / Vce-time (picoseconds) of the top transistor T2 of the second stage of the multistage "current-mode" amplifier of Figure 21, according to at least one embodiment of the present disclosure. Graph 2310 is a time-domain plot of the Vce voltage and Ic current at the T2 device. Graph 2310 shows that the voltage at the T2 device remains below the unsafe operating region 2315.

[0136] Figure 24A is a graph 2400 showing the simulation results of the Ic-Vce of the bottom transistor T3 of the second stage of the multistage "current-mode" amplifier of Figure 21, according to at least one embodiment of the present disclosure. Graph 2400 shows a load line plot of the swept input power (Pin) of the Ic-Vce of the T3 device. The curve shows that the output voltage at the T3 device remains below the unsafe operating region (i.e., the device failure region) 2405.

[0137] Figure 24B is graph 2410 showing the simulation results of the Ic / Vce-time (picoseconds) of the bottom transistor T3 of the second stage of the multistage "current-mode" amplifier of Figure 21, according to at least one embodiment of the present disclosure. Graph 2410 is a time-domain plot of the Vce voltage and Ic current at the T3 device. Graph 2410 shows that the voltage at the T3 device remains below the unsafe operating region 2415.

[0138] Figure 25 is a graph 2500 showing the simulation results of the output current density (Ice)-Vce-input power (Pin) of the second stage transistors T2 and T3 of the multistage "current-mode" amplifier of Figure 21, according to at least one embodiment of the present disclosure. Graph 2500 shows that the device output current density (Ice) remains below the unsafe operating region 2510 for devices T2 and T3.

[0139] While specific embodiments have been illustrated and described, it should be understood that the foregoing description is not intended to limit the scope of these embodiments. Many embodiments and variations of the present invention have been disclosed and described herein, but this disclosure is provided for illustrative and illustrative purposes only. Therefore, various changes and modifications can be made without departing from the claims.

[0140] Where the previously described method indicates that certain events occur in a certain order, a person skilled in the art who benefits from this disclosure will see that this order may be changed, and that such change is in accordance with the modifications of this disclosure. Furthermore, parts of the method may be performed concurrently by parallel processing, or sequentially, where possible. In addition, the method may involve more or fewer steps.

[0141] Therefore, the embodiments are intended to illustrate alternative examples, variations, and equivalents that may be included within the scope of the claims.

[0142] Furthermore, this disclosure includes embodiments as defined below.

[0143] Clause 1. A method (1800) for the operation of a high-voltage signal amplifier (1300), Each of the multiple transconductance cells (1310a, 1310b) receives a direct current (DC) supply current (Idc) and an alternating current (AC) radio frequency (RF) input current (Idc). RF_IN ), and RF input signal (RF IN Entering (1850) and outputting a DC supply current (Idc) and an AC RF output current (I RF_OUT ) by each of the transconductance cells among the plurality of transconductance cells (1310a, 1310b) (1860), wherein the transconductance cells (1310a, 1310b) are cascode-connected to each other for the DC supply current (Idc), are connected in parallel to each other for an RF input signal (RF IN ) and are connected in parallel to each other for the AC RF output current (I RF_OUT ), A method (1800) for operating a high voltage signal amplifier (1300).

[0144] Clause 2. The method according to Clause 1, further comprising providing (1820) the RF input signal (RF IN ) to an input matching network (M1) (1320) by an input signal source (Vin).

[0145] Clause 3. The method according to Clause 2, wherein the input matching network (M1) (1320) is a single-input single-output matching network.

[0146] Clause 4. The method according to Clause 2, further comprising converting (1830), by the input matching network (M1) (1320), the RF input signal (RF IN ) to provide power matching to respective inputs of the transconductance cells (1310a, 1310b).

[0147] Clause 5. The method according to Clause 1, further comprising inputting the AC RF output current (I RF_OUT ) output from the transconductance cells among the plurality of transconductance cells (1310a, 1310b) into an output matching network (M2) (1330), and transferring (1870) power to a load impedance (R L ).

[0148] Clause 6. The method of Clause 5, wherein the output matching network (M2) (1330) is a single-input single-output matching network.

[0149] Clause 7. The method of Clause 1, wherein each of the transconductance cells (1310a, 1310b) comprises a metal oxide silicon field effect transistor (MOSFET).

[0150] Clause 8. The method of Clause 1, wherein each of the transconductance cells (1310a, 1310b) comprises a bipolar junction transistor (BJT).

[0151] Clause 9. The method of Clause 1, further comprising: equally distributing a power supply voltage (Vdd) between the transconductance cells (1310a, 1310b) to supply power to the transconductance cells (1310a, 1310b) (1840).

[0152] Clause 10. The method of Clause 9, wherein a DC supply voltage drop across each of the transconductance cells (1310a, 1310b) is Vdd / N, where N is the number of transconductance cells (1310a, 1310b).

[0153] Clause 11. A method (1800) for operating a high voltage signal amplifier (1300), comprising: inputting, to each transconductance cell of a plurality of transconductance cells (1310a, 1310b), a direct current (DC) supply current (Idc), an alternating current (AC) radio frequency (RF) input current (I RF_IN ), and an RF input signal (RF IN ) (1850); and outputting, by each of the transconductance cells among the plurality of transconductance cells (1310a, 1310b), the DC supply current (Idc) and an AC RF output current (I RF_OUT ) (1860), wherein the transconductance cells (1310a, 1310b) are cascode-connected to each other for the DC supply current (Idc), and the RF input signal (RFIN They are connected in parallel to each other for the purpose of ) and AC RF output current (I RF_OUT A method for the operation of high-voltage signal amplifiers (1300) (1800) that are cascaded to each other for the purpose of (1800).

[0154] Clause 12. The RF input signal (RF) is determined by the input signal source (Vin). IN The method according to Clause 11, further comprising providing (1820) an input matching network (M1) (1320).

[0155] Clause 13. The method according to Clause 12, wherein the input matching network (M1)(1320) is a single-input single-output matching network.

[0156] Clause 14. Input matching network (M1)(1320) to the RF input signal (RF IN The method according to clause 12, further comprising converting (1830) to provide power matching to the respective inputs of the transconductance cells (1310a, 1310b).

[0157] Clause 15. AC RF output current (I) from one of the transconductance cells (1310a, 1310b) RF_OUT ) is input to the output matching network (M2) (1330) and the load impedance (R L The method of Article 11, further including transmitting power to (1870).

[0158] Clause 16. The method according to Clause 15, wherein the output matching network (M2)(1330) is a single-input single-output matching network.

[0159] Clause 17. The method according to Clause 15, wherein the output matching network (M2) (1330) is connected to one of the output junctions of the transconductance cells (1310a, 1310b).

[0160] Clause 18. The method according to Clause 11, wherein each of the transconductance cells (1310a, 1310b) comprises a metal-oxide-silicon field-effect transistor (MOSFET).

[0161] Clause 19. The method according to Clause 11, wherein each of the transconductance cells (1310a, 1310b) includes a bipolar junction transistor (BJT).

[0162] The method according to Clause 20, further comprising supplying power to the transconductance cells (1310a, 1310b) by equally distributing the power supply voltage (Vdd) among the transconductance cells (1310a, 1310b) (1840).

[0163] Clause 21. The method according to Clause 20, wherein the DC supply voltage drop across each of the transconductance cells (1310a, 1310b) is Vdd / N, where N is the number of transconductance cells (1310a, 1310b).

[0164] Clause 22. A method (1800) for the operation of a high-voltage signal amplifier (1300), Each of the multiple transconductance cells (1310a, 1310b) receives a direct current (DC) supply current (Idc) and an alternating current (AC) radio frequency (RF) input current (Idc). RF_IN ), and RF input signal (RF IN Entering (1850) and Each of the transconductance cells (1310a, 1310b) controls the DC supply current (Idc) and the AC RF output current (Idc). RF_OUT ) to output (1860), Includes, The transconductance cells (1310a, 1310b) are cascoded together for the DC supply current (Idc) and the RF input signal (RF IN They are cascaded to each other for the purpose of AC RF output current (I RF_OUT They are connected in parallel to each other for the purpose of A method (1800) for operation of a high voltage signal amplifier (1300).

[0165] Clause 23. An RF input signal (RF IN ) is further comprising providing (1820) the same to an input matching network (M1) (1320) by an input signal source (Vin), the method according to Clause 22.

[0166] Clause 24. The method according to Clause 23, wherein the input matching network (M1) (1320) is a single-input single-output matching network.

[0167] Clause 25. The RF input signal (RF IN ) is further comprising converting (1830) the same by the input matching network (M1) (1320) to provide power matching to respective inputs of transconductance cells (1310a, 1310b), the method according to Clause 23.

[0168] Clause 26. The method according to Clause 23, wherein the input matching network (M1) (1320) is connected to an input junction of one of the transconductance cells (1310a, 1310b).

[0169] Clause 27. An AC RF output current (I RF_OUT ) output from a transconductance cell among a plurality of transconductance cells (1310a, 1310b) is input to an output matching network (M2) (1330) for load impedance (R L ) is further comprising transmitting (1870) power to the same, the method according to Clause 22.

[0170] Clause 28. The method according to Clause 27, wherein the output matching network (M2) (1330) is a single-input single-output matching network.

[0171] Clause 29. The method according to Clause 22, wherein each of the transconductance cells (1310a, 1310b) comprises a metal oxide silicon field effect transistor (MOSFET).

[0172] Clause 30. The method according to Clause 22, wherein each of the transconductance cells (1310a, 1310b) includes a bipolar junction transistor (BJT).

[0173] The method according to Clause 31, further comprising distributing the power supply voltage (Vdd) equally among the transconductance cells (1310a, 1310b) to supply power to the transconductance cells (1310a, 1310b) (1840).

[0174] Clause 32. The method according to Clause 31, wherein the DC supply voltage drop across each of the transconductance cells (1310a, 1310b) is Vdd / N, where N is the number of transconductance cells (1310a, 1310b).

[0175] Clause 33. A method (1800) for the operation of a high-voltage signal amplifier (1300), Each of the multiple transconductance cells (1310a, 1310b) receives a direct current (DC) supply current (Idc) and an alternating current (AC) radio frequency (RF) input current (Idc). RF_IN ), and RF input signal (RF IN Entering (1850) and Each of the transconductance cells (1310a, 1310b) controls the DC supply current (Idc) and the AC RF output current (Idc). RF_OUT ) to output (1860), Includes, The transconductance cells (1310a, 1310b) are cascoded together for the DC supply current (Idc) and the RF input signal (RF IN They are cascaded to each other for the purpose of AC RF output current (I RF_OUT They are cascaded to each other for the purpose of A method (1800) for the operation of a high-voltage signal amplifier (1300).

[0176] Clause 34. The RF input signal (RF) is determined by the input signal source (Vin).IN The method according to Clause 33, further comprising providing (1820) an input matching network (M1) (1320).

[0177] Clause 35. The method according to Clause 34, wherein the input matching network (M1)(1320) is a single-input single-output matching network.

[0178] Clause 36. The RF input signal (RF) is transmitted through the input matching network (M1)(1320). IN The method according to clause 34, further comprising converting (1830) to provide power matching to the respective inputs of the transconductance cells (1310a, 1310b).

[0179] Clause 37. The method according to Clause 34, wherein the input matching network (M1)(1320) is connected to one of the input junctions of the transconductance cells (1310a, 1310b).

[0180] Clause 38. AC RF output current (I) from one of the transconductance cells (1310a, 1310b) RF_OUT ) is input to the output matching network (M2) (1330) and the load impedance (R L The method described in Article 33, further including transmitting power to (1870).

[0181] Clause 39. The method according to Clause 38, wherein the output-matched network (M2)(1330) is a single-input, single-output matched network.

[0182] Clause 40. The method according to Clause 38, wherein the output matching network (M2) (1330) is connected to one of the output junctions of the transconductance cells (1310a, 1310b).

[0183] Clause 41. The method according to Clause 33, wherein each of the transconductance cells (1310a, 1310b) comprises a metal-oxide-silicon field-effect transistor (MOSFET).

[0184] Clause 42. The method according to Clause 33, wherein each of the transconductance cells (1310a, 1310b) includes a bipolar junction transistor (BJT).

[0185] The method according to Clause 43, further comprising distributing the power supply voltage (Vdd) equally among the transconductance cells (1310a, 1310b) to supply power to the transconductance cells (1310a, 1310b) (1840).

[0186] Clause 44. The method according to Clause 43, wherein the DC supply voltage drop across each of the transconductance cells (1310a, 1310b) is Vdd / N, where N is the number of transconductance cells (1310a, 1310b).

[0187] Clause 45. A method (2000) for the operation of a high-voltage multi-stage signal amplifier (1900), Each transconductance cell of the multiple transconductance cells (1970a, 1970b) in the first stage receives a direct current (DC) supply current (Idc) and an alternating current (AC) radio frequency (RF) input current (Idc). RF_IN ), and RF input signal (RF IN Entering (2050) and In the second stage, each transconductance cell (1970e, 1970f) receives a DC supply current (Idc) and an AC RF input current (Idc). RF_IN ), and RF input signal (RF IN Entering (2060) and Each of the transconductance cells (1970a, 1970b) in the first stage controls the DC supply current (Idc) and the AC RF output current (Idc). RF_OUT Outputting (2070), Each of the transconductance cells (1970e, 1970f) in the second stage controls the DC supply current (Idc) and the AC RF output current (Idc). RF_OUT Outputting (2080) and Includes, The first stage transconductance cells (1970a, 1970b) are cascoded together for the DC supply current (Idc) and the RF input signal (RF IN They are connected in parallel or cascaded to each other for the purpose of AC RF output current (I RF_OUT They are connected in parallel or cascaded to each other for the purpose of: The second stage transconductance cells (1970e, 1970f) are cascoded together for the DC supply current (Idc), and the RF input signal (RF IN They are connected in parallel or cascaded to each other for the purpose of AC RF output current (I RF_OUT They are connected in parallel or cascaded to each other for the purpose of: The first and second stages are cascode-connected to each other for DC supply current. A method for operating a high-voltage multi-stage signal amplifier (1900) (2000).

[0188] The method of the

[0189] Clause 47. The method according to Clause 46, wherein the DC supply voltage drop across each of the first and second stage transconductance cells (1970a, 1970b, 1970e, 1970f) is Vdd / N, where N is the number of first and second stage transconductance cells (1970a, 1970b, 1970e, 1970f).

[0190] Clause 48. The RF input signal (RF) is determined by the input signal source (Vin). IN The method described in Clause 45, further including providing (M1)(1920) to the input matching network (M1)(2020).

[0191] Clause 49. The method according to Clause 48, wherein the input matching network (M1)(1920) is a single-input single-output matching network.

[0192] Clause 50. The RF input signal (RF) is transmitted through the input matching network (M1)(1920). IN The method of Clause 48, further comprising converting (2030) to provide power matching to the respective inputs of the first stage transconductance cells (1970a, 1970b).

[0193] Clause 51. AC RF output current (I) from at least one transconductance cell of the multiple transconductance cells (1970a, 1970b) of the first stage. RF_OUT The method of Clause 45, further comprising inputting (1930) into an internal stage matching network (M2) (1930) to transmit power to the transconductance cells (1970e, 1970f) of the second stage (2090).

[0194] Clause 52. The method according to Clause 51, wherein the input-matched network (M2)(1930) is a single-input, single-output matched network.

[0195] Clause 53. AC RF output current (I) from at least one transconductance cell of the multiple transconductance cells (1970e, 1970f) of the second stage. RF_OUT ) is input to the output matching network (M3) (1940) and the load (R L The method of Clause 45, further including transmitting power to (2095).

[0196] Clause 54. The method according to Clause 53, wherein the output-matched network (M3) (1940) is a single-input, single-output matched network.

[0197] Clause 55. High-voltage signal amplifier (1300), Multiple transconductance cells (1310a, 1310b), each receiving a direct current (DC) supply current (Idc) and an alternating current (AC) high-frequency (RF) input current (Idc).RF_IN ), and RF input signal (RF IN ) are configured to receive a DC supply current (Idc) and an AC RF output current (Idc), respectively. RF_OUT It includes multiple transconductance cells (1310a, 1310b) configured to output ), The transconductance cells (1310a, 1310b) are cascoded together for the DC supply current (Idc) and the RF input signal (RF IN They are connected in parallel to each other for the purpose of ) and AC RF output current (I RF_OUT They are connected in parallel to each other for the purpose of High-voltage signal amplifier (1300).

[0198] Clause 56. The system receives an RF input signal (RF IN The amplifier according to Clause 55 further includes an input signal source (Vin) that provides an input matching network (M1) (1320).

[0199] Clause 57. The amplifier described in Clause 56, wherein the input matching network (M1)(1320) is a single-input, single-output matching network.

[0200] Clause 58. Input matching network (M1)(1320) shall have an RF input signal (RF IN The amplifier described in Clause 56 converts ) to provide power matching to the respective inputs of the transconductance cells (1310a, 1310b).

[0201] Clause 59. AC RF output current (I) from one of the transconductance cells (1310a, 1310b) RF_OUT ) is input to the output matching network (M2) (1330), and the load impedance (R L The amplifier described in Clause 55, to which power is transmitted.

[0202] Clause 60. The amplifier described in Clause 59, wherein the output matching network (M2)(1330) is a single-input, single-output matching network.

[0203] Clause 61. The amplifier according to Clause 55, wherein each of the transconductance cells (1310a, 1310b) includes a metal-oxide-silicon field-effect transistor (MOSFET).

[0204] Clause 62. The amplifier according to Clause 55, wherein each of the transconductance cells (1310a, 1310b) includes a bipolar junction transistor (BJT).

[0205] Clause 63. The amplifier according to Clause 55, wherein the power supply voltage (Vdd) is evenly distributed among the transconductance cells (1310a, 1310b) to supply power to the transconductance cells (1310a, 1310b).

[0206] Clause 64. The amplifier described in Clause 63, wherein the DC supply voltage drop across each of the transconductance cells (1310a, 1310b) is Vdd / N, where N is the number of transconductance cells (1310a, 1310b).

[0207] Clause 65. High-voltage signal amplifier (1300), Multiple transconductance cells (1310a, 1310b), each receiving a direct current (DC) supply current (Idc) and an alternating current (AC) high-frequency (RF) input current (Idc). RF_IN ), and RF input signal (RF IN ) are configured to receive a DC supply current (Idc) and an AC RF output current (Idc), respectively. RF_OUT It includes multiple transconductance cells (1310a, 1310b) configured to output ), The transconductance cells (1310a, 1310b) are cascoded together for the DC supply current (Idc) and the RF input signal (RF IN They are connected in parallel to each other for the purpose of ) and AC RF output current (I RF_OUT They are cascaded to each other for the purpose of High-voltage signal amplifier (1300).

[0208] Clause 66. The amplifier receives an RF input signal (RF IN The amplifier according to Clause 65, including an input signal source (Vin) that provides an input matching network (M1) (1320).

[0209] Clause 67. The amplifier described in Clause 66, wherein the input matching network (M1)(1320) is a single-input, single-output matching network.

[0210] Clause 68. Input matching network (M1)(1320) shall have an RF input signal (RF IN The amplifier described in Clause 66, which converts ) to provide power matching to the respective inputs of the transconductance cells (1310a, 1310b).

[0211] Clause 69. AC RF output current (I) from one of the transconductance cells (1310a, 1310b) RF_OUT ) is input to the output matching network (M2) (1330), and the load impedance (R L The amplifier described in Clause 65, to which power is transmitted.

[0212] Clause 70. The amplifier described in Clause 69, wherein the output matching network (M2)(1330) is a single-input, single-output matching network.

[0213] Clause 71. The amplifier according to Clause 69, wherein the output matching network (M2) (1330) is connected to the output junction of one of the transconductance cells (1310a, 1310b).

[0214] Clause 72. The amplifier according to Clause 65, wherein each of the transconductance cells (1310a, 1310b) includes a metal-oxide-silicon field-effect transistor (MOSFET).

[0215] Clause 73. The amplifier according to Clause 65, wherein each of the transconductance cells (1310a, 1310b) includes a bipolar junction transistor (BJT).

[0216] Clause 74. The amplifier according to Clause 65, wherein the power supply voltage (Vdd) is evenly distributed among the transconductance cells (1310a, 1310b) to supply power to the transconductance cells (1310a, 1310b).

[0217] Clause 75. The amplifier described in Clause 74, wherein the DC supply voltage drop across each of the transconductance cells (1310a, 1310b) is Vdd / N, where N is the number of transconductance cells (1310a, 1310b).

[0218] Article 76. High-voltage signal amplifier (1300), Multiple transconductance cells (1310a, 1310b), each receiving a direct current (DC) supply current (Idc) and an alternating current (AC) high-frequency (RF) input current (Idc). RF_IN ), and RF input signal (RF IN ) are configured to receive a DC supply current (Idc) and an AC RF output current (Idc), respectively. RF_OUT It includes multiple transconductance cells (1310a, 1310b) configured to output ), The transconductance cells (1310a, 1310b) are cascoded together for the DC supply current (Idc) and the RF input signal (RF IN They are cascaded to each other for the purpose of AC RF output current (I RF_OUT They are connected in parallel to each other for the purpose of High-voltage signal amplifier (1300).

[0219] Clause 77. The amplifier receives an RF input signal (RF IN The amplifier according to Clause 76, further comprising an input signal source (Vin) for providing an input matching network (M1) (1320).

[0220] Clause 78. The amplifier described in Clause 77, wherein the input matching network (M1)(1320) is a single-input, single-output matching network.

[0221] Clause 79. Input matching network (M1)(1320) shall have an RF input signal (RF IN The amplifier described in Clause 77 converts ) to provide power matching to the respective inputs of the transconductance cells (1310a, 1310b).

[0222] Clause 80. The amplifier according to Clause 77, wherein the input matching network (M1) (1320) is connected to one of the input junctions of the transconductance cells (1310a, 1310b).

[0223] Clause 81. AC RF output current (I) from one of the transconductance cells (1310a, 1310b) RF_OUT ) is input to the output matching network (M2) (1330), and the load impedance (R L The amplifier described in Clause 76, to which power is transmitted.

[0224] Clause 82. The amplifier described in Clause 81, wherein the output matching network (M2)(1330) is a single-input, single-output matching network.

[0225] Clause 83. The amplifier according to Clause 76, wherein each of the transconductance cells (1310a, 1310b) comprises a metal-oxide-silicon field-effect transistor (MOSFET).

[0226] Clause 84. The amplifier according to Clause 76, wherein each of the transconductance cells (1310a, 1310b) includes a bipolar junction transistor (BJT).

[0227] Clause 85. The amplifier according to Clause 76, wherein the power supply voltage (Vdd) is evenly distributed among the transconductance cells (1310a, 1310b) to supply power to the transconductance cells (1310a, 1310b).

[0228] Clause 86. The amplifier described in Clause 85, wherein the DC supply voltage drop across each of the transconductance cells (1310a, 1310b) is Vdd / N, where N is the number of transconductance cells (1310a, 1310b).

[0229] Article 87. High-voltage signal amplifier (1300), Multiple transconductance cells (1310a, 1310b), each receiving a direct current (DC) supply current (Idc) and an alternating current (AC) high-frequency (RF) input current (Idc). RF_IN ), and RF input signal (RF IN ) are configured to receive a DC supply current (Idc) and an AC RF output current (Idc), respectively. RF_OUT It includes multiple transconductance cells (1310a, 1310b) configured to output ), The transconductance cells (1310a, 1310b) are cascoded together for the DC supply current (Idc) and the RF input signal (RF IN They are cascaded to each other for the purpose of AC RF output current (I RF_OUT They are cascaded to each other for the purpose of High-voltage signal amplifier (1300).

[0230] Clause 88. The amplifier receives an RF input signal (RF IN The amplifier according to Clause 87, further comprising an input signal source (Vin) for providing an input matching network (M1) (1320).

[0231] Clause 89. The amplifier described in Clause 88, wherein the input matching network (M1)(1320) is a single-input, single-output matching network.

[0232] Clause 90. Input matching network (M1)(1320) is an RF input signal (RF IN The amplifier described in Clause 88 converts ) to provide power matching to the respective inputs of the transconductance cells (1310a, 1310b).

[0233] Clause 91. The amplifier according to Clause 88, wherein the input matching network (M1) (1320) is connected to one of the input junctions of the transconductance cells (1310a, 1310b).

[0234] Clause 92. AC RF output current (I) from one of the transconductance cells (1310a, 1310b) RF_OUT ) is input to the output matching network (M2) (1330), and the load impedance (R L An amplifier as described in Clause 87, to which power is transmitted.

[0235] Clause 93. The amplifier described in Clause 92, wherein the output matching network (M2)(1330) is a single-input, single-output matching network.

[0236] Clause 94. The amplifier according to Clause 92, wherein the output matching network (M2) (1330) is connected to the output junction of one of the transconductance cells (1310a, 1310b).

[0237] Clause 95. The amplifier according to Clause 87, wherein each of the transconductance cells (1310a, 1310b) comprises a metal-oxide-silicon field-effect transistor (MOSFET).

[0238] Clause 96. The amplifier described in Clause 87, wherein each of the transconductance cells (1310a, 1310b) includes a bipolar junction transistor (BJT).

[0239] Clause 97. The amplifier according to Clause 87, wherein the power supply voltage (Vdd) is evenly distributed among the transconductance cells (1310a, 1310b) to supply power to the transconductance cells (1310a, 1310b).

[0240] Clause 98. The amplifier described in Clause 97, wherein the DC supply voltage drop across each of the transconductance cells (1310a, 1310b) is Vdd / N, where N is the number of transconductance cells (1310a, 1310b).

[0241] Article 99. High-voltage multi-stage signal amplifier (1900), The first stage consists of multiple transconductance cells (1970a, 1970b), each receiving a direct current (DC) supply current (Idc) and an alternating current (AC) radio frequency (RF) input current (Idc). RF_IN ), and RF input signal (RF IN ) are configured to receive a DC supply current (Idc) and an AC RF output current (Idc), respectively. RF_OUT A first stage consisting of multiple transconductance cells (1970a, 1970b) configured to output ), The second stage consists of multiple transconductance cells (1970e, 1970f), each receiving a direct current (DC) supply current (Idc) and an alternating frequency (AC) radio frequency (RF) input current (Idc). RF_IN ), and RF input signal (RF IN ) are configured to receive a DC supply current (Idc) and an AC RF output current (Idc), respectively. RF_OUT The second stage consists of multiple transconductance cells (1970e, 1970f) configured to output ), Includes, The first stage transconductance cells (1970a, 1970b) are cascoded together for the DC supply current (Idc) and the RF input signal (RF IN They are connected in parallel or cascaded to each other for the purpose of AC RF output current (I RF_OUT They are connected in parallel or cascaded to each other for the purpose of: The second stage transconductance cells (1970e, 1970f) are cascoded together for the DC supply current (Idc) and the RF input signal (RF IN They are connected in parallel or cascaded to each other for the purpose of AC RF output current (I RF_OUT They are connected in parallel or cascaded to each other for the purpose of: The first and second stages are cascaded to each other for DC supply current. High-voltage multi-stage signal amplifier (1900).

[0242] Clause 100. The amplifier according to Clause 99, wherein the power supply voltage (Vdd) is evenly distributed among the transconductance cells (1970a, 1970b, 1970e, 1970f) of the first and second stages to supply power to the transconductance cells (1970a, 1970b, 1970e, 1970f) of the first and second stages.

[0243] Clause 101. The amplifier according to Clause 100, wherein the DC supply voltage drop in the first and second stage transconductance cells (1970a, 1970b, 1970e, 1970f) is Vdd / N, where N is the number of first and second stage transconductance cells (1970a, 1970b, 1970e, 1970f).

[0244] Clause 102. The amplifier receives an RF input signal (RF IN The amplifier according to Clause 99 further includes an input signal source (Vin) that provides an input matching network (M1) (1920).

[0245] Clause 103. The amplifier described in Clause 102, wherein the input matching network (M1)(1920) is a single-input, single-output matching network.

[0246] Clause 104. Input matching network (M1)(1920) shall have an RF input signal (RF IN The amplifier described in Clause 102, which converts ) to provide power matching to the respective inputs of the first stage transconductance cells (1970a, 1970b).

[0247] Clause 105. The AC RF output current (I) from at least one of the transconductance cells (1970a, 1970b) of the multiple transconductance cells in the first stage. RF_OUT The amplifier described in Clause 99, wherein the power is input to an internal stage matching network (M2) (1930) and power is transferred to the transconductance cells (1970e, 1970f) of the second stage.

[0248] Clause 106. The amplifier described in Clause 105, wherein the internal stage matching network (M2) (1930) is a single-input, single-output matching network.

[0249] Clause 107. AC RF output current (I) from at least one transconductance cell among the multiple transconductance cells (1970e, 1970f) of the second stage. RF_OUT ) is input to the output matching network (M3) (1940), and the load impedance (R L The amplifier described in Clause 99, to which power is transmitted.

[0250] Clause 108. The amplifier described in Clause 107, wherein the output matching network (M3) (1940) is a single-input, single-output matching network.

[0251] Clause 109. A method (1800) for the operation of a high-voltage signal amplifier (1300), Each of the multiple transconductance cells (1310a, 1310b) receives a direct current (DC) supply current (Idc) and an alternating current (AC) radio frequency (RF) input current (Idc). RF_IN ), and RF input signal (RF IN Entering (1850) and Each of the transconductance cells (1310a, 1310b) controls the DC supply current (Idc) and the AC RF output current (Idc). RF_OUT ) to output (1860), Includes, The transconductance cells (1310a, 1310b) are cascoded together for the DC supply current (Idc) and the RF input signal (RF IN They are connected in parallel or cascaded to each other for the purpose of AC RF output current (I RF_OUT They are connected in parallel or cascaded to each other for the purpose of: A method (1800) for the operation of a high-voltage signal amplifier (1300).

[0252] Clause 110. The RF input signal (RF) is determined by the input signal source (Vin). IN The method according to Clause 109, further comprising providing (1820) an input matching network (M1) (1320).

[0253] Clause 111. The method according to Clause 110, wherein the input matching network (M1)(1320) is a single-input single-output matching network.

[0254] Clause 112. Input matching network (M1)(1320) enables RF input signal (RF IN The method according to clause 110, further comprising converting (1830) to provide power matching to the respective inputs of the transconductance cells (1310a, 1310b).

[0255] Clause 113. Transconductance cells (1310a, 1310b) receive an RF input signal (RF IN The method according to clause 110, wherein the input matching network (M1)(1320) is cascaded to one of the transconductance cells (1310a, 1310b) and connected to an input junction.

[0256] Clause 114. AC RF output current (I) from one of the transconductance cells (1310a, 1310b) RF_OUT ) is input to the output matching network (M2) (1330) and the load impedance (R L The method described in Article 109, further including transmitting power to (1870).

[0257] Clause 115. The method according to Clause 114, wherein the output-matched network (M2)(1330) is a single-input, single-output matched network.

[0258] Clause 116. Transconductance cells (1310a, 1310b) have AC RF output current (I RF_OUTThe method according to clause 114, wherein the output matching network (M2)(1330) is cascaded to one of the transconductance cells (1310a, 1310b) and connected to an output junction.

[0259] Clause 117. The method according to Clause 109, wherein each of the transconductance cells (1310a, 1310b) comprises a metal-oxide-silicon field-effect transistor (MOSFET).

[0260] Clause 118. The method according to Clause 109, wherein each of the transconductance cells (1310a, 1310b) includes a bipolar junction transistor (BJT).

[0261] The method according to Clause 119, further comprising distributing the power supply voltage (Vdd) equally among the transconductance cells (1310a, 1310b) to supply power to the transconductance cells (1310a, 1310b) (1840).

[0262] Clause 120. The method according to Clause 119, wherein the DC supply voltage drop across each of the transconductance cells (1310a, 1310b) is Vdd / N, where N is the number of transconductance cells (1310a, 1310b).

[0263] Clause 121. High-voltage signal amplifier (1300), Multiple transconductance cells (1310a, 1310b), each receiving a direct current (DC) supply current (Idc) and an alternating current (AC) high-frequency (RF) input current (Idc). RF_IN ), and RF input signal (RF IN ) are configured to receive a DC supply current (Idc) and an AC RF output current (Idc), respectively. RF_OUT It includes multiple transconductance cells (1310a, 1310b) configured to output ), The transconductance cells (1310a, 1310b) are cascoded together for the DC supply current (Idc) and the RF input signal (RF INThey are connected in parallel or cascaded to each other for the purpose of AC RF output current (I RF_OUT They are connected in parallel or cascaded to each other for the purpose of: High-voltage signal amplifier (1300).

[0264] Clause 122. The amplifier receives an RF input signal (RF IN The amplifier according to Clause 121, including an input signal source (Vin) that provides an input matching network (M1) (1320).

[0265] Clause 123. The amplifier described in Clause 122, wherein the input matching network (M1)(1320) is a single-input, single-output matching network.

[0266] Clause 124. Input matching network (M1) (1320) is an RF input signal (RF IN The amplifier described in Clause 122 converts ) to provide power matching to the respective inputs of the transconductance cells (1310a, 1310b).

[0267] Clause 125. Transconductance cells (1310a, 1310b) receive an RF input signal (RF IN The amplifier according to Clause 122, wherein the input matching network (M1)(1320) is cascaded to one of the transconductance cells (1310a, 1310b) and the input matching network (M1)(1320) is connected to the input junction of one of the transconductance cells (1310a, 1310b).

[0268] Clause 126. AC RF output current (I) from one of the transconductance cells (1310a, 1310b) RF_OUT ) is input to the output matching network (M2) (1330), and the load impedance (R L The amplifier described in Clause 121, to which power is transmitted.

[0269] Clause 127. The amplifier described in Clause 126, wherein the output matching network (M2) (1330) is a single-input, single-output matching network.

[0270] Clause 128. Transconductance cells (1310a, 1310b) AF RF output current (I RF_OUT The amplifier according to Clause 126, wherein output matching networks (M2) (1330) are cascaded to each other for the purpose of connecting to the output junction of one of the transconductance cells (1310a, 1310b).

[0271] Clause 129. The amplifier according to Clause 121, wherein each of the transconductance cells (1310a, 1310b) includes a metal-oxide-silicon field-effect transistor (MOSFET).

[0272] Clause 130. The amplifier according to Clause 121, wherein each of the transconductance cells (1310a, 1310b) includes a bipolar junction transistor (BJT).

[0273] Clause 131. The amplifier according to Clause 121, wherein the power supply voltage (Vdd) is evenly distributed among the transconductance cells (1310a, 1310b) to supply power to the transconductance cells (1310a, 1310b).

[0274] Clause 132. The amplifier described in Clause 131, wherein the DC supply voltage drop across each of the transconductance cells (1310a, 1310b) is Vdd / N, where N is the number of transconductance cells (1310a, 1310b).

[0275] While certain exemplary embodiments and methods have been disclosed herein, it will be apparent to those skilled in the art from the foregoing disclosure that such embodiments and methods can be modified and altered without departing from the true spirit and scope of this disclosure. Many other examples exist, each differing in its details from others. Accordingly, this disclosure is intended to be limited to the extent required by the appended claims and applicable rules and principles of law.

Claims

1. A method for operating a high-voltage multi-stage signal amplifier (1900), Distributing the power supply voltage (Vdd) among the multiple transconductance cells of the first and second stages to supply power to the transconductance cells of the first and second stages (2040), The above-mentioned transconductance cells of the first stage (1970a, 1970b) are to be supplied with at least a direct current (DC) supply current (Idc) and an RF input signal (RFIN) (2050), The following is done: a DC supply current (Idc), an alternating current (AC) high-frequency (RF) input current (IRF_IN), and the RF input signal (RF IN) are input to each of the transconductance cells (1970e, 1970f) of the second stage (2060), Each of the transconductance cells (1970a, 1970b) in the first stage outputs the DC supply current (Idc) and the AC RF output current (2070), Each of the transconductance cells (1970e, 1970f) in the second stage outputs the DC supply current (Idc) and the AC RF output current (2080), Includes, The transconductance cells (1970a, 1970b) of the first stage are cascoded to each other for the direct current (DC) supply current (Idc), connected in parallel or cascaded to each other for the RF input signal (RFIN), and connected in parallel or cascaded to each other for the AC RF output current. The transconductance cells (1970e, 1970f) of the second stage are cascoded to each other for the direct current (DC) supply current (Idc), connected in parallel or cascaded to each other for the RF input signal (RF IN), and connected in parallel or cascaded to each other for the AC RF output current. The first stage and the second stage are cascode-connected to each other for the DC supply current. A method for operating a high-voltage multi-stage signal amplifier (1900).

2. The method according to claim 1, further comprising providing the RF input signal (RFIN) to an input matching network (M1) (1920) (2020) via an input signal source (Vin).

3. The method according to claim 2, wherein the input matching network (M1) (1920) is a single-input single-output matching network.

4. The method of claim 2, further comprising: an input matching network (M1) (1920) converting the RF input signal (RFIN) to provide power matching to the respective inputs of the first stage transconductance cells (1970a, 1970b) (2030).

5. The method according to claim 1, further comprising inputting the AC RF output current output from at least one of the plurality of transconductance cells (1970a, 1970b) of the first stage to an internal stage matching network (M2) (1930) to transmit power to the plurality of transconductance cells (1970e, 1970f) of the second stage (2090).

6. The method according to claim 5, wherein the internal stage matching network (M2) (1930) is a single-input single-output matching network.

7. The method according to claim 1, further comprising inputting the AC RF output current output from at least one of the plurality of transconductance cells (1970e, 1970f) of the second stage into an output matching network (M3) (1940) to transmit power to a load (R L) (2095).

8. The method according to claim 7, wherein the output matching network (M3) (1940) is a single-input single-output matching network.

9. The method according to claim 1, wherein each of the transconductance cells (1970a, 1970b) of the first stage includes a metal-oxide-silicon field-effect transistor (MOSFET), and / or each of the transconductance cells (1970e, 1970f) of the second stage includes a metal-oxide-silicon field-effect transistor (MOSFET).

10. The method according to claim 1, wherein each of the transconductance cells (1970a, 1970b) of the first stage includes a bipolar junction transistor (BJT), and / or each of the transconductance cells (1970e, 1970f) of the second stage includes a bipolar junction transistor (BJT).

11. The method according to claim 1, wherein the power supply voltage (Vdd) is evenly distributed among the plurality of transconductance cells of the first and second stages, and the plurality of transconductance cells of the first and second stages are powered.

12. The method according to claim 11, wherein the DC supply voltage drop at each of the transconductance cells (1970a, 1970b, 1970e, 1970f) of the first and second stages is Vdd / N, where N is the number of transconductance cells (1970a, 1970b, 1970e, 1970f) of the first and second stages.

13. A high-voltage multi-stage signal amplifier, A plurality of transconductance cells (1970a, 1970b) of the first stage, each configured to receive at least a direct current (DC) supply current (Idc) and an RF input signal (RFIN), and each configured to output the said direct current (DC) supply current (Idc) and an alternating current (AC) high-frequency (RF) output current, A plurality of transconductance cells (1970e, 1970f) in the second stage, each configured to receive a direct current (DC) supply current (Idc), an alternating current (AC) high frequency (RF) input current (IRF_IN), and an RF input signal (RF IN), and each configured to output the said direct current (DC) supply current (Idc) and AC RF output current, Includes, The power supply voltage (Vdd) is distributed among the transconductance cells (1970a, 1970b, 1970e, 1970f) of the first and second stages, and power is supplied to the transconductance cells (1970a, 1970b, 1970e, 1970f) of the first and second stages. The transconductance cells (1970a, 1970b) of the first stage are cascoded together for the direct current (DC) supply current (Idc), and the RF input signal (RF ＩＮ They are connected in parallel or cascaded to each other for the purpose of, and are connected in parallel or cascaded to each other for the purpose of the AC RF output current, The transconductance cells (1970e, 1970f) of the second stage are cascoded to each other for the DC supply current (Idc), connected in parallel or cascaded to each other for the RF input signal (RF IN), and connected in parallel or cascaded to each other for the AC RF output current. The first stage and the second stage are cascode-connected to each other for the DC supply current. High-voltage multi-stage signal amplifier.

14. The high-voltage multistage signal amplifier according to claim 13, further comprising an input signal source (Vin) that provides the RF input signal (RFIN) to an input matching network (M1) (1920).

15. The high-voltage multi-stage signal amplifier according to claim 14, wherein the input matching network (M1) (1920) is a single-input single-output matching network.

16. The high-voltage multistage signal amplifier according to claim 14, wherein the input matching network (M1) (1920) converts the RF input signal (RFIN) to provide power matching to the respective inputs of the first stage transconductance cells (1970a, 1970b).

17. The high-voltage multi-stage signal amplifier according to claim 13, wherein the AC RF output current output from at least one of the plurality of transconductance cells (1970a, 1970b) of the first stage is input to an internal stage matching network (M2) (1930) to transmit power to the plurality of transconductance cells (1970e, 1970f) of the second stage.

18. The high-voltage multi-stage signal amplifier according to claim 17, wherein the internal stage matching network (M2) (1930) is a single-input single-output matching network.

19. The high-voltage multi-stage signal amplifier according to claim 13, wherein the AC RF output current output from at least one of the plurality of transconductance cells (1970e, 1970f) of the second stage is input to an output matching network (M3) (1940) to transmit power to a load impedance (RL).

20. The high-voltage multi-stage signal amplifier according to claim 19, wherein the output matching network (M3) (1940) is a single-input single-output matching network.

21. The high-voltage multi-stage signal amplifier according to claim 13, wherein each of the transconductance cells (1970a, 1970b) of the first stage includes a metal-oxide-silicon field-effect transistor (MOSFET), and / or each of the transconductance cells (1970e, 1970f) of the second stage includes a metal-oxide-silicon field-effect transistor (MOSFET).

22. The high-voltage multi-stage signal amplifier according to claim 13, wherein each of the transconductance cells (1970a, 1970b) of the first stage includes a bipolar junction transistor (BJT), and / or each of the transconductance cells (1970e, 1970f) of the second stage includes a bipolar junction transistor (BJT).

23. The high-voltage multi-stage signal amplifier according to claim 13, wherein the power supply voltage (Vdd) is evenly distributed among the transconductance cells (1970a, 1970b, 1970e, 1970f) of the first and second stages to supply power to the transconductance cells (1970a, 1970b, 1970e, 1970f) of the first and second stages.

24. The high-voltage multi-stage signal amplifier according to claim 23, wherein the DC supply voltage drop in each of the transconductance cells of the first stage and the second stage is Vdd / N, where N is the number of transconductance cells of the first stage and the second stage.

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