Multilayer substrates and methods for manufacturing multilayer substrates

Abstract

To ensure that nickel-gold plating on pads for mounting smaller diameter semiconductor elements is not spherical and that the probes make good contact.SOLUTION: A multilayer substrate 20 has a plurality of insulating layers 22 and a plurality of metal layers 27 patterned and formed within each insulating layer 22. Each metal layer 27 is interlayer connected by vias. A plurality of pads 21 for mounting semiconductor elements are formed on one side and pads 24 for external connection are formed on the other side. Each pad 21 for mounting semiconductor elements is formed to be the same surface as the surface of the insulating layer 22 located on the one side.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a multilayer substrate and a method for manufacturing a multilayer substrate. Background Art

[0002] An interposer for mounting a semiconductor element is formed of a multilayer substrate, wherein one surface of the interposer is provided with semiconductor element mounting pads for mounting the semiconductor element, and the other surface is provided with external connection pads for connection to the outside such as a mother board (for example, Patent Document 1: Japanese Patent No. 5566200).

[0003] Furthermore, it is described that in the interposer of Patent Document 1, the semiconductor element mounting pads are formed in a circular shape in plan view, have a diameter of 50 to 100 µm, and are set to have an arrangement pitch of 90 to 150 µm. Prior Art Literature Patent Literature

[0004] Patent Document 1 Japanese Patent No. 5566200 Summary of Invention Problem to be Solved by the Invention

[0005] Along with the reduction in size and improvement in performance of semiconductor elements, the size of bumps (electrodes) of semiconductor elements has been reduced in diameter, and furthermore, the distance between adjacent bumps has been shortened, resulting in narrower pitches. For this reason, it is necessary to further promote the reduction in diameter and narrowing of pitch of the semiconductor element mounting pads of the interposer.

[0006] It is generally known that the semiconductor element mounting pads of an interposer are formed by applying nickel-gold (Ni-Au) plating to a copper surface in order to ensure corrosion resistance, contact characteristics and the like. However, when nickel-gold plating is applied to semiconductor device mounting pads that protrude from the insulating layer surface and have a reduced diameter, the nickel-gold plating takes on a nearly spherical shape, creating a risk that the probe may detach and fall off when attempting to make contact with it using a probe card during inspection. Furthermore, since the nickel-gold plating is also applied to the sides of the semiconductor device mounting pads in a way that protrudes laterally, there is a challenge in that it is not possible to narrow the pitch between the semiconductor device mounting pads. [Means for solving the problem]

[0007] Therefore, the present invention has been made to solve the above problems, and its objective is to provide a multilayer substrate that can be inspected without problems even if the pads for mounting semiconductor elements are made smaller in diameter and narrower in pitch, and a method for manufacturing a multilayer substrate that can make the pads for mounting semiconductor elements smaller in diameter and narrower in pitch.

[0008] The multilayer substrate according to the present invention has a plurality of insulating layers and a plurality of metal layers formed in a pattern within each insulating layer, the metal layers are interlayer-connected by vias, a plurality of pads for mounting semiconductor elements are formed on one side and pads for external connections are formed on the other side, and each of the semiconductor element mounting pads is formed to be on the same surface as the insulating layer located on one side. The surface of each pad for mounting the semiconductor element is smoothly covered with a nickel-gold plating layer. It is characterized by the following. By adopting this configuration, the pads for mounting semiconductor devices do not protrude from the surface of the insulating layer. Therefore, even if nickel-gold plating is applied to the pads for mounting semiconductor devices, the nickel-gold plating does not become spherical, preventing the probe from detaching from the pad.

[0009] Furthermore, each of the aforementioned external connection pads may be characterized by being made of conductive paste. With this configuration, when laminating the multilayer substrate of the present invention onto other multilayer substrates such as motherboards, an adhesive layer is not required, and the time required for lamination onto other multilayer substrates can be reduced.

[0010] Furthermore, the diameter of each pad for mounting the semiconductor element may be 25 μm to 30 μm, and the distance between the centers of adjacent pads for mounting the semiconductor element may be 40 μm or less.

[0011] Furthermore, the invention may be characterized in that a via formed in a predetermined insulating layer and a metal layer formed in an insulating layer located on the other side of the via are integrally formed, and one side of the integrally formed via and metal layer is covered by a seed metal layer.

[0012] The present invention relates to a method for manufacturing a multilayer substrate having a plurality of insulating layers and a plurality of metal layers patterned and formed within each insulating layer, with the metal layers interlayer-connected by vias, a plurality of pads for semiconductor element mounting formed on one side, and pads for external connections formed on the other side. The method involves first forming the pads for semiconductor element mounting on one side, and finally forming the pads for external connections on the other side so that the spacing between them is wider than the spacing between the pads for semiconductor element mounting. The step of forming the pads for semiconductor element mounting includes the steps of forming a metal layer as a pad for semiconductor element mounting on the upper surface of a support, and forming an insulating layer on the upper surface of the support such that the metal layer is embedded, and the surface of the pads for semiconductor element mounting is formed to be the same surface as the surface of the insulating layer located on one side. Furthermore, when forming the external connection pad on the other side, via holes are formed in the insulating layer on the other side, and conductive paste is filled into the via holes to form the conductive paste as the external connection pad. After the formation of the external connection pad, the support is peeled off, and nickel-gold plating is applied to the surface of the semiconductor element mounting pad that is exposed by peeling off the support. It is characterized by the following. By adopting this method, fine-pitch pads for semiconductor device mounting are formed first, which prevents warping of the multilayer substrate at an early stage and enables the manufacture of flat multilayer substrates. Furthermore, since the pads for mounting semiconductor devices do not protrude from the surface of the insulating layer, even when nickel-gold plating is applied to the pads for mounting semiconductor devices with reduced diameter, the nickel-gold plating does not become spherical, making it possible to manufacture a multilayer substrate that prevents the probe from coming off the pad. In addition, since the sides of the pads for mounting semiconductor devices are not exposed from the insulating layer, nickel-gold plating is not formed on the sides of the pads for mounting semiconductor devices, and the spacing between adjacent pads for mounting semiconductor devices can be narrowed. Furthermore, this method eliminates the need for an adhesive layer when laminating a multilayer substrate onto other multilayer substrates such as motherboards, thereby reducing the time required for lamination onto other multilayer substrates.

[0013] Furthermore, the support may be characterized in that a metal layer is formed on the surface of a glass plate.

[0014] Furthermore, the method may be characterized by including the steps of: forming via holes in each insulating layer that communicate with the metal layer; forming a seed metal layer on the insulating layer including the via holes by sputtering; forming vias and a metal layer on the seed metal layer by electroplating; and etching the metal layer formed on the seed metal layer into a predetermined pattern. This method does not involve the formation of vias and metal layers by electroless plating, thus preventing palladium deposition and maintaining good insulation properties between metal patterns. [Effects of the Invention]

[0016] According to the present invention, since the pads for mounting semiconductor devices do not protrude from the surface of the insulating layer, the nickel-gold plating on the reduced-diameter pads for mounting semiconductor devices does not become spherical, and good probe contact can be achieved. Furthermore, since it is possible to manufacture multilayer substrates in which the pads for semiconductor device mounting do not protrude from the surface of the insulating layer, it is possible to reduce the diameter and pitch of the pads for semiconductor device mounting. [Brief explanation of the drawing]

[0017] [Figure 1] This is a schematic cross-sectional view showing an example of a multilayer substrate. [Figure 2] It is a schematic cross-sectional view (Part 1) showing an example of a method for manufacturing a multilayer substrate. [Figure 3] It is a schematic cross-sectional view (Part 2) showing an example of a method for manufacturing a multilayer substrate. [Figure 4] It is a schematic cross-sectional view (Part 3) showing an example of a method for manufacturing a multilayer substrate. [Figure 5] It is a schematic cross-sectional view (Part 4) showing an example of a method for manufacturing a multilayer substrate. [Figure 6] It is a schematic cross-sectional view (Part 5) showing an example of a method for manufacturing a multilayer substrate. [Figure 7] It is a schematic cross-sectional view (Part 6) showing an example of a method for manufacturing a multilayer substrate. [Figure 8] It is a schematic cross-sectional view (Part 7) showing an example of a method for manufacturing a multilayer substrate. [Figure 9] It is a schematic cross-sectional view (Part 8) showing an example of a method for manufacturing a multilayer substrate. [Figure 10] It is a schematic cross-sectional view (Part 9) showing an example of a method for manufacturing a multilayer substrate. [Figure 11] It is a schematic cross-sectional view (Part 10) showing an example of a method for manufacturing a multilayer substrate. [Figure 12] It is a schematic cross-sectional view (Part 11) showing an example of a method for manufacturing a multilayer substrate. [Figure 13] It is a schematic cross-sectional view (Part 12) showing an example of a method for manufacturing a multilayer substrate. [Figure 14] It is a schematic cross-sectional view (Part 13) showing an example of a method for manufacturing a multilayer substrate. [Figure 15] It is a schematic cross-sectional view (Part 14) showing an example of a method for manufacturing a multilayer substrate. [Figure 16] It is a schematic cross-sectional view (Part 15) showing an example of a method for manufacturing a multilayer substrate. [Figure 17] It is a schematic cross-sectional view showing a state where the resin film and the support have been peeled off from the completed multilayer substrate. [Figure 18] It is a schematic cross-sectional view showing nickel-gold plating on the surface of a pad for mounting a semiconductor element. [Figure 19]This is a schematic cross-sectional view showing nickel-gold plating on the surface of a pad for semiconductor device mounting as a comparative example. [Modes for carrying out the invention]

[0018] (Multilayer board) Figure 1 shows a schematic cross-sectional view of a multilayer substrate capable of mounting semiconductor devices. In this embodiment, the multilayer substrate 20 has multiple semiconductor element mounting pads 21 formed on one side so that semiconductor elements 10 can be mounted on that side. Furthermore, external connection pads 24 are formed on the other side of the multilayer substrate 20. The external connection pads 24 are connected to another multilayer substrate 40, such as a motherboard.

[0019] The multilayer substrate 20 has a plurality of insulating layers 22, a patterned metal layer 27 embedded on the semiconductor element mounting side of each of the plurality of insulating layers 22, and vias 28 that electrically connect the metal layers 27 to each other. The spacing between the semiconductor element mounting pads 21 is narrow, while the spacing between the external connection pads 24 is wider than the spacing between the semiconductor element mounting pads 21, as the interlayer metal layers 27 and vias 28 are configured to connect the respective pads.

[0020] As the insulating layer 22, a resin film made of a thermosetting resin mainly composed of epoxy resin or polyimide can be used. Furthermore, the pair of metal layers 27 and vias 28 between the layers are formed in a convex shape, with the via 28 formed within the insulating layer 22 on the semiconductor element mounting side and the metal layer 27 embedded within the insulating layer 22 on the external connection side of the via 28. In addition, the semiconductor element mounting side of the metal layer 27 and via 28, which are formed in a convex shape, is covered with seed metal 30. Via 28 has a trapezoidal shape when viewed from the side, with a smaller diameter on the semiconductor element mounting side and a larger diameter on the external connection side.

[0021] The seed metal 30 can be made of copper formed by sputtering. Using this seed metal 30 as an electrode, the metal layer 27 and vias 28 can be formed by electroplating. In other words, in this embodiment, the multilayer substrate 20 can form the metal layer 27 and vias 28 without performing electroless plating, thus eliminating the problem of palladium deposition in electroless plating and maintaining good insulation resistance.

[0022] Furthermore, the semiconductor device mounting pad 21 is formed so as to be on the same surface as the insulating layer 22 on one side. In other words, the semiconductor device mounting pad 21 does not protrude from the surface of the insulating layer 22 on one side. The pads 21 for mounting semiconductor elements are nickel-gold plated because the bumps 11 of the semiconductor elements 10 are connected to them. Since the pads 21 for mounting semiconductor elements do not protrude from the surface of the insulating layer 22 on one side, the nickel-gold plating does not form a sphere, but rather smoothly covers the surface of the pads 21 for mounting semiconductor elements. Therefore, when inspecting the multilayer substrate 20, it is possible to prevent the probe from detaching and slipping off when attempting to make contact with the probe card.

[0023] In this embodiment, the multilayer substrate 20 is designed to accommodate the reduction in diameter and narrowing of the pads 21 for mounting semiconductor elements. Specifically, the multilayer substrate 20 can have a width (diameter) A of the semiconductor device mounting pads 21 set to 25 to 30 μm. This is because the semiconductor device mounting pads 21 are formed to be on the same surface as the insulating layer 22 on one side, and even if nickel-gold plating is applied to the semiconductor device mounting pads 21, they do not become spherical, so even if the diameter is reduced, the probe will not come off during inspection. Also, spherical nickel-gold plating does not come into close proximity to adjacent semiconductor device mounting pads 21.

[0024] Specifically, the multilayer substrate 20 allows the spacing (pitch) B between the center of one semiconductor device mounting pad 21 and the center of an adjacent semiconductor device mounting pad 21 to be 40 μm or less. This is because, since there is no palladium deposition, even if the pitch between pads is shortened, short circuits between adjacent pads due to deposited palladium do not occur. Furthermore, because the nickel-gold plating is not spherical, the nickel-gold plating formed on adjacent semiconductor device mounting pads 21 does not come into close proximity to each other.

[0025] (Manufacturing method for multilayer substrates) Next, we will explain how to manufacture the multilayer substrate 20. The manufacturing method for the multilayer substrate 20 in this embodiment is characterized by starting the formation from the semiconductor element mounting side. As described above, the spacing between the semiconductor element mounting pads 21 on the multilayer substrate 20 is narrow, while the spacing between the external connection pads 24 is wider than the spacing between the semiconductor element mounting pads 21. By forming the layers starting with the narrow-pitch layers, it is possible to prevent waviness in the substrate at an early stage during the manufacturing of the multilayer substrate 20.

[0026] As shown in Figure 2, first, a support 50, which will serve as the base for the multilayer substrate 20, is formed. The support 50 has a glass plate 52 with a thickness of several millimeters to several centimeters, and a metal layer 54 formed on the surface of the glass plate 52. The surface of the glass plate 52 is formed in a planar shape, and the metal layer 54 is formed on the surface of the glass plate 52 by sputtering or the like. Copper, nickel, and the like can be used for the metal layer 54.

[0027] Next, as shown in Figure 3, a resist layer 56 is formed on the surface of the metal layer 54 of the support 50. The resist layer 56 may be formed by applying a resist using a spin coater or slit coater, or by attaching a film-like dry film resist (DFR).

[0028] Then, as shown in Figure 4, the resist layer 56 formed on the surface of the metal layer 54 of the support 50 is exposed to light in a predetermined pattern to remove unwanted portions and form a resist layer 56 with a predetermined pattern. Subsequently, in areas where the resist layer 56 with the predetermined pattern has not been formed, copper is electroplated using the metal layer 54 as an electrode to form a pad 21 for mounting semiconductor devices.

[0029] Next, as shown in Figure 5, the resist layer 56 is peeled off. After peeling off the resist layer 56, an insulating layer 22 is formed on the surface of the semiconductor device mounting pad 21 and the metal layer 54 of the support 50, as shown in Figure 6. The insulating layer 22 can be formed by attaching an insulating resin film. A thermosetting film can be used as the insulating resin film.

[0030] Next, as shown in Figure 7, through holes 62 are formed in the insulating layer 22 so as to reach the surface of the pad 21 for mounting the semiconductor element. The through-hole 48 can be formed by laser processing. When forming the through-hole 62 with a laser, the type of laser used can be a CO2 laser, a UV laser, etc., and can be selected as appropriate. There are also no particular restrictions on the laser power, and it can be selected as appropriate.

[0031] Then, as shown in Figure 8, copper seed metal 64 is formed on the surface of the insulating layer 22 and on the inner wall surface of the through hole 62. The copper seed metal 64 is formed by sputtering. Next, a resist layer 68 is formed on the surface of the seed metal 64. The resist layer 68 may be formed by applying a resist using a spin coater or slit coater, or by attaching a film-like dry film resist (DFR). Then, as shown in Figure 9, the resist layer 68 formed on the surface of the seed metal 64 is exposed to light in a predetermined pattern to remove unwanted portions, thereby forming a resist layer 68 with a predetermined pattern.

[0032] Next, as shown in Figure 10, in areas where a resist layer 68 of a predetermined pattern has not been formed, copper vias 28 are formed in the through holes 62 by electroplating copper using the seed metal 64 as an electrode, and a patterned copper metal layer 27 is formed on the flat surface. Thus, the via 28 and the metal layer 27 located above the via 28 are integrally formed as a convex shape that is convex downwards. In addition, since the through hole 62 is processed by a laser to become smaller in diameter downwards, the via 28 has a trapezoidal shape that becomes smaller in diameter downwards.

[0033] Next, as shown in Figure 11, the resist layer 68 is peeled off. Then, the seed metal 64 is also peeled off by etching using the metal layer 27 as a mask. As a result, the seed metal 30 remains, which is convex downwards, covering the via 28 and the lower surface of the metal layer 27.

[0034] Then, as shown in Figure 12, an additional insulating layer 22 is formed on the surfaces of the insulating layer 22 and the metal layer 27. The formation of this insulating layer 22 follows the same process as the formation of the insulating layer 22 shown in Figure 6, and can be formed by attaching an insulating resin film as the insulating layer 22. Furthermore, a thermosetting film can be used as the insulating resin film.

[0035] The process from forming the insulating layer 22 shown in Figure 6 to forming the insulating layer 22 shown in Figure 12 constitutes the formation of one intermediate layer, and this process of forming one intermediate layer is repeated until a predetermined number of layers are reached.

[0036] The intermediate layer formation process shown in Figures 6 to 12 is repeatedly performed. For example, if the intermediate layer formation process is repeated three times, then, as shown in Figure 13, three layers of vias 28 and metal layers 27 are formed, and an insulating layer 22 is formed on the top surface.

[0037] After forming the desired number of layers, a protective resin film 70 is attached to the surface of the insulating layer 22, as shown in Figure 14. Any material can be used for the resin film 70, but for example, PET film can be used.

[0038] Next, as shown in Figure 15, through holes 72 are formed in the resin film 70 and the insulating layer 22 so as to reach the surface of the uppermost metal layer 27. The through-hole 72 can be formed by laser processing. When forming the through-hole 72 with a laser, examples of lasers include CO2 lasers and UV lasers, which can be selected as appropriate. Furthermore, there are no particular restrictions on the laser output, which can also be selected as appropriate.

[0039] Next, as shown in Figure 16, the conductive paste 76 is filled into the through hole 72. The conductive paste 76 can be one that contains a conductive filler and a binder resin. Examples of conductive fillers include metal particles such as copper, gold, silver, palladium, nickel, tin, and bismuth. These metal particles may be used individually or as a mixture of two or more types. As the binder resin, for example, epoxy resin, a type of thermosetting resin, can be used. However, it is not limited to epoxy resin; polyimide resin or other resins may also be used. Furthermore, the binder resin may be a thermoplastic resin instead of a thermosetting resin.

[0040] Then, as shown in Figure 17, the resin film 70 is peeled off, and the glass plate 52 and metal layer 54 that make up the support 50 are separated. By peeling off the resin film 70, the conductive paste 76 protrudes from the surface of the insulating layer 22 by the thickness of the resin film 70, forming a pad 24 for external connection.

[0041] Furthermore, by peeling off the glass plate 52 and the metal layer 54, the pads 21 for semiconductor element mounting are exposed. Nickel-gold plating 77 is applied to the pads 21 for semiconductor element mounting in order to connect the bumps 11 of the semiconductor element 10. As shown in Figure 18, the semiconductor device mounting pad 21 is formed so as to be on the same surface as the insulating layer 22 without protruding, so the nickel-gold plating 77 does not become spherical, but smoothly covers the surface of the semiconductor device mounting pad 21.

[0042] As a comparative example, Figure 19 shows a case where the pad 21 for mounting semiconductor devices protrudes from the insulating layer 22. If the pad 21 for mounting semiconductor elements protrudes from the insulating layer 22, the nickel-gold plating 77 will take on a nearly spherical shape, causing the probe to detach and fall off when attempting to make contact with it using a probe card during inspection. However, by forming the pad 21 for mounting semiconductor elements on the same surface as the insulating layer 22 without protruding, as in this embodiment, the nickel-gold plating 77 will not take on a spherical shape, preventing the probe from detaching and falling off.

[0043] Furthermore, as shown in the comparative example in Figure 19, when the nickel-gold plating 77 of the semiconductor element mounting pad 21 protruding from the surface of the insulating layer 22 becomes nearly spherical, nickel-gold plating 77 is also formed on the side surface of the semiconductor element mounting pad 21, making it impossible to accommodate a narrow pitch by reducing the spacing between adjacent semiconductor element mounting pads 21. However, by forming the semiconductor element mounting pad 21 on the same surface without protruding from the insulating layer 22, as in this embodiment, it is possible to achieve a narrow pitch for the semiconductor element mounting pad 21.

[0044] Furthermore, in the manufacturing method of the multilayer substrate 20 described above, the narrow-pitch semiconductor element mounting pads 21 are formed first, and the external connection pads 24, which have a wider pitch than the semiconductor element mounting pads 21, are formed last. This makes it possible to prevent waviness in the multilayer substrate at an early stage and to manufacture a flat multilayer substrate. Thus, after manufacturing the multilayer substrate 20 from a narrow pitch to a wide pitch, when mounting the semiconductor elements 10 and stacking them with other multilayer substrates 40, the manufactured multilayer substrate 20 is flipped upside down.

[0045] Furthermore, the multilayer substrate manufacturing method described above allows for the formation of metal layers and vias without using electroless plating, thus eliminating the need for palladium as a plating medium. This eliminates the problem of palladium deposition, allowing for the maintenance of good insulation resistance. [Explanation of Symbols]

[0046] 10 Semiconductor devices 11 Bump 20 Multilayer board 21 Pads for semiconductor device mounting 22 Insulating layer 24 Pads for external connections 27 Metal layer 28 Beer 30 Seedmetal 40 Other multilayer substrates 48 through holes 50 Support 52 Glass plate 54 Metal layer 56 Resist Layers 62 through holes 64 Seedmetal 68 Resist Layers 70 Resin film 72 through holes 76 Conductive paste

Claims

1. A multilayer substrate having multiple insulating layers and multiple metal layers formed in a pattern within each insulating layer, with the metal layers interlayer-connected by vias, having multiple pads for semiconductor device mounting formed on one side and pads for external connections formed on the other side, Each of the aforementioned semiconductor element mounting pads is formed so as to be on the same surface as the insulating layer located on one side. A multilayer substrate characterized in that the surface of each pad for mounting the semiconductor element is smoothly covered with a nickel-gold plating layer.

2. The multilayer substrate according to claim 1, characterized in that each of the external connection pads is made of conductive paste.

3. The multilayer substrate according to claim 1 or 2, characterized in that the diameter of each pad for mounting the semiconductor element is 25 μm to 30 μm, and the distance between the centers of adjacent pads for mounting the semiconductor element is 40 μm or less.

4. The multilayer substrate according to claim 1, characterized in that a via formed in a predetermined insulating layer and a metal layer formed in an insulating layer located on the other side of the via are integrally formed, and one side of the integrally formed via and metal layer is covered by a seed metal layer.

5. A manufacturing method for producing a multilayer substrate having multiple insulating layers and multiple metal layers formed in a pattern within each insulating layer, with the metal layers interlayer-connected by vias, with multiple pads for semiconductor element mounting formed on one side and pads for external connections formed on the other side, First, pads for mounting semiconductor elements are formed on one side, and finally, pads for external connections are formed on the other side so that they are wider than the spacing between the pads for mounting semiconductor elements. The process of forming pads for semiconductor device mounting is A process of forming a metal layer on the upper surface of a support as a pad for mounting semiconductor elements, The process includes forming an insulating layer on the upper surface of the support such that the metal layer is embedded therein. The surface of the pad for mounting the semiconductor element is formed to be the same surface as the surface of the insulating layer located on one side. When forming the external connection pad on the other side, via holes are formed in the insulating layer on the other side, and conductive paste is filled into these via holes to form the conductive paste as the external connection pad. After the external connection pads are formed, the support is peeled off. A method for manufacturing a multilayer substrate, characterized by applying nickel-gold plating to the surface of the semiconductor element mounting pads that are exposed by peeling off the support.

6. The method for manufacturing a multilayer substrate according to claim 5, characterized in that the support is a glass plate with a metal layer formed on its surface.

7. The process of forming via holes in each of the insulating layers that communicate with the metal layer, A step of forming a seed metal layer on an insulating layer including the via holes by sputtering, The process involves electroplating the seed metal layer to form vias and a metal layer, The method for manufacturing a multilayer substrate according to claim 5, comprising the step of etching a metal layer formed on the seed metal layer into a predetermined pattern.

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