Quantum information processing device and quantum information processing system

Abstract

To provide a quantum information processing device capable of reducing computation errors associated with failure in electron capture.SOLUTION: A quantum information processing device disclosed herein comprises a control unit for controlling a quantum bit array and common control gate lines that enable control of multiple quantum bits. The common control gate lines are commonly connected to multiple transistors, and the control unit provides control such that the number of quantum bits operating in the quantum bit array is equal to or less than the total number of the transistors.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to a quantum information processing apparatus and a quantum information processing system. Background Art

[0002] Quantum computers have attracted attention because they are capable of higher-speed information processing than existing computers. While existing computers handle two binary values of 0 and 1, quantum computers are characterized by being capable of handling superposition states of these values.

[0003] Quantum operation is realized by performing appropriate operations on each quantum bit or two quantum bits. In computer science, it is known that any operation can be realized by a combination of two types of single-qubit operations and one type of two-qubit operation.

[0004] Semiconductor quantum bits are quantum bits born from silicon semiconductor engineering that supports the modern information society. A semiconductor quantum bit is a system in which a single electron is trapped by an electrostatic effect, and the spin direction of the electron is associated with 0 and 1.

[0005] There are two methods for integrating semiconductor quantum bits: a method in which each quantum bit is provided with an individual gate electrode for electron trapping, and a method in which quantum bits are arranged in an array using a gate electrode common to a plurality of quantum bits (common gate electrode method). The method of providing an individual gate electrode for electron trapping for each quantum bit has only remained at the concept proposal stage due to wiring difficulties.

[0006] As a technology related to the common gate electrode method in which quantum bits are arranged in an array using a gate electrode common to a plurality of quantum bits, Patent Document 1 is known, for example. Prior Art Literature Patent Literature

[0007] Patent Document 1 Japanese Patent Publication No. 2021-27142 [Overview of the project] [Problems that the invention aims to solve]

[0008] While quantum processors using a common gate electrode design can achieve higher integration, the common gate electrode design sacrifices the individual controllability of the qubits. One of the functions required of quantum processors employing electron spin-based qubits is the ability to capture the electrons used as qubits.

[0009] Electron capture is performed by applying a voltage to the gate electrode. Due to the Coulomb interaction between the electrons being captured, the gate voltage required for electron capture is not necessarily the same for all electrons in the quantum processor. Therefore, in a common gate electrode configuration, it is necessary to design the system so that electrons can be captured within a certain voltage margin.

[0010] However, since the voltage margins of each electron acting as a qubit in a quantum processor are different, there is a possibility that calculation errors may occur due to the breaking of electron trapping.

[0011] The objective of this invention is to reduce computational errors caused by the breaking of electron trapping in a quantum information processing device. [Means for solving the problem]

[0012] A quantum information processing apparatus according to one aspect of the present invention comprises a qubit array in which a plurality of qubits are arranged in a two-dimensional square lattice, a control unit for controlling the qubit array, and a common control gate line capable of controlling the plurality of qubits, wherein the common control gate line is commonly connected to a plurality of transistors, and the control unit controls the number of qubits operating in the qubit array to be less than or equal to half the total number of transistors. [Effects of the Invention]

[0013] According to one aspect of the present invention, in a quantum information processing apparatus, calculation errors caused by broken electron confinement can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] [Figure 1] It is an explanatory diagram of a qubit using an electron spin state. [Figure 2] It is a diagram showing the basic structure of an electron spin type qubit semiconductor device. [Figure 3] It is a circuit diagram of a quantum processor composed of electron spin type qubits adopting a common gate scheme. [Figure 4] It is a schematic configuration diagram of a quantum computer. [Figure 5] It is a diagram showing an example of gate voltage application to a quantum processor. [Figure 6] It is a diagram showing an example of gate voltage application and accompanying electron confinement in a quantum processor. [Figure 7] It is a diagram showing an example of gate voltage application and accompanying electron confinement in a quantum processor with a restricted use region. [Figure 8] It is a diagram showing another example of gate voltage application to a quantum processor. [Figure 9] It is a diagram showing an example of gate voltage application and accompanying electron confinement in a quantum processor. [Figure 10] It is a diagram showing an example of gate voltage application and accompanying electron confinement in a quantum processor with a restricted use region. [Figure 11] It is a diagram showing an example of use region restriction for a quantum processor. [Figure 12] It is a diagram showing an example of use region restriction for a quantum processor. [Figure 13] It is a diagram showing an example of use region restriction for a quantum processor. [Figure 14] It is a diagram showing an example of use region restriction for a quantum processor. [Figure 15] It is a diagram showing an example of use region restriction for a quantum processor. [Figure 16]FIG. 1 is a diagram illustrating an example of an algorithm that limits the usable area of a quantum processor. [Figure 17] FIG. 2 is a diagram showing a state of a quantum device in which quantum dots are arranged in an array. DETAILED DESCRIPTION OF EMBODIMENTS

[0015] Hereinafter, examples will be described in detail with reference to the drawings. However, the present invention should not be construed as being limited to the contents described in the examples shown below. It is easily understood by those skilled in the art that the specific configuration of the present invention can be modified without departing from the spirit or scope of the present invention.

[0016] In the configuration of the invention described below, the same reference numerals are used for the same parts or parts having similar functions in different drawings, and overlapping descriptions may be omitted. When there are a plurality of elements having the same or similar functions, different subscripts may be added for description. However, the subscript may be omitted in some descriptions.

[0017] In addition, numbers for identifying constituent elements are used for each context, and a number used in one context does not necessarily indicate the same constituent element in another context. Furthermore, a constituent element identified by a certain number does not preclude the function of a constituent element identified by another number.

[0018] Positions, sizes, shapes, ranges, and the like of respective components shown in the drawings and the like may not represent actual positions, sizes, shapes, ranges, and the like in order to facilitate understanding of the invention. Therefore, the present invention is not necessarily limited to the positions, sizes, shapes, ranges, and the like disclosed in the drawings and the like.

[0019] Hereinafter, examples will be described with reference to the drawings. EXAMPLES

[0020] FIG. 1 exemplarily shows an electron spin or hole spin state and a value associated therewith. The symbol consisting of a circle and an arrow in the diagram is a stylized representation of electron spin 101. In this way, electron spin 1010 is represented as a vector. The basis of the vector is the spin-down state and the spin-up state. For example, these can be associated with the numerical values ​​0 and 1, respectively.

[0021] Controlling the electron spin 101, for example, changing the spin state associated with a numerical value from an up state to a down state, is the operation for a quantum computer. A distinctive feature of qubits is their ability to create superpositions of up and down states. Handling superpositions of 0 and 1 is one of the characteristics of quantum computers.

[0022] Figure 2 shows the basic structure of an electron spin-based qubit semiconductor device. A qubit semiconductor device consists of gate electrodes 201-1 to 201-5, insulating layers 202 and 205, and a semiconductor layer 203. This structure is similar to that of an electrostatic transistor. By applying a voltage to the gate electrodes, electrons are trapped in the semiconductor layer by the electrostatic effect. These electrons are used as qubits. Conversely, electrons can also be excluded by applying a negative voltage.

[0023] Electrons are arranged in an ordered manner by combining capture and exclusion. Electrons are captured in the valleys of the electrostatic potential 204 in Figure 2. During 2-qubit operations, the height of the potential peak separating the two electrons is controlled by the voltage applied to the gate electrodes 201-3.

[0024] Figure 17 shows a quantum device in which quantum dots are arranged in an array.

[0025] The qubit array 171 has multiple qubits formed in a two-dimensional square lattice, and interactions (potential barriers) are formed between the quantum dots. It also has semiconductor (e.g., poly-Si) gate electrodes. There are two types of gate electrodes: a quantum dot control gate 172 and an exchange interaction control gate 173.

[0026] Two layers of quantum dot control gates 172 and exchange interaction control gates 173 are arranged alternately directly above the substrate. The quantum dot control gates 172 are used to control one quantum gate operation. The exchange interaction control gates 173 are used to control two quantum gate operations.

[0027] Figure 3 shows how the quantum processor 304 is described as a transistor circuit. This circuit diagram is described using three types of transistors 301-303. Transistor 301 is a triode transistor and represents an electron trapping transistor. Transistor 302 is a pentode transistor and represents an electron trapping transistor. Transistor 302 has channels connected in four directions: up, down, left, and right. This four-way connection allows the quantum processor 304 to be configured in two dimensions.

[0028] Transistor 303 represents a barrier transistor for rejecting electrons. This transistor 303 corresponds to 201-3 in Figure 2, and a 2-qubit operation is performed by changing the gate voltage of this transistor 303.

[0029] A key feature of Figure 3 is the use of three types of transistors 301, 302, and 303, as well as the fact that transistors 301, 302, and 303 share a gate electrode. This arrangement of transistors sharing a gate electrode enables the two-dimensional arrangement of the quantum processor 304. Note that the arrangement of transistors 301, 302, and 303 in Figure 3 is merely an example.

[0030] As shown in Figure 17, the common control gate line consists of the quantum dot control gate 172 and the exchange interaction control gate 173. In addition to the quantum dot control gate 172 and the exchange interaction control gate 173, the quantum processor 304 is also provided with a source drain.

[0031] Figure 4 shows the overall configuration of the quantum computer system, including the quantum processor shown in Figure 3. 304 is the quantum processor explained in Figure 3. 402 is a microwave antenna necessary for controlling the quantum processor. The quantum processor drive unit (control unit) 401 is the circuit that drives the quantum processor 304 and the antenna 402. The quantum processor drive unit 401 is controlled by a standard host computer 403. A communication path 404 is provided between the quantum processor drive unit 401 and the host computer 403.

[0032] Here, the host computer 403 includes, for example, a main memory, a general arithmetic unit, a control unit, an auxiliary memory, an input device, an output device, and the like.

[0033] Referring to Figures 5 to 10, the relationship between the gate voltage applied to each transistor and electron trapping will be explained.

[0034] Figure 5 shows an example of how to apply voltage to a gate electrode. This example involves applying voltage to the gate electrodes of electron trapping transistors 301 and 302. This gate electrode is the same type of black terminal as 304-1 and 304-1.

[0035] Next, we present the simulation results based on an equivalent circuit predicting electron sufficiency at the scale of quantum processor 304, which has 8 electrons vertically and 7 electrons horizontally, for a total of 56 electrons. In this simulation, typical values ​​were used for the transistor capacitance.

[0036] Figure 6 shows the electron saturation in response to the voltage applied to the gate electrode shown in Figure 5. The voltage applied to the gate electrodes of all these transistors is the same. As shown at the top of Figure 6, electrons are filled into each transistor in the quantum processor as the gate voltage for each voltage is increased.

[0037] The voltage margin at which all transistors are filled with electrons is approximately 0.4V. Outside this range, even with the same gate voltage, there are two types of transistors: those that are filled with electrons and those that are not. Coulomb interaction between electrons causes this result.

[0038] The simulation results show that electron trapping is easily broken in the central and peripheral regions of the quantum processor when the voltage falls outside the voltage margin range.

[0039] Figure 7 shows electron trapping with respect to gate voltage only for transistors located in regions other than the central or edge areas shown in the figure.

[0040] By limiting the range within the quantum processor, the voltage margin can be expanded from approximately 0.4V to approximately 2.0V.

[0041] Figure 8 shows another example of how to apply voltage to the gate electrode. This example involves applying voltage to the gate electrode of a barrier transistor. This gate electrode is the same as 304-2 and the black terminal of the same type as 304-2.

[0042] Figure 9 shows the electron saturation in response to the voltage applied to the gate electrode shown in Figure 8. The voltage applied to the gate electrodes of these transistors is all the same. The voltage margin without region limitations for the quantum processor is approximately 1.4V.

[0043] Figure 10 shows the electron sufficiency when limited to the range shown in the figure. Figure 10 shows the electron sufficiency for the gate voltage only for transistors in the region excluding the edges shown in the figure. In this way, a voltage margin of more than 5V can be obtained by limiting the range.

[0044] As described above, quantum processors can obtain a larger voltage margin by limiting the area used. Note that semiconductors have two types of carriers: electrons and holes. Holes may be used instead of electrons.

[0045] Next, we will explain examples of domain constraints with reference to Figures 11 to 15.

[0046] Figure 11 shows examples of region restrictions for the left and right edges. Although qubits exist at the left and right edges, their use is restricted to qubits excluding these qubits with narrow margins.

[0047] Furthermore, the number of qubits restricted at this time shall be less than or equal to half the total number of capture transistors 301 and 302 and barrier transistor 303. In addition, the number of qubits restricted to perform practical calculations shall be two or more.

[0048] Figure 12 shows examples of region restrictions for the left edge, right edge, and central region. Although qubits also exist at the left edge, right edge, and center, their use is restricted to the qubits excluding these qubits with narrow margins.

[0049] Furthermore, the number of qubits restricted at this time shall be less than or equal to half the total number of capture transistors 301 and 302 and barrier transistor 303. In addition, the number of qubits restricted to perform practical calculations shall be two or more.

[0050] Figure 13 shows examples of region restrictions for the upper and lower edges. Although qubits also exist at the upper and lower edges, their use is restricted to the qubits excluding these qubits with narrow margins.

[0051] Furthermore, the number of qubits restricted at this time shall be less than or equal to half the total number of capture transistors 301 and 302 and barrier transistor 303. In addition, the number of qubits restricted to perform practical calculations shall be two or more.

[0052] Figure 14 shows examples of region restrictions for the upper edge, lower edge, and central area. Although qubits exist at the upper, lower, and central edges, their use is restricted to the qubits excluding these qubits with narrow margins.

[0053] Furthermore, the number of qubits restricted at this time shall be less than or equal to half the total number of capture transistors 301 and 302 and barrier transistor 303. In addition, the number of qubits restricted to perform practical calculations shall be two or more.

[0054] Figure 15 shows examples of region restrictions for the left edge, right edge, upper edge, lower edge, and central region. Although qubits exist at the left edge, right edge, upper edge, lower edge, and center, their use is restricted to the qubits excluding these qubits with narrow margins.

[0055] Furthermore, the number of qubits restricted at this time shall be less than or equal to half the total number of capture transistors 301 and 302 and barrier transistor 303. In addition, the number of qubits restricted to perform practical calculations shall be two or more.

[0056] Figure 16 shows the operations required of the quantum processor and the operations performed by the quantum processor. As mentioned above, the operating area of ​​the quantum processor is limited. If the required operation spans qubits in different regions, it is converted to an operation using qubits in the same region. This conversion is performed in the quantum processor drive unit 401 or the host computer 403 shown in Figure 4.

[0057] In this way, the control unit (quantum processor drive unit 401 or host computer 403) controls the number of qubits operating in the qubit array so that it is less than or equal to half the total number of transistors. The control unit (quantum processor drive unit 401 or host computer 403) also controls the number of qubits operating in the qubit array so that it is two or more.

[0058] According to the above embodiment, by using only electrons with a relatively large voltage margin in quantum computation, it is possible to reduce computational errors caused by the breaking of electron trapping. [Explanation of Symbols]

[0059] 10¹ Electron spin or qubit 201 Guard Station 202 Insulating layer 203 Semiconductor layer 204 Electrostatic potential 205 Insulating layer 301 Three-terminal transistor for electronic trapping 302 5-terminal transistor for electronic capture 303 Barrier Transistor 304 Quantum Processor 401 Quantum Processor Drive Unit 402 Microwave Antenna 403 Host Computer 404 Communication Line

Claims

1. A qubit array in which multiple qubits are arranged in a two-dimensional square lattice, A control unit for controlling the qubit array, It has a common control gate line capable of controlling multiple qubits, The aforementioned common control gate line is Multiple transistors are connected in common, The control unit, The number of qubits operating within the qubit array is controlled to be less than or equal to half the total number of transistors. The control unit, A quantum information processing apparatus characterized by controlling the qubits, which are located in at least one portion of the central portion and edge portion of the qubit array, to a non-operating state.

2. The control unit, The quantum information processing apparatus according to claim 1, characterized in that it controls the number of qubits operating in the qubit array to be two or more.

3. The aforementioned transistor is The quantum information processing apparatus according to claim 1, characterized in that it is an electron trapping transistor or a barrier transistor.

4. The aforementioned qubit is The quantum information processing apparatus according to claim 1, characterized in that it is an electron or a hole.

5. The quantum information processing apparatus according to claim 1, A host computer that controls the aforementioned quantum information processing device, A quantum information processing system characterized by having the following features.

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