Semiconductor devices and communication systems

Abstract

To provide a semiconductor device capable of suppressing malfunctions that may occur when connected to a transmitting / receiving device which can perform communication by a differential voltage system.SOLUTION: A semiconductor device (1) comprises a communication unit (11) configured to receive reception data (RX) and transmit transmission data (TX). The communication unit comprises: a counter (11B); and a synchronization unit (11C) configured to monitor the transmission data when the own semiconductor device is other than a target device set in the reception data, and reset a count by the counter upon detecting a stop bit and a start bit at frame switching in the transmission data.SELECTED DRAWING: Figure 8

Description

[[Technical Field]]

[0001] The present disclosure relates to a semiconductor device and a communication system. [[Background Art]]

[0002] Semiconductor devices having a serial communication function are used in various applications.

[0003] An example of circuit technology related to serial communication is disclosed in Patent Document 1. [[Prior Art Documents]] [[Patent Documents]]

[0004] [[Patent Document 1]] Japanese Unexamined Patent Application Publication No. 2017-224946 [[Summary of the Invention]] [[Problem to be Solved by the Invention]]

[0005] For example, in in-vehicle applications, the semiconductor device may perform communication via a CAN (Controller Area Network) bus when communicating with an MCU (Micro Controller Unit). CAN is a serial communication protocol standardized in the international standard ISO 11898 and the like. CAN uses a differential voltage method in which data is transmitted according to the level of the voltage difference generated between two communication lines.

[0006] When communication is performed using a CAN bus as described above, a CAN transceiver that converts between serial data and CAN signals is used. In the above semiconductor device, it is demanded to suppress malfunctions that occur when connected to such a CAN transceiver.

[0007] An object of the present disclosure is to provide a semiconductor device capable of suppressing malfunctions that occur when connected to a transmission / reception device capable of performing communication based on a differential voltage method. [Means for solving the problem]

[0008] A semiconductor device relating to one aspect of this disclosure is A receiving data input terminal configured to receive data which is serial data, A transmission data output terminal configured to output transmission data, which is serial data, A communication unit configured to receive the received data and transmit the transmitted data, Equipped with, The aforementioned communications unit is The counter, A synchronization unit is configured to monitor the transmitted data and reset the counter when it detects stop bits and start bits at frame transitions in the transmitted data, if the semiconductor device itself is not the target device set in the received data. It has a configuration that includes the following:

[0009] Furthermore, a semiconductor device according to one aspect of this disclosure is A receiving data input terminal configured to receive data which is serial data, A transmission data output terminal configured to output transmission data, which is serial data, A communication unit configured to receive the received data and transmit the transmitted data, Equipped with, The aforementioned communications unit is The counter, A synchronization unit is configured to monitor the received data if its own semiconductor device is not the target device set in the received data, and to reset the counter when it detects stop bits and start bits at frame switching in the received data. It has a configuration that includes the following: [Effects of the Invention]

[0010] According to the exemplary semiconductor device of the present disclosure, it is possible to suppress malfunctions that occur when connected to a transmission / reception device capable of differential voltage communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] [Figure 1] FIG. 1 is a diagram showing the configuration of a communication system according to an exemplary embodiment of the present disclosure. [Figure 2] FIG. 2 is a diagram showing the configuration of a communication system according to another exemplary embodiment of the present disclosure. [Figure 3] FIG. 3 is a diagram showing a configuration example of a CAN transceiver. [Figure 4] FIG. 4 is a diagram showing a partial block configuration of a semiconductor device. [Figure 5] FIG. 5 is a timing chart showing Read processing when a semiconductor device according to a comparative example is used in the communication system shown in FIG. 2. [Figure 6] FIG. 6 is a timing chart showing Read processing when a semiconductor device according to a comparative example is used in the communication system shown in FIG. 1. [Figure 7A] FIG. 7A is a timing chart showing an example of received data RX and an internal state near the timing of transitioning to an idle state in device #2. [Figure 7B] FIG. 7B is a timing chart showing another example of received data RX and an internal state near the timing of transitioning to an idle state in device #2. [Figure 8] FIG. 8 is a diagram showing the configuration of a communication unit in the semiconductor device according to the first embodiment of the present disclosure. [Figure 9] FIG. 9 is a timing chart showing Read processing when the semiconductor device according to the first embodiment is used in the communication system shown in FIG. 1. [Figure 10] FIG. 10 is a diagram showing the configuration of a communication unit in the semiconductor device according to the second embodiment of the present disclosure. [Figure 11]FIG. 11 is a timing chart showing Read processing when the semiconductor device according to the second embodiment is used in the communication system shown in FIG. 1. [Figure 12] FIG. 12 is a diagram showing a configuration of a communication unit in a semiconductor device according to a third embodiment of the present disclosure. [Figure 13] FIG. 13 is a timing chart showing Read processing when the semiconductor device according to the third embodiment is used in the communication system shown in FIG. 1. MODE FOR CARRYING OUT THE INVENTION

[0012] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0013] <1. Communication System> FIG. 1 is a diagram showing a configuration of a communication system 101 according to an exemplary embodiment of the present disclosure. The communication system 101 includes n devices 1 (where n is an integer of 2 or greater), an MCU 2, a CAN transceiver 3, a CAN bus 4, and a CAN transceiver 5. As an example, the communication system 101 is for in-vehicle use, and the same applies to other communication systems described below.

[0014] Communication by UART (Universal Asynchronous Receiver / Transmitter) is performed between the MCU 2 and the CAN transceiver 3. UART is a protocol for exchanging serial data between two devices. In UART, bidirectional communication is performed via two lines between a transmission side and a reception side.

[0015] Communication via the CAN bus 4 is performed between the CAN transceivers 3 and 5. The CAN transceiver 3 has a TXD (transmission data input) terminal 3A and an RXD (reception data output) terminal 3B. The CAN transceiver 3 outputs data input to the TXD terminal 3A to the CAN bus 4, and outputs data input from the CAN bus 4 from the RXD terminal 3B.

[0016] CAN transceiver 5 has an RXD terminal 5A and a TXD terminal 5B. CAN transceiver 5 outputs data input to TXD terminal 5B to CAN bus 4, and outputs data input from CAN bus 4 to RXD terminal 5A.

[0017] The semiconductor device 1 is an integrated circuit (IC) in which circuits with predetermined functions are integrated, and is configured, for example, as an LED (light-emitting diode) driver IC. Note that the n semiconductor devices 1 are not necessarily all devices with the same function.

[0018] The semiconductor device 1 has an RX (receive data input) terminal 1A and a TX (transmit data output) terminal 1B. The n RX terminals 1A are commonly connected to an RXD terminal 5A. The n TX terminals 1B are commonly connected to a TXD terminal 5B.

[0019] Since n semiconductor devices 1 support the same protocol, they can be connected to the same CAN transceiver 5. The received data RX output from the RXD terminal 5A is input to the n RX terminals 1A. The received data RX is specified to the device address of one of the n semiconductor devices 1. The transmitted data TX output from the TX terminal 1B is input to the TXD terminal 5B.

[0020] The MCU2 and CAN transceiver 3 are mounted on board 6. The n semiconductor devices 1 and CAN transceivers 5 are mounted on board 7, which is different from board 6. Boards 6 and 7 are connected by a harness (not shown). The CAN bus 4 is provided by this harness.

[0021] Figure 2 shows the configuration of a different communication system 102 from that shown in Figure 1. The communication system 102 comprises an MCU 2 and n semiconductor devices 1. The MCU 2 and the n semiconductor devices 1 are mounted on the same circuit board 8. In other words, the communication system 102 does not use a CAN transceiver and does not require a harness.

[0022] n RX terminals 1A are commonly connected to RXD terminal 2A of MCU2. n TX terminals 1B are commonly connected to TXD terminal 2B of MCU2.

[0023] <2. CAN Transceiver Configuration> Figure 3 shows the configuration of the CAN transceivers 3 and 5 used in the communication system 101 described in Figure 1. The CAN transceivers 3 and 5 each include a driver control unit 91, a driver 92, a receiver 93, and an output unit 94. The CAN transceivers 3 and 5 also have a TXD terminal, an RXD terminal, a CANH terminal, and a CANL terminal.

[0024] The CANH and CANL terminals are connected to the respective lines of the CAN bus 4. Termination resistors R1 and R2 are connected in series between the CANH and CANL terminals. The resistance values ​​of the termination resistors are defined by ISO 11898, and each of the termination resistors R1 and R2 consists of a 60Ω resistor. One end of capacitor C1 is connected to connection node N1, where resistors R1 and R2 are connected.

[0025] The driver 92 includes a PMOS transistor (P-channel MOSFET (metal-oxide-semiconductor field-effect transistor)) 92A, a diode 92B, an NMOS transistor (N-channel MOSFET) 92C, and a diode 92D. The source of the PMOS transistor 92A is connected to the terminal to which the power supply voltage VCC is applied. The drain of the PMOS transistor 92A is connected to the anode of diode 92B. The cathode of diode 92B is connected to the CANH terminal. The source of the NMOS transistor 92C is connected to the ground terminal. The drain of the NMOS transistor 92C is connected to the cathode of diode 92D. The anode of diode 92D is connected to the CANL terminal. Diodes 92B and 92D are used to prevent reverse current during surges.

[0026] The driver control unit 91 controls the on / off state of the PMOS transistor 92A and the NMOS transistor 92C based on the transmission data TX input from an external source via the TXD terminal.

[0027] More specifically, when the PMOS transistor 92A and NMOS transistor 92C are turned on, the current flowing through termination resistors R1 and R2 is common, so the voltage drops across termination resistors R1 and R2 are the same. As a result, the high-side signal CANH at the CANH terminal will be higher than the voltage at connection node N1 (=midpoint voltage) by the amount of the voltage drop, and the low-side signal CANL at the CANL terminal will be lower than the voltage at connection node N1 (=midpoint voltage) by the amount of the voltage drop. In this case, the high-side signal CANH will be high level, and the low-side signal CANL will be low level.

[0028] Here, the CANH terminal and the CANL terminal are connected to the application terminal of the power supply voltage VCC2 via resistors R91 and R92, respectively. When the PMOS transistor 92A and NMOS transistor 92C are in the off state, the voltage at connection node N1 is gradually brought closer to the second power supply voltage VCC2 due to the action of resistors R91 and R92, which have relatively high resistance values. The second power supply voltage VCC2 is the low level of the high-side signal CANH and the high level of the low-side signal CANL, and is the same voltage as the intermediate voltage mentioned above.

[0029] In this way, the transmission data TX input to the TXD terminal is output to the CAN bus 4 from the CANH terminal and CANL terminal.

[0030] On the other hand, the output section 94 has a PMOS transistor 94A and an NMOS transistor 94B. The source of the PMOS transistor 94A is connected to the terminal to which the power supply voltage VCC is applied. The drain of the PMOS transistor 94A is connected to the drain of the NMOS transistor 94B at node N92. The source of the NMOS transistor 94B is connected to the ground terminal. The receiver 93 receives the voltages from the CANH terminal and the CANL terminal, respectively. The output terminal of the receiver 93 is connected to node N91, to which the gates of the PMOS transistor 94A and the NMOS transistor 94B are connected. Node N92 is connected to the RXD terminal.

[0031] The receiver 93 applies a high-level or low-level signal to node N91 depending on the difference in the input voltage. Accordingly, the output unit 94 outputs a signal obtained by logically inverting the output of the receiver 93 as received data RX from the RXD terminal. In this way, data input from the CAN bus 4 is output from the RXD terminal.

[0032] <3. Comparative Examples> Before describing embodiments of this disclosure, we will now describe comparative examples for comparison. This will make the problems more apparent.

[0033] <3-1. Semiconductor device configuration> Figure 4 shows a partial block configuration of the semiconductor device 1. The semiconductor device 1 includes a communication unit 11 for UART communication. Note that the semiconductor device 1 may also include other functional blocks not shown in Figure 4. For example, if the semiconductor device 1 is an LED driver, it will include block functions related to LED driving (such as a DC / DC converter function and a current driver).

[0034] The communication unit 11 receives received data RX via the RX terminal 1A. The communication unit 11 outputs transmitted data TX via the TX terminal 1B. The communication unit 11 has a register 11A for storing data. The communication unit 11 also has a counter 11B that counts the clock CLK to control the transition of the internal state.

[0035] <3-2. Structure of Received Data> Here, we will explain the data structure of the received data RX using the timing chart shown in Figure 5. Details of Figure 5 will be discussed later.

[0036] UART communication uses data units called frames. A frame consists of bit data from a start bit to a stop bit. The start bit is low level, and the stop bit is high level. A predetermined number of bits of bit data are placed between the start bit and the stop bit. For example, if the predetermined number of bits is 8 bits, a frame will consist of 10 bits of bit data.

[0037] As shown in Figure 5, the received data RX consists of the following frames in order from beginning to end: synchronization frame SYN, device frame DV, data count frame ND, register address frame AD, data frame DT, CRC (Cyclic Redundancy Check) frame CRL, and CRC frame CRH.

[0038] The synchronization frame SYN is bit data used to set the baud rate for semiconductor device 1. The baud rate is an indicator value that shows how many times digital data can be modulated per second. For example, in serial communication, where one bit of digital data is transmitted per modulation, the baud rate can be understood as an indicator value of the communication speed (unit: bps [bits per second]).

[0039] The device frame DV includes the device address and Read / Write bits. The device address is bit data indicating the address of the target device (semiconductor device 1). The Read / Write bits are bit data indicating either a Read or a Write operation. Read indicates reading data from semiconductor device 1 (Read operation), and Write indicates writing data to semiconductor device 1 (Write operation).

[0040] The data number frame ND is bit data indicating the number of frames in the data frame DT. The register address frame AD is bit data indicating the address in register 11A. The data frame DT is bit data indicating the data body to be transmitted by the received data RX. The CRC frames CRL and CRH are bit data indicating error detection codes added to the data frame DT.

[0041] <3-3. If not connecting to the CAN bus> Figure 5 is a timing chart showing the Read process when using the semiconductor device 1 according to the comparative example in the communication system 102 shown in Figure 2. For convenience, in the following explanation, we will assume that n = 2 for n semiconductor devices 1.

[0042] In Figure 5 and the other drawings described later, the received data RX, transmitted data TX, and internal state of the communication unit 11 for device #1 (semiconductor device 1) are shown from top to bottom, followed by the received data RX, transmitted data TX, and internal state of the communication unit 11 for device #2 (semiconductor device 1).

[0043] As shown in Figure 5, as an example, let's assume that the device address in the device frame DV of the received data RX indicates device #1 of the two semiconductor devices 1. In other words, let's assume that device #1 is set as the target device. Also, the Read / Write bit in the device frame DV of the received data RX is set to Read.

[0044] In this case, after receiving the received data RX, the communication unit 11 of device #1 outputs the transmission data TX from the TX terminal 1B as a read back. The communication unit 11 outputs the transmission data TX as a read data frame RDT, using the data read from register 11A. If the communication unit 11 transmits multiple read data frames RDT as shown in Figure 5, it outputs the CRC frame RCRCL and CRC frame RCRCH as transmission data TX after the last read data frame RDT.

[0045] At this time, the communication unit 11 of device #1 transitions its internal state in accordance with the transmission timing of the transmitted data TX. In Figure 5 and other drawings, hatching H1 indicates the data or internal state of device #1 based on the transmission timing.

[0046] Meanwhile, in the communication unit 11 of device #2, which is not the target device, internal state transition control is performed based on the count of the clock CLK by counter 11B after receiving the received data RX. The transition control is performed based on the baud rate (bps) and the frequency of the clock CLK. The clock CLK of device #2 is asynchronous with the clock CLK of device #1, and device #2 performs internal state transition control at its own timing. In Figure 5 and other drawings, the blacked-out B1 indicates the internal state of device #2 based on its timing.

[0047] <3-4. When connecting to the CAN bus> Figure 6 is a timing chart showing the Read process when using the semiconductor device 1 according to the comparative example in the communication system 101 shown in Figure 1. Specifically, Figure 6 is a timing chart when the semiconductor device 1 is connected to the CAN transceiver 5.

[0048] In Figure 6, a difference from Figure 5 is that, because the semiconductor device 1 is connected to the CAN transceiver 5, when device #1 outputs the transmit data TX as a Read Back, the same data as the transmit data TX is generated in the receive data RX. This is because, as described above, with the configuration of the CAN transceiver 5 (Figure 3), when the transmit data TX input to the TXD terminal is output from the CANH terminal and CANL terminal, the receive data RX is output from the RXD terminal via the receiver 93 and output unit 94.

[0049] In this case, the following problems arise. In Figure 6, the communication unit 11 of device #2, which is not the target device, controls the transition of its internal state at the timing of device #2, which is asynchronous with device #1 as described above, when device #1 is transmitting the transmission data TX. After RData and RCRC16L, when RCRC16H is completed, it transitions to the idle state (IDLE) (dashed line box in Figure 6).

[0050] In the communication unit 11 of device #2, the transition of internal states is controlled based on the count of the clock CLK by the counter 11B, but sampling errors may cause a timing discrepancy in the transition to the idle state. The more frames processed, the more sampling errors accumulate, and the larger the timing discrepancy becomes.

[0051] Here, Figures 7A and 7B are timing charts showing the received data RX and internal state around the time of transition to the idle state in device #2. In other words, Figures 7A and 7B are enlarged views of the dashed box in Figure 6.

[0052] Figures 7A and 7B illustrate the case where the data frame contains 8 bits of data excluding the start and stop bits, i.e., a total of 10 bits. Figures 7A and 7B illustrate the 7th bit B7, the 8th bit B8, and the stop bit STOP of the last CRC frame RCRC16H in the received data RX. Ideally, the timing tB at which the internal state transitions from RCRC16H to the idle state coincides with the timing tA at the boundary between the 8th bit B8 and the stop bit STOP.

[0053] Figure 7A shows the case where the deviation of timing tB from the ideal timing tA is small. In this case, timing tB is after timing tC, which is the boundary between the 7th bit B7 and the 8th bit B8.

[0054] However, Figure 7B shows a case where the timing tB deviates significantly from the ideal timing tA. In Figure 7B, timing tB is before timing tC, which is the boundary between the 7th bit B7 and the 8th bit B8. As a result, as shown in Figure 7B, after transitioning to the idle state, the switch from high level to low level of the received data RX at timing tC is mistakenly detected as the start bit of the received data RX, causing the internal state to transition to SYNC. Note that in the case of Figure 7A, such a malfunction does not occur, so there is no problem.

[0055] For example, if the sampling error is such that 8 bits are shifted by 1 clock cycle, then 10 frames (10 bits x 10) would result in an error of 12.5 clock cycles. If the upper limit of the acceptable shift is 32 clock cycles, then 32 clock cycles x 8 bits = 256 bits, meaning that malfunctions could occur in 26 frames.

[0056] <4. First Embodiment> As described above, in order to solve the problem of malfunctions caused by readback when the semiconductor device 1 is connected to the CAN transceiver 5, various embodiments described below are implemented.

[0057] Figure 8 shows the configuration of the communication unit 11 in the semiconductor device 1 according to the first embodiment of this disclosure. The communication unit 11 according to this embodiment has a synchronization unit 11C. The synchronization unit 11C is capable of monitoring the transmitted data TX.

[0058] Figure 9 is a timing chart showing the Read process when the semiconductor device 1 according to the first embodiment is used in the communication system 101 shown in Figure 1. Specifically, Figure 9 is a timing chart when the semiconductor device 1 is connected to the CAN transceiver 5.

[0059] In this embodiment, when device #1, which is the target device, outputs transmission data TX as a Read back, the communication unit 11 of device #2, which is not the target device, performs the following operation. Here, the synchronization unit 11C monitors the transmission data TX, and when it detects the stop bit and start bit at the frame switching in the transmission data TX, the synchronization unit 11C resets the clock CLK count by the counter 11B (arrow in Figure 9). As a result, sampling errors are accumulated only within one frame, which suppresses the timing difference when the internal state transitions to the idle state and makes it possible to suppress malfunctions.

[0060] Furthermore, even in the case of a communication system 102 (Figure 2) in which a CAN transceiver is not connected to the semiconductor device 1, in this embodiment, the communication unit 11 of device #2 other than the target device performs control using the synchronization unit 11C which monitors the transmitted data TX in the same manner as above when device #1 reads back, so there is no need to switch control depending on the configuration of the communication system.

[0061] <5. Second Embodiment> Figure 10 shows the configuration of the communication unit 11 in the semiconductor device 1 according to the second embodiment of this disclosure. The communication unit 11 according to this embodiment has a synchronization unit 11C. The synchronization unit 11C can monitor the transmitted data RX.

[0062] Figure 11 is a timing chart showing the Read process when the semiconductor device 1 according to the second embodiment is used in the communication system 101 shown in Figure 1. Specifically, Figure 11 is a timing chart when the semiconductor device 1 is connected to the CAN transceiver 5.

[0063] In this embodiment, when the target device, device #1, outputs transmission data TX as a Read back, the communication unit 11 of device #2, which is not the target device, performs the following operation. Here, the synchronization unit 11C monitors the received data RX, and when it detects the stop bit and start bit at the frame switching in the received data RX, the synchronization unit 11C resets the clock CLK count by the counter 11B (arrow in Figure 11). As a result, sampling errors are accumulated only within one frame, which suppresses the timing difference when the internal state transitions to the idle state and prevents malfunctions. In particular, in this embodiment, since the received data RX and the count are synchronized, the timing of the transition to the idle state can be controlled with greater precision.

[0064] However, in the case of a communication system 102 (Figure 2) in which a CAN transceiver is not connected to semiconductor device 1, the received data RX is not received during Readback, so the communication unit 11 of device #2 does not perform control by the synchronization unit 11C (for example, count control is performed as in the comparative example described above).

[0065] <6. Third Embodiment> Figure 12 shows the configuration of the communication unit 11 in the semiconductor device 1 according to the third embodiment of this disclosure. The communication unit 11 according to this embodiment has a synchronization unit 11C. The synchronization unit 11C can monitor the transmitted data RX. In this embodiment, the transmitted data TX is input to the received data RX.

[0066] Figure 13 is a timing chart showing the Read process when the semiconductor device 1 according to the third embodiment is used in the communication system 101 shown in Figure 1. Specifically, Figure 13 is a timing chart when the semiconductor device 1 is connected to the CAN transceiver 5.

[0067] In this embodiment, when device #1, the target device, outputs transmit data TX as a read back, the transmit data TX is input to the receive data RX. At this time, the communication unit 11 of device #2, which is not the target device, performs the following operation. Here, the synchronization unit 11C monitors the receive data RX, and when it detects the stop bit and start bit at the frame switching in the receive data RX, the synchronization unit 11C resets the clock CLK count by the counter 11B (arrow in Figure 13). As a result, sampling errors are accumulated only within one frame, which suppresses the timing difference when the internal state transitions to the idle state and prevents malfunctions. In particular, in this embodiment, since the receive data RX and the count are synchronized, the timing of the transition to the idle state can be controlled with greater precision.

[0068] Furthermore, in this embodiment, even in the case of a communication system 102 (Figure 2) in which a CAN transceiver is not connected to the semiconductor device 1, when device #1 outputs transmission data TX as a Read back, the transmission data TX is input to the reception data RX. Therefore, the communication unit 11 of device #2 performs control using the synchronization unit 11C. In other words, in this embodiment, there is no need to switch control depending on the configuration of the communication system.

[0069] Furthermore, in this embodiment, when receiving data RX (from SYNC to CRC16H), the communication unit 11 uses the synchronization unit 11C, which monitors the received data RX, to perform control. Therefore, except when outputting transmission data TX, internal state transition control can be performed based on the received data RX.

[0070] <7. Other> Furthermore, the various technical features disclosed herein can be modified in various ways, in addition to the embodiments described above, without departing from the spirit of the technical creation. In other words, the embodiments described above should be considered in all respects to be illustrative and not restrictive, and the technical scope of the present invention should be understood to include all modifications that fall within the meaning and scope equivalent to the claims, rather than being limited to the embodiments described above.

[0071] <8. Addendum> As described above, the semiconductor device (1) according to one aspect of this disclosure is A receiving data input terminal (1A) is configured to receive serial data (RX), A transmit data output terminal (1B) is configured to output transmit data (TX), which is serial data, A communication unit (11) configured to receive the received data and transmit the transmitted data, Equipped with, The aforementioned communications unit is Counter (11B), The configuration includes a synchronization unit (11C) which, if its own semiconductor device is not the target device set in the received data, monitors the transmitted data and resets the counter when it detects stop bits and start bits at frame switching in the transmitted data (first configuration, Figure 8).

[0072] Furthermore, a semiconductor device (1) according to one aspect of this disclosure is A receiving data input terminal (1A) is configured to receive serial data (RX), A transmit data output terminal (1B) is configured to output transmit data (TX), which is serial data, A communication unit (11) configured to receive the received data and transmit the transmitted data, Equipped with, The aforementioned communications unit is Counter (11B), The second configuration includes a synchronization unit (11C) which, if its own semiconductor device is not the target device set in the received data, monitors the received data and resets the counter when it detects stop bits and start bits at frame switching in the received data.

[0073] Furthermore, in the second configuration described above, the synchronization unit (11C) may be configured to switch whether or not to perform synchronization control depending on whether or not the semiconductor device (1) is connected to a transceiver (5) capable of communication using a differential voltage method (third configuration, Figure 10).

[0074] Furthermore, in the third configuration described above, the transmitting and receiving device may be a CAN transceiver (5) (fourth configuration).

[0075] Furthermore, in the second configuration described above, the synchronization unit (11C) may be configured to monitor the received data as a result of the transmitted data (TX) being input to the received data (RX) (fifth configuration, Figure 12).

[0076] Furthermore, a communication system (101) according to one aspect of the present disclosure comprises a plurality of semiconductor devices (1) having any of the configurations described in the first to fifth above, The configuration includes a transceiver (5) that has a receiving data output terminal (5A) to which the receiving data input terminals (1A) of the plurality of semiconductor devices are commonly connected, and a transmitting data input terminal (5B) to which the transmitting data output terminals (1B) of the plurality of semiconductor devices are commonly connected, and that is capable of communication using a differential voltage method (sixth configuration, Figure 1).

[0077] Furthermore, in the sixth configuration described above, the transmitting and receiving device may be a CAN transceiver (5) (seventh configuration).

[0078] Furthermore, a communication system (101) according to one aspect of the present disclosure comprises a plurality of semiconductor devices (1) having any of the configurations described in the first to fifth above, The configuration includes an MCU (2) having a received data output terminal (2A) to which the received data input terminals (1A) of the plurality of semiconductor devices are commonly connected, and a transmitted data input terminal (2B) to which the transmitted data output terminals (1B) of the plurality of semiconductor devices are commonly connected (8th configuration, Figure 2). [Industrial applicability]

[0079] This disclosure can be used, for example, in in-vehicle communication systems. [Explanation of Symbols]

[0080] 1 Semiconductor device 1A RX terminal 1B TX terminal 2A RXD terminal 2B TXD terminal 3.5 CAN transceiver 3A TXD terminal 3B RXD terminal 4 CAN bus 5A RXD terminal 5B TXD terminal 6 circuit boards 7 circuit boards 8 circuit boards 11 Communications Department 11A Register 11B Counter 11C Synchronization section 91 Driver Control Unit 92 drivers 92A PMOS Transistor 92B diode 92C NMOS transistor 92D diode 93 Receiver 94 Output section 94A PMOS Transistor 94B NMOS transistor 101 Communication Systems 102 Communication Systems C1 Capacitor R1, R2 terminating resistor R91,R92 resistance

Claims

1. A receiving data input terminal configured to receive data which is serial data, A transmission data output terminal configured to output transmission data, which is serial data, A communication unit configured to receive the received data and transmit the transmitted data, Equipped with, The aforementioned communications unit is The counter, A synchronization unit is configured to monitor the transmitted data and reset the counter when it detects stop bits and start bits at frame transitions in the transmitted data, if the semiconductor device itself is not the target device set in the received data. A semiconductor device having the following features.

2. A receiving data input terminal configured to receive data which is serial data, A transmission data output terminal configured to output transmission data, which is serial data, A communication unit configured to receive the received data and transmit the transmitted data, Equipped with, The aforementioned communications unit is The counter, A synchronization unit is configured to monitor the received data if its own semiconductor device is not the target device set in the received data, and to reset the counter when it detects stop bits and start bits at frame switching in the received data. A semiconductor device having the following features.

3. The semiconductor device according to claim 2, wherein the synchronization unit is configured to switch whether or not to perform synchronization control depending on whether or not the semiconductor device is connected to a transceiver capable of communication using a differential voltage method.

4. The semiconductor device according to claim 3, wherein the transmitting and receiving device is a CAN transceiver.

5. The semiconductor device according to claim 2, wherein the synchronization unit is configured to monitor the received data as a result of the transmitted data being input to the received data.

6. A plurality of semiconductor devices according to any one of claims 1 to 5, A transceiver having a receiving data output terminal to which the receiving data input terminals of the plurality of semiconductor devices are commonly connected, and a transmitting data input terminal to which the transmitting data output terminals of the plurality of semiconductor devices are commonly connected, and capable of communication using a differential voltage scheme, A communication system equipped with these features.

7. The communication system according to claim 6, wherein the transmitting and receiving device is a CAN transceiver.

8. A plurality of semiconductor devices according to any one of claims 1 to 5, An MCU having a received data output terminal to which the received data input terminals of the plurality of semiconductor devices are commonly connected, and a transmitted data input terminal to which the transmitted data output terminals of the plurality of semiconductor devices are commonly connected, A communication system equipped with these features.

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