Semiconductor devices and ultrasonic sensors

Abstract

This semiconductor device comprises: a drive circuit configured so as to be capable of supplying drive signals in an ultrasonic band to a piezoelectric element; a damping circuit having a resistor load and an induction load; and a control circuit that is capable of controlling the drive circuit, and that is configured so as to be capable of executing a reverberation-reducing operation after supply of the drive signal to the piezoelectric element is stopped. The control circuit is configured so as to be capable, in the reverberation-reducing operation, of connecting the damping circuit to the piezoelectric element after a braking signal having a phase different than that of the drive signal is supplied to the piezoelectric element by the drive circuit.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices and ultrasonic sensors. [Background technology]

[0002] Ultrasonic sensors equipped with piezoelectric elements are used in a variety of applications. In ultrasonic sensors, a transmitted wave signal is sent by driving a piezoelectric element, and the distance or proximity of an object is detected by receiving a reflected wave signal (see, for example, Patent Document 1). [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2018-96752 [Overview of the project] [Problems that the invention aims to solve]

[0004] Even after the supply of the drive signal to the piezoelectric element for transmitting the wave signal is stopped, the piezoelectric element continues to vibrate for a while based on the mechanical energy it has stored. This vibration of the piezoelectric element after the drive signal supply is stopped is called reverberation. If the duration of reverberation (reverberation time) is long, it becomes difficult to detect objects at close range. Therefore, the development of technologies that can effectively reduce reverberation time is expected.

[0005] The purpose of this disclosure is to provide a semiconductor device and an ultrasonic sensor that contribute to reducing reverberation time. [Means for solving the problem]

[0006] The semiconductor device according to this disclosure includes a drive circuit configured to supply an ultrasonic drive signal to a piezoelectric element, a damping circuit having a resistive load and an inductive load, and a control circuit capable of controlling the drive circuit and capable of performing a reverberation reduction operation after the supply of the drive signal to the piezoelectric element is stopped, wherein the control circuit is configured to connect to the piezoelectric element after the drive circuit has supplied a damping signal having a phase different from the phase of the drive signal to the piezoelectric element in the reverberation reduction operation. [Effects of the Invention]

[0007] This disclosure makes it possible to provide a semiconductor device and an ultrasonic sensor that contribute to reducing reverberation time. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is an overall configuration diagram of an ultrasonic sensor according to the present disclosure. [Figure 2] Figure 2 shows the relationship between the output wave signal and the reflected wave signal in an ultrasonic sensor according to an embodiment of the present disclosure. [Figure 3] Figure 3 is a diagram showing the internal configuration of a semiconductor device constituting an ultrasonic sensor according to an embodiment of the present disclosure. [Figure 4] Figure 4 is a diagram showing multiple states that the drive circuit can take according to an embodiment of the present disclosure. [Figure 5] Figure 5 shows the relationship between the amplified voltage signal and the envelope signal based on the received signal according to an embodiment of the present disclosure. [Figure 6] Figure 6 shows the relationship between several control signals and the output voltages of two output buffers according to an embodiment of the present disclosure. [Figure 7] Figure 7 shows an example of the internal configuration of a damping circuit according to an embodiment of the present disclosure. [Figure 8] Figure 8 shows the waveforms of the voltage supplied to the piezoelectric element and the main drive signal during the transmission period, according to an embodiment of the present disclosure. [Figure 9]Figure 9 is a waveform diagram of the voltage supplied to the piezoelectric element and the main damping signal during the first damping period, relating to an embodiment of the present disclosure. [Figure 10] Figure 10 is a diagram showing the phase relationship between the main drive signal and the main braking signal according to an embodiment of the present disclosure. [Figure 11] Figure 11 is a timing chart of an operation (detection unit operation) involving the supply of a main drive signal and a main damping signal to a piezoelectric element according to an embodiment of the present disclosure. [Figure 12] Figure 12 shows how, according to an embodiment of the present disclosure, multiple detection unit operations are repeatedly executed during a normal detection operation. [Figure 13] Figure 13 is a flowchart of the overall operation of an ultrasonic sensor according to an embodiment of the present disclosure. [Figure 14] Figure 14 is an explanatory diagram of data stored in a memory circuit of a semiconductor device according to an embodiment of the present disclosure. [Figure 15] Figure 15 is a timing chart of the adjustment unit operation according to an embodiment of the present disclosure. [Figure 16] Figure 16 is a waveform diagram of the voltage supplied to the piezoelectric element during the adjustment transmission period and the adjustment drive signal according to an embodiment of the present disclosure. [Figure 17] Figure 17 is a waveform diagram of the voltage supplied to the piezoelectric element and the adjustment braking signal during the first adjustment braking period, relating to an embodiment of the present disclosure. [Figure 18] Figure 18 is a diagram showing the phase relationship between the adjustment drive signal and the adjustment brake signal according to an embodiment of the present disclosure. [Figure 19] Figure 19 is a flowchart of the adjustment operation according to an embodiment of the present disclosure. [Figure 20] Figure 20 is an explanatory diagram illustrating the search range related to the adjustment operation in an embodiment of the present disclosure. [Figure 21] Figure 21 is a flowchart of the adjustment operation for a resistive load according to an embodiment of the present disclosure. [Figure 22] Figure 22 is a diagram illustrating an example of the relationship between the resistance value of a resistive load and the ringing time according to an embodiment of the present disclosure. [Figure 23] Figure 23 is a diagram illustrating a first pattern of adjustment operation for a resistive load according to an embodiment of the present disclosure. [Figure 24] Figure 24 is a diagram illustrating a second pattern of flow related to the adjustment operation for a resistive load according to an embodiment of the present disclosure. [Figure 25] Figure 25 is a diagram illustrating a first termination condition related to the adjustment operation for a resistive load according to an embodiment of the present disclosure. [Figure 26] Figure 26 is a diagram illustrating a second termination condition related to the adjustment operation for a resistive load, according to an embodiment of the present disclosure. [Figure 27] Figure 27 is a diagram illustrating a third termination condition related to the adjustment operation for a resistive load, relating to an embodiment of the present disclosure. [Figure 28] Figure 28 is a flowchart of the adjustment operation for an inductive load according to an embodiment of the present disclosure. [Figure 29] Figure 29 is a flowchart of the phase adjustment operation according to an embodiment of the present disclosure. [Figure 30] Figure 30 is a diagram illustrating the restart conditions in relation to an embodiment of the present disclosure. [Figure 31] Figure 31 is a schematic top view of a vehicle equipped with a plurality of ultrasonic sensors according to an embodiment of the present disclosure. [Modes for carrying out the invention]

[0009] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the referenced figures, the same parts are denoted by the same reference numerals, and redundant descriptions relating to the same parts are omitted as a general rule. In addition, in this specification, for the sake of simplification of description, symbols or reference numerals that refer to information, signals, physical quantities, elements, or parts may be used, and the names of the information, signals, physical quantities, elements, or parts corresponding to such symbols or reference numerals may be omitted or abbreviated. For example, the adjustment control signal referenced by "MV1_CNT" described later (see Figure 3) may be written as adjustment control signal MV1_CNT, or abbreviated as control signal MV1_CNT, but all of these refer to the same thing.

[0010] First, some terms used in the description of embodiments of this disclosure will be explained. A line refers to wiring through which an electrical signal is propagated or applied. Ground refers to a reference conductive part having a reference potential of 0V (zero volts), or the potential of 0V itself. The reference conductive part is formed of a conductor such as metal. The potential of 0V is sometimes called the ground potential. In embodiments of this disclosure, voltages shown without specifying a reference represent the potential as seen from ground. A level refers to the level of potential, and for any signal or voltage of interest, a high level has a higher potential than a low level. Any digital signal can have a high-level or low-level signal. For any signal or voltage of interest, when the signal or voltage is at a high level, it strictly means that the level of the signal or voltage is at a high level, and when the signal or voltage is at a low level, it strictly means that the level of the signal or voltage is at a low level. The level for a signal may be expressed as the signal level, and the level for a voltage may be expressed as the voltage level.

[0011] For any transistor configured as a FET (field-effect transistor), including MOSFETs, the "on" state refers to the state in which the drain and source of the transistor are conducting, and the "off" state refers to the state in which the drain and source of the transistor are not conducting (blocked state). The same applies to transistors not classified as FETs. Unless otherwise specified, MOSFETs are understood to be enhancement-type MOSFETs. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor".

[0012] Any switch can be constructed using one or more FETs (field-effect transistors). When a switch is in the ON state, the terminals of that switch conduct electricity, while when a switch is in the OFF state, the terminals of that switch do not conduct electricity. Hereinafter, the ON state and OFF state of any transistor or switch may be simply referred to as ON and OFF. Connections between multiple parts forming a circuit, such as any circuit elements, wiring (lines), or nodes, should be understood to refer to electrical connections unless otherwise specified.

[0013] Figure 1 shows the overall configuration of the ultrasonic sensor 1 according to the embodiment of this disclosure. Figure 1 also shows an upper block 2 connected to the ultrasonic sensor 1 and a detection target object OBJ located at a position physically separated from the ultrasonic sensor 1. The ultrasonic sensor 1 comprises a semiconductor device 10 consisting of a semiconductor integrated circuit for ultrasonic sensors, a piezoelectric element 20, and capacitors 31 and 32. Only a part of the internal configuration of the semiconductor device 10 is shown in Figure 1.

[0014] The ultrasonic sensor 1 transmits an output wave signal W1 in the ultrasonic band towards the space outside the ultrasonic sensor 1 (away from the ultrasonic sensor 1). The output wave signal W1 is reflected by the object OBJ to be detected, generating a reflected wave signal W2. The reflected wave signal W2 is received by the ultrasonic sensor 1. Based on the received signal of the reflected wave signal W2, the ultrasonic sensor 1 performs functions such as detecting the distance to the object OBJ and detecting the approach of the object OBJ. The ultrasonic band refers to a frequency band that is higher than the frequency band of sound waves that can be heard by the human ear, but is inaudible to the human ear, and generally refers to a band of 20 kHz or higher. For example, the output wave signal W1 has a frequency in the range of 30 kHz to 80 kHz. Both the output wave signal W1 and the reflected wave signal W2 belong to the ultrasonic signal category.

[0015] The piezoelectric element 20 has a first end and a second end. The piezoelectric element 20 generates mechanical displacement (vibration) in response to a voltage signal applied between the first and second ends, and generates an output wave signal W1 through its own mechanical displacement. Therefore, the piezoelectric element 20 functions as a transmitter for the output wave signal W1. In addition, the piezoelectric element 20 has the characteristic of generating an electromotive force between the first and second ends in response to the mechanical displacement (vibration) applied to it, and also functions as a receiver for the reflected wave signal W2.

[0016] The semiconductor device 10 uses a piezoelectric element 20 to transmit an output wave signal W1 and receive a reflected wave signal W2. Hereinafter, the combined operation of transmitting the output wave signal W1 and receiving the reflected wave signal W2 may be referred to as the transmit / receive operation. The semiconductor device 10 includes a transmit circuit 11, a receive circuit 12, and a control circuit 13. The semiconductor device 10 is an electronic component formed by enclosing a semiconductor integrated circuit in a resin housing (package), and each circuit constituting the semiconductor device 10 is integrated using semiconductors. The housing of the electronic component as the semiconductor device 10 is provided with a plurality of external terminals exposed from the outside of the semiconductor device 10. As some of the plurality of external terminals provided on the semiconductor device 10, Figure 1 shows output terminals DRV1 and DRV2 and input terminals IN1 and IN2. Outside the semiconductor device 10, output terminal DRV1 is connected to the first end of the piezoelectric element 20, and output terminal DRV2 is connected to the second end of the piezoelectric element 20. Furthermore, outside the semiconductor device 10, input terminal IN1 is connected to the first end of the piezoelectric element 20 via capacitor 31, and input terminal IN2 is connected to the second end of the piezoelectric element 20 via capacitor 32. Note that capacitors 31 and 32 may be built into the semiconductor device 10.

[0017] The transmitting circuit 11 transmits an output wave signal W1 using a piezoelectric element 20 externally connected between output terminals DRV1 and DRV2. The receiving circuit 12 receives an input wave signal in the ultrasonic band using a piezoelectric element 20 externally connected between input terminals IN1 and IN2. The main input wave signal to be received is the reflected wave signal W2 based on the output wave signal W1. Thus, in this embodiment, a common piezoelectric element 20 is externally connected between output terminals DRV1 and DRV2 and between input terminals IN1 and IN2, and this common piezoelectric element 20 is shared by the transmitting circuit 11 and the receiving circuit 12 as a transducer.

[0018] However, as a variation, another piezoelectric element (not shown) different from the piezoelectric element 20 may be externally connected between input terminals IN1 and IN2 (in this case, the other piezoelectric element is also included as a component of the ultrasonic sensor 1). Alternatively, when a common piezoelectric element 20 is shared between the transmitting circuit 11 and the receiving circuit 12, the output terminal DRV1 and input terminal IN1 may be realized by one first input / output terminal, and the output terminal DRV2 and input terminal IN2 may be realized by one second input / output terminal, and the first and second input / output terminals may be connected in parallel to both the transmitting circuit 11 and the receiving circuit 12 (in this case, capacitors 31 and 32 may be inserted between the first input / output terminal and the second input / output terminal and the receiving circuit 12). The receiving circuit 12 receives an input wave signal in the ultrasonic band using the piezoelectric element 20 or the other piezoelectric element, and performs predetermined receiving signal processing on the received signal.

[0019] The control circuit 13 controls the transmitting circuit 11 and the receiving circuit 12. By controlling the transmitting circuit 11, the control circuit 13 causes the piezoelectric element 20 to transmit the output wave signal W1 using the transmitting circuit 11. In addition, based on the received signal from the receiving circuit 12 (the input wave signal received by the receiving circuit 12), the control circuit 13 detects the distance to the object to be detected OBJ and detects the approach of the object to be detected OBJ.

[0020] Figure 2 shows the transmission and reception operation of the ultrasonic sensor 1. The control circuit 13 can perform distance detection processing and proximity detection processing. In distance detection processing, the control circuit 13 calculates the distance between the ultrasonic sensor 1 and the object OBJ by measuring the length of time from when the output wave signal W1 is transmitted at time t1 until when the reflected wave signal W2 is received at time t2 (i.e., the length of time between t1 and t2). Time t1 represents the start time of transmission of the output wave signal W1 using the transmission circuit 11 and piezoelectric element 20, and time t2 represents the start time of reception of the reflected wave signal W2 using the reception circuit 12 and piezoelectric element 20. In proximity detection processing, the control circuit 13 detects the proximity of the object OBJ based on whether or not the reflected wave signal W2 is received. More specifically, for example, in proximity detection processing, if the control circuit 13 receives a reflected wave signal W2 within a predetermined time elapsed since transmitting the output wave signal W1 at time t1, it determines that the object to be detected OBJ is approaching the ultrasonic sensor 1 (for example, the vehicle on which the ultrasonic sensor 1 is mounted). Otherwise, it determines that the object to be detected OBJ is not approaching the ultrasonic sensor 1 (for example, the vehicle on which the ultrasonic sensor 1 is mounted).

[0021] The control circuit 13 is connected to the upper block 2 shown in Figure 1 in a manner that enables bidirectional communication. The upper block 2 can give various instructions to the semiconductor device 10 by sending predetermined commands to the semiconductor device 10, and the semiconductor device 10 performs various operations and processes according to the commands from the upper block 2. The results of the distance detection process and proximity detection process are transmitted from the semiconductor device 10 to the upper block 2. The upper block 2 consists of a microcomputer or the like. When the ultrasonic sensor 1 and the upper block 2 are mounted on a vehicle such as an automobile, the upper block 2 may be an ECU (Electronic Control Unit). In addition, the measurement of the length between times t1 and t2, the calculation of the distance between the ultrasonic sensor 1 and the object OBJ to be detected based on the measurement results, and the determination of whether or not the object OBJ to be detected is approaching the ultrasonic sensor 1 (for example, the vehicle on which the ultrasonic sensor 1 is mounted) may be performed by the upper block 2. In this case, for example, a signal such as signal 602 in Figure 2, which indicates the period during which the output wave signal W1 is being transmitted and the period during which the reflected wave signal W2 is being received, can be transmitted from the control circuit 13 to the upper block 2.

[0022] Figure 3 shows the internal configuration diagram of the semiconductor device 10. The semiconductor device 10 comprises a drive circuit 111, a gate driver 112, a receiving circuit 120, and a control circuit 130. The drive circuit 111 and the gate driver 112 constitute the transmitting circuit 11 in Figure 1. The receiving circuit 120 corresponds to the receiving circuit 12 in Figure 1 and has the functions of the receiving circuit 12 described above. The control circuit 130 corresponds to the control circuit 13 in Figure 1 and has the functions of the control circuit 13 described above. The semiconductor device 10 further comprises a damping circuit 140, switch circuits 150 and 160, an adjustment drive circuit 170, and an internal power supply circuit 180.

[0023] The drive circuit 111 includes transistors M1H, M1L, M2H, and M2L as four switching elements (switches). Transistors M1H and M2H are P-channel type MOSFETs, and transistors M1L and M2L are N-channel type MOSFETs. Transistors M1H and M1L are connected in series to form a first half-bridge circuit (first series circuit), and transistors M2H and M2L are connected in series to form a second half-bridge circuit (second series circuit). The first and second half-bridge circuits constitute a full-bridge circuit (H-bridge circuit). The sources of transistors M1H and M2H are connected to line LN2. A drive power supply voltage VDRV having a predetermined positive DC voltage value is applied to line LN2. The drains of transistors M1H and M1L are connected in common to line LN10, and through line LN10 to the output terminal DRV1. The drains of transistors M2H and M2L are connected to line LN20, and through line LN20, they are connected to output terminal DRV2. The sources of transistors M1L and M2L are connected to line LN1. Ground potential is applied to line LN1. As described above, output terminal DRV1 and input terminal IN1 are connected to the first end of piezoelectric element 20 outside the semiconductor device 10, and output terminal DRV2 and input terminal IN2 are connected to the second end of piezoelectric element 20 outside the semiconductor device 10 (however, input terminals IN1 and IN2 are connected to the first and second ends of piezoelectric element 20 via capacitors 31 and 32). Furthermore, the voltage or signal at output terminal DRV1 is referred to by the symbol "V1", and the voltage or signal at output terminal DRV2 is referred to by the symbol "V2". Note that it is also possible to configure transistors M1H and M2H as N-channel type MOSFETs (in this case, a circuit that generates a voltage higher than the drive power supply voltage VDRV is added).

[0024] The gate driver 112 drives the transistors using the drive power supply voltage VDRV applied to line LN2 as the positive power supply voltage and the ground voltage (0V) applied to line LN1 as the negative power supply voltage. The gate driver 112 controls the on / off state of transistors M1H, M1L, M2H, and M2L individually by controlling the gate potentials of each transistor M1H, M1L, M2H, and M2L according to the control signal CNT1 supplied from the control circuit 130. By controlling the gate potentials of each transistor M1H, M1L, M2H, and M2L, the state of the drive circuit 111 can be set to any of the states 611 to 614 in Figure 4. The drive circuit 111 may be in a state different from any of the states 611 to 614.

[0025] State 611 is the first applied state. In the first applied state, transistors M1H and M2L are ON and transistors M2H and M1L are OFF. State 612 is the second applied state. In the second applied state, transistors M1L and M2H are ON and transistors M1H and M2L are OFF. State 613 is the all-off state. In the all-off state, transistors M1H, M1L, M2H, and M2L are all OFF. State 614 is the braked state. In the braked state, transistors M1L and M2L are ON and transistors M1H and M2H are OFF.

[0026] The receiving circuit 120 is connected to input terminals IN1 and IN2 and receives the voltage signal applied between input terminals IN1 and IN2. Therefore, when the reflected wave signal W2 is received by the piezoelectric element 20, the voltage signal generated between the first and second ends of the piezoelectric element 20 based on the reflected wave signal W2 is input to the receiving circuit 120 through input terminals IN1 and IN2. The receiving circuit 120 generates a detected signal based on the voltage signal between input terminals IN1 and IN2 by applying predetermined receiving signal processing to the voltage signal between input terminals IN1 and IN2. The receiving signal processing includes DC removal processing to remove the DC component from the voltage signal between input terminals IN1 and IN2, amplification processing to amplify the voltage signal after DC removal processing, and envelope detection processing to detect the envelope of the amplified voltage signal (hereinafter referred to as the amplified voltage signal). However, as shown in Figure 3, if capacitors 31 and 32 are provided between the input terminals IN1 and IN2 and the piezoelectric element 20, the DC rejection process at the receiving signal processing stage can be omitted. The detected signal generated by the received signal 120 includes an envelope signal. In Figure 5, the solid waveform 631 is the waveform of the amplified voltage signal, and the dashed waveform 632 is the waveform of the envelope signal. The envelope signal is a voltage signal whose voltage value is the magnitude of the amplitude of the amplified voltage signal. Therefore, the envelope signal is a voltage value (hereinafter referred to as the voltage value V) that is proportional to the amplitude of the received signal of the receiving circuit 120 (i.e., the voltage signal between input terminals IN1 and IN2). EV It has (which is called).

[0027] The control circuit 130 performs the distance detection and proximity detection processing described above based on the detection signal generated by the receiving circuit 120, and also comprehensively controls the operation of each part within the semiconductor device 10. In this control, the control circuit 130 controls the control signals CNT1 to CNT4 and CNT ADJThe control circuit 130 generates and outputs the following, as well as the adjustment control signals MV1_CNT and MV2_CNT. The control circuit 130 also includes a memory circuit 131. The memory circuit 131 is provided with non-volatile memory and volatile memory. The non-volatile memory in the memory circuit 131 includes either a memory that can be written to only once (One Time Programmable ROM) or a memory that can be rewritten. The volatile memory in the memory circuit 131 includes registers.

[0028] The damping circuit 140 comprises a resistive component 141, an inductive component 142, and a bias supply circuit 143. The resistive component 141 and the inductive component 142 are elements used to reduce the reverberation of the piezoelectric element 20 and function as loads for the piezoelectric element 20. For this reason, the resistive component 141 and the inductive component 142 will hereafter be referred to as resistive load 141 and inductive load 142, respectively. The resistive load 141 and the inductive load 142 are connected in parallel to each other, and the parallel circuit of the resistive load 141 and the inductive load 142 is connected between lines LN12 and LN22. The bias supply circuit 143 supplies a predetermined DC bias voltage (e.g., 2V) to line LN22. The resistive load 141 is formed so that its resistance value is variable, and the inductive load 142 is formed so that its inductance value is variable. Control signal CNT from control circuit 130 ADJ The resistance value of the resistive load 141 and the inductance value of the inductive load 142 are set to be variable accordingly.

[0029] Switch circuit 150 includes switches 151 and 152. Switch circuit 160 includes switches 161 and 162. Each switch in switch circuits 150 and 160 can be configured with one or more MOSFETs. Each switch in switch circuits 150 and 160 may be a bus switch capable of propagating analog signals. The first end of switch 151 is connected to line LN10, and the second end of switch 151 is connected to line LN11. The first end of switch 152 is connected to line LN20, and the second end of switch 152 is connected to line LN21. The first end of switch 161 is connected to line LN11, and the second end of switch 161 is connected to line LN12. The first end of switch 162 is connected to line LN21, and the second end of switch 162 is connected to line LN22.

[0030] Switches 151 and 152 are controlled to be either ON or OFF based on the control signal CNT2 supplied from the control circuit 130. Switches 161 and 162 are controlled to be either ON or OFF based on the control signal CNT3 supplied from the control circuit 130. Control signals CNT2, CNT3, and CNT4 are each binarized signals with a value of "0" or "1". When control signal CNT2 has a value of "1", switches 151 and 152 are both ON, and when control signal CNT2 has a value of "0", switches 151 and 152 are both OFF. When control signal CNT3 has a value of "1", switches 161 and 162 are both ON, and when control signal CNT3 has a value of "0", switches 161 and 162 are both OFF.

[0031] The adjustment drive circuit 170 includes output buffers 171 and 172. Each of the output buffers 171 and 172 is a three-state buffer having an input terminal, an output terminal, and a control terminal. The control terminal of each buffer 171 and 172 receives the control signal CNT4 from the control circuit 130. The input terminal of output buffer 171 receives the adjustment control signal MV1_CNT, and the input terminal of output buffer 172 receives the adjustment control signal MV2_CNT. The output terminal of output buffer 171 is connected to line LN11, and the output terminal of output buffer 172 is connected to line LN21. Output buffers 171 and 172 are driven based on the internal power supply voltage VDD. The adjustment control signals MV1_CNT and MV2_CNT are digital signals with high-level or low-level signal levels, respectively. The voltage or signal at the output terminal of output buffer 171 is referred to by the symbol "MV1," and the voltage or signal at the output terminal of output buffer 172 is referred to by the symbol "MV2."

[0032] Figure 6 shows the relationships between signals CNT4, MV1_CNT, MV1, MV2_CNT, and MV2. Output buffer 171 outputs a high-level signal MV1 to line LN11 when the adjustment control signal MV1_CNT is high-level during the period when control signal CNT4 has a value of "1", and outputs a low-level signal MV1 to line LN11 when the adjustment control signal MV1_CNT is low-level. Output buffer 172 outputs a high-level signal MV2 to line LN21 when the adjustment control signal MV2_CNT is high-level during the period when control signal CNT4 has a value of "1", and outputs a low-level signal MV2 to line LN21 when the adjustment control signal MV2_CNT is low-level. The high levels of the output signals of output buffers 171 and 172 have the potential of the internal power supply voltage VDD, and the low levels of the output signals of output buffers 171 and 172 have the potential of ground. During the period when the control signal CNT4 has a value of "0", the adjustment drive circuit 170 is in a high-impedance state. In the high-impedance state of the adjustment drive circuit 170, the input impedance of the output terminal of the output buffer 171 as seen from line LN11 is sufficiently high, and the input impedance of the output terminal of the output buffer 172 as seen from line LN21 is sufficiently high. Therefore, during the period when the control signal CNT4 has a value of "0", it can be assumed that there is no input / output of current between line LN11 and output buffer 171, and no input / output of current between line LN21 and output buffer 172.

[0033] The internal power supply circuit 180 generates a number of power supply voltages, including a drive power supply voltage VDRV and an internal power supply voltage VDD, based on the power supply voltage VCC supplied to the semiconductor device 10 from an external power supply device (not shown). Each circuit within the semiconductor device 10 is driven based on one of the power supply voltages generated by the internal power supply circuit 180. For example, the control circuit 130, the damping circuit 140, and the adjustment drive circuit 170 may be driven based on the internal power supply voltage VDD. Here, both the drive power supply voltage VDRV and the internal power supply voltage VDD have positive DC voltage values, but the internal power supply voltage VDD is smaller than the drive power supply voltage VDRV. For example, the drive power supply voltage VDRV is 36V or 72V, while the internal power supply voltage VDD is 3V or 5V.

[0034] Figure 7 shows a specific configuration example of the damping circuit 140. Within the semiconductor device 10, the inductance value of the inductive load 142 can be arbitrarily changed by forming the inductive load 142 using a pseudo-inductor. In Figure 7, the inductive load 142 is formed by a GIC (Generalized Inpedance Converter) circuit. Specifically, the inductive load 142 in Figure 7 is composed of operational amplifiers 142a and 142b, fixed resistors 142c and 142e, variable resistors 142d and 142g, and a capacitor 142f. The fixed resistors 142c and 142e each have fixed resistance values. In contrast, the resistance values ​​of the variable resistors 142d and 142g are the same as the resistance values ​​of the resistive load 141, and are controlled by the control signal CNT from the control circuit 130. ADJ Accordingly, it can be changed independently. The inductance value of the inductive load 142 connected between lines LN12 and LN22 changes as the resistance values ​​of the variable resistors 142d and 142g change.

[0035] The first terminal of the fixed resistor 142c is commonly connected to line LN12 and the non-inverting input terminal of the operational amplifier 142a. The second terminal of resistor 142c is commonly connected to the first terminal of the variable resistor 142d and the output terminal of the operational amplifier 142b. The second terminal of the variable resistor 142d is commonly connected to the inverting input terminals of the operational amplifiers 142a and 142b and the first terminal of the fixed resistor 142e. The second terminal of the fixed resistor 142e is commonly connected to the output terminal of the operational amplifier 142a and the first terminal of capacitor 142f. The second terminal of capacitor 142f is commonly connected to the first terminal of the variable resistor 142g and the non-inverting input terminal of the operational amplifier 142b. The second terminal of the variable resistor 142g is connected to line LN22. The power supply voltages for operational amplifiers 142a and 142b are determined so that the GIC circuit functions as an inductive load for the piezoelectric element 20 during the period when switches 151, 152, 161, and 162 are ON.

[0036] Furthermore, as shown in Figure 7, switches 151 and 152 can each be configured as N-channel MOSFETs. In this case, the drain of the MOSFET as switch 151 is connected to line LN10 while the source is connected to line LN11, and the drain of the MOSFET as switch 152 is connected to line LN20 while the source is connected to line LN21. A common control signal CNT2 is then input to the gates of each MOSFET as switches 151 and 152, causing switches 151 and 152 to be turned on or off. Note that the configuration of switches 151 and 152 is not limited to that shown in Figure 7 and may be arbitrary.

[0037] Figure 8 shows the voltage and signal waveform supplied from the drive circuit 111 to the piezoelectric element 20 in order to transmit the output wave signal W1. The period during which the output wave signal W1 is transmitted is called the transmission period. In Figure 8, waveforms 651 and 652 are the waveforms of the voltage V1 applied to output terminal DRV1 and the voltage V2 applied to output terminal DRV2 by the drive circuit 111 during the transmission period, respectively. In Figure 8, waveform 653 is the waveform of the drive signal supplied to the piezoelectric element 20 by the drive circuit 111 during the transmission period. In order to clearly distinguish the drive signal supplied from the drive circuit 111 to the piezoelectric element 20 from the adjustment drive circuit 170, which will be described later as the adjustment drive signal (second drive signal), the drive signal supplied from the drive circuit 111 to the piezoelectric element 20 will be referred to as the main drive signal (first drive signal) below.

[0038] Under the control of the control circuit 130, during the transmission period, the state of the drive circuit 111 periodically transitions alternately between a first applied state and a second applied state. As a result, during the transmission period, voltages V1 and V2 each become square wave signals that alternate between low and high levels, and the phases of voltages V1 and V2 are 180° apart. During the transmission period, the voltage difference between the low and high levels of voltage V1 is equal to the magnitude of the drive power supply voltage VDRV. The same applies to voltage V2. The main drive signal corresponds to the voltage signal applied between output terminals DRV1 and DRV2 during the transmission period, and here it is assumed to be a voltage signal having the potential of output terminal DRV1 as seen from the potential of output terminal DRV2. Therefore, during the transmission period, the main drive signal becomes a square wave signal with twice the amplitude of voltage V1. During the transmission period, the frequencies f of voltages V1 and V2 and the main drive signal are, of course, equal to each other.

[0039] After supplying the main drive signal to the piezoelectric element 20 and then stopping the supply of the main drive signal, the piezoelectric element 20 continues to vibrate for a while based on the mechanical energy it has accumulated during the transmission period. The vibration of the piezoelectric element 20 after the supply of the main drive signal is stopped is called reverberation. The time during which the reverberation continues is called the reverberation time. If the reverberation time is long, it becomes difficult to detect objects at close range. After the supply of the main drive signal to the piezoelectric element 20 is stopped, the reverberation time can be reduced by supplying the piezoelectric element 20 with a signal that is out of phase with respect to the main drive signal. In this embodiment, after the supply of the main drive signal to the piezoelectric element 20 is stopped, a signal that has a different phase from the main drive signal is supplied to the piezoelectric element 20 from the drive circuit 111 as a main damping signal (first damping signal), thereby reducing the reverberation time. The period during which the main damping signal is supplied to the piezoelectric element 20 is called the first damping period.

[0040] Figure 9 shows the waveform 661 of the voltage V1 applied to the output terminal DRV1 by the drive circuit 111, the waveform 662 of the voltage V2 applied to the output terminal DRV2 by the drive circuit 111, and the waveform 663 of the main braking signal supplied to the piezoelectric element 20 by the drive circuit 111 during the first braking period. Under the control of the control circuit 130, the state of the drive circuit 111 periodically transitions alternately between the first application state and the second application state during the first braking period. As a result, during the first braking period, voltages V1 and V2 each become square wave signals that alternate between low and high levels, and the phases of voltages V1 and V2 differ by 180° from each other. During the first braking period, the voltage difference between the low and high levels of voltage V1 is equal to the magnitude of the drive power supply voltage VDRV. The same applies to voltage V2. The main braking signal corresponds to the voltage signal applied between output terminals DRV1 and DRV2 during the first braking period. Here, it is assumed to be a voltage signal having the potential of output terminal DRV1 as seen from the potential of output terminal DRV2. Therefore, during the first braking period, the main braking signal becomes a square wave signal with twice the amplitude of voltage V1. During the first braking period, the frequencies f of voltages V1 and V2 and the main braking signal are, of course, equal to each other. Also, the frequency f of the main drive signal during the transmission period is the same as the frequency f of the main braking signal during the first braking period.

[0041] Figure 10 shows the waveforms 653 and 663 of the main drive signal and the main braking signal. Although the main drive signal and the main braking signal are not supplied to the piezoelectric element 20 simultaneously, for convenience, the waveforms 653 and 663 of the main drive signal and the main braking signal are shown side by side in Figure 10 to show their phase relationship. The phase of the main braking signal relative to the phase of the main drive signal is referred to by the symbol "φ". Here, it is assumed that the phase of the main braking signal lags behind the phase of the main drive signal, and the amount of the phase delay of the main braking signal relative to the main drive signal is defined as the phase φ.

[0042] The main damping signal is sometimes referred to as the damping pulse signal. The damping pulse signal is effective in reducing reverberation in regions where the amplitude of reverberation (the amplitude of the piezoelectric element 20 due to reverberation) is high, but as the amplitude of reverberation decreases, the damping pulse signal itself can become a new source of reverberation. On the other hand, reverberation can also be reduced by connecting a resistive load or inductive load to the piezoelectric element 20 after the supply of the main drive signal is stopped, through the absorption of mechanical energy by the piezoelectric element 20. Here, the inventors have found that a resistive load or inductive load exhibits a relatively high reverberation reduction effect when the amplitude of reverberation is small, while the reverberation reduction effect becomes relatively low when the amplitude of reverberation is large due to voltage constraints of the circuit, etc.

[0043] Based on this knowledge, the inventors developed the following reverberation reduction operation. The reverberation reduction operation is performed by the control circuit 130 using the drive circuit 111 and damping circuit 140 after the supply of the main drive signal to the piezoelectric element 20 is stopped. In short, in the reverberation reduction operation, after the supply of the main drive signal to the piezoelectric element 20 is stopped, the drive circuit 111 supplies a main damping signal to the piezoelectric element 20, and after the supply of the main damping signal is stopped, the damping circuit 140 is connected to the piezoelectric element 20. This reverberation reduction operation makes it possible to quickly reduce reverberation (i.e., to keep the reverberation time low).

[0044] FIG. 11 is a timing chart of an operation involving supply of a main drive signal and a main braking signal to the piezoelectric element 20 (corresponding to a detection unit operation described later). In FIG. 11, the uppermost part shows the voltage value V of the envelope signal obtained by the receiving circuit 120 EV (see FIG. 5) is schematically illustrated. It is assumed that with the passage of time, time t A1 , t A2 , t A3 , t A4 , t A5 , t A6 and t A7 come in this order. The operation from time t A2 to time t A7 corresponds to a reverberation reduction operation.

[0045] The period between time t A1 and t A2 is a transmission period P during which the main drive signal is supplied from the drive circuit 111 to the piezoelectric element 20 A1 . The length of the transmission period P A1 corresponds to the product of the reciprocal of the frequency f of the main drive signal and the wave number of the transmitted wave. The wave number of the transmitted wave in the transmission period P A1 matches the number of cycles of the main drive signal in the transmission period P A1 . The wave number of the transmitted wave in the transmission period P A1 has a predetermined value (a predetermined value of 2 or more, for example 10), and is set based on data in a predetermined register of the storage circuit 131. Here, it is assumed that the transmission period P A1 starts when the drive circuit 111 switches from a braking state to a first application state at time t A1 , and thereafter the transmission period P A2 ends when the drive circuit 111 transitions from a second application state to the braking state at time t A1 (see FIG. 4 as appropriate).

[0046] The period between time t A2 and t A3 is a first braking period P A2 . In the first braking period P A2 , the drive circuit 111 is maintained in the braking state. In the first braking period P A2The length is shorter than the reciprocal of frequency f (i.e., the length of one period of the main drive signal), and is equal to or close to half the reciprocal of frequency f.

[0047] time t A3 and t A4 During the interval, the first braking period P is when the main braking signal is supplied from the drive circuit 111 to the piezoelectric element 20. A3 This is the first braking period P. A3 The length of the first braking period P corresponds to the product of the reciprocal of the frequency f of the main braking signal and the wavenumber of the braking wave. A3 The wavenumber of the bremssing wave in the first bremssing period P is A3 This matches the number of cycles of the main braking signal in the first braking period P. A3 The wavenumber of the bremssed wave in this case may be constant regardless of the wavenumber of the transmitted wave. First bremssed period P A3 The length may be a fixed length determined based on the stored value of the non-volatile memory in the memory circuit 131. A3 The drive circuit 111 switches from the braking state to the first applied state, which triggers the first braking period P. A3 It starts, and then at time t A4 As the drive circuit 111 transitions from the second applied state to the brake state, the first braking period P begins. A3 The process ends (see Figure 4 as appropriate). The phase φ of the main braking signal corresponds to the first braking period P. A2 It is determined by the length of the first braking period P. A2 If the length is represented by T, the phase φ of the main braking signal is given by "φ = T ÷ (1 / f) × 2π" in radians.

[0048] time t A4 and t A5 The period in between is the second braking period P. A4 This is the second braking period P. A4 Then, the drive circuit 111 is maintained in the braking state. Second braking period P A4 The second braking period P may have a predetermined length that depends on the frequency f. A4 The length should be shorter than the reciprocal of the frequency f (i.e., the length of one cycle of the main drive signal). Furthermore, the second braking period P A4It is also possible to remove the element, in which case time t A4 and time t A5 It is understood that these refer to the same time.

[0049] time t A5 and t A7 During the interval, the damping circuit 140 is connected to the piezoelectric element 20. Second damping period P A5 This is the second braking period P. A5 Then the drive circuit 111 is kept in the completely off state. In Figure 11, the shaded areas in the waveforms of voltages V1 and V2 represent the completely off state of the drive circuit 111. Time t A1 and t A5 During this time, both control signals CNT2 and CNT3 have a value of "0", and at time t A5 and t A7 During this time, both control signals CNT2 and CNT3 have a value of "1". Therefore, at time t A1 and t A7 Within that time, t A5 and t A7 The damping circuit 140 is connected to the piezoelectric element 20 only during the interval between times t, via the switch circuits 160 and 150 and the output terminals DRV1 and DRV2 (specifically, line LN12 is connected to the first end of the piezoelectric element 20 and line LN22 is connected to the second end of the piezoelectric element 20). The value of the control signal CNT4 is at time t A1 and t A7 It remains at "0" in between, and therefore the adjustment drive circuit 170 is not involved in the operation shown in Figure 11.

[0050] The control circuit 130 controls the time t A7 At this point, the values ​​of the control signals CNT2 and CNT3 are switched from "1" to "0", thereby disconnecting the damping circuit 140 from the piezoelectric element 20 (disconnecting the damping circuit 140 and the piezoelectric element 20). Also, at time t A7 Subsequently, the control circuit 130 sets the state of the drive circuit 111 to a specified state (corresponding to the dotted area in Figure 11). Typically, at time t A7Hereinafter, in preparation for a reception operation, the drive circuit 111 is set to a fully off state, but a modification is also possible in which only one of the output terminals DRV1 and DRV2 is fixed to a predetermined potential (e.g., ground potential) and the other is set to an open state.

[0051] Voltage value V of the envelope signal EV decreases from time t A4 onward. Then, after passing through time t A5 and with time t A6 as a boundary, voltage value V EV transitions from a state higher than predetermined threshold V TH#A to a state lower than predetermined threshold V TH#A . The time between time t A5 and t A6 is particularly referred to as ringing time T R#A . The control circuit 130 has a comparator (not shown) that compares voltage value V EV with predetermined threshold V TH#A , and detects ringing time T R#A based on the comparison result of the comparator. The control circuit 130 determines the time at which the damping circuit 140 is disconnected from the piezoelectric element 20, that is, time t R#A , based on the detection result of ringing time T A7 . For example, the control circuit 130 sets, as time t A6 , the time obtained after a period equal to a predetermined coefficient times (e.g., 0.25 times) ringing time T R#A has elapsed from time t A7 . It is also acceptable to set, as time t A6 , the time obtained after a predetermined time Δt that does not depend on ringing time T R#A has elapsed from time t A7 .

[0052] At time t A7 or immediately after time t A7 , reverberation has been sufficiently reduced. The reception circuit 120 generates a detected signal (hereinafter referred to as the detected signal during the reception period) based on the voltage signal between the input terminals IN1 and IN2 during the reception period set after time t A7 . The control circuit 130 can perform the above-described distance detection processing and approach detection processing based on the detected signal during the reception period.

[0053] Referring to FIG. 12, from time t A1 to t A7 , a series of operations consisting of the above-described operation until the interval and the operation during the reception period subsequent to time t A7 is referred to as a detection unit operation. In the semiconductor device 10, one or more detection unit operations can be performed under the control of the control circuit 130 in accordance with a command from the upper block 2. Distance detection processing and proximity detection processing are performed in each detection unit operation. FIG. 12 shows a state where a plurality of detection unit operations are sequentially and repeatedly executed. An operation including one or more detection unit operations is referred to as a normal detection operation.

[0054] In order to efficiently reduce reverberation, it is necessary to appropriately set the phase φ of the main braking signal corresponding to the damping pulse. However, the appropriate phase φ varies variously depending on individual differences of the piezoelectric element 20, the ambient temperature of the ultrasonic sensor 1, and the like. Similarly, in order to efficiently reduce reverberation, the resistance value of the resistive load 141 and the inductance value of the inductive load 142 should be appropriately set. In consideration of these factors, in the semiconductor device 10, prior to the normal detection operation, an adjustment operation for appropriately setting the phase φ of the main braking signal, the resistance value of the resistive load 141, and the inductance value of the inductive load 142 is executed.

[0055] FIG. 13 shows a flowchart of the overall operation of the ultrasonic sensor 1. FIG. 14 shows some data stored in the memory circuit 131 of FIG. 3. When the semiconductor device 10 is started by the start of supply of the power supply voltage VCC to the semiconductor device 10, a predetermined initial operation is performed in step S1, and then the adjustment operation is started by the semiconductor device 10 in step S2. In the initial operation, a flag FLG managed by the control circuit 130 is initialized to "0" (that is, "0" is assigned to the flag FLG). Through execution of the adjustment operation, in step S3, a set resistance value R SET , a set inductance value L SET , a set phase φ SET and a ringing time T R#HOLD are acquired, and with respect to the memory circuit 131 (see FIG. 14), the set resistance value R SETSetting data 131b_R and set inductance value L are shown. SET Setting data 131b_L and setting phase φ are shown. SET The setting data 131b_φ and ringing time T are shown. R#HOLD Ringing data 131c indicating this is stored. Furthermore, in step S3, direction data 131d_R, 131d_L, and 131d_φ are also acquired and stored in the memory circuit 131 (see Figure 14). The significance of this data will be described later. After the acquisition and storage in step S3, when the adjustment operation is completed in step S4, the semiconductor device 10 transitions to a state where it can perform normal detection operations in step S5. Thereafter, in response to a command from the upper block 2, the semiconductor device 10 performs detection unit operations in step S6. Ringing time T is set for each detection unit operation. R#A The values ​​are measured and acquired. Each time a detection unit operation is performed, the control circuit 130 determines in step S7 whether a predetermined restart condition is met. If the restart condition is not met, the process returns to step S6. If the restart condition is met, in step S8, the flag FLG is set to "1" and the process returns to step S2, where the adjustment operation is performed again. The restart condition will be described later. Hereinafter, a value of "0" for the flag FLG will be written as "FLG=0", and a value of "1" for the flag FLG will be written as "FLG=1".

[0056] Each data acquired in step S3 is stored in the volatile memory (registers, etc.) within the memory circuit 131. However, it is also possible to store each data acquired in step S3 in the non-volatile memory within the memory circuit 131. Furthermore, an initial resistance value R is set in advance for the non-volatile memory within the memory circuit 131. INT Initial data 131a_R and initial inductance value L are shown. INT Setting data 131a_L and initial phase φ are shown. INT Initial data 131a_φ is stored to indicate this. The control circuit 130 can access each initial data at the start of the adjustment operation.

[0057] [Adjustment operation] The adjustment operation will be explained. The adjustment operation can also be called the calibration operation. There are adjustment operations for resistive loads, adjustment operations for inductive loads, and adjustment operations for phase. In the adjustment operation for resistive loads, the ringing time T in the normal detection operation is explained. R#A Set the resistance value R of the resistive load 141 to be suitable for reducing (ideally minimizing) the resistance value R SET It is acquired as follows. In the adjustment operation for inductive loads, the ringing time T in the normal detection operation is obtained. R#A Set the inductance value L of the inductive load 142 to be suitable for reducing (ideally minimizing) the inductance. SET It is acquired as follows. In the phase adjustment operation, the ringing time T in the normal detection operation is obtained. R#A Set a phase φ suitable for reducing (ideally minimizing) the phase φ SET It will be acquired as follows.

[0058] Each of the adjustment operations for resistive loads, inductive loads, and phases includes multiple adjustment unit operations. In the adjustment operation for resistive loads, an adjustment unit operation to measure the reverberation state when the piezoelectric element 20 is driven is performed multiple times, switching the resistance value of the resistive load 141 in multiple stages, similar to the detection unit operation, until the resistance value of the resistive load 141 that is expected to minimize the reverberation time is set to the resistance value R SET This is obtained as follows. The same applies to the adjustment operation for inductive loads and the adjustment operation for phase. However, if the adjustment operation is performed using a large amplitude drive signal from the drive power supply voltage VDRV, the signal components of reflected waves from the surroundings and the signal components of reverberation may mix, and the adjustment may not be performed accurately (i.e., the optimal setting resistance value R SET (It becomes difficult to obtain such values). Taking this into consideration, in the adjustment operation, the piezoelectric element 20 is driven using the adjustment drive circuit 170, which is a small amplitude driver, and the set resistance value R is obtained from the reverberation state at that time. SET To find the following:

[0059] Figure 15 shows the timing chart of the adjustment unit operation. In Figure 15, the voltage value V of the envelope signal from the receiving circuit 120 is shown at the top. EV (See Figure 5) This is shown schematically. As time progresses, time t B1 tB2 t B3 t B4 t B5 t B6 and t B7 However, these events are assumed to occur in this order. In each adjustment unit operation, the value of the control signal CNT2 is at time t B1 It was "1" from earlier, and at time t B7 At this point, it switches from "1" to "0". However, the value of the control signal CNT2 may remain fixed at "1" from the time the adjustment operation starts in step S2 in Figure 13 until the adjustment operation is completed in step S4. In each adjustment unit operation, the value of the control signal CNT3 is at time t B5 and t B7 It is "1" only during the interval and "0" during the other intervals. In each adjustment unit operation, the value of the control signal CNT4 is at time t B1 It was "1" from earlier, and at time t B5 At this point, it switches from "1" to "0," and thereafter remains "0." During the period when the values ​​of control signals CNT2 and CNT4 are both "1," the output voltage MV1 of output buffer 171 matches the voltage V1 at output terminal DRV1, and the output voltage MV2 of output buffer 172 matches the voltage V2 at output terminal DRV2. From the start of the adjustment operation in step S2 in Figure 13 until the completion of all adjustment operations in step S4, the drive circuit 111 is kept in a completely off state, and the input impedance of the drive circuit 111 as seen from output terminals DRV1 and DRV2 can be considered sufficiently high.

[0060] time t B1 and t B2 The interval is the adjustment transmission period P during which the adjustment drive signal is supplied from the adjustment drive circuit 170 to the piezoelectric element 20. B1 In Figure 16, waveforms 671 and 672 correspond to the adjustment transmission period P, respectively. B1 These are the output voltages MV1 and MV2 (and therefore the waveforms of voltages V1 and V2) of the adjustment drive circuit 170 in Figure 16. In Figure 16, waveform 673 is the adjustment transmission period P B1 This is the waveform of the adjustment drive signal supplied to the piezoelectric element 20 by the adjustment drive circuit 170. Adjustment transmission period P B1Then, according to the adjustment control signals MV1_CNT and MV2_CNT from the control circuit 130, voltages MV1 and MV2 become square wave signals that alternate between low and high levels, and the phases of voltages MV1 and MV2 are 180° apart. Adjustment transmission period P B1 In this configuration, the voltage difference between the low and high levels of voltage MV1 is equal to the magnitude of the internal power supply voltage VDD. The same applies to voltage MV2. The adjustment drive signal is transmitted during the adjustment transmission period P. B1 This corresponds to the voltage signal applied between output terminals DRV1 and DRV2, and here it is defined as a voltage signal having the potential of output terminal DRV1 as seen from the potential of output terminal DRV2. Therefore, the adjustment transmission period P B1 In this configuration, the adjustment drive signal is a square wave signal with twice the amplitude of the voltage MV1. Adjustment transmission period P B1 The voltages MV1 and MV2 and the frequency of the adjustment drive signal are as follows during the transmission period P A1 The frequency f of the main drive signal is the same as that of the main drive signal. Therefore, the adjustment drive signal is also an ultrasonic band signal, just like the main drive signal. The amplitude of the adjustment drive signal is smaller than the amplitude of the main drive signal, and the ratio of the amplitude of the adjustment drive signal to the amplitude of the main drive signal is "VDD / VDRV".

[0061] Also, adjustment transmission period P B1 The length is the transmission period P A1 It is the same length as, and therefore, the adjustment transmission period P B1 The number of cycles (wavelengths) of the adjustment drive signal in this case is the transmission period P A1 This is the same as the number of periods (wavelengths) of the main drive signal in . Here, time t B1 Before that, both voltages MV1 and MV2 are at a low level, and at time t B1 The voltage MV1 switches from a low level to a high level, which triggers the adjustment transmission period P. B1 It is assumed that this will begin. Then, at time t B2 The voltage MV2 switches from a high level to a low level, which triggers the adjustment transmission period P. B1 The process is ending.

[0062] time t B2 and tB3 The interval is the first adjustment brake period P. B2 This is the first adjustment brake period P. B2 Then, voltages MV1 and MV2 are both maintained at a low level. First adjustment brake period P B2 The length is shorter than the reciprocal of frequency f (i.e., the length of one cycle of the adjustment drive signal), and is equal to or close to half the reciprocal of frequency f.

[0063] time t B3 and t B4 During the interval, the adjustment braking signal (second braking signal) is supplied from the adjustment drive circuit 170 to the piezoelectric element 20 during the first adjustment braking period P. B3 In Figure 17, waveforms 681 and 682 correspond to the first adjustment damping period P, respectively. B3 These are the waveforms of the output voltages MV1 and MV2 of the adjustment drive circuit 170 (and therefore the waveforms of voltages V1 and V2). In Figure 17, waveform 683 represents the first adjustment damping period P B3 This is the waveform of the adjustment braking signal supplied to the piezoelectric element 20 by the adjustment drive circuit 170. First adjustment braking period P B3 Then, according to the adjustment control signals MV1_CNT and MV2_CNT from the control circuit 130, voltages MV1 and MV2 become square wave signals that alternate between low and high levels, and the phases of voltages MV1 and MV2 are 180° apart. First adjustment damping period P B3 In this configuration, the voltage difference between the low and high levels of voltage MV1 is equal to the magnitude of the internal power supply voltage VDD. The same applies to voltage MV2. The adjustment damping signal is applied during the first adjustment damping period P. B3 In this case, it corresponds to the voltage signal applied between output terminals DRV1 and DRV2, and here it is defined as a voltage signal having the potential of output terminal DRV1 as seen from the potential of output terminal DRV2. Therefore, the first adjustment damping period P B3 In this case, the adjustment damping signal is a square wave signal having twice the amplitude of the voltage MV1. First adjustment damping period P B3 The voltages MV1 and MV2 and the frequency of the adjustment braking signal are as follows during the transmission period P A1The frequency f is the same as that of the main braking signal (see Figure 11). Just as the amplitude of the adjustment drive signal is smaller than that of the main drive signal, the amplitude of the adjustment braking signal is smaller than that of the main braking signal, and the ratio of the amplitude of the adjustment braking signal to the amplitude of the main braking signal is "VDD / VDRV".

[0064] Furthermore, the first adjustment braking period P B3 The length is the first braking period P A3 (See Figure 11) This is the same length as the first adjustment braking period P. B3 The number of cycles (wavelengths) of the adjustment braking signal in this case is the first braking period P A3 This is the same as the period (wavelength) of the main braking signal at time t. B3 When the voltage MV1 switches from a low level to a high level, the first adjustment damping period P B3 It starts, and then at time t B4 When the voltage MV2 switches from a high level to a low level, the first adjustment damping period P B3 The process is ending.

[0065] Figure 18 shows the waveforms 673 and 683 of the adjustment drive signal and the adjustment brake signal. Although the adjustment drive signal and the adjustment brake signal are not supplied to the piezoelectric element 20 simultaneously, for convenience, the waveforms 673 and 683 of the adjustment drive signal and the adjustment brake signal are shown side by side vertically in Figure 18 to show their phase relationship. The phase of the adjustment brake signal is the phase relative to the phase of the adjustment drive signal. It is assumed that the phase of the adjustment brake signal lags behind the phase of the adjustment drive signal, and the amount of the phase lag of the adjustment brake signal relative to the adjustment drive signal is considered to be the phase of the adjustment brake signal. The phase of the adjustment brake signal is also represented by the symbol "φ", similar to the phase of the main brake signal. The phase φ of the adjustment brake signal is the first adjustment brake period P B2 Determined by the length of the first adjustment brake period P. B2 If the length is represented by T, the phase φ of the adjustment braking signal is given by "φ = T ÷ (1 / f) × 2π" in radians.

[0066] time t B4 and t B5The interval is the second adjustment brake period P. B4 This is the second adjustment brake period P. B4 Then, voltages MV1 and MV2 are both maintained at a low level. Second adjustment brake period P B4 The length of the second braking period P A4 (See Figure 11) This is the same length as the second braking period P in normal detection operation. A4 If it is deleted, then the adjustment operation will also have a second adjustment brake period P B4 It is deleted, and in this case, time t B4 and time t B5 It is understood that these refer to the same time.

[0067] time t B5 and t B7 During the interval, the damping circuit 140 is connected to the piezoelectric element 20. Second adjustment damping period P B5 This is the second adjustment braking period P. B5 Then the adjustment drive circuit 170 enters a high-impedance state, and in Figure 15, the shaded areas in the waveforms of voltages MV1 and MV2 represent the high-impedance state of the adjustment drive circuit 170. Second adjustment damping period P B5 In this configuration, the damping circuit 140 is connected to the piezoelectric element 20 through the switch circuits 160 and 150 and the output terminals DRV1 and DRV2 (specifically, line LN12 is connected to the first end of the piezoelectric element 20 and line LN22 is connected to the second end of the piezoelectric element 20).

[0068] In the adjustment unit operation, the voltage value V of the envelope signal. EV is, time t B4 It decreases from there. And at time t B5 After passing time t B6 The voltage value V EV The predetermined threshold V TH#B From a higher state to a predetermined threshold V TH#B It transitions to a lower state. Time t B5 and t B6 The time in between is specifically the ringing time T. R#B It is called that. The control circuit 130 has a voltage value V EV set to a predetermined threshold V TH#BIt has a comparator (not shown) that compares with the ringing time T based on the comparison result of the comparator. R#B The control circuit 130 detects the ringing time T during the adjustment unit operation. R#B Any time after detection is time t B7 It is acceptable to define it as such.

[0069] Predetermined threshold V TH#B This is determined based on the value stored in the non-volatile memory within the memory circuit 131. In contrast, a predetermined threshold V in normal detection operation TH#A (See Figure 11) is set based on commands from the upper block 2. However, a predetermined threshold V is set based on the stored value in the non-volatile memory within the memory circuit 131. TH#A It may be determined in such a way that the predetermined threshold V TH#A and a predetermined threshold V TH#B These may differ from each other, or they may be in agreement.

[0070] The following describes several specific operational examples, application techniques, and modification techniques related to the ultrasonic sensor 1 within the context of multiple embodiments. Unless otherwise specified and without contradiction, the matters described above apply to each of the following embodiments. In the event of any inconsistency between the above and the embodiments described above, the description in the respective embodiment may take precedence. Furthermore, unless there is a contradiction, the matters described in any of the embodiments shown below can be applied to any other embodiment (i.e., any two or more embodiments from the multiple embodiments can be combined).

[0071] <<First Example>> A first embodiment will be described. Figure 19 shows a flowchart of the adjustment operation according to the first embodiment. In the adjustment operation in Figure 19, the adjustment operation for the resistive load in step S20, the adjustment operation for the inductive load in step S40, and the phase adjustment operation in step S60 are performed sequentially, and finally the ringing time T is set in step S80. R#HOLDRinging data 131c (see Figure 14) indicating this is stored in the memory circuit 131. The combination of processes in steps S20, S40, S60, and S80 corresponds to the combination of steps S2 to S4 in Figure 13. The execution order of steps S20, S40, and S60 can be different from that shown in Figure 19, but in the first embodiment, the operations of steps S20, S40, and S60 are performed in this order.

[0072] As shown in Figure 20, the search range R is relative to the resistance value of the resistive load 141. RNG The search range L is set for the inductance value of the inductive load 142. RNG The following is set. In addition, the search range φ is set relative to the phase φ of the main braking signal and the adjustment braking signal. RNG This is set. In the following explanation, when simply referred to as phase φ, phase φ refers to the phase of the main braking signal and the adjustment braking signal. Also, below, the resistance value of the resistive load 141 may be referred to as resistance value R, and the inductance value of the inductive load 142 may be referred to as inductance value L.

[0073] Search range R RNG The minimum value is R MIN From the maximum value R MAX This is the variable range of the resistance value R up to (R MIN <R MAX ). Search range R RNG (N R The search range R is divided into -1) parts (for example, equally divided). RNG Within the first to the Nth R Candidate resistance values ​​are set. The first candidate resistance value is the minimum value R. MIN and the Nth R The candidate resistance value is the maximum value R MAX The (j+1)th candidate resistance value is greater than the jth candidate resistance value for any integer j. The resistance R of the resistive load 141 is the first to the Nth R It can take any of the candidate resistance values. Therefore, the initial resistance value R INT and the set resistance value R SET (See Figure 14) are the 1st to Nth R It will be one of the candidate resistance values.

[0074] Search range L RNG The minimum value is L MIN From the maximum value L MAX This is the variable range of the inductance value L up to (L MIN <L MAX ). Search range L RNG (N L The search range L is divided into -1) parts (for example, equally divided). RNG Within the first to the Nth L Candidate inductance values ​​are set. The first candidate inductance value is the minimum value L. MIN and the Nth L The candidate inductance value is the maximum value L. MAX The inductance value L of the inductive load 142 is the first to the Nth candidate inductance value. L It can take any of the candidate inductance values. Therefore, the initial inductance value L INT and the set inductance value L SET (See Figure 14) are the 1st to Nth L It will be one of the candidate inductance values.

[0075] Search range φ RNG The minimum phase is φ MIN From maximum phase φ MAX This is the variable range of the phase φ up to (φ MIN <φ MAX ). Search range φ RNG The search range φ is created when it is divided into (Nφ-1) parts (for example, equally divided). RNG Within this, the first to Nth candidate phases are set. The first candidate phase is the minimum phase φ MIN And the Nth candidate phase is the maximum phase φ MAX Therefore, for any integer j, the (j+1)th candidate phase is assumed to be greater than the jth candidate phase. The phase φ of the main braking signal and the adjustment braking signal can take any of the 1st to Nth candidate phases. Thus, the initial phase φ INT and setting phase φ SET (See Figure 14) represents one of the first to Nφ candidate phases.

[0076] Furthermore, the search range RRNG , L RNG and φ RNG This is determined based on the contents of the memory circuit 131. The above N R , N L And Nφ has a predetermined integer of 2 or more (for example, the number 10). R , N L The agreement or disagreement of the values ​​of Nφ is irrelevant. Furthermore, for the resistance value R, the change between the j-th candidate resistance value and the (j+n)-th candidate resistance value is referred to as an n-step shift (where j is a natural number). The same applies to the inductance value L and phase φ. n is any integer greater than or equal to 1.

[0077] [Adjustment operation for resistive loads] Figure 21 shows a flowchart of the adjustment operation for a resistive load. The adjustment operation for a resistive load shown in Figure 21 can be performed in step S20 of Figure 19. The adjustment operation for a resistive load begins with the processing in step S21. In step S21, the control circuit 130 refers to the memory circuit 131 (see Figure 14) and sets the initial resistance value R INT The resistance value R[1] is set to the resistance value R of the resistive load 141. In addition, the control circuit 130 sets the initial inductance value L for the inductance value L and the phase φ, respectively. INT and initial phase φ INT Set the inductance value L. However, if the order of execution of steps S20, S40, and S60 shown in Figure 19 is reversed and the adjustment operation for the inductive load has already been performed before the adjustment operation for the resistive load, then the set inductance value L is set relative to the inductance value L. SET It is acceptable to set the phase φ, and similarly, if the phase adjustment operation has already been performed before the adjustment operation for the resistive load, then the set phase φ is relative to the phase φ. SET You can set it.

[0078] In step S22 following step S21, the control circuit 130 performs the first adjustment unit operation and the ringing time T measured in the first adjustment unit operation R#B Ringing time T R#B[1] is obtained. Then, in step S23, the control circuit 130 sets the direction of change. In this case, if "FLG=0" (see Figure 13), the direction of change is set to the positive direction. However, even if "FLG=0", the resistance value R[1] is the maximum value R MAX If it matches, or if the resistance value when the resistance value R[1] is shifted in the positive direction by n steps is the search range R RNG If it exceeds a certain value, a negative direction is set as the direction of change. If "FLG=1", the opposite of the direction of change indicated by direction data 131d_R is to be set as the direction of change in step S23 (the significance of this will become clear later). Note that a positive direction means the direction that increases the value, and a negative direction means the direction that decreases the value.

[0079] After step S23, in step S24 the control circuit 130 assigns "1" to the variable i and then proceeds to step S25. In step S25, the control circuit 130 determines the resistance value R[i+1] by shifting the resistance value R[i] in n steps in the set direction of change, and sets the resistance value R[i+1] to the resistance value R of the resistive load 141. In step S26 following step S25, the control circuit 130 adds "1" to the variable i. In the subsequent step S27, the control circuit 130 performs the i-th adjustment unit operation and the ringing time T measured in the i-th adjustment unit operation is determined. R#B Ringing time T R#B [i] is obtained. In the following step S28, the control circuit 130 is given the inequality "T R#B [i] <T R#B [i-1]” is determined to determine if it is true, that is, the ringing time T in this case. R#B [i] is the previous ringing time T R#B Determine if it is less than [i-1]. In step S28, the inequality "T R#B [i] <T R#B If [i-1] is true, proceed to step S29; otherwise, proceed to step S31.

[0080] In step S29, the control circuit 130 determines whether any of the termination conditions are met. There are first to third termination conditions, the details of which will be described later. If any of the termination conditions are met in step S29, the process proceeds to step S30. If no termination conditions are met, the process returns to step S25 and the process from step S25 onward is repeated. In step S31, the control circuit 130 reverses the direction of change set in step S23. If step S31 is reached, the direction of change of the resistance value R thereafter is the reversed direction of change. In step S32, following step S31, the control circuit 130 determines whether "i=2" is met. If "i=2" is met, the process proceeds from step S32 to step S34. If "i=2" is not met, the process proceeds from step S32 to step S33. In step S33, the control circuit 130 determines whether any of the termination conditions are met. In step S33, if any termination condition is met, the process proceeds to step S30; however, if no termination condition is met, the process proceeds to step S34. In step S34, the control circuit 130 determines the resistance value R[i+1] by shifting the resistance value R[i] in the set direction of change (the direction of change after reversal) by (2 × n) steps, and sets the resistance value R[i+1] to the resistance value R of the resistive load 141. After step S34, the process returns to step S26.

[0081] In step S30, the control circuit 130 sets the resistance value R[i-1] or R[i] according to the termination condition that was met in step S29 or S33. SET Determine (substitute) and set the resistance value R SETSetting data 131b_R indicating the value R is stored in the memory circuit 131, and direction data 131d_R corresponding to the resistance value R is also stored in the memory circuit 131. If step S30 is reached without going through step S31, the stored direction data 131d_R indicates the positive direction, and if step S30 is reached via step S31, the stored direction data 131d_R indicates the negative direction. Upon completion of the processing in step S30, the adjustment operation for the resistive load is completed, and in the subsequent normal detection operation, the control circuit 130 determines that the resistance value R of the resistive load 141 is the set resistance value R in the setting data 131b_R. SET The damping circuit 140 is controlled to have the following properties.

[0082] The technical significance of the adjustment operation for resistive loads will be explained by illustrating several patterns. When reducing reverberation using the resistive load 141, the reverberation time, including the ringing time, varies depending on the resistance value R of the resistive load 141. As shown in Figure 22, the ringing time can be considered to decrease monotonically as the resistance value R increases, reaching a minimum value, and then increasing monotonically.

[0083] In the first pattern shown in Figure 23, the ringing time decreases with increasing resistance R (increase from R[1] to R[2]). In this case, the set resistance R is maintained in the positive direction until the termination condition is met. SET The process then searches for the desired resistance value R. The first pattern corresponds to the pattern in Figure 21 where, after steps 21 to S29, steps S25 to S29 are repeated at least once before proceeding to step 30. Note that in Figure 23 and Figures 24 to 27 described later, it is assumed that the direction of change is set to the positive direction in step S23.

[0084] In the second pattern shown in Figure 24, the ringing time increases as the resistance value R is increased from resistance value R[1] to resistance value R[2]. In this case, after steps S21 to S28 in Figure 21, the process proceeds to step S31, where the direction of change is switched to the negative direction. Thereafter, the resistance value R is changed in the negative direction while searching for the resistance value R that is most suitable for minimizing the ringing time. Note that, due to the (2 × n) step shift in step S34, in the second pattern, resistance value R[3] is obtained by shifting resistance value R[2] by (2 × n) steps in the negative direction. Also, in the second pattern, the ringing time T corresponding to resistance value R[2] R#B If, immediately after obtaining [2], the termination condition (the second termination condition corresponding to Figure 26 described later) is met and the process proceeds to step S30, the opportunity to explore in the negative direction is lost. A branching process in step S32 is provided to avoid this loss of opportunity.

[0085] The first termination condition will be explained with reference to Figure 25. The first termination condition is that the change in ringing time when the resistance value R is changed from resistance value R[i-1] to resistance value R[i] is within a predetermined time T. TH1 This holds true when it does not exceed (for example, 40 microseconds). That is, (T R#B [i]-T R#B [i-1]) The absolute value of the predetermined time T TH1 The first termination condition is met if the following conditions are met. This is because it is assumed that the change in ringing time due to the change in resistance R becomes small near the minimum value of the ringing time. If the first termination condition is met and step S30 is reached, the control circuit 130 will control the ringing time T R#B [i] and T R#B Compare [i-1] and “T R#B [i]≧T R#B If [i-1], set the resistance value R[i-1]. SET Determine (substitute) to “T R#B [i] <T R#B If [i-1], set the resistance value R[i]. SET Determine (substitute) it.

[0086] The second termination condition will be explained with reference to Figure 26. The second termination condition is that the change in ringing time when the resistance value R is changed from resistance value R[i-1] to resistance value R[i] is within a predetermined time T. TH1 This holds true when the time increases beyond (for example, 40 μs). That is, “T R#B [i]-T R#B [i-1]≧T TH1 The second termination condition is met when " is true. Considering individual differences in the piezoelectric element 20 and the ambient temperature of the ultrasonic sensor 1, it is conceivable that the ringing time may increase sharply in response to a constant change in the resistance value R near the point where the ringing time is minimized. The second termination condition addresses this case. R#B [i]-T R#B [i-1]≧T TH1 If the second termination condition is met by the fulfillment of ", set the resistance value R[i-1] to the set resistance value R SET Determine (substitute) it.

[0087] The third termination condition will be explained with reference to Figure 27. In step S25 or S34, the resistance value R will be updated from resistance value R[i] to resistance value R[i+1], but the updated resistance value R will be within the search range R. RNG If it exceeds (in other words, if the updated resistance value R is within the search range R) RNG If it does not belong to the condition, the third termination condition is met. If the third termination condition is met, the resistance value R[i] which is the resistance value before the update is set to the new resistance value R SET Determine (substitute) it.

[0088] Thus, in the adjustment operation for the resistive load, the control circuit 130 performs the adjustment unit operation multiple times while switching the resistance value R of the resistive load 141 in multiple stages, thereby performing multiple ringing times T R#B The multiple ringing times T obtained are acquired. R#B The minimum ringing time T among them R#B This identifies the first to the Nth. The control circuit 130 then controls the first to the Nth. R Among the candidate resistance values ​​(see Figure 20), the minimum ringing time T R#B The corresponding candidate resistance value is set to the resistance value R SET It can be defined as follows.

[0089] In the adjustment operation for a resistive load, the object of adjustment is the resistance value R of the resistive load 141, and the set resistance value R for the resistive load 141 is set in the adjustment operation for a resistive load. SET The resistance value R of the resistive load 141 is set in the subsequent normal detection operation. SET In contrast, in the adjustment operation for inductive loads, the object of adjustment is the inductance L of the inductive load 142, and the set inductance value L for the inductive load 142 is determined in the adjustment operation for inductive loads. SET The inductance value L of the inductive load 142 is determined, and in the subsequent normal detection operation, the inductance value L is set. SET Similarly, in the phase adjustment operation, the object of adjustment is the phase φ (which is both the phase of the main braking signal and the phase of the adjustment braking signal), and in the phase adjustment operation, the set phase φ is relative to the phase φ. SET Once determined, the phase φ of the main braking signal is set during the subsequent normal detection operation. SET Thus, the only difference between the adjustment operation for resistive loads and the adjustment operation for inductive loads and phase is the object being adjusted. Aside from this difference, the adjustment operation for inductive loads and phase is basically the same as the adjustment operation for resistive loads. However, there are a few other differences, so the flow of the adjustment operation for inductive loads and phase is explained below.

[0090] [Adjustment operation for inductive loads] Figure 28 shows a flowchart of the adjustment operation for inductive loads. The adjustment operation for inductive loads shown in Figure 28 can be performed in step S40 of Figure 19. The adjustment operation for inductive loads begins with the processing in step S41. In step S41, the control circuit 130 refers to the memory circuit 131 (see Figure 14) and sets the initial inductance value L INT The inductance value L[1] is set to the inductance value L of the inductive load 142. In addition, the control circuit 130 sets the initial phase φ with respect to the phase φ. INT Set the resistance value R, and set the resistance value R obtained in step S20. SET Set the initial resistance value R. INTIt is also possible to modify the settings. In particular, for example, in cases where the adjustment operation for an inductive load is performed without going through the adjustment operation for a resistive load, the resistance value R is set to the initial resistance value R in step S41. INT This will be set.

[0091] In step S42 following step S41, the control circuit 130 performs the first adjustment unit operation and the ringing time T measured in the first adjustment unit operation R#B Ringing time T R#B [1] is obtained. Then, in step S43, the control circuit 130 sets the direction of change. In this case, if "FLG=0" (see Figure 13), the direction of change is set to the positive direction. However, even if "FLG=0", if the inductance value L[1] is at its maximum value L MAX If it matches, or if the inductance value L[1] is shifted in the positive direction by n steps, the inductance value will be within the search range L. RNG If it exceeds this value, a negative direction is set as the direction of change. If "FLG=1", the opposite of the direction of change indicated by direction data 131d_L is set as the direction of change to be set in step S43 (the significance of this will become clear later).

[0092] After step S43, in step S44 the control circuit 130 assigns "1" to the variable i and then proceeds to step S45. In step S45, the control circuit 130 determines the inductance value L[i+1] by shifting the inductance value L[i] in n steps in the set direction of change, and sets the inductance value L[i+1] to the inductance value L of the inductive load 142. In step S46 following step S45, the control circuit 130 adds "1" to the variable i. In the subsequent step S47, the control circuit 130 performs the i-th adjustment unit operation and the ringing time T measured in the i-th adjustment unit operation is determined. R#B Ringing time T R#B [i] is obtained. In the following step S48, the control circuit 130 is given the inequality "T R#B [i] <T R#BDetermine whether the inequality "T R#B [i] <T R#B If [i-1] is true, proceed to step S49; otherwise, proceed to step S51.

[0093] In step S49, the control circuit 130 determines whether any of the termination conditions are met. If any of the termination conditions are met in step S49, the process proceeds to step S50. If no termination conditions are met, the process returns to step S45 and the subsequent steps are repeated. In step S51, the control circuit 130 reverses the direction of change set in step S43. Once step S51 is reached, the direction of change of the inductance value L thereafter is the reversed direction of change. In step S52, following step S51, the control circuit 130 determines whether "i=2" is met. If "i=2" is met, the process proceeds from step S52 to step S54. If "i=2" is not met, the process proceeds from step S52 to step S53. In step S53, the control circuit 130 determines whether any of the termination conditions are met. If any of the termination conditions are met in step S53, the process proceeds to step S50. If no termination conditions are met, the process proceeds to step S54. In step S54, the control circuit 130 determines the inductance value L[i+1] by shifting the inductance value L[i] in the set direction of change (the direction of change after reversal) by (2 × n) steps, and sets the inductance value L[i+1] to the inductance value L of the inductive load 142. After step S54, the process returns to step S46.

[0094] In step S50, the control circuit 130 sets the inductance value L[i-1] or L[i] according to the termination condition met in step S49 or S53. SET Determine (substitute) and set the inductance value L SETSetting data 131b_L indicating the direction is stored in the memory circuit 131, and direction data 131d_L corresponding to the inductance value L is also stored in the memory circuit 131. If step S50 is reached without going through step S51, the stored direction data 131d_L indicates the positive direction, and if step S50 is reached via step S51, the stored direction data 131d_L indicates the negative direction. Upon completion of the processing in step S50, the adjustment operation for the inductive load is completed, and in the subsequent normal detection operation, the control circuit 130 determines that the inductance value L of the inductive load 142 is the set inductance value L in the setting data 131b_L. SET The damping circuit 140 is controlled to have the following properties.

[0095] The termination conditions for adjustment operations for inductive loads are the same as those for adjustment operations for resistive loads, and the termination conditions described for adjustment operations for resistive loads also apply to adjustment operations for inductive loads. In this application, the resistance values ​​R, R[1], R[2], R[3], R[i-1], R[i], R[i+1] and R[i] used in the description of adjustment operations for resistive loads are also applied. SET These are inductance values ​​L, L[1], L[2], L[3], L[i-1], L[i], L[i+1], and L SET You can then reinterpret this and replace steps S21 to S34 in the explanation of the adjustment operation for resistive loads with steps S41 to S54, respectively.

[0096] Thus, in the adjustment operation for the inductive load, the control circuit 130 performs the adjustment unit operation multiple times while switching the inductance value L of the inductive load 142 in multiple stages, thereby performing multiple ringing times T R#B The multiple ringing times T obtained are acquired. R#B The minimum ringing time T among them R#B This identifies the first to the Nth. The control circuit 130 then controls the first to the Nth. L Among the candidate inductance values ​​(see Figure 20), the minimum ringing time T R#B Set the corresponding candidate inductance value L SET It can be defined as follows.

[0097] [Phase adjustment operation] Figure 29 shows a flowchart of the phase adjustment operation. The phase adjustment operation shown in Figure 29 can be performed in step S60 of Figure 19. The phase adjustment operation starts from the process in step S61. In step S61, the control circuit 130 refers to the memory circuit 131 (see Figure 14) and sets the initial phase φ INT The phase φ[1] is set to the phase φ of the adjustment braking signal. In addition, the control circuit 130 sets the resistance value R to the set resistance value R obtained in step S20. SET The inductance value L is set, and the set inductance value L obtained in step S40 is used for the inductance value L. SET Set the initial resistance value R. INT A modification to set the initial inductance value R relative to the inductance value L. INT It is also possible to modify the settings. In particular, for example, in cases where the phase adjustment operation is performed without going through the adjustment operation for the resistive load, unlike the operation flow in Figure 19, the resistance value R is set to an initial resistance value R in step S61. INT If the initial inductance value L is set, and similarly the phase adjustment operation is performed without going through the adjustment operation for the inductive load, then in step S61 the inductance value L is set to the initial inductance value L INT This will be set.

[0098] In step S62 following step S61, the control circuit 130 performs the first adjustment unit operation and the ringing time T measured in the first adjustment unit operation R#B Ringing time T R#B [1] is obtained. Then, in step S63, the control circuit 130 sets the direction of change. In this case, if "FLG=0" (see Figure 13), the direction of change is set to the positive direction. However, even if "FLG=0", the phase φ[1] is the maximum phase φ MAX If it matches, or if the phase when the phase φ[1] is shifted in the positive direction by n steps is within the search range φ RNGIf it exceeds this value, a negative direction is set as the direction of change. If "FLG=1", the opposite of the direction of change indicated by direction data 131d_φ is set as the direction of change to be set in step S63 (the significance of this will become clear later).

[0099] After step S63, in step S64 the control circuit 130 assigns "1" to the variable i and then proceeds to step S65. In step S65, the control circuit 130 determines the phase φ[i+1] by shifting the phase φ[i] in n steps in the set direction of change, and sets the phase φ[i+1] to the phase φ of the adjustment damping signal. In step S66 following step S65, the control circuit 130 adds "1" to the variable i. In the subsequent step S67, the control circuit 130 executes the i-th adjustment unit operation and the ringing time T measured in the i-th adjustment unit operation is determined. R#B Ringing time T R#B [i] is obtained. In the following step S68, the control circuit 130 is given the inequality "T R#B [i] <T R#B Determine whether the inequality "T R#B [i] <T R#B If [i-1] is true, proceed to step S69; otherwise, proceed to step S71.

[0100] In step S69, the control circuit 130 determines whether any of the termination conditions are met. If any of the termination conditions are met in step S69, the process proceeds to step S70. If no termination conditions are met, the process returns to step S65 and the subsequent steps are repeated. In step S71, the control circuit 130 reverses the direction of change set in step S63. If step S71 is reached, the direction of change of the phase φ thereafter is the reversed direction of change. In step S72, following step S71, the control circuit 130 determines whether "i=2" is met. If "i=2" is met, the process proceeds from step S72 to step S74. If "i=2" is not met, the process proceeds from step S72 to step S73. In step S73, the control circuit 130 determines whether any of the termination conditions are met. If any of the termination conditions are met in step S73, the process proceeds to step S70. If no termination conditions are met, the process proceeds to step S74. In step S74, the control circuit 130 determines phase φ[i+1] by shifting phase φ[i] in the set direction of change (direction of change after reversal) by (2 × n) steps, and sets phase φ[i+1] to the phase φ of the adjustment braking signal. After step S74, the process returns to step S66.

[0101] In step S70, the control circuit 130 sets phase φ[i-1] or φ[i] according to the termination condition that was met in step S69 or S73. SET Determine (substitute) and set phase φ SET Setting data 131b_φ indicating the phase φ is stored in the memory circuit 131, and direction data 131d_φ corresponding to the phase φ is also stored in the memory circuit 131. If step S70 is reached without going through step S71, the stored direction data 131d_φ indicates the positive direction, and if step S70 is reached via step S71, the stored direction data 131d_φ indicates the negative direction. Upon completion of the processing in step S70, the phase adjustment operation is finished, and in the subsequent normal detection operation, the control circuit 130 checks that the phase φ of the main damping signal is the set phase φ in the setting data 131b_φ. SETThe drive circuit 111 is controlled via the gate driver 112 to have the first braking period P in Figure 11. A2 (Controls the length).

[0102] The termination conditions for the phase adjustment operation are the same as those for the adjustment operation for a resistive load, and the termination conditions described for the adjustment operation for a resistive load also apply to the phase adjustment operation. In this application, the resistance values ​​R, R[1], R[2], R[3], R[i-1], R[i], R[i+1] and R[i] described in the explanation of the adjustment operation for a resistive load are also applied. SET These are the phases φ, φ[1], φ[2], φ[3], φ[i-1], φ[i], φ[i+1], and φ, respectively. SET You can then read it as such, and replace steps S21 to S34 in the explanation of the adjustment operation for resistive loads with steps S61 to S74, respectively.

[0103] Thus, in the phase adjustment operation, the control circuit 130 performs the adjustment unit operation multiple times while switching the phase φ of the adjustment damping signal in multiple stages, thereby performing multiple ringing times T. R#B The multiple ringing times T obtained are acquired. R#B The minimum ringing time T among them R#B The control circuit 130 then identifies the minimum ringing time T among the first to Nφ candidate phases (see Figure 20). R#B The corresponding candidate phase is set to phase φ SET It can be defined as follows.

[0104] [Ringing time T] R#HOLD [Holding] The ringing data 131c to be saved in step S80 of Figure 19 is described below. The resistance value R of the resistive load 141 is set to the resistance value R. SET To match this, and to set the inductance value L of the inductive load 142, the inductance value L SET To match, and to set the phase φ of the adjustment braking signal to phase φ SET The state that matches this is called the optimized state. The ringing time T shown in ringing data 131c R#HOLDThis is the ringing time T obtained during the adjustment unit operation in the optimized state. R#B Therefore, if the adjustment operations in steps S20, S40, and S60 are performed in the order shown in Figure 19, the ringing time T will already be optimized by the time step S70 in Figure 29 is reached. R#B This is obtained. However, the ringing time T in the optimized state in step S80 is R#B It is also acceptable to obtain the following. In any case, the control circuit 130 will control the ringing time T R#HOLD The ringing data 131c that points to this is stored in the memory circuit 131 in step S80.

[0105] [Regarding the conditions for reopening] The restart conditions described in Figure 13 will now be explained. The optimized state during the adjustment operation may change to a state that is not optimal during normal detection operation due to subsequent temperature changes, etc. As an example of this change, Figure 30 shows the change from the dashed waveform 701 to the solid waveform 702. To address such changes, as mentioned above (see Figure 13), the ringing time T after the transition to normal detection operation is explained. R#A The ringing time T is measured and acquired for each detection unit operation, and the success or failure of the restart condition is determined in step S7 of Figure 13. In step S7, the control circuit 130 reads the latest ringing time T obtained in step S6. R#A Ringing time T in ringing data 131c R#HOLD Compared to the latest ringing time T R#A Ringing time T R#HOLD Rather than a predetermined time T TH2 When it is longer than this (i.e., “T R#A -T R#HOLD ≧T TH2 When the condition is met, determine that the restart condition is met.

[0106] If the restart condition is met, as already mentioned, the flag FLG is set to "1" in step S8, and then the process returns to step S2, where the adjustment operation is performed again. Through this repeated adjustment operation, the optimal resistance value R, inductance value L, and phase φ for the ultrasonic sensor 1 at this time are searched again, and after the search, the system returns to a state that is advantageous for reducing reverberation time.

[0107] As mentioned above, the adjustment operation for resistive loads may also end when the third termination condition shown in Figure 27 is met. In this case, when the restart condition is met and the second adjustment operation is performed, the direction of change is set to the opposite direction to when the first adjustment operation ended, and the set resistance value R SET It is preferable to search for the appropriate resistance value R that should result in this. Taking this into consideration, in the adjustment operation for resistive loads, in step S30 (see Figure 21), direction data 131d_R indicating the direction of change at that time is stored, and in the adjustment operation for resistive loads that is performed again, the direction of change is set by referring to the direction data 131d_R (step S23). The same applies to the adjustment operation for inductive loads and the adjustment operation for phase.

[0108] <<Second Example>> A second embodiment will be described. In the first embodiment, the resistance value R, inductance value L, and phase φ are the first, second, and third adjustment targets, and the set resistance value R for the first to third adjustment targets is... SET , set inductance value L SET and setting phase φ SET While all of these are determined, it is also possible to adjust only one or two of the resistance value R, inductance value L, and phase φ. That is, the control circuit 130 may perform only one or two of the adjustment operations for resistive loads, inductive loads, and phases. For example, if the appropriate resistance value R for reducing reverberation time (reducing ringing time) is known in advance, it is possible to not perform the adjustment operation for resistive loads.

[0109] <<Third Example>> A third embodiment will be described. In the third embodiment, application techniques, modification techniques, and supplementary information for each of the above-described techniques will be explained.

[0110] The ultrasonic sensor 1 can be mounted on any device. For example, as shown in Figure 31, one or more ultrasonic sensors 1 may be installed on a vehicle CR such as an automobile. In the example in Figure 31, four ultrasonic sensors 1 are installed on the rear of the vehicle CR, and distance detection processing and proximity detection processing can be performed on an object that may be located at the rear of the vehicle CR (example of the detection target object OBJ in Figure 1). In this case, the upper block 2 may be an ECU (Electronic Control Unit) mounted on the vehicle CR.

[0111] Although a drive circuit 111 consisting of a full-bridge circuit is shown as a drive circuit for converting the main drive signal to the piezoelectric element 20, a drive circuit using a transformer may also be constructed. The configuration and operation of a drive circuit using a transformer are well known, so an explanation is omitted here.

[0112] With respect to any signal or voltage, the relationship between their high and low levels can be the reverse of that described above, without compromising the main point stated above.

[0113] The channel types of FETs (field-effect transistors) shown in each embodiment are illustrative, and the configuration of the circuit including the FETs can be modified so that an N-channel FET is changed to a P-channel FET, or a P-channel FET is changed to an N-channel FET.

[0114] As long as no inconvenience arises, any transistor described above may be any type of transistor. For example, any transistor described above as a MOSFET can be replaced with a junction FET, an IGBT (Insulated Gate Bipolar Transistor), or a bipolar transistor, as long as no inconvenience arises. Any transistor has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is the drain and the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector and the other is the emitter, and the control electrode is the gate. In a bipolar transistor that does not belong to the IGBT category, one of the first and second electrodes is the collector and the other is the emitter, and the control electrode is the base.

[0115] The embodiments of this disclosure can be modified in various ways as appropriate within the scope of the technical idea set forth in the claims. The embodiments described above are merely examples of embodiments of this disclosure, and the meaning of the terms in this disclosure or each constituent element is not limited to those described above. The specific numerical values ​​given in the above description are merely examples and can, of course, be changed to various numerical values.

[0116] <<Note>> A note is provided regarding this disclosure in which specific configuration examples are shown in the embodiments described above.

[0117] A semiconductor device (10; see Figure 3) relating to one aspect of the present disclosure comprises a drive circuit (111) configured to supply an ultrasonic drive signal to a piezoelectric element (20), a damping circuit (140) having a resistive load (141) and an inductive load (142), and a control circuit (130) capable of controlling the drive circuit and capable of performing a reverberation reduction operation after the supply of the drive signal to the piezoelectric element is stopped, wherein the control circuit is configured to connect to the piezoelectric element after the drive circuit supplies a damping signal having a phase different from the phase of the drive signal to the piezoelectric element in the reverberation reduction operation (first configuration).

[0118] By supplying a damping signal with a phase different from the drive signal to the piezoelectric element after the supply of the drive signal to the piezoelectric element has been stopped, the reverberation of the piezoelectric element can be reduced. The damping signal is effective in reducing reverberation in regions where the amplitude of reverberation (amplitude of the piezoelectric element due to reverberation) is high, but as the amplitude of reverberation decreases, the damping signal itself may become a new source of reverberation. On the other hand, reverberation can also be reduced by connecting a resistive load or inductive load to the piezoelectric element after the supply of the drive signal has been stopped, through the absorption of the mechanical energy of the piezoelectric element. Here, the inventors have found that resistive loads or inductive loads have a relatively high reverberation reduction effect when the amplitude of reverberation is small, but the reverberation reduction effect is relatively low when the amplitude of reverberation is large due to circuit voltage constraints, etc. By performing the above reverberation reduction operation based on this finding, it is possible to reduce reverberation quickly (i.e., the reverberation time can be kept low).

[0119] In the semiconductor device according to the first configuration, the device further comprises an adjustment drive circuit (170) configured to supply a second drive signal in the ultrasonic band to the piezoelectric element, in addition to the first drive signal which is the drive signal, wherein the control circuit is configured to perform an adjustment operation using the adjustment drive circuit before a normal detection operation which includes supplying the first drive signal to the piezoelectric element, the adjustment operation determines a set physical quantity for the adjustment target based on the reverberation state of the piezoelectric element after the second drive signal is supplied to the piezoelectric element, and the normal detection operation provides the adjustment target with the set physical quantity, and the adjustment target may be configured to include at least one of the resistance value of the resistive load, the inductance value of the inductive load, and the phase of the damping signal (second configuration).

[0120] This allows the adjustment target to have a set physical quantity (a set physical quantity appropriate for reducing reverberation) that reflects individual differences in piezoelectric elements or ambient temperature, thereby enabling a rapid reduction of reverberation.

[0121] In the semiconductor device according to the second configuration, the adjustment drive circuit is configured to supply to the piezoelectric element a second braking signal having a different phase from the second drive signal, in addition to the first braking signal which is the braking signal, and the adjustment operation includes an adjustment unit operation (see Figure 15). The control circuit, in the adjustment unit operation, supplies the second drive signal to the piezoelectric element, stops supplying the second drive signal, then supplies the second braking signal to the piezoelectric element from the adjustment drive circuit, and then connects the damping circuit to the piezoelectric element. The adjustment operation can be performed multiple times, switching the adjustment target in multiple stages, and the set physical quantity may be determined based on the reverberation state of the piezoelectric element when the damping circuit is connected to the piezoelectric element in each adjustment unit operation (third configuration).

[0122] In a semiconductor device relating to any of the third configurations (see Figures 11 to 13), a receiving circuit (120) configured to receive the ultrasonic band signal is further provided, the normal detection operation includes one or more detection unit operations, in each detection unit operation, the reverberation reduction operation is performed after the supply of the first drive signal to the piezoelectric element and after the supply of the first drive signal is stopped, and the control circuit sets the time from when the damping circuit is connected to the piezoelectric element until the voltage value proportional to the amplitude of the received signal of the receiving circuit falls below a predetermined threshold to be the ringing time (T R#A , T R#B ) is detected as, and in the adjustment operation, the ringing time (T) when the target to be set has the set physical quantity is detected. R#HOLD The system may also be configured (fourth configuration) in which the adjustment operation is acquired and held, and after the adjustment operation is performed and the normal detection operation is started, the adjustment operation can be performed again when the relationship between the ringing time detected in the normal detection operation and the held ringing time satisfies a predetermined restart condition (see S7 in Figure 13).

[0123] This allows for further adjustment when the ringing time increases due to changes in ambient temperature or other factors after the normal detection operation has started, enabling the adjustment target to be adjusted to the current situation.

[0124] In a semiconductor device relating to the third or fourth configuration, the control circuit is capable of performing the adjustment unit operation multiple times while switching the resistance value of the resistive load in multiple stages during the adjustment operation, and in each adjustment unit operation, based on the reverberation state of the piezoelectric element when the damping circuit is connected to the piezoelectric element, a set resistance value (R) for the resistive load is set. SET The configuration may be such that the set resistance value is determined and the resistive load has the set resistance value in the normal detection operation (fifth configuration).

[0125] In the semiconductor device relating to the third to fifth configurations, the control circuit is capable of performing the adjustment unit operation multiple times while switching the inductance value of the inductive load in multiple stages during the adjustment operation, and in each adjustment unit operation, based on the reverberation state of the piezoelectric element when the damping circuit is connected to the piezoelectric element, the set inductance value (L) for the inductive load is determined. SET The configuration may be such that the inductive load has the set inductance value in the normal detection operation (sixth configuration).

[0126] In a semiconductor device relating to any of the third to sixth configurations, the control circuit is capable of performing the adjustment unit operation multiple times while switching the phase of the second damping signal as seen from the second drive signal in multiple stages during the adjustment operation, and in each adjustment unit operation, the set phase (φ) relative to the first damping signal is determined based on the reverberation state of the piezoelectric element when the damping circuit is connected to the piezoelectric element. SET The configuration may be such that the first braking signal has the set phase in the normal detection operation (seventh configuration).

[0127] In a semiconductor device relating to any of the second to seventh configurations, the amplitude of the second drive signal may be smaller than the amplitude of the first drive signal (eighth configuration).

[0128] If an adjustment operation is performed using a drive signal having the same amplitude as that of the first drive signal, the signal component of reflected waves from the surroundings and the signal component of reverberation may mix, which may make it difficult to perform a favorable adjustment operation. By performing the adjustment operation using a second drive signal having an amplitude smaller than that of the first drive signal, the reflected waves during the adjustment operation can be sufficiently reduced, thereby enabling a favorable adjustment operation to be achieved.

[0129] In the semiconductor device according to any one of the first to eighth configurations, the damping circuit may have a configuration (ninth configuration) in which the resistive load and the inductive load are connected in parallel.

[0130] In the semiconductor device according to any one of the first to ninth configurations, the drive circuit includes a first half-bridge circuit to be connected to a first end of the piezoelectric element, and a second half-bridge circuit to be connected to a second end of the piezoelectric element, and may have a configuration (tenth configuration) configured to be capable of supplying a rectangular wave signal as the first drive signal between the first end and the second end of the piezoelectric element using the first half-bridge circuit and the second half-bridge circuit.

[0131] An ultrasonic sensor according to one aspect of the present disclosure has a configuration (eleventh configuration) including the semiconductor device according to any one of the first to tenth configurations, and a piezoelectric element connected to the semiconductor device. Description of Reference Signs

[0132] 1 Ultrasonic sensor 2 Upper-level block 10 Semiconductor device 11 Transmission circuit 12 Reception circuit 13 Control circuit 20 Piezoelectric element W1 Output wave signal W2 Reflected wave signal 111 Drive circuit 112 Gate driver 120 Reception circuit 130 Control circuit 140 Damping Circuit 141 Resistive load 142 Inductive load 150 Switch Circuits 160 Switch Circuits 170 Adjustment drive circuit 180 Internal power supply circuit

Claims

1. A drive circuit configured to supply a first drive signal in the ultrasonic band to a piezoelectric element, A damping circuit having a resistive load and an inductive load, A control circuit capable of controlling the drive circuit and configured to perform reverberation reduction operation after the supply of the first drive signal to the piezoelectric element is stopped, The circuit comprises an adjustment drive circuit configured to supply a second drive signal in the ultrasonic band to the piezoelectric element, separate from the first drive signal, The control circuit is configured to connect to the piezoelectric element after supplying a first damping signal having a phase different from the phase of the first drive signal from the drive circuit to the piezoelectric element during the reverberation reduction operation. The control circuit is configured to perform an adjustment operation using the adjustment drive circuit before a normal detection operation, which includes supplying a first drive signal to the piezoelectric element. In the adjustment operation, a set physical quantity for the object to be adjusted is determined based on the reverberation state of the piezoelectric element after supplying a second drive signal to the piezoelectric element. In the normal detection operation, the object to be adjusted is given the set physical quantity. The adjustment target includes at least one of the resistance value of the resistive load, the inductance value of the inductive load, and the phase of the first damping signal. The adjustment drive circuit is configured to supply a second braking signal to the piezoelectric element, which has a different phase from the second drive signal, in addition to the first braking signal. The adjustment operation includes adjustment unit operation, The aforementioned control circuit is In the adjustment unit operation, after supplying the second drive signal to the piezoelectric element and then stopping the supply of the second drive signal, the second braking signal is supplied to the piezoelectric element from the adjustment drive circuit, and thereafter the damping circuit is connected to the piezoelectric element. In the adjustment operation, the adjustment unit operation can be performed multiple times while switching the adjustment target in multiple stages, and the set physical quantity is determined based on the reverberation state of the piezoelectric element when the damping circuit is connected to the piezoelectric element in each adjustment unit operation. Semiconductor equipment.

2. The receiving circuit further comprises a receiving circuit configured to receive the aforementioned ultrasonic band signals, The aforementioned normal detection operation includes one or more detection unit operations. In each detection unit operation, the reverberation reduction operation is performed after the supply of the first drive signal to the piezoelectric element has been stopped and the supply of the first drive signal has been stopped. The aforementioned control circuit is In each adjustment unit operation in the adjustment operation and in each detection unit operation in the normal detection operation, the time from when the damping circuit is connected to the piezoelectric element until the voltage value proportional to the amplitude of the received signal of the receiving circuit falls below a predetermined threshold is detected as the ringing time. In the adjustment operation, the ringing time when the object to be adjusted has the set physical quantity is acquired and held, After the adjustment operation has been performed and the normal detection operation has started, the adjustment operation can be made to run again when the relationship between the ringing time detected by the normal detection operation and the retained ringing time satisfies a predetermined restart condition. The semiconductor device according to claim 1.

3. The control circuit is capable of performing the adjustment unit operation multiple times while switching the resistance value of the resistive load in multiple stages during the adjustment operation, and in each adjustment unit operation, it determines a set resistance value for the resistive load based on the reverberation state of the piezoelectric element when the damping circuit is connected to the piezoelectric element, and in the normal detection operation, it gives the resistive load the set resistance value. The semiconductor device according to claim 1 or 2.

4. The control circuit is capable of performing the adjustment unit operation multiple times while switching the inductance value of the inductive load in multiple stages during the adjustment operation, and in each adjustment unit operation, it determines the set inductance value for the inductive load based on the reverberation state of the piezoelectric element when the damping circuit is connected to the piezoelectric element, and in the normal detection operation, it gives the inductive load the set inductance value. or semiconductor device according to any one of claims 1 to 3.

5. The control circuit is capable of executing the adjustment unit operation multiple times while switching the phase of the second damping signal as seen from the second drive signal in multiple stages during the adjustment operation, and in each adjustment unit operation, it determines the set phase for the first damping signal based on the reverberation state of the piezoelectric element when the damping circuit is connected to the piezoelectric element, and in the normal detection operation, it gives the first damping signal the set phase. or semiconductor device according to any one of claims 1 to 4.

6. The amplitude of the second drive signal is smaller than the amplitude of the first drive signal. , the semiconductor device according to any one of claims 1 to 5.

7. In the damping circuit, the resistive load and the inductive load are connected in parallel. , the semiconductor device according to any one of claims 1 to 6.

8. The drive circuit comprises a first half-bridge circuit to be connected to the first end of the piezoelectric element and a second half-bridge circuit to be connected to the second end of the piezoelectric element, and is configured to supply a square wave signal as the first drive signal between the first and second ends of the piezoelectric element using the first and second half-bridge circuits. , the semiconductor device according to any one of claims 1 to 7.

9. A semiconductor device according to any one of Claims 1 to 8, The semiconductor device is equipped with a piezoelectric element connected to the semiconductor device. Ultrasonic sensor.

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