Gate driver

Abstract

A gate driver 401 comprises: a gate driving circuit 410 configured to generate a gate driving signal G1 for a power element 402 in response to a gate control signal S1; and a driving performance switching circuit 420 configured to enhance the gate driving performance of the gate driving circuit 410 when a time change amount signal S21 obtained by passing the gate driving signal G1 during an on-transition period of the power element 402 through a high-pass filter 421, becomes smaller than a threshold value REF.

Description

Technical Field

[0001] The invention disclosed in the present specification relates to a gate driver. Background Art

[0002] Conventionally, gate drivers that drive power elements such as MOSFETs [metal oxide semiconductor field effect transistors] or IGBTs [insulated gate bipolar transistors] have been used in various applications.

[0003] As an example of the related prior art mentioned above, Patent Document 1 can be cited. Prior Art Documents Patent Documents

[0004] Patent Document 1 Japanese Unexamined Patent Application Publication No. 2021-010258 Summary of the Invention Problem to be Solved by the Invention

[0005] However, in conventional gate drivers, there has been a trade-off: if the turn-on speed of the gate of the power element is too fast, this causes surges and noise, while conversely, if the speed is too slow, switching loss increases.

[0006] In view of the above problem discovered by the inventor of the present application, an object of the invention disclosed in the present specification is to provide a gate driver that can achieve both reduction of surges and noise and suppression of switching loss. Means for Solving the Problem

[0007] For example, a gate driver disclosed herein includes a gate drive circuit configured to generate a gate drive signal for a power element in response to a gate control signal, and a drive capability switching circuit configured to increase the gate drive capability of the gate drive circuit when the time change signal obtained by passing the gate drive signal during the on-transition period of the power element through a high-pass filter becomes smaller than a threshold.

[0008] Further details regarding other features, elements, steps, advantages, and characteristics will become clearer from the embodiments for carrying out the invention and the accompanying drawings. [Effects of the Invention]

[0009] The inventions disclosed herein make it possible to provide a gate driver that can achieve both surge and noise reduction and suppression of switching losses. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 shows the basic configuration of a signal transmission device. [Figure 2] Figure 2 shows the basic structure of a transformer chip. [Figure 3] Figure 3 is a perspective view of a semiconductor device used as a 2-channel transformer chip. [Figure 4] Figure 4 is a plan view of the semiconductor device shown in Figure 3. [Figure 5] Figure 5 is a plan view showing the layer in the semiconductor device of Figure 3 where the low-potential coil is formed. [Figure 6] Figure 6 is a plan view showing the layer in the semiconductor device of Figure 3 where the high-potential coil is formed. [Figure 7] Figure 7 is a cross-sectional view along the line VIII-VIII shown in Figure 6. [Figure 8] Figure 8 is a cross-sectional view along the IX-IX line shown in Figure 6. [Figure 9]Figure 9 is an enlarged view of region X shown in Figure 6. [Figure 10] Figure 10 is an enlarged view of region XI shown in Figure 6. [Figure 11] Figure 11 is an enlarged view of region XII shown in Figure 6. [Figure 12] Figure 12 is a diagram showing an enlarged view (separation structure) of region XIII shown in Figure 7. [Figure 13] Figure 13 is a diagram schematically showing an example of a transformer chip layout. [Figure 14] Figure 14 is a diagram showing a first embodiment (comparative example) of a gate driver. [Figure 15] Figure 15 is a diagram showing a gate driving operation in the first embodiment (comparative example). [Figure 16] Figure 16 is a diagram showing a second embodiment of a gate driver. [Figure 17] Figure 17 is a diagram showing a gate driving operation in the second embodiment. [Figure 18] Figure 18 is a diagram showing one configuration example of a high-pass filter. [Figure 19] Figure 19 is a diagram showing one configuration example of a gate drive circuit. [Figure 20] Figure 20 is a diagram showing one configuration example of a first gate drive unit and a second gate drive unit. [Figure 21] Figure 21 is a diagram showing the difference between a constant current driving method and a voltage driving method. DETAILED DESCRIPTION OF THE INVENTION

[0011] <Signal Transmission Device (Basic Configuration)> Figure 1 shows the basic configuration of a signal transmission device. The signal transmission device 200 in this example configuration is a semiconductor integrated circuit device (a so-called isolated gate driver IC) that transmits pulse signals from the primary circuit system 200p to the secondary circuit system 200s while insulating the primary circuit system 200p (VCC1-GND1 system) and the secondary circuit system 200s (VCC2-GND2 system), and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 consists of a controller chip 210, a driver chip 220, and a transformer chip 230, all packaged together.

[0012] The controller chip 210 is a semiconductor chip that operates on a power supply voltage VCC1 (for example, up to 7V relative to GND1). The controller chip 210 integrates, for example, a pulse transmission circuit 211 and buffers 212 and 213.

[0013] The pulse transmission circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 in response to the input pulse signal IN. More specifically, when the pulse transmission circuit 211 indicates that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal S11 (outputting a single or multiple transmission pulses), and when it indicates that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal S21. In other words, the pulse transmission circuit 211 pulse-drives either the transmission pulse signal S11 or S21 depending on the logic level of the input pulse signal IN.

[0014] The buffer 212 receives the input of the transmitted pulse signal S11 from the pulse transmission circuit 211 and pulses the transformer chip 230 (specifically the transformer 231).

[0015] The buffer 213 receives the input of the transmitted pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically the transformer 232).

[0016] The driver chip 220 is a semiconductor chip that operates on a power supply voltage VCC2 (for example, up to 30V relative to GND2). The driver chip 220 integrates, for example, buffers 221 and 222, a pulse receiving circuit 223, and a driver 224.

[0017] Buffer 221 shapes the waveform of the received pulse signal S12 induced in the transformer chip 230 (specifically the transformer 231) and outputs it to the pulse receiving circuit 223.

[0018] Buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically the transformer 232) and outputs it to the pulse receiving circuit 223.

[0019] The pulse receiving circuit 223 generates an output pulse signal OUT by driving a driver 224 in response to received pulse signals S12 and S22 input via buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 to raise the output pulse signal OUT to a high level in response to the pulse drive of the received pulse signal S12, and to lower the output pulse signal OUT to a low level in response to the pulse drive of the received pulse signal S22. In other words, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT according to the logic level of the input pulse signal IN. For example, an RS flip-flop can be suitably used as the pulse receiving circuit 223.

[0020] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223.

[0021] The transformer chip 230 uses transformers 231 and 232 to DC-isolate the controller chip 210 and the driver chip 220, and outputs the transmitted pulse signals S11 and S21 input from the pulse transmitting circuit 211 as received pulse signals S12 and S22, respectively, to the pulse receiving circuit 223. In this specification, "DC-isolated" means that the objects to be isolated are not connected by a conductor.

[0022] More specifically, transformer 231 outputs a received pulse signal S12 from its secondary coil 231s in response to a transmitted pulse signal S11 input to its primary coil 231p. On the other hand, transformer 232 outputs a received pulse signal S22 from its secondary coil 232s in response to a transmitted pulse signal S21 input to its primary coil 232p.

[0023] Thus, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to the rise signal and fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0024] In this example, the signal transmission device 200 has a separate transformer chip 230 containing only transformers 231 and 232, in addition to the controller chip 210 and driver chip 220, and these three chips are sealed in a single package.

[0025] With this configuration, both the controller chip 210 and the driver chip 220 can be formed using a general low-to-medium voltage process (several volts to tens of volts), eliminating the need to use a dedicated high-voltage process (several kV voltage), and thus reducing manufacturing costs.

[0026] The signal transmission device 200 can be suitably used, for example, in a power supply unit or motor drive unit for in-vehicle equipment mounted on a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (xEVs such as BEV [battery electric vehicle], HEV [hybrid electric vehicle], PHEV / PHV (plug-in hybrid electric vehicle / plug-in hybrid vehicle], or FCEV / FCV (fuel cell electric vehicle / fuel cell vehicle)).

[0027] <Trans-chip (basic structure)> Next, the basic structure of the transformer chip 230 will be described. Figure 2 shows the basic structure of the transformer chip 230. In the transformer chip 230 shown in this figure, the transformer 231 includes a primary coil 231p and a secondary coil 231s that are opposed to each other in the vertical direction. The transformer 232 includes a primary coil 232p and a secondary coil 232s that are opposed to each other in the vertical direction.

[0028] The primary coils 231p and 232p are both formed in the first wiring layer (lower layer) 230a of the transformer chip 230. The secondary coils 231s and 232s are both formed in the second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is positioned directly above the primary coil 231p and faces it. Similarly, the secondary coil 232s is positioned directly above the primary coil 232p and faces it.

[0029] The primary coil 231p is laid in a spiral pattern, starting from its first end connected to internal terminal X21 and surrounding internal terminal X21 in a clockwise direction, with its second end, corresponding to its endpoint, connected to internal terminal X22. On the other hand, the primary coil 232p is laid in a spiral pattern, starting from its first end connected to internal terminal X23 and surrounding internal terminal X23 in a counterclockwise direction, with its second end, corresponding to its endpoint, connected to internal terminal X22. Internal terminals X21, X22, and X23 are arranged linearly in the order shown in the figure.

[0030] Internal terminal X21 is connected to external terminal T21 of the second layer 230b via conductive wiring Y21 and via Z21. Internal terminal X22 is connected to external terminal T22 of the second layer 230b via conductive wiring Y22 and via Z22. Internal terminal X23 is connected to external terminal T23 of the second layer 230b via conductive wiring Y23 and via Z23. External terminals T21 to T23 are arranged in a straight line and are used for wire bonding to the controller chip 210.

[0031] The secondary coil 231s is laid in a spiral pattern, starting from its first end connected to the external terminal T24 and surrounding the external terminal T24 in a counterclockwise direction, with its second end, corresponding to its endpoint, connected to the external terminal T25. On the other hand, the secondary coil 232s is laid in a spiral pattern, starting from its first end connected to the external terminal T26 and surrounding the external terminal T26 in a clockwise direction, with its second end, corresponding to its endpoint, connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure and are used for wire bonding with the driver tip 220.

[0032] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, respectively, and are DC-isolated from the primary coils 231p and 232p. In other words, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-isolated from the controller chip 210 by the transformer chip 230.

[0033] <Trans-chip (2-channel type)> Figure 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. Figure 4 is a plan view of the semiconductor device 5 shown in Figure 3. Figure 5 is a plan view showing the layer in the semiconductor device 5 shown in Figure 3 where the low-potential coil 22 (corresponding to the primary coil of the transformer) is formed. Figure 6 is a plan view showing the layer in the semiconductor device 5 shown in Figure 3 where the high-potential coil 23 (corresponding to the secondary coil of the transformer) is formed. Figure 7 is a cross-sectional view along the line VIII-VIII shown in Figure 6. Figure 8 is a cross-sectional view along the line IX-IX shown in Figure 6. Figure 9 is an enlarged view of region X shown in Figure 6. Figure 10 is an enlarged view of region XI shown in Figure 6. Figure 11 is an enlarged view of region XII shown in Figure 6. Figure 12 is an enlarged view of region XIII shown in Figure 7, showing the separation structure 130.

[0034] Referring to Figures 3 to 7, the semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. The semiconductor chip 41 includes at least one of silicon, a wide-bandgap semiconductor, and a compound semiconductor.

[0035] Wide-bandgap semiconductors consist of semiconductors with a bandgap exceeding that of silicon (approximately 1.12 eV). The bandgap of a wide-bandgap semiconductor is preferably 2.0 eV or greater. The wide-bandgap semiconductor may be SiC (silicon carbide). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may contain at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0036] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may also be an epitaxial substrate having a laminated structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0037] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a rectangular shape (in this form, a rectangular shape) when viewed in a plan view from their normal direction Z (hereinafter simply referred to as "plan view").

[0038] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long side of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along a first direction X and face a second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short side of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in a second direction Y and face a first direction X. The chip sidewalls 44A to 44D consist of a ground surface.

[0039] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating side walls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that aligns with the first main surface 42 in a plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0040] The insulating sidewalls 53A to 53D include the first insulating sidewall 53A, the second insulating sidewall 53B, the third insulating sidewall 53C, and the fourth insulating sidewall 53D. The insulating sidewalls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are connected to the chip sidewalls 44A to 44D. Specifically, the insulating sidewalls 53A to 53D are formed flush with the chip sidewalls 44A to 44D. The insulating sidewalls 53A to 53D form a ground surface that is flush with the chip sidewalls 44A to 44D.

[0041] The insulating layer 51 consists of a multilayer insulating laminate structure including a bottom insulating layer 55, an upper insulating layer 56, and a plurality (11 layers in this embodiment) of interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The upper insulating layer 56 is an insulating layer that forms the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the upper insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the upper insulating layer 56 has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the thickness of the upper insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

[0042] Each of the multiple interlayer insulating layers 57 has a laminated structure including a first insulating layer 58 on the bottom insulating layer 55 side and a second insulating layer 59 on the top insulating layer 56 side. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, about 0.3 μm).

[0043] The second insulating layer 59 is formed on the first insulating layer 58. It contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, about 2 μm). Preferably, the thickness of the second insulating layer 59 exceeds the thickness of the first insulating layer 58.

[0044] The total thickness DT of the insulating layer 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layer 51 and the number of layers of the interlayer insulating layer 57 are arbitrary and are adjusted according to the dielectric strength (dielectric breakdown voltage) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layer 57 are arbitrary and are not limited to any specific insulating material.

[0045] The semiconductor device 5 includes a first functional device 45 formed on the insulating layer 51. The first functional device 45 includes one or more (in this embodiment, more) transformers 21 (corresponding to the transformers mentioned earlier). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed in the inner part of the insulating layer 51, spaced apart from the insulating side walls 53A to 53D. The multiple transformers 21 are formed spaced apart in the first direction X.

[0046] The multiple transformers 21 specifically include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating sidewall 53C to the insulating sidewall 53D in a plan view. The multiple transformers 21A to 21D each have a similar structure. The structure of the first transformer 21A will be used as an example below. The explanation of the structures of the second transformer 21B, the third transformer 21C, and the fourth transformer 21D will be omitted, as the explanation of the structure of the first transformer 21A will be applied mutatis mutandis.

[0047] Referring to Figures 5 to 8, the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed within the insulating layer 51. The high-potential coil 23 is formed within the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in the region sandwiched between the bottom insulating layer 55 and the top insulating layer 56 (i.e., multiple interlayer insulating layers 57).

[0048] The low-potential coil 22 is formed within the insulating layer 51 on the side of the bottom insulating layer 55 (semiconductor chip 41), and the high-potential coil 23 is formed within the insulating layer 51 on the side of the top insulating layer 56 (main insulating surface 52) relative to the low-potential coil 22. In other words, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 in between. The placement of the low-potential coil 22 and the high-potential coil 23 is arbitrary. Furthermore, the high-potential coil 23 only needs to face the low-potential coil 22 with one or more interlayer insulating layers 57 in between.

[0049] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of interlayer insulating layer 57) is appropriately adjusted according to the dielectric breakdown voltage and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this configuration, the low-potential coil 22 is formed in the third interlayer insulating layer 57 counting from the bottom insulating layer 55. In this configuration, the high-potential coil 23 is formed in the first interlayer insulating layer 57 counting from the top insulating layer 56.

[0050] The low-potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first helical portion 26 that is spirally routed between the first inner end 24 and the first outer end 25. The first helical portion 26 is spirally routed in an elliptical (long oval) shape in plan view. The portion forming the innermost periphery of the first helical portion 26 defines an elliptical first inner region 66 in plan view.

[0051] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the first helical portion 26 is 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in the direction perpendicular to the helical direction. The first turn pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. Preferably, the first turn pitch is 1 μm or more and 3 μm or less. The first turn pitch is defined by the distance between two adjacent portions in the first helical portion 26 in the direction perpendicular to the helical direction.

[0052] The winding shape of the first helical portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the forms shown in Figure 5, etc. The first helical portion 26 may be wound in a polygonal shape such as a triangle or a square, or in a circular shape in a plan view. The first inner region 66 may be divided into a polygonal shape such as a triangle or a square, or in a circular shape in a plan view, depending on the winding shape of the first helical portion 26.

[0053] The low-potential coil 22 may contain at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a laminated structure including a barrier layer and a main body layer. The barrier layer partitions a recess space within the interlayer insulating layer 57. The main body layer is embedded in the recess space partitioned by the barrier layer. The barrier layer may contain at least one of titanium and titanium nitride. The main body layer may contain at least one of copper, aluminum, and tungsten.

[0054] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second helical portion 29 that is spirally routed between the second inner end 27 and the second outer end 28. The second helical portion 29 is spirally routed in an elliptical (oval) shape in plan view. In this embodiment, the portion forming the innermost periphery of the second helical portion 29 defines an elliptical second inner region 67 in plan view. The second inner region 67 of the second helical portion 29 faces the first inner region 66 of the first helical portion 26 in the normal direction Z.

[0055] The number of turns of the second helical section 29 may be between 5 and 30. The number of turns of the second helical section 29 relative to the number of turns of the first helical section 26 is adjusted according to the voltage value to be boosted. It is preferable that the number of turns of the second helical section 29 exceeds the number of turns of the first helical section 26. Of course, the number of turns of the second helical section 29 may be less than the number of turns of the first helical section 26, or it may be equal to the number of turns of the first helical section 26.

[0056] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the second helical portion 29 is 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in the direction perpendicular to the helical direction. Preferably, the width of the second helical portion 29 is equal to the width of the first helical portion 26.

[0057] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. Preferably, the second winding pitch is 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions in the second helical portion 29 in a direction perpendicular to the helical direction. Preferably, the second winding pitch is equal to the first winding pitch of the first helical portion 26.

[0058] The winding shape of the second helical portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the forms shown in Figure 6, etc. The second helical portion 29 may be wound in a polygonal shape such as a triangle or a square, or in a circular shape in a plan view. The second inner region 67 may be divided into a polygonal shape such as a triangle or a square, or in a circular shape in a plan view, depending on the winding shape of the second helical portion 29.

[0059] It is preferable that the high-potential coil 23 is formed from the same conductive material as the low-potential coil 22. In other words, it is preferable that the high-potential coil 23 includes a barrier layer and a main body layer, similar to the low-potential coil 22.

[0060] Referring to Figure 4, the semiconductor device 5 includes a plurality (12 in this figure) of low-potential terminals 11 and a plurality (12 in this figure) of high-potential terminals 12. The plurality of low-potential terminals 11 are electrically connected to the low-potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high-potential terminals 12 are electrically connected to the high-potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0061] Multiple low-potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the multiple low-potential terminals 11 are formed in the region on the insulating side wall 53B side, spaced apart in the second direction Y from the multiple transformers 21A to 21D, and are arranged with spacing in the first direction X.

[0062] The multiple low-potential terminals 11 include a first low-potential terminal 11A, a second low-potential terminal 11B, a third low-potential terminal 11C, a fourth low-potential terminal 11D, a fifth low-potential terminal 11E, and a sixth low-potential terminal 11F. In this configuration, two of each of the multiple low-potential terminals 11A to 11F are formed. The number of multiple low-potential terminals 11A to 11F is arbitrary.

[0063] The first low-potential terminal 11A faces the first transformer 21A in the second direction Y in a plan view. The second low-potential terminal 11B faces the second transformer 21B in the second direction Y in a plan view. The third low-potential terminal 11C faces the third transformer 21C in the second direction Y in a plan view. The fourth low-potential terminal 11D faces the fourth transformer 21D in the second direction Y in a plan view. The fifth low-potential terminal 11E is formed in the region between the first low-potential terminal 11A and the second low-potential terminal 11B in a plan view. The sixth low-potential terminal 11F is formed in the region between the third low-potential terminal 11C and the fourth low-potential terminal 11D in a plan view.

[0064] The first low-potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low-potential coil 22). The second low-potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low-potential coil 22). The third low-potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low-potential coil 22). The fourth low-potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low-potential coil 22).

[0065] The fifth low-potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low-potential coil 22) and the first outer end 25 of the second transformer 21B (low-potential coil 22). The sixth low-potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low-potential coil 22) and the first outer end 25 of the fourth transformer 21D (low-potential coil 22).

[0066] Multiple high-potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51, spaced apart from multiple low-potential terminals 11. Specifically, the multiple high-potential terminals 12 are formed in the region on the insulating side wall 53A side, spaced apart in the second direction Y from the multiple low-potential terminals 11, and are arranged with spacing in the first direction X.

[0067] Multiple high-potential terminals 12 are each formed in a region adjacent to the corresponding transformers 21A to 21D in a plan view. The proximity of the high-potential terminals 12 to the transformers 21A to 21D means that, in a plan view, the distance between the high-potential terminals 12 and the transformer 21 is less than the distance between the low-potential terminals 11 and the high-potential terminals 12.

[0068] Specifically, the multiple high-potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A to 21D in a plan view. More specifically, the multiple high-potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high-potential coil 23 and in the region between adjacent high-potential coils 23 in a plan view. As a result, the multiple high-potential terminals 12 are arranged in a line with the multiple transformers 21A to 21D in the first direction X in a plan view.

[0069] The multiple high-potential terminals 12 include a first high-potential terminal 12A, a second high-potential terminal 12B, a third high-potential terminal 12C, a fourth high-potential terminal 12D, a fifth high-potential terminal 12E, and a sixth high-potential terminal 12F. In this configuration, two of each of the multiple high-potential terminals 12A to 12F are formed. The number of multiple high-potential terminals 12A to 12F is arbitrary.

[0070] The first high-potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high-potential coil 23) in a plan view. The second high-potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high-potential coil 23) in a plan view. The third high-potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high-potential coil 23) in a plan view. The fourth high-potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high-potential coil 23) in a plan view. The fifth high-potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high-potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0071] The first high-potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high-potential coil 23). The second high-potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high-potential coil 23). The third high-potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high-potential coil 23). The fourth high-potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high-potential coil 23).

[0072] The fifth high-potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high-potential coil 23) and the second outer end 28 of the second transformer 21B (high-potential coil 23). The sixth high-potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high-potential coil 23) and the second outer end 28 of the fourth transformer 21D (high-potential coil 23).

[0073] Referring to Figures 5 to 8, the semiconductor device 5 includes a first low-potential wiring 31, a second low-potential wiring 32, a first high-potential wiring 33, and a second high-potential wiring 34, each formed within the insulating layer 51. In this embodiment, a plurality of first low-potential wirings 31, a plurality of second low-potential wirings 32, a plurality of first high-potential wirings 33, and a plurality of second high-potential wirings 34 are formed.

[0074] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. Furthermore, the first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this configuration, the first low-potential wiring 31 and the second low-potential wiring 32 fix all the low-potential coils 22 of transformers 21A to 21D to the same potential.

[0075] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. Furthermore, the first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this configuration, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of transformers 21A to 21D to the same potential.

[0076] Multiple first low-potential wirings 31 are electrically connected to the corresponding low-potential terminals 11A to 11D and the first inner ends 24 of the corresponding transformers 21A to 21D (low-potential coils 22), respectively. Multiple first low-potential wirings 31 have similar structures. Below, the structure of the first low-potential wiring 31 connected to the first low-potential terminal 11A and the first transformer 21A will be described as an example. For descriptions of the structures of other first low-potential wirings 31, the description of the structure of the first low-potential wiring 31 connected to the first transformer 21A will be applied mutatis mutandis, and the description will be omitted.

[0077] The first low-potential wiring 31 includes a through-wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (in this embodiment, multiple) pad plug electrodes 76, and one or more (in this embodiment, multiple) substrate plug electrodes 77.

[0078] It is preferable that the through-wiring 71, low-potential connection wiring 72, lead-out wiring 73, first connection plug electrode 74, second connection plug electrode 75, pad plug electrode 76, and substrate plug electrode 77 are each formed from the same conductive material as the low-potential coil 22, etc. In other words, it is preferable that the through-wiring 71, low-potential connection wiring 72, lead-out wiring 73, first connection plug electrode 74, second connection plug electrode 75, pad plug electrode 76, and substrate plug electrode 77 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0079] The through-wiring 71 penetrates multiple interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this configuration, the through-wiring 71 is formed in the region between the lowest insulating layer 55 and the uppermost insulating layer 56 in the insulating layer 51. The through-wiring 71 has an upper end on the side of the uppermost insulating layer 56 and a lower end on the side of the lowest insulating layer 55. The upper end of the through-wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through-wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0080] In this embodiment, the through-wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through-wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed from the same conductive material as the low-potential coil 22, etc. That is, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0081] The first electrode layer 78 forms the upper end of the through-wiring 71. The second electrode layer 79 forms the lower end of the through-wiring 71. The first electrode layer 78 is formed in an island shape and faces the low-potential terminal 11 (first low-potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0082] Multiple wiring plug electrodes 80 are embedded in multiple interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The multiple wiring plug electrodes 80 are stacked from the bottom insulating layer 55 to the top insulating layer 56 so as to be electrically connected to each other, and also electrically connect the first electrode layer 78 and the second electrode layer 79. Each of the multiple wiring plug electrodes 80 has a planar area less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0083] The number of stacked wiring plug electrodes 80 corresponds to the number of stacked interlayer insulating layers 57. In this configuration, six wiring plug electrodes 80 are embedded within each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded within each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 may be formed penetrating multiple interlayer insulating layers 57.

[0084] The low-potential connection wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) within the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connection wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. It is preferable that the low-potential connection wiring 72 has a planar area that exceeds the planar area of ​​the wiring plug electrode 80. The low-potential connection wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0085] The lead wire 73 is formed in the region between the semiconductor chip 41 and the through-wiring 71 within the interlayer insulating layer 57. In this embodiment, the lead wire 73 is formed in the first interlayer insulating layer 57 counting from the bottom insulating layer 55. The lead wire 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first and second ends. The first end of the lead wire 73 is located in the region between the semiconductor chip 41 and the lower end of the through-wiring 71. The second end of the lead wire 73 is located in the region between the semiconductor chip 41 and the low-potential connection wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip-like manner in the region between the first and second ends.

[0086] The first connecting plug electrode 74 is formed in the region between the through-wiring 71 and the lead-out wiring 73 within the interlayer insulating layer 57 and is electrically connected to the first ends of the through-wiring 71 and the lead-out wiring 73. The second connecting plug electrode 75 is formed in the region between the low-potential connecting wiring 72 and the lead-out wiring 73 within the interlayer insulating layer 57 and is electrically connected to the second ends of the low-potential connecting wiring 72 and the lead-out wiring 73.

[0087] Multiple pad plug electrodes 76 are formed in the region between the low-potential terminal 11 (first low-potential terminal 11A) and the through-wiring 71 within the uppermost insulating layer 56, and are electrically connected to the upper ends of the low-potential terminal 11 and the through-wiring 71, respectively. Multiple substrate plug electrodes 77 are formed in the region between the semiconductor chip 41 and the lead-out wiring 73 within the lowermost insulating layer 55. In this embodiment, the substrate plug electrodes 77 are formed in the region between the semiconductor chip 41 and the first end of the lead-out wiring 73, and are electrically connected to the first end of the semiconductor chip 41 and the lead-out wiring 73, respectively.

[0088] Referring to Figure 8, the multiple second low-potential wirings 32 are electrically connected to the corresponding low-potential terminals 11E, 11F, and the first outer ends 25 of the low-potential coils 22 of the corresponding transformers 21A to 21D, respectively. Each of the multiple second low-potential wirings 32 has a similar structure. Below, the structure of the second low-potential wiring 32 connected to the fifth low-potential terminal 11E and the first transformer 21A (second transformer 21B) will be described as an example. For descriptions of the structures of the other second low-potential wirings 32, the description of the structure of the second low-potential wiring 32 connected to the first transformer 21A (second transformer 21B) will be applied mutatis mutandis, and the descriptions will be omitted.

[0089] The second low-potential wiring 32, like the first low-potential wiring 31, includes through wiring 71, low-potential connection wiring 72, lead wiring 73, first connection plug electrode 74, second connection plug electrode 75, pad plug electrode 76, and substrate plug electrode 77. The second low-potential wiring 32 has the same structure as the first low-potential wiring 31, except that the low-potential connection wiring 72 is electrically connected to the first outer end 25 of the first transformer 21A (low-potential coil 22) and the first outer end 25 of the second transformer 21B (low-potential coil 22).

[0090] The low-potential connection wiring 72 of the second low-potential wiring 32 is formed around the low-potential coil 22 within the same interlayer insulating layer 57 as the low-potential coil 22. Specifically, the low-potential connection wiring 72 is formed in the region between two adjacent low-potential coils 22 in a plan view. The pad plug electrode 76 is formed in the region between the low-potential terminal 11 (fifth low-potential terminal 11E) and the low-potential connection wiring 72 within the uppermost insulating layer 56 and is electrically connected to the low-potential terminal 11 and the low-potential connection wiring 72.

[0091] Referring to Figure 7, the multiple first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 12A to 12D and the second inner ends 27 of the corresponding transformers 21A to 21D (high-potential coils 23), respectively. The multiple first high-potential wirings 33 each have a similar structure. Below, the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A will be described as an example. For descriptions of the structures of the other first high-potential wirings 33, the description of the structure of the first high-potential wiring 33 connected to the first transformer 21A will be applied mutatis mutandis, and the descriptions will be omitted.

[0092] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (in this embodiment, more) pad plug electrodes 82. Preferably, the high-potential connection wiring 81 and the pad plug electrodes 82 are formed of the same conductive material as the low-potential coil 22, etc. That is, preferably, the high-potential connection wiring 81 and the pad plug electrodes 82 include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0093] The high-potential connection wiring 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connection wiring 81 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The high-potential connection wiring 81 is electrically connected to the second inner end 27 of the high-potential coil 23. In a plan view, the high-potential connection wiring 81 is formed at a distance from the low-potential connection wiring 72 and does not face the low-potential connection wiring 72 in the normal direction Z. As a result, the insulation distance between the low-potential connection wiring 72 and the high-potential connection wiring 81 is increased, and the dielectric strength of the insulating layer 51 is enhanced.

[0094] Multiple pad plug electrodes 82 are formed within the uppermost insulating layer 56 in the region between the high-potential terminal 12 (first high-potential terminal 12A) and the high-potential connection wiring 81, and are electrically connected to the high-potential terminal 12 and the high-potential connection wiring 81, respectively. Each of the multiple pad plug electrodes 82 has a planar area less than the planar area of ​​the high-potential connection wiring 81 in a plan view.

[0095] Referring to Figure 8, the multiple second high-potential wirings 34 are electrically connected to the corresponding high-potential terminals 12E and 12F and the second outer ends 28 of the corresponding transformers 21A to 21D (high-potential coils 23), respectively. Each of the multiple second high-potential wirings 34 has a similar structure. Below, the structure of the second high-potential wiring 34 connected to the fifth high-potential terminal 12E and the first transformer 21A (second transformer 21B) will be described as an example. For descriptions of the structures of other second high-potential wirings 34, the description of the structure of the second high-potential wiring 34 connected to the first transformer 21A (second transformer 21B) will be applied mutatis mutandis, and the descriptions will be omitted.

[0096] The second high-potential wiring 34 includes a high-potential connection wiring 81 and a pad plug electrode 82, similar to the first high-potential wiring 33. The second high-potential wiring 34 has the same structure as the first high-potential wiring 33, except that the high-potential connection wiring 81 is electrically connected to the second outer end 28 of the first transformer 21A (high-potential coil 23) and the second outer end 28 of the second transformer 21B (high-potential coil 23).

[0097] The high-potential connection wiring 81 of the second high-potential wiring 34 is formed around the high-potential coil 23 within the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connection wiring 81 is formed in a region between two adjacent high-potential coils 23 in plan view, and faces the high-potential terminal 12 (the fifth high-potential terminal 12E) in the normal direction Z. The high-potential connection wiring 81 is formed spaced apart from the low-potential connection wiring 72 in plan view, and does not face the low-potential connection wiring 72 in the normal direction Z.

[0098] The plurality of pad plug electrodes 82 are formed in a region between the high-potential terminal 12 (the fifth high-potential terminal 12E) and the high-potential connection wiring 81 within the uppermost insulating layer 56, and are electrically connected to the high-potential terminal 12 and the high-potential connection wiring 81, respectively.

[0099] Referring to Figs. 7 and 8, the distance D1 between the low-potential terminal 11 and the high-potential terminal 12 preferably exceeds the distance D2 between the low-potential coil 22 and the high-potential coil 23 (D2 < D1). The distance D1 preferably exceeds the total thickness DT of the plurality of interlayer insulating layers 57 (DT < D1). A ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. The distance D1 is preferably 100 µm or more and 500 µm or less. The distance D2 may be 1 µm or more and 50 µm or less. The distance D2 is preferably 5 µm or more and 25 µm or less. The values of the distance D1 and the distance D2 are arbitrary, and are appropriately adjusted according to the dielectric strength voltage to be achieved.

[0100] Referring to Figs. 6 to 11, the semiconductor device 5 includes a dummy pattern 85 embedded in the insulating layer 51 so as to be positioned around the transformers 21A to 21D in plan view. In Figs. 9 to 11, the dummy pattern 85 is shown by hatching. The dummy pattern 85 includes a conductor. The dummy pattern 85 is preferably formed of the same conductive material as that of the low-potential coil 22 and the like. That is, like the low-potential coil 22 and the like, the dummy pattern 85 preferably includes a barrier layer and a body layer.

[0101] The dummy pattern 85 is formed with a different pattern (discontinuous pattern) from the high-potential coil 23 and the low-potential coil 22, and is independent of the transformers 21A to 21D. In other words, the dummy pattern 85 does not function as a transformer 21A to 21D. The dummy pattern 85 is formed as a shielding conductor layer in the transformers 21A to 21D to shield the electric field between the low-potential coil 22 and the high-potential coil 23 and suppress electric field concentration on the high-potential coil 23.

[0102] In this embodiment, the dummy pattern 85 is routed in a dense linear fashion so as to partially cover and partially expose the area around one or more high-potential coils 23 in a plan view. In this embodiment, the dummy pattern 85 is routed at a line density equal to that of the high-potential coils 23 per unit area. The line density of the dummy pattern 85 being equal to that of the high-potential coils 23 means that the line density of the dummy pattern 85 falls within ±20% of the line density of the high-potential coils 23.

[0103] It is preferable that the dummy pattern 85 is formed in a region that is close to the high-potential coil 23 relative to the low-potential terminal 11 in a plan view. In a plan view, the dummy pattern 85 being close to the high-potential coil 23 means that the distance between the dummy pattern 85 and the high-potential coil 23 is less than the distance between the dummy pattern 85 and the low-potential terminal 11.

[0104] The depth position of the dummy pattern 85 within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be mitigated. Preferably, the dummy pattern 85 is formed in a region adjacent to the high-potential coil 23 with respect to the low-potential coil 22 with respect to the normal direction Z. Note that when we say that the dummy pattern 85 is adjacent to the high-potential coil 23 with respect to the normal direction Z, it means that the distance between the dummy pattern 85 and the high-potential coil 23 is less than the distance between the dummy pattern 85 and the low-potential coil 22 with respect to the normal direction Z.

[0105] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. The smaller the distance between the dummy pattern 85 and the high-potential coil 23 with respect to the normal direction Z, the more effectively electric field concentration on the high-potential coil 23 can be suppressed. It is preferable that the dummy pattern 85 is formed within the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be suppressed even more effectively.

[0106] It is preferable that the dummy pattern 85 is formed around the multiple high-potential coils 23 so as to be interposed in the region between adjacent high-potential coils 23 in a plan view. In this case, the region between adjacent high-potential coils 23 can be used to suppress unwanted electric field concentration on the multiple high-potential coils 23.

[0107] It is preferable that the dummy pattern 85 is interposed in the region between the low-potential terminal 11 and the high-potential coil 23 in a plan view. In this case, unwanted conduction between the low-potential terminal 11 and the high-potential coil 23 caused by electric field concentration in the high-potential coil 23 can be suppressed. It is preferable that the dummy pattern 85 is interposed in the region between the low-potential terminal 11 and the high-potential terminal 12 in a plan view. In this case, unwanted conduction between the low-potential terminal 11 and the high-potential terminal 12 caused by electric field concentration in the high-potential coil 23 can be suppressed.

[0108] In this configuration, the dummy pattern 85 is formed along the multiple high-potential coils 23 in a plan view and interposed in the region between adjacent high-potential coils 23. Furthermore, the dummy pattern 85 collectively surrounds the region containing the multiple high-potential coils 23 and the multiple high-potential terminals 12 in a plan view. Additionally, the dummy pattern 85 is interposed in the region between the multiple low-potential terminals 11A-11F and the multiple high-potential coils 23 in a plan view. Furthermore, the dummy pattern 85 is interposed in the region between the multiple low-potential terminals 11A-11F and the multiple high-potential terminals 12A-12F in a plan view.

[0109] Referring to Figures 6 to 11, the dummy pattern 85 includes multiple dummy patterns with different electrical states. The dummy pattern 85 includes a high-potential dummy pattern 86. The high-potential dummy pattern 86 is formed within the insulating layer 51 so as to be located around the transformers 21A to 21D in a plan view. The high-potential dummy pattern 86 is formed with a different pattern (discontinuous pattern) from the high-potential coil 23 and the low-potential coil 22 and is independent of the transformers 21A to 21D. In other words, the high-potential dummy pattern 86 does not function as a transformer 21A to 21D.

[0110] In this embodiment, the high-potential dummy pattern 86 is routed in a dense linear pattern such that it partially covers and partially exposes the area surrounding the high-potential coil 23 in a plan view. In this embodiment, the high-potential dummy pattern 86 is routed at a line density equal to that of the high-potential coil 23 per unit area. The line density of the high-potential dummy pattern 86 being equal to that of the high-potential coil 23 means that the line density of the high-potential dummy pattern 86 falls within ±20% of the line density of the high-potential coil 23.

[0111] The high-potential dummy pattern 86 shields the electric field between the low-potential coil 22 and the high-potential coil 23 in transformers 21A to 21D, suppressing electric field concentration on the high-potential coil 23. Specifically, the high-potential dummy pattern 86 shields the electric field between the low-potential coil 22 and the high-potential coil 23, thereby keeping the electric field leaking above the high-potential coil 23 away from the high-potential coil 23. This suppresses electric field concentration on the high-potential coil 23 caused by the electric field leaking above the high-potential coil 23.

[0112] A voltage exceeding the voltage applied to the low-potential coil 22 is applied to the high-potential dummy pattern 86. This suppresses the voltage drop between the high-potential coil 23 and the high-potential dummy pattern 86, thereby suppressing electric field concentration on the high-potential coil 23. Preferably, the voltage applied to the high-potential dummy pattern 86 is the same voltage applied to the high-potential coil 23. In other words, it is preferable that the high-potential dummy pattern 86 is fixed at the same potential as the high-potential coil 23. This reliably suppresses the voltage drop between the high-potential coil 23 and the high-potential dummy pattern 86, thereby appropriately suppressing electric field concentration on the high-potential coil 23.

[0113] The depth position of the high-potential dummy pattern 86 within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be mitigated. Preferably, the high-potential dummy pattern 86 is formed in a region adjacent to the high-potential coil 23 with respect to the normal direction Z relative to the low-potential coil 22. The high-potential dummy pattern 86 being adjacent to the high-potential coil 23 with respect to the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22 with respect to the normal direction Z.

[0114] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. With respect to the normal direction Z, the smaller the distance between the high-potential dummy pattern 86 and the high-potential coil 23, the more effectively electric field concentration on the high-potential coil 23 can be suppressed. It is preferable that the high-potential dummy pattern 86 is formed within the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be suppressed even more effectively.

[0115] The high-potential dummy pattern 86 is preferably formed in a region that is close to the high-potential coil 23 relative to the low-potential terminal 11 in a plan view. In a plan view, the high-potential dummy pattern 86 being close to the high-potential coil 23 means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 is less than the distance between the high-potential dummy pattern 86 and the low-potential terminal 11.

[0116] It is preferable that the high-potential dummy pattern 86 is formed around the multiple high-potential coils 23 so as to be interposed in the region between adjacent high-potential coils 23 in a plan view. In this case, the region between adjacent high-potential coils 23 can be used to suppress unwanted electric field concentration on the multiple high-potential coils 23.

[0117] The high-potential dummy pattern 86 is preferably interposed in the region between the low-potential terminal 11 and the high-potential coil 23 in a plan view. In this case, unwanted conduction between the low-potential terminal 11 and the high-potential coil 23 due to electric field concentration of the high-potential coil 23 can be suppressed. The high-potential dummy pattern 86 is preferably interposed in the region between the low-potential terminal 11 and the high-potential terminal 12 in a plan view. In this case, unwanted conduction between the low-potential terminal 11 and the high-potential terminal 12 due to electric field concentration of the high-potential coil 23 can be suppressed.

[0118] In this configuration, the high-potential dummy pattern 86 is formed along the multiple high-potential coils 23 in a plan view and interposed in the region between adjacent high-potential coils 23. Furthermore, the high-potential dummy pattern 86 collectively surrounds the region containing the multiple high-potential coils 23 and the multiple high-potential terminals 12 in a plan view. Additionally, the high-potential dummy pattern 86 is interposed in the region between the multiple low-potential terminals 11A-11F and the multiple high-potential coils 23 in a plan view. Furthermore, the high-potential dummy pattern 86 is interposed in the region between the multiple low-potential terminals 11A-11F and the multiple high-potential terminals 12A-12F in a plan view.

[0119] The high-potential dummy pattern 86 is routed around the high-potential terminals 12E and 12F such that, in a plan view, it exposes the area directly beneath the high-potential terminals 12E and 12F in the region between adjacent high-potential coils 23. A portion of the high-potential dummy pattern 86 may face the high-potential terminals 12A to 12F in the normal direction Z. In this case, the high-potential terminals 12E and 12F, like the high-potential dummy pattern 86, suppress the electric field leaking above the high-potential coils 23 by shielding the electric field. In other words, the high-potential terminals 12E and 12F are formed together with the high-potential dummy pattern 86 as a shielding conductor layer that suppresses electric field concentration on the high-potential coils 23.

[0120] It is preferable that the high-potential dummy pattern 86 is formed with ends. In this case, the formation of a current loop circuit (closed circuit) in the high-potential dummy pattern 86 can be suppressed. This suppresses noise caused by the current flowing through the high-potential dummy pattern 86. As a result, unwanted electric field concentration caused by noise can be suppressed, and at the same time, fluctuations in the electrical characteristics of transformers 21A to 21D can be suppressed.

[0121] The high-potential dummy pattern 86 specifically includes a first high-potential dummy pattern 87 and a second high-potential dummy pattern 88. The first high-potential dummy pattern 87 is formed in the region between a plurality of adjacent transformers 21A to 21D (a plurality of high-potential coils 23) in a plan view. The second high-potential dummy pattern 88 is formed in the region outside the region between the plurality of adjacent transformers 21A to 21D (a plurality of high-potential coils 23) in a plan view.

[0122] In the following, the region between the adjacent first transformer 21A (high-potential coil 23) and second transformer 21B (high-potential coil 23) will be referred to as the first region 89. The region between the second transformer 21B (high-potential coil 23) and the third transformer 21C (high-potential coil 23) will be referred to as the second region 90. The region between the third transformer 21C (high-potential coil 23) and the fourth transformer 21D (high-potential coil 23) will be referred to as the third region 91.

[0123] In this configuration, the first high-potential dummy pattern 87 is electrically connected to the high-potential terminal 12 (fifth high-potential terminal 12E) via the first high-potential wiring 33. Specifically, the first high-potential dummy pattern 87 includes a first connection 92 connected to the first high-potential wiring 33. The position of the first connection 92 is arbitrary. This fixes the first high-potential dummy pattern 87 at the same potential as the multiple high-potential coils 23.

[0124] The first high-potential dummy pattern 87 specifically includes a first pattern 93 formed in the first region 89, a second pattern 94 formed in the second region 90, and a third pattern 95 formed in the third region 91. As a result, the first high-potential dummy pattern 87 suppresses the electric field leaking above the high-potential coil 23 in the first region 89, the second region 90, and the third region 91, thereby suppressing electric field concentration for multiple adjacent high-potential coils 23.

[0125] In this embodiment, the first pattern 93, the second pattern 94, and the third pattern 95 are integrally formed and fixed at the same potential. The first pattern 93, the second pattern 94, and the third pattern 95 may be separated, as long as they are fixed at the same potential.

[0126] Referring to Figures 6 and 9, the first pattern 93 is connected to the first high-potential wiring 33 via the first connection part 92. The first pattern 93 is routed in a dense line shape so as to cover a portion of the first region 89 in a plan view. In a plan view, the first pattern 93 is formed in the first region 89 at a distance from the high-potential terminal 12 (fifth high-potential terminal 12E) and does not face the high-potential terminal 12 in the normal direction Z. Also, in a plan view, the first pattern 93 is formed at a distance from the low-potential connection wiring 72 and does not face the low-potential connection wiring 72 in the normal direction Z. As a result, the insulation distance between the first pattern 93 and the low-potential connection wiring 72 is increased, and the dielectric strength of the insulating layer 51 is enhanced.

[0127] The first pattern 93 includes a first outer perimeter line 96, a second outer perimeter line 97, and a plurality of first intermediate lines 98. The first outer perimeter line 96 extends in a band shape around the high-potential coil 23 of the first transformer 21A. In this embodiment, the first outer perimeter line 96 is formed in a ring shape with an open end in a first region 89 in plan view. The width of the open end of the first outer perimeter line 96 is less than the width along the second direction Y of the high-potential coil 23.

[0128] The width of the first outer perimeter line 96 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the first outer perimeter line 96 is 1 μm or more and 3 μm or less. The width of the first outer perimeter line 96 is defined by the width in the direction perpendicular to the direction in which the first outer perimeter line 96 extends. Preferably, the width of the first outer perimeter line 96 is equal to the width of the high-potential coil 23. The width of the first outer perimeter line 96 being equal to the width of the high-potential coil 23 means that the width of the first outer perimeter line 96 falls within ±20% of the width of the high-potential coil 23.

[0129] The first pitch between the first outer circumference line 96 and the high-potential coil 23 (first transformer 21A) may be 0.1 μm or more and 5 μm or less. Preferably, the first pitch is 1 μm or more and 3 μm or less. Preferably, the first pitch is equal to the second winding pitch of the high-potential coil 23. 2 Equal to the winding pitch means that the first pitch is equal to the second pitch. 2 This means that the winding pitch will fall within a range of ±20%.

[0130] The second outer perimeter line 97 extends in a band-like manner around the high-potential coil 23 of the second transformer 21B. In this embodiment, the second outer perimeter line 97 is formed in a ring shape with an open end in the first region 89 in a plan view. The width of the open end of the second outer perimeter line 97 is less than the width of the high-potential coil 23 along the second direction Y. The open end of the second outer perimeter line 97 faces the open end of the first outer perimeter line 96 along the first direction X.

[0131] The width of the second outer perimeter line 97 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the second outer perimeter line 97 is 1 μm or more and 3 μm or less. The width of the second outer perimeter line 97 is defined by the width in the direction perpendicular to the direction in which the second outer perimeter line 97 extends. Preferably, the width of the second outer perimeter line 97 is equal to the width of the high-potential coil 23. The width of the second outer perimeter line 97 being equal to the width of the high-potential coil 23 means that the width of the second outer perimeter line 97 falls within ±20% of the width of the high-potential coil 23.

[0132] The second pitch between the second outer circumference line 97 and the high-potential coil 23 (second transformer 21B) may be 0.1 μm or more and 5 μm or less. Preferably, the second pitch is 1 μm or more and 3 μm or less. Preferably, the second pitch is equal to the second winding pitch of the high-potential coil 23. Equaling the second pitch to the second winding pitch means that the second pitch falls within a range of ±20% of the second winding pitch.

[0133] Multiple first intermediate lines 98 extend in a strip-like manner in the region between the first outer perimeter line 96 and the second outer perimeter line 97 in the first region 89. Each of the multiple first intermediate lines 98 includes at least one (one in this embodiment) first connecting line 99 that electrically connects the first outer perimeter line 96 and the second outer perimeter line 97.

[0134] From the viewpoint of preventing the formation of current loop circuits, it is preferable that the plurality of first intermediate lines 98 include only one first connection line 99. The position of the first connection line 99 is arbitrary. At least one of the plurality of first intermediate lines 98 has a slit 100 formed therein to interrupt the current loop circuit. The position of the slit 100 is appropriately adjusted depending on the design of the plurality of first intermediate lines 98.

[0135] Preferably, the multiple first intermediate lines 98 are formed in a strip shape extending along the opposing directions of the multiple high-potential coils 23. In this embodiment, each of the multiple first intermediate lines 98 is formed in a strip shape extending in a first direction X and is formed with gaps in the second direction Y. In a plan view, the multiple first intermediate lines 98 as a whole are formed in a stripe shape extending in the first direction X.

[0136] The multiple first intermediate lines 98 specifically include multiple first lead-out sections 101 and multiple second lead-out sections 102. The multiple first lead-out sections 101 are drawn out in a stripe pattern from the first outer peripheral line 96 toward the second outer peripheral line 97. The tips of the multiple first lead-out sections 101 are formed with a gap between them and the second outer peripheral line 97 side from the first outer peripheral line 96.

[0137] Multiple second extensions 102 are drawn out in a stripe pattern from the second outer circumference line 97 toward the first outer circumference line 96. The tips of the multiple second extensions 102 are formed with a gap between them and the first outer circumference line 96 from the second outer circumference line 97. In this configuration, the multiple second extensions 102 are formed alternately with the multiple first extensions 101 in the second direction Y, sandwiching one first extension 101.

[0138] Furthermore, the multiple second lead portions 102 may sandwich the multiple first lead portions 101. Also, a group including the multiple second lead portions 102 may be formed adjacent to a group including the multiple first lead portions 101. The slit 100, the multiple first lead portions 101, and the multiple second lead portions 102 suppress the formation of a current loop circuit in the first pattern 93.

[0139] With respect to the second direction Y, the width of the first intermediate line 98 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the first intermediate line 98 is 1 μm or more and 3 μm or less. Preferably, the width of the first intermediate line 98 is equal to the width of the high-potential coil 23. The width of the first intermediate line 98 being equal to the width of the high-potential coil 23 means that the width of the first intermediate line 98 is within ±20% of the width of the high-potential coil 23.

[0140] The third pitch of two adjacent first intermediate lines 98 may be between 0.1 μm and 5 μm. Preferably, the third pitch is between 1 μm and 3 μm. The third pitch is defined by the distance between a plurality of adjacent first intermediate lines 98 with respect to the second direction Y. Preferably, the third pitches are equal to each other. Equal third pitches mean that the third pitches fall within a range of ±20% of the third pitch. Preferably, the third pitch is equal to the second winding pitch of the high-potential coil 23. Equal third pitches mean that the third pitch falls within a range of ±20% of the second winding pitch.

[0141] Referring to Figures 6 and 10, the second pattern 94 is electrically connected to the high-potential terminal 12 via the first high-potential wiring 33. In this embodiment, the second pattern 94 is electrically connected to the first high-potential wiring 33 (fifth high-potential terminal 12E) via the second outer periphery line 97 of the first pattern 93. The second pattern 94 is routed in a dense linear fashion so as to cover the second region 90.

[0142] The second pattern 94 includes the aforementioned second outer perimeter line 97, third outer perimeter line 103, and a plurality of second intermediate lines 104. The third outer perimeter line 103 extends in a band shape around the high-potential coil 23 of the third transformer 21C. In this embodiment, the third outer perimeter line 103 is formed in a ring shape with an open end in the third region 91 in plan view. The width of the open end of the third outer perimeter line 103 is less than the width along the second direction Y of the high-potential coil 23 of the third transformer 21C.

[0143] The width of the third outer perimeter line 103 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the third outer perimeter line 103 is 1 μm or more and 3 μm or less. The width of the third outer perimeter line 103 is defined by the width in the direction perpendicular to the direction in which the third outer perimeter line 103 extends. Preferably, the width of the third outer perimeter line 103 is equal to the width of the high-potential coil 23. The width of the third outer perimeter line 103 being equal to the width of the high-potential coil 23 means that the width of the third outer perimeter line 103 falls within ±20% of the width of the high-potential coil 23.

[0144] The fourth pitch between the third outer circumference line 103 and the high-potential coil 23 (third transformer 21C) may be 0.1 μm or more and 5 μm or less. Preferably, the fourth pitch is 1 μm or more and 3 μm or less. Preferably, the fourth pitch is equal to the second winding pitch of the high-potential coil 23. Equal to the second winding pitch means that the fourth pitch is within ±20% of the second winding pitch.

[0145] The multiple second intermediate lines 104 extend in a strip-like manner in the region between the second outer perimeter line 97 and the third outer perimeter line 103 in the second region 90. The multiple second intermediate lines 104 include at least one (one in this embodiment) second connecting line 105 that electrically connects the second outer perimeter line 97 and the third outer perimeter line 103.

[0146] From the viewpoint of preventing the formation of current loop circuits, it is preferable that the plurality of second intermediate lines 104 include only one second connecting line 105. The second connecting line 105 may have a width exceeding the width of the other second intermediate lines 104. The position of the second connecting line 105 is arbitrary. At least one of the plurality of second intermediate lines 104 has a slit 106 formed therein to interrupt the current loop circuit. The position of the slit 106 is appropriately adjusted depending on the design of the plurality of second intermediate lines 104.

[0147] Preferably, the multiple second intermediate lines 104 are formed in a strip shape extending along the opposing directions of the multiple high-potential coils 23. In this embodiment, each of the multiple second intermediate lines 104 is formed in a strip shape extending in the first direction X and is formed with gaps in the second direction Y. In a plan view, the multiple second intermediate lines 104 as a whole are formed in a stripe shape extending in the first direction X.

[0148] The multiple second intermediate lines 104 specifically include multiple third lead sections 107 and multiple fourth lead sections 108. The multiple third lead sections 107 are drawn out in a stripe pattern from the second outer perimeter line 97 toward the third outer perimeter line 103. The tips of the multiple third lead sections 107 are formed with a gap between the third outer perimeter line 103 and the second outer perimeter line 97.

[0149] Multiple fourth extensions 108 are drawn out in a stripe pattern from the third outer circumference line 103 toward the second outer circumference line 97. The tips of the multiple fourth extensions 108 are formed with a gap between them and the third outer circumference line 103 from the second outer circumference line 97. In this configuration, the multiple fourth extensions 108 are formed alternately with the multiple third extensions 107 in the second direction Y, sandwiching one third extension 107.

[0150] Furthermore, the multiple fourth lead portions 108 may sandwich the multiple third lead portions 107. Also, a group including the multiple fourth lead portions 108 may be formed adjacent to a group including the multiple third lead portions 107. The slit 106, the multiple third lead portions 107, and the multiple fourth lead portions 108 suppress the formation of a current loop circuit in the second pattern 94.

[0151] With respect to the second direction Y, the width of the second intermediate line 104 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the second intermediate line 104 is 1 μm or more and 3 μm or less. Preferably, the width of the second intermediate line 104 is equal to the width of the high-potential coil 23. When the width of the second intermediate line 104 is equal to the width of the high-potential coil 23, it means that the width of the second intermediate line 104 is within ±20% of the width of the high-potential coil 23.

[0152] The fifth pitch of two adjacent second intermediate lines 104 may be 0.1 μm or more and 5 μm or less. Preferably, the fifth pitch is 1 μm or more and 3 μm or less. The fifth pitch is defined by the distance between a plurality of adjacent second intermediate lines 104 with respect to the second direction Y. Preferably, the fifth pitches are equal to each other. Equal fifth pitches mean that the fifth pitch falls within a range of ±20% of the fifth pitch. Preferably, the fifth pitch is equal to the second winding pitch of the high-potential coil 23. Equal fifth pitches mean that the fifth pitch falls within a range of ±20% of the second winding pitch.

[0153] Referring to Figures 6 and 11, the third pattern 95 is electrically connected to the first high-potential wiring 33. In this embodiment, the third pattern 95 is electrically connected to the first high-potential wiring 33 via the second pattern 94 and the first pattern 93. The third pattern 95 is routed in a dense line pattern so as to cover a portion of the third region 91. In a plan view, the third pattern 95 is formed in the third region 91 at a distance from the high-potential terminal 12 (sixth high-potential terminal 12F) and does not face the high-potential terminal 12 in the normal direction Z.

[0154] The third pattern 95 is formed at a distance from the low-potential connection wiring 72 in a plan view and does not face the low-potential connection wiring 72 in the normal direction Z. As a result, the insulation distance between the third pattern 95 and the low-potential connection wiring 72 is increased in the normal direction Z, and the dielectric strength of the insulating layer 51 is increased.

[0155] The third pattern 95 includes the aforementioned third outer perimeter line 103, fourth outer perimeter line 109, and a plurality of third intermediate lines 110. The fourth outer perimeter line 109 extends in a band shape around the high-potential coil 23 of the fourth transformer 21D. In this embodiment, the fourth outer perimeter line 109 is formed in a ring shape with an open end in the third region 91 in plan view. The width of the open end of the fourth outer perimeter line 109 is less than the width along the second direction Y of the high-potential coil 23 of the fourth transformer 21D. The open end of the fourth outer perimeter line 109 faces the open end of the third outer perimeter line 103 along the first direction X.

[0156] The width of the fourth outer perimeter line 109 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the fourth outer perimeter line 109 is 1 μm or more and 3 μm or less. The width of the fourth outer perimeter line 109 is defined by the width in the direction perpendicular to the direction in which the fourth outer perimeter line 109 extends. Preferably, the width of the fourth outer perimeter line 109 is equal to the width of the high-potential coil 23. When the width of the fourth outer perimeter line 109 is equal to the width of the high-potential coil 23, it means that the width of the fourth outer perimeter line 109 falls within a range of ±20% of the width of the high-potential coil 23.

[0157] The sixth pitch between the fourth outer circumference line 109 and the high-potential coil 23 (fourth transformer 21D) may be 0.1 μm or more and 5 μm or less. Preferably, the sixth pitch is 1 μm or more and 3 μm or less. The sixth pitch is equal to the second winding pitch of the high-potential coil 23. The sixth pitch being equal to the second winding pitch means that the sixth pitch is within ±20% of the second winding pitch.

[0158] The multiple third intermediate lines 110 extend in a strip-like manner in the third region 91 between the third outer perimeter line 103 and the fourth outer perimeter line 109. The multiple third intermediate lines 110 include at least one (one in this embodiment) third connecting line 111 that electrically connects the third outer perimeter line 103 and the fourth outer perimeter line 109.

[0159] From the viewpoint of preventing the formation of current loop circuits, it is preferable that the plurality of third intermediate lines 110 include only one third connecting line 111. The position of the third connecting line 111 is arbitrary. At least one of the plurality of third intermediate lines 110 has a slit 112 formed therein to interrupt the current loop circuit. The position of the slit 112 is appropriately adjusted depending on the design of the plurality of third intermediate lines 110.

[0160] Preferably, the multiple third intermediate lines 110 are formed in a strip shape extending along the opposing directions of the multiple high-potential coils 23. In this embodiment, each of the multiple third intermediate lines 110 is formed in a strip shape extending in the first direction X and is formed with gaps in the second direction Y. The multiple third intermediate lines 110 are formed in a stripe shape as a whole in a plan view.

[0161] In this embodiment, the multiple third intermediate lines 110 include multiple fifth lead sections 113 and multiple sixth lead sections 114. The multiple fifth lead sections 113 are drawn out in a stripe pattern from the third outer perimeter line 103 toward the fourth outer perimeter line 109. The ends of the multiple fifth lead sections 113 are formed with a gap between the fourth outer perimeter line 109 and the third outer perimeter line 103.

[0162] Multiple sixth extension sections 114 are drawn out in a stripe pattern from the fourth outer circumference line 109 toward the third outer circumference line 103. The tips of the multiple sixth extension sections 114 are formed with a gap between them, from the third outer circumference line 103 toward the fourth outer circumference line 109. In this configuration, the multiple sixth extension sections 114 are formed alternately with the multiple fifth extension sections 113 in the second direction Y, sandwiching one fifth extension section 113.

[0163] Furthermore, the multiple sixth lead portions 114 may sandwich the multiple fifth lead portions 113. Also, a group including the multiple sixth lead portions 114 may be formed adjacent to a group including the multiple fifth lead portions 113. The slit 112, the multiple fifth lead portions 113, and the multiple sixth lead portions 114 suppress the formation of a current loop circuit in the third pattern 95.

[0164] With respect to the second direction Y, the width of the third intermediate line 110 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the third intermediate line 110 is 1 μm or more and 3 μm or less. Preferably, the width of the third intermediate line 110 is equal to the width of the high-potential coil 23. When the width of the third intermediate line 110 is equal to the width of the high-potential coil 23, it means that the width of the third intermediate line 110 is within ±20% of the width of the high-potential coil 23.

[0165] The seventh pitch of two adjacent third intermediate lines 110 may be 0.1 μm or more and 5 μm or less. Preferably, the seventh pitch is 1 μm or more and 3 μm or less. The seventh pitch is defined by the distance between a plurality of adjacent third intermediate lines 110 with respect to the second direction Y. Preferably, the seventh pitches are equal to each other. Equal seventh pitches mean that the seventh pitch falls within a range of ±20% of the seventh pitch. Preferably, the seventh pitch is equal to the second winding pitch of the high-potential coil 23. Equal seventh pitch means that the seventh pitch falls within a range of ±20% of the second winding pitch.

[0166] Referring to Figures 6 to 11, the second high-potential dummy pattern 88 is electrically connected to the high-potential terminal 12 via the first high-potential dummy pattern 87 in this configuration. Specifically, the second high-potential dummy pattern 88 includes a second connection 115 connected to the first high-potential dummy pattern 87. The position of the second connection 115 is arbitrary. This fixes the second high-potential dummy pattern 88 at the same potential as the multiple high-potential coils 23.

[0167] The second high-potential dummy pattern 88 suppresses the electric field leaking above the high-potential coil 23 in the regions outside the first region 89, the second region 90, and the third region 91, thereby suppressing electric field concentration on the multiple high-potential coils 23. In this configuration, the second high-potential dummy pattern 88 collectively surrounds the region containing the multiple high-potential coils 23 and the multiple high-potential terminals 12A to 12F in a plan view. In this configuration, the second high-potential dummy pattern 88 is formed in an oval (elliptical) shape in a plan view.

[0168] As a result, the second high-potential dummy pattern 88 is interposed in the region between the multiple low-potential terminals 11A to 11F and the multiple high-potential coils 23 in a plan view. Furthermore, the second high-potential dummy pattern 88 is interposed in the region between the multiple low-potential terminals 11A to 11F and the multiple high-potential terminals 12A to 12F in a plan view.

[0169] The second high-potential dummy pattern 88 includes multiple (six in this configuration) high-potential lines 116A, 116B, 116C, 116D, 116E, and 116F. The number of high-potential lines is adjusted according to the electric field to be mitigated. The multiple high-potential lines 116A to 116F are formed in this order, spaced apart, in a direction away from the multiple high-potential coils 23.

[0170] Multiple high-potential lines 116A to 116F collectively surround multiple high-potential coils 23 in a plan view. Specifically, multiple high-potential lines 116A to 116F collectively surround the region containing multiple high-potential coils 23 and multiple high-potential terminals 12A to 12F in a plan view. In this configuration, multiple high-potential lines 116A to 116F are formed in an oval (elliptical) shape in a plan view.

[0171] Each of the multiple high-potential lines 116A to 116F includes a slit 117 that interrupts the current loop circuit. The position of the slit 117 is adjusted as appropriate depending on the design of the multiple high-potential lines 116A to 116F.

[0172] The width of the high-potential lines 116A to 116F may be 0.1 μm or more and 5 μm or less. Preferably, the width of the high-potential lines 116A to 116F is 1 μm or more and 3 μm or less. The width of the high-potential lines 116A to 116F is defined by the width in the direction perpendicular to the direction in which the high-potential lines 116A to 116F extend. Preferably, the width of the high-potential lines 116A to 116F is equal to the width of the high-potential coil 23. When the width of the high-potential lines 116A to 116F is equal to the width of the high-potential coil 23, it means that the width of the high-potential lines 116A to 116F falls within ±20% of the width of the high-potential coil 23.

[0173] The eighth pitch of two adjacent high-potential lines 116A to 116F may be 0.1 μm or more and 5 μm or less. Preferably, the eighth pitch is 1 μm or more and 3 μm or less. Preferably, the eighth pitches are equal to each other. Equal eighth pitches mean that the eighth pitches fall within a range of ±20% of the eighth pitch of that eighth pitch.

[0174] The ninth pitch between adjacent first high-potential dummy patterns 87 and second high-potential dummy patterns 88 may be 0.1 μm or more and 5 μm or less. Preferably, the ninth pitch is 1 μm or more and 3 μm or less. Preferably, the ninth pitch is equal to the second winding pitch of the high-potential coil 23. Equaling the ninth pitch to the second winding pitch means that the ninth pitch falls within a range of ±20% of the second winding pitch. The number, width, pitch, etc. of the multiple high-potential lines 116A to 116F are arbitrary and are adjusted according to the electric field to be mitigated.

[0175] Referring to Figures 6 to 11, the dummy pattern 85 includes a floating dummy pattern 121 that is electrically floating within the insulating layer 51 so as to be located around the transformers 21A to 21D in a plan view. The floating dummy pattern 121 is formed with a different pattern (discontinuous pattern) from the high-potential coil 23 and the low-potential coil 22 and is independent of the transformers 21A to 21D. In other words, the floating dummy pattern 121 does not function as a transformer 21A to 21D.

[0176] In this embodiment, the floating dummy pattern 121 is routed in a dense linear fashion so as to partially cover and partially expose the area surrounding the high-potential coil 23 in a plan view. The floating dummy pattern 121 may be formed with ends or as an endless pattern.

[0177] The floating dummy pattern 121 is routed at a line density equal to that of the high-potential coil 23 per unit area. The line density of the floating dummy pattern 121 being equal to that of the high-potential coil 23 means that the line density of the floating dummy pattern 121 falls within ±20% of the line density of the high-potential coil 23.

[0178] Furthermore, the floating dummy pattern 121 is routed with a line density equal to that of the high-potential dummy pattern 86 per unit area. The line density of the floating dummy pattern 121 being equal to that of the high-potential dummy pattern 86 means that the line density of the floating dummy pattern 121 falls within ±20% of the line density of the high-potential dummy pattern 86.

[0179] The floating dummy pattern 121 shields the electric field between the low-potential coil 22 and the high-potential coil 23 in transformers 21A to 21D, suppressing electric field concentration on the high-potential coil 23. Specifically, the floating dummy pattern 121 disperses the electric field leaking above the high-potential coil 23 away from the high-potential coil 23. This suppresses electric field concentration on the high-potential coil 23.

[0180] Furthermore, the floating dummy pattern 121 disperses the electric field leaking above the high-potential dummy pattern 86 in a direction away from the high-potential coil 23 and the high-potential dummy pattern 86. This suppresses electric field concentration on the high-potential dummy pattern 86 while also appropriately suppressing electric field concentration on the high-potential coil 23.

[0181] The depth position of the floating dummy pattern 121 within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be mitigated. Preferably, the floating dummy pattern 121 is formed in a region adjacent to the high-potential coil 23 with respect to the normal direction Z, relative to the low-potential coil 22. Adjacent to the high-potential coil 23 with respect to the normal direction Z means that the distance between the floating dummy pattern 121 and the high-potential coil 23 is less than the distance between the floating dummy pattern 121 and the low-potential coil 22, with respect to the normal direction Z.

[0182] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. The smaller the distance between the floating dummy pattern 121 and the high-potential coil 23 with respect to the normal direction Z, the more effectively electric field concentration on the high-potential coil 23 can be suppressed. It is preferable that the floating dummy pattern 121 is formed within the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be suppressed even more effectively.

[0183] The floating dummy pattern 121 is preferably interposed in the region between the low-potential terminal 11 and the high-potential coil 23 in a plan view. In this case, unwanted conduction between the low-potential terminal 11 and the high-potential coil 23 caused by electric field concentration in the high-potential coil 23 can be suppressed. The floating dummy pattern 121 is preferably interposed in the region between the low-potential terminal 11 and the high-potential terminal 12 in a plan view. In this case, unwanted conduction between the low-potential terminal 11 and the high-potential terminal 12 caused by electric field concentration in the high-potential coil 23 can be suppressed.

[0184] In this embodiment, the floating dummy pattern 121 is formed along a plurality of high-potential coils 23 in a plan view. Specifically, the floating dummy pattern 121 collectively surrounds an area containing a plurality of high-potential coils 23 and a plurality of high-potential terminals 12 in a plan view. In this embodiment, the floating dummy pattern 121 collectively surrounds an area containing a plurality of high-potential coils 23 and a plurality of high-potential terminals 12, with the high-potential dummy pattern 86 (second high-potential dummy pattern 88) in between, in a plan view.

[0185] As a result, the floating dummy pattern 121 is interposed in the region between the multiple low-potential terminals 11A to 11F and the multiple high-potential coils 23 in a plan view. Furthermore, the floating dummy pattern 121 is interposed in the region between the multiple low-potential terminals 11A to 11F and the multiple high-potential terminals 12A to 12F in a plan view.

[0186] The number of floating lines is arbitrary and is adjusted according to the electric field to be mitigated. In this configuration, the floating dummy pattern 121 includes multiple (six in this figure) floating lines 122A, 122B, 122C, 122D, 122E, and 122F. The multiple floating lines 122A to 122F are formed in this order, spaced apart, in the direction away from the multiple high-potential coils 23.

[0187] The multiple floating lines 122A to 122F collectively surround the multiple high-potential coils 23 in a plan view. Specifically, the multiple floating lines 122A to 122F collectively surround the region containing the multiple high-potential coils 23 and the multiple high-potential terminals 12A to 12F, with the high-potential dummy pattern 86 in between, in a plan view. In this configuration, the multiple floating lines 122A to 122F are formed in an oval (elliptical) shape in a plan view.

[0188] The width of the floating lines 122A to 122F may be 0.1 μm or more and 5 μm or less. Preferably, the width of the floating lines 122A to 122F is 1 μm or more and 3 μm or less. The width of the floating lines 122A to 122F is defined by the width in the direction perpendicular to the direction in which the floating lines 122A to 122F extend.

[0189] The tenth pitch between two adjacent floating lines 122A to 122F may be 0.1 μm or more and 5 μm or less. Preferably, the tenth pitch is 1 μm or more and 3 μm or less. Preferably, the width of the floating lines 122A to 122F is equal to the width of the high-potential coil 23. The width of the floating lines 122A to 122F being equal to the width of the high-potential coil 23 means that the width of the floating lines 122A to 122F is within ±20% of the width of the high-potential coil 23.

[0190] The 11th pitch between the floating dummy pattern 121 and the high-potential dummy pattern 86 (second high-potential dummy pattern 88) may be 0.1 μm or more and 5 μm or less. Preferably, the 11th pitch is 1 μm or more and 3 μm or less. Preferably, the 11th pitches are equal to each other. Equal to each other means that the 11th pitches fall within a range of ±20% of the given 11th pitch.

[0191] The 11th pitch is preferably equal to the second winding pitch of the high-potential coil 23. The 11th pitch between the floating lines 122A to 122F being equal to the second winding pitch means that the 11th pitch falls within ±20% of the second winding pitch. Note that Figures 4 to 6 show examples where the 11th pitch exceeds the second winding pitch for clarity.

[0192] The 12th pitch between the floating dummy pattern 121 and the high-potential dummy pattern 86 is preferably equal to the second winding pitch. The 12th pitch being equal to the second winding pitch means that the 12th pitch falls within a range of ±20% of the second winding pitch. The number, width, pitch, etc., of the multiple floating lines 122A to 122F are adjusted according to the electric field to be mitigated and are not limited to specific values.

[0193] Referring to Figures 7 and 8, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed using the surface layer of the first main surface 42 of the semiconductor chip 41 and / or the region above the first main surface 42 of the semiconductor chip 41, and is covered by an insulating layer 51 (bottom insulating layer 55). In Figures 7 and 8, the second functional device 60 is simplified by dashed lines shown on the surface layer of the first main surface 42.

[0194] The second functional device 60 is electrically connected to the low-potential terminal 11 via low-potential wiring and to the high-potential terminal 12 via high-potential wiring. The low-potential wiring has the same structure as the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed within the insulating layer 51 to connect to the second functional device 60. The high-potential wiring has the same structure as the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed within the insulating layer 51 to connect to the second functional device 60. A detailed explanation of the low-potential and high-potential wiring related to the second functional device 60 is omitted.

[0195] The second functional device 60 may include at least one of a passive device, a semiconductor rectifier device, and a semiconductor switching device. The passive device may include a circuit network in which any two or more devices from among the passive device, semiconductor rectifier device, and semiconductor switching device are selectively combined. The circuit network may form part or all of an integrated circuit.

[0196] Passive devices may include semiconductor passive devices. Passive devices may include either a resistor or a capacitor, or both. Semiconductor rectifier devices may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. Semiconductor switching devices may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0197] Referring to Figures 7 and 8, the semiconductor device 5 further includes a sealing conductor 61 embedded in the insulating layer 51. In a plan view, the sealing conductor 61 is embedded in the insulating layer 51 in a wall-like manner, spaced apart from the insulating side walls 53A to 53D, and divides the insulating layer 51 into a device region 62 and an outer region 63. The sealing conductor 61 suppresses the intrusion of moisture and cracks from the outer region 63 into the device region 62.

[0198] The device region 62 is the region that includes the first functional device 45 (multiple transformers 21), the second functional device 60, multiple low-potential terminals 11, multiple high-potential terminals 12, the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85. The outer region 63 is the region outside the device region 62.

[0199] The sealing conductor 61 is electrically isolated from the device region 62. Specifically, the sealing conductor 61 is electrically isolated from the first functional device 45 (multiple transformers 21), the second functional device 60, multiple low-potential terminals 11, multiple high-potential terminals 12, the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85. More specifically, the sealing conductor 61 is electrically suspended. The sealing conductor 61 does not form a current path that connects to the device region 62.

[0200] In a plan view, the sealing conductor 61 is formed in a strip shape along the insulating side walls 53-53D. In this configuration, the sealing conductor 61 is formed in a rectangular ring shape (specifically, a rectangular ring shape) in a plan view. As a result, the sealing conductor 61 demarcates a rectangular (specifically, rectangular) device region 62 in a plan view. Furthermore, the sealing conductor 61 demarcates the outer rectangular ring (specifically, a rectangular ring shape) region 63 surrounding the device region 62 in a plan view.

[0201] Specifically, the seal conductor 61 has an upper end on the insulating main surface 52 side, a lower end on the semiconductor chip 41 side, and a wall portion extending wall-like between the upper end and the lower end. In this embodiment, the upper end of the seal conductor 61 is formed with a gap from the insulating main surface 52 toward the semiconductor chip 41 side and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed with a gap from the semiconductor chip 41 toward the upper end side.

[0202] Thus, in this embodiment, the sealing conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side relative to the multiple low-potential terminals 11 and the multiple high-potential terminals 12. Furthermore, within the insulating layer 51, the sealing conductor 61 faces the first functional device 45 (multiple transformers 21), the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85 in a direction parallel to the insulating main surface 52. Within the insulating layer 51, the sealing conductor 61 may also face a portion of the second functional device 60 in a direction parallel to the insulating main surface 52.

[0203] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (in this embodiment, multiple) seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 of the plurality of seal plug conductors 64 forms the upper end of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end of the seal conductor 61. It is preferable that the seal plug conductors 64 and seal via conductors 65 are made of the same conductive material as the low-potential coil 22. That is, it is preferable that the seal plug conductors 64 and seal via conductors 65 include a barrier layer and a body layer, similar to the low-potential coil 22, etc.

[0204] Multiple seal plug conductors 64 are embedded in multiple interlayer insulating layers 57, and in a plan view, they are each formed in a rectangular ring (specifically, a rectangular ring) surrounding the device region 62. Multiple seal plug conductors 64 are stacked from the bottom insulating layer 55 toward the top insulating layer 56 so as to be connected to each other. The number of stacked seal plug conductors 64 corresponds to the number of stacked interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0205] If a single annular seal conductor 61 is formed by an assembly of multiple seal plug conductors 64, it is not necessary for all of the multiple seal plug conductors 64 to be formed in an annular shape. For example, at least one of the multiple seal plug conductors 64 may be formed with ends. Alternatively, at least one of the multiple seal plug conductors 64 may be divided into multiple end-shaped strips. However, considering the risk of moisture and cracks entering the device region 62, it is preferable that the multiple seal plug conductors 64 be formed in an endless (annular) shape.

[0206] Multiple seal via conductors 65 are formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the bottom insulating layer 55. The multiple seal via conductors 65 are formed at intervals from the semiconductor chip 41 and connected to the seal plug conductor 64. The multiple seal via conductors 65 have a planar area less than the planar area of ​​the seal plug conductor 64. If a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area greater than or equal to the planar area of ​​the seal plug conductor 64.

[0207] The width of the seal conductor 61 may be 0.1 μm or more and 10 μm or less. Preferably, the width of the seal conductor 61 is 1 μm or more and 5 μm or less. The width of the seal conductor 61 is defined by the width in the direction perpendicular to the direction in which the seal conductor 61 extends.

[0208] Referring to Figures 7, 8, and 12, the semiconductor device 5 further includes an isolation structure 130 interposed between the semiconductor chip 41 and the sealing conductor 61, electrically isolating the sealing conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 consists of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0209] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). Preferably, the field insulating film 131 consists of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidation of the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0210] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41 and extends in a strip shape along the seal conductor 61 in a plan view. In this embodiment, the isolation structure 130 is formed in a rectangular ring shape (specifically, a rectangular ring shape) in a plan view. The isolation structure 130 has a connection portion 132 to which the lower end (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion to which the lower end (seal via conductor 65) of the seal conductor 61 bites toward the semiconductor chip 41 side. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0211] The separation structure 130 includes an inner end portion 130A on the device region 62 side, an outer end portion 130B on the outer region 63 side, and a main body portion 130C between the inner end portion 130A and the outer end portion 130B. The inner end portion 130A demarcates the region where the second functional device 60 is formed (i.e., the device region 62) in a plan view. The inner end portion 130A may be integrally formed with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0212] The outer end portion 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is connected to the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end portion 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end portion 130B forms a flush grinding surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end portion 130B may be formed within the first main surface 42 at a distance from the chip sidewalls 44A to 44D.

[0213] The main body portion 130C has a flat surface that extends substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body portion 130C has a connection portion 132 to which the lower end (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in the main body portion 130C at a distance from the inner end portion 130A and the outer end portion 130B. The separation structure 130 can take various forms other than the field insulating film 131.

[0214] Referring to Figures 7 and 8, the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating main surface 52 of the insulating layer 51 to cover the seal conductor 61. The inorganic insulating layer 140 may be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating main surface 52.

[0215] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. Preferably, the first inorganic insulating layer 141 contains USG (undopped silicate glass), which is silicon oxide without impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the dielectric strength on the high-potential coil 23 can be increased.

[0216] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the dielectric breakdown voltage (V / cm) of USG exceeds the dielectric breakdown voltage (V / cm) of silicon nitride. Therefore, when thickening the inorganic insulating layer 140, it is preferable to form the first inorganic insulating layer 141 which is thicker than the second inorganic insulating layer 142.

[0217] The first inorganic insulating layer 141 may contain at least one of BPSG (boron-doped phosphor silicate glass) and PSG (phosphorus silicate glass) as examples of silicon oxide. However, in this case, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable that the first inorganic insulating layer 141 be made of USG in order to increase the dielectric strength on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure consisting of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0218] The inorganic insulating layer 140 covers the entire area of ​​the seal conductor 61 and has a plurality of low-potential pad openings 143 and a plurality of high-potential pad openings 144 formed in the area outside the seal conductor 61. The plurality of low-potential pad openings 143 expose a plurality of low-potential terminals 11, respectively. The plurality of high-potential pad openings 144 expose a plurality of high-potential terminals 12, respectively. The inorganic insulating layer 140 may have overlapping portions that ride up over the periphery of the low-potential terminals 11. The inorganic insulating layer 140 may also have overlapping portions that ride up over the periphery of the high-potential terminals 12.

[0219] The semiconductor device 5 further includes an organic insulating layer 145 formed on an inorganic insulating layer 140. The organic insulating layer 145 may contain a photosensitive resin. The organic insulating layer 145 may contain at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 contains polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0220] The thickness of the organic insulating layer 145 is preferably greater than the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably greater than or equal to the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably 2 μm or more and 10 μm or less. Also, the thickness of the organic insulating layer 145 is preferably 5 μm or more and 50 μm or less. With these structures, the thickness of the inorganic insulating layer 140 and the organic insulating layer 145 can be suppressed, and at the same time, the dielectric strength on the high-potential coil 23 can be appropriately increased by the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145.

[0221] The organic insulating layer 145 includes a first portion 146 that covers the low-potential region and a second portion 147 that covers the high-potential region. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 in between. The first portion 146 has a plurality of low-potential terminal openings 148 that expose a plurality of low-potential terminals 11 (low-potential pad openings 143) in the region outside the seal conductor 61. The first portion 146 may have overlapping portions that ride up on the periphery (overlap portion) of the low-potential pad openings 143.

[0222] The second portion 147 is formed at a distance from the first portion 146, exposing the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high-potential terminal openings 149 that expose a plurality of high-potential terminals 12 (high-potential pad openings 144). The second portion 147 may have overlapping portions that ride up on the periphery (overlap portion) of the high-potential pad openings 144.

[0223] The second section 147 covers the transformers 21A to 21D and the dummy pattern 85 together. Specifically, the second section 147 covers the multiple high-potential coils 23, the multiple high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121 together.

[0224] If the organic insulating layer 145 is not formed, damage may occur to multiple high-potential coils 23, multiple high-potential terminals 12, sealing conductors 61, first high-potential dummy pattern 87, second high-potential dummy pattern 88, and floating dummy pattern 121 due to fillers contained in the package body 2 (molding resin). This type of damage is called filler attack.

[0225] The organic insulating layer 145 protects the multiple high-potential coils 23, multiple high-potential terminals 12, sealing conductors 61, first high-potential dummy pattern 87, second high-potential dummy pattern 88, and floating dummy pattern 121 from fillers contained in the package body 2 (molded resin). The slit between the first part 146 and the second part 147 functions as an anchor to the package body 2 (molded resin).

[0226] A portion of the package body 2 (molded resin) enters the slit between the first portion 146 and the second portion 147 and connects to the inorganic insulating layer 140. This increases the adhesion of the package body 2 (molded resin) to the semiconductor device 5. Of course, the first portion 146 and the second portion 147 may be formed integrally. Also, the organic insulating layer 145 may consist of only one of the first portion 146 and the second portion 147. However, in this case, attention must be paid to filler attack.

[0227] Embodiments of the present invention can be implemented in yet other forms. In the embodiments described above, an example was described in which a first functional device 45 and a second functional device 60 are formed. However, an embodiment may be adopted in which only the second functional device 60 is present, without the first functional device 45. In this case, the dummy pattern 85 may be removed. With this structure, the second functional device 60 can achieve the same effects as described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0228] In other words, when a voltage is applied to the second functional device 60 via the low-potential terminal 11 and the high-potential terminal 12, unwanted conduction between the high-potential terminal 12 and the sealing conductor 61 can be suppressed.

[0229] Furthermore, the above-described embodiment described an example in which a second functional device 60 is formed. However, the second functional device 60 is not necessarily required and may be removed.

[0230] Furthermore, the above-described embodiment described an example in which a dummy pattern 85 is formed. However, the dummy pattern 85 is not necessarily required and may be removed.

[0231] Furthermore, in the embodiments described above, an example was given in which the first functional device 45 consists of a multi-channel type including multiple transformers 21. However, a first functional device 45 consisting of a single-channel type including a single transformer 21 may also be employed.

[0232] <Trans arrangement> Figure 13 is a schematic plan view (top view) showing an example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the semiconductor device 5 mentioned earlier). The transformer chip 300 in this figure includes a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0233] In the transformer chip 300, pads a1 and b1 are connected to one end of the secondary coil L1s that forms the first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of the secondary coil L2s that forms the second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0234] Furthermore, pads a3 and b3 are connected to one end of the secondary coil L3s forming the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of the secondary coil L4s forming the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0235] Note that the primary coil L1p forming the first transformer 301, the primary coil L2p forming the second transformer 302, the primary coil L3p forming the third transformer 303, and the primary coil L4p forming the fourth transformer 304 are not explicitly shown in this figure. However, the primary coils L1p to L4p each have basically the same configuration as the secondary coils L1s to L4s, and are positioned directly below the secondary coils L1s to L4s, facing each of them.

[0236] Specifically, pads a5 and b5 are connected to one end of the primary coil L1p that forms the first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil L1p. In addition, pads a6 and b6 are connected to one end of the primary coil L2p that forms the second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil L2p.

[0237] Furthermore, pads a7 and b7 are connected to one end of the primary coil L3p that forms the third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil L3p. Also, pads a8 and b8 are connected to one end of the primary coil L4p that forms the fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil L4p.

[0238] However, pads a5-a8, b5-b8, c3 and c4, and d3 and d4 are led from the inside of the trans tip 300 to the surface via vias (not shown).

[0239] Of the above multiple pads, pads a1 to a8 correspond to the first current supply pads, pads b1 to b8 correspond to the first voltage measurement pads, pads c1 to c4 correspond to the second current supply pads, and pads d1 to d4 correspond to the second voltage measurement pads.

[0240] Therefore, with the transformer chip 300 in this configuration example, the series resistance component of each coil can be accurately measured during defective product inspection. Consequently, it becomes possible to appropriately reject not only defective products with open circuits in each coil, but also defective products with abnormal resistance values ​​in each coil (for example, short circuits between coils), and ultimately, to prevent defective products from reaching the market.

[0241] Furthermore, for the transformer chip 300 that has passed the above-mentioned defect inspection, the multiple pads can be used as means of connecting to the primary chip and the secondary chip (for example, the controller chip 210 and driver chip 220 mentioned above).

[0242] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 should be connected to the signal input terminal or signal output terminal of the secondary chip, respectively. Also, pads c1 and d1, and pads c2 and d2 should be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0243] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 should be connected to the signal input terminal or signal output terminal of the primary chip, respectively. Also, pads c3 and d3, and pads c4 and d4 should be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0244] Here, the first transformers 301 to the fourth transformers 304 are arranged in a coupled configuration according to their respective signal transmission directions, as shown in Figure 13. Referring to this figure, for example, the first transformer 301 and the second transformer 302, which transmit signals from the primary side chip to the secondary side chip, are connected as a first pair by the first guard ring 305. Similarly, the third transformer 303 and the fourth transformer 304, which transmit signals from the secondary side chip to the primary side chip, are connected as a second pair by the second guard ring 306.

[0245] The reason for this coupling is to ensure voltage resistance between the primary and secondary coils when the primary and secondary coils forming the first to fourth transformers 301 to 304 are stacked in the vertical direction on the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0246] The first guard ring 305 and the second guard ring 306 can be connected to low-impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0247] Furthermore, in the transchip 300, pads c1 and d1 are shared between the secondary coil L1s and the secondary coil L2s. Pads c2 and d2 are shared between the secondary coil L3s and the secondary coil L4s. Pads c3 and d3 are shared between the primary coil L1p and the primary coil L2p. Pads c4 and d4 are shared between the primary coil L3p and the primary coil L4p. By adopting this configuration, it is possible to reduce the number of pads and miniaturize the transchip 300.

[0248] Furthermore, as shown in Figure 13, it is desirable that the primary and secondary coils forming the first to fourth transformers 301 to 304 be wound in a rectangular shape (or a track shape with rounded corners) when viewed from above the transformer tip 300. This configuration increases the area of ​​the overlapping portion between the primary and secondary coils, thereby improving the transmission efficiency of the transformer.

[0249] Of course, the transformer arrangement in this diagram is merely an example, and the number, shape, and placement of coils, as well as the placement of pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to semiconductor devices in general that integrate coils on a semiconductor chip.

[0250] <Gate driver (first embodiment)> Figure 14 shows a first embodiment of the gate driver (a comparative example to be compared with the second embodiment described later). The gate driver 401 of the first embodiment is a semiconductor device that integrates a gate drive circuit 410 for driving a power element 402 (an n-channel IGBT in this figure). The gate driver 401 corresponds to the signal transmission device 200 described earlier. The gate drive circuit 410 corresponds to the driver 224 described earlier.

[0251] The gate drive circuit 410 generates a gate drive signal G1 for the power element 402 in response to the gate control signal S1 and outputs this signal to the gate of the power element 402 from the external terminal T1. For example, if the power element 402 is an n-channel type, the power element 402 is turned on when the gate drive signal G1 is at a high level, and turned off when the gate drive signal G1 is at a low level.

[0252] Figure 15 shows the gate drive operation in the first embodiment (comparative example), and from top to bottom, it depicts the gate control signal S1, the gate drive signal G1, the collector-emitter voltage Vce of the power element 402, and the change in output current Io ΔIo flowing through the power element 402.

[0253] As shown in this figure, when the gate control signal S1 rises from a low level to a high level, the gate drive signal G1 also rises from a low level (VL) to a high level (VH). As a result, the power element 402 transitions from the off state to the on state, so the output current Io flows and the collector-emitter voltage Vce of the power element 402 decreases.

[0254] More specifically, the output current Io begins to increase when the gate drive signal G1 becomes higher than the on-threshold voltage of the power element 402 (ΔIo>0). Subsequently, when the gate drive signal G1 approaches the plateau voltage Vp, the increase in output current Io stops, and the collector-emitter voltage Vce of the power element 402 begins to decrease. Note that the plateau voltage Vp is the power element 40 This is the gate voltage value at which charging and discharging of the Miller capacitance begins during switching.

[0255] Incidentally, region α in this figure is the region that mainly contributes to the generation of surges and noise. On the other hand, region β in this figure is the region that mainly contributes to switching losses. In other words, by driving the power element 402 at a low speed in region α and driving the power element 402 at a high speed in region β, it is possible to achieve both a reduction in surges and noise and a suppression of switching losses.

[0256] However, the rising speed of the gate drive signal G1 and the plateau voltage Vp vary greatly depending on factors such as the type of the power element 402, manufacturing variations, and junction temperature. Therefore, a novel embodiment of a gate driver 401 capable of detecting the state of the power element 402 and actively switching the gate driving capability is proposed below.

[0257] <Gate Driver (Second Embodiment)> FIG. 16 is a diagram showing a second embodiment of a gate driver. The gate driver 401 according to the second embodiment is based on the foregoing first embodiment (FIG. 14), and further includes a driving capability switching circuit 420. Note that both the gate drive circuit 410 and the driving capability switching circuit 420 are integrated in the gate driver 401 (=semiconductor device).

[0258] The driving capability switching circuit 420 includes a high-pass filter 421, a comparator 422, a latch 423, and a delay unit 424.

[0259] The high-pass filter 421 extracts frequency components higher than a cut-off frequency fc from the gate drive signal G1 to generate a time variation signal S421 (=corresponding to the amount of change of the gate drive signal G1 per unit time). The time variation signal S421 can also be understood as a differential signal of the gate drive signal G1.

[0260] The comparator 422 compares the time variation signal S421 input to an inverting input terminal (-) with a threshold REF input to a non-inverting input terminal (+), and generates a comparison signal S422. Accordingly, the comparison signal S422 is at a low level when S421>REF, and is at a high level when S421<REF. Note that the threshold REF may be a variable value that can be arbitrarily adjusted using an external signal or a non-volatile memory or the like.

[0261] Latch 423 receives inputs of gate control signal S1 and comparison signal S422 to generate a drive capability switching signal S423 for the gate drive circuit 410. Preferably, the latch 423 is an RS flip-flop that sets the drive capability switching signal S423 to a high level when the comparison signal S422 input to the set terminal (S) rises to a high level. In this case, the latch 423 should be in a reset state when the gate control signal S1 input to the reset terminal (R) is at a low level (=logic level when off), and conversely, in an unlocked state when the gate control signal S1 is at a high level (=logic level when on). In the reset state of latch 423, the drive capability switching signal S423 is at a low level.

[0262] Furthermore, the gate drive capability of the gate drive circuit 410 may be set to a first drive capability when the drive capability switching signal S423 is at a low level, and to a second drive capability higher than the first drive capability when the drive capability switching signal S423 is at a high level.

[0263] The delay unit 424 delays the gate control signal S1 and outputs it to the reset terminal (R) of the latch 423. By providing such a delay unit 424, the reset state of the latch 423 can be released after the comparison signal S422 falls to a low level during the ON transition period of the power element 402. Therefore, the stability of the drive capability switching operation can be improved.

[0264] The drive capability switching circuit 420, configured as described above, increases the gate drive capability of the gate drive circuit 410 (= ability to charge the gate capacitance of the power element 402) when the time change signal S421, obtained by passing the gate drive signal G1 during the ON transition period of the power element 402 through the high-pass filter 421, becomes smaller than the threshold REF. The operation of the drive capability switching circuit 420 will be described in detail below with reference to the drawings.

[0265] Figure 17 shows the gate drive operation (particularly the gate drive capability switching operation) in the second embodiment, and from top to bottom, the gate control signal S1, gate drive signal G1, time change amount signal S421, comparison signal S422, and drive capability switching signal S423 are depicted.

[0266] At time t1, when the gate control signal S1 rises from a low level to a high level, the gate drive signal G1 begins to rise from a low level (VL). At this time, the time change signal S421 becomes higher than the threshold REF, so the comparison signal S422 falls from a high level to a low level. As a result, the drive capability switching signal S423 is maintained at a low level, and the gate drive capability of the gate drive circuit 410 is set to the first drive capability (low speed). Therefore, during the low-level period of the drive capability switching signal S423 (= low-speed drive period), the gate drive signal G1 rises relatively slowly at the first drive capability.

[0267] At time t2, when the gate drive signal G1 approaches the plateau voltage Vp, the rise of the gate drive signal G1 stagnates, and the time change signal S421 falls below the threshold REF, causing the comparison signal S422 to rise from a low level to a high level. As a result, the drive capability switching signal S423 rises from a low level to a high level, and the gate drive capability of the gate drive circuit 410 is switched from the first drive capability (low speed) to the second drive capability (high speed). Therefore, during the high-level period of the drive capability switching signal S423 (= high-speed drive period), the gate drive signal G1 rises relatively quickly at the second drive capability.

[0268] At time t3, once the charging and discharging of the Miller capacitance during the ON transition period of the power element 402 is complete, the gate drive signal G1 begins to rise again. As a result, a fluctuation occurs in the time change signal S421, and a pulse is generated in the comparison signal S422. However, at this point, the drive capability switching signal S423 is already set to a high level, so the gate drive capability of the gate drive circuit 410 is maintained at the second drive capability (high speed).

[0269] According to the series of gate driving operations described above (particularly the switching operation of gate driving capability), the power element 402 can be driven at low speed in the region α and driven at high speed in the region β. Therefore, it is possible to achieve both reduction of surges and noise and suppression of switching loss.

[0270] <High-pass filter> FIG. 18 is a diagram showing a configuration example of the high-pass filter 421. The high-pass filter 421 of this configuration example includes a capacitor 4211 (capacitance value: C) and a resistor 4212 (resistance value: R).

[0271] A first terminal of the capacitor 4211 is connected to an application terminal for the gate drive signal G1. The second terminal of the capacitor 4211 and the first 1 terminal are both connected to an application terminal for the time variation signal S421. A second terminal of the resistor 4212 is connected to a ground terminal. The cut-off frequency fc of the high-pass filter 421 can be expressed as fc=1 / (2πRC).

[0272] As described above, when a first-order CR high-pass filter is used as the high-pass filter 421, an increase in circuit area can be avoided when integrated into a semiconductor device. In particular, in consideration of integration into the gate driver 401 that requires compatibility with large current and high voltage, it is desirable to employ the high-pass filter 421 as a means for detecting the time variation of the gate drive signal G1.

[0273] <Gate drive circuit> FIG. 19 is a diagram showing a configuration example of the gate drive circuit 410. The gate drive circuit 410 of this configuration example includes a first gate drive unit 411, a second gate drive unit 412, and a logic gate 413.

[0274] The first gate drive unit 411 outputs a charging current Ic1 toward the gate of the power element 402 when the gate control signal S1 is at a high level.

[0275] The second gate driving unit 412 outputs the charging current Ic2 toward the gate of the power element 402 when the AND signal S413 is at a high level.

[0276] The logic gate 413 generates the AND signal S413 of the gate control signal S1 and the driving capability switching signal S423. The AND signal S413 is at a low level when at least one of the gate control signal S1 and the driving capability switching signal S423 is at a low level, and is at a high level when both the gate control signal S1 and the driving capability switching signal S423 are at a high level. That is, the logic gate 413 is configured to switch enabling / disabling of the second gate driving unit 412 in accordance with the driving capability switching signal S423 (corresponding to an instruction from the driving capability switching circuit 420).

[0277] Describing in accordance with the present drawing, during the on-transition period of the power element 402 (S1=H), when the driving capability switching signal S423 is at a low level, the AND signal S413 is fixed at a low level. Accordingly, while the charging current Ic1 is output from the first gate driving unit 411, the charging current Ic2 is not output from the second gate driving unit 412. Such a state corresponds to a state where the gate driving capability of the gate driving circuit 410 is set to the aforementioned first driving capability (low speed).

[0278] On the other hand, during the on-transition period of the power element 402 (S1=H), when the driving capability switching signal S423 is at a high level, the AND signal S413 becomes a high level. Accordingly, the charging current Ic1 is output from the first gate driving unit 411, and at the same time, the charging current Ic2 is also output from the second gate driving unit 412. Such a state corresponds to a state where the gate driving capability of the gate driving circuit 410 is set to the second driving capability (high speed).

[0279] In this example configuration, the first gate drive unit 411 is always enabled, and the second gate drive unit 412 is enabled or disabled according to the drive capability switching signal S423. However, in other configuration examples, the first gate drive unit 411 and the second gate drive unit 412 may be enabled or disabled exclusively according to the drive capability switching signal S423.

[0280] Specifically, in the aforementioned region α, the first gate drive unit 411 may be enabled and the second gate drive unit 412 may be disabled, and conversely, in the aforementioned region β, the first gate drive unit 411 may be disabled and the second gate drive unit 412 may be enabled. In this case, it is preferable to set the drive capability of the first gate drive unit 411 to be smaller than that of the second gate drive unit 412. For example, by increasing the impedance of the first gate drive unit 411 compared to the impedance of the second gate drive unit 412, the charging current Ic1 may be set to be smaller than the charging current Ic2.

[0281] Figure 20 shows an example configuration of the first gate drive unit 411 and the second gate drive unit 412.

[0282] The first gate drive unit 411 includes a constant current source 4111. The constant current source 4111 is connected between the power supply terminal and the gate of the power element 402 and generates a constant charging current Ic1 in accordance with the gate control signal S1. For example, the constant current source 4111 generates the charging current Ic1 when the gate control signal S1 is at a high level and stops generating the charging current Ic1 when the gate control signal S1 is at a low level. In this way, the first gate drive unit 411 charges the gate capacitance of the power element 402 using a constant current drive method.

[0283] The second gate drive unit 412 includes a switch 4121 and a resistor 4122. The switch 4121 and resistor 4122 are connected in series between the power supply terminal and the gate of the power element 402, and generate a charging current Ic2 in accordance with the logical AND signal S413. For example, in the second gate drive unit 412, when the logical AND signal S413 is at a high level, the switch 4121 is turned on and a charging current Ic2 is generated, while when the logical AND signal S413 is at a low level, the switch 4121 is turned off and the generation of the charging current Ic2 is stopped.

[0284] The charging current Ic2 varies depending on the voltage across resistor 4122. Specifically, as the gate capacitance charges and the gate drive signal G1 increases, the charging current Ic2 decreases. In this way, the second gate drive unit 412 charges the gate capacitance of power element 402 using a voltage drive method (which we will call this for convenience to contrast with the constant current drive method mentioned earlier).

[0285] Figure 21 shows the difference between constant current drive and voltage drive methods. As shown on the left side of the figure, in the voltage drive method, the amount of charge injected into the gate changes depending on the variation in the plateau voltage Vp. On the other hand, as shown on the right side of the figure, in the constant current drive method, the amount of charge injected into the gate does not change even if the plateau voltage Vp varies.

[0286] Considering this, it is desirable to adopt a constant current drive method when driving the power element 402 at low speed in the aforementioned region α, prioritizing the raising of the gate drive signal G1 at a desired slope, while adopting a voltage drive method when driving the power element 402 at high speed in the aforementioned region β, prioritizing the raising of the gate drive signal G1 at high speed.

[0287] <Summary> The various embodiments described above will be summarized below.

[0288] For example, the gate driver disclosed herein has a configuration (first configuration) that includes a gate drive circuit configured to generate a gate drive signal for a power element in response to a gate control signal, and a drive capability switching circuit configured to increase the gate drive capability of the gate drive circuit when the time change signal obtained by passing the gate drive signal during the on-transition period of the power element through a high-pass filter becomes smaller than a threshold.

[0289] In addition, in the gate driver according to the first configuration described above, the drive capability switching circuit may be configured to include (second configuration) a high-pass filter configured to extract frequency components higher than the cutoff frequency from the gate drive signal to generate the time change amount signal, a comparator configured to compare the time change amount signal with the threshold to generate a comparison signal, and a latch configured to receive the input of the gate control signal and the comparison signal to generate a drive capability switching signal for the gate drive circuit.

[0290] Furthermore, in the gate driver according to the second configuration described above, the latch may be configured to be in a reset state when the gate control signal is at the logic level of the off state, and in a reset-release state when the gate control signal is at the logic level of the on state (third configuration).

[0291] Furthermore, in the gate driver according to the second or third configuration described above, the drive capability switching circuit may further include a delay unit configured to delay the gate control signal and output it to the latch (fourth configuration).

[0292] Furthermore, in a gate driver according to any of the first to fourth configurations described above, the high-pass filter may be configured as a first-order CR high-pass filter including a capacitor and a resistor (fifth configuration).

[0293] Furthermore, the gate driver according to any of the first to fifth configurations described above may also be configured such that the threshold value is a variable value (sixth configuration).

[0294] Further, in the gate driver according to any one of the first to sixth configurations described above, the gate drive circuit may be configured (the seventh configuration) to include a first gate drive unit, a second gate drive unit, and a logic gate configured to switch enable / disable of the second gate drive unit in response to an instruction from the driving capability switching circuit.

[0295] Further, in the gate driver according to the seventh configuration described above, the first gate drive unit may be configured to charge a gate capacitance of the power element by a constant current driving method, and the second gate drive unit may be configured (the eighth configuration) to be configured to charge the gate capacitance of the power element by a voltage driving method.

[0296] Further, in the gate driver according to the eighth configuration described above, the first gate drive unit may include a constant current source, the constant current source is configured to be connected between a power supply terminal and a gate of the power element, and the second gate drive unit may include a switch and a resistor, wherein the switch and the resistor are configured (the ninth configuration) to be connected in series between the power supply terminal and the gate of the power element.

[0297] Further, in the gate driver according to any one of the first to sixth configurations described above, the gate drive circuit may include a first gate drive unit and a second gate drive unit configured to have a driving capability different from that of the first gate drive unit, and the first gate drive unit and the second gate drive unit may be configured (the tenth configuration) such that enable / disable thereof are exclusively switched respectively in response to an instruction from the driving capability switching circuit.

[0298] Further, in the gate driver according to any one of the first to tenth configurations described above, the gate drive circuit and the driving capability switching circuit may both be configured (the eleventh configuration) to be integrated in a semiconductor device.

[0299] <Other Modifications> Furthermore, various technical features disclosed herein can be modified in various ways, in addition to the embodiments described above, without departing from the spirit of the technical creation. In other words, the embodiments described above should be considered in all respects to be illustrative and not restrictive, and the technical scope of the present invention should be understood to include all modifications that fall within the meaning and scope equivalent to the claims, rather than being limited to the embodiments described above. [Explanation of Symbols]

[0300] 5 Semiconductor Equipment 11, 11A~11F Low potential terminal 12, 12A~12F high potential terminal 21, 21A~21D Transformers 22 Low-potential coil (primary coil) 23. High-potential coil (secondary coil) 24 1st medial end 25 First outer end 26 1st spiral part 27 Second medial end 28 Second outer end 29 Second spiral part 31 1st low potential wiring 32 2nd low potential wiring 33 1st high potential wiring 34 2nd high potential wiring 41 Semiconductor chips 42. First Main Surface 43 Second Main Surface 44A~44D Chip sidewall 45. First Functional Device 51 Insulating layer 52 Insulation main surface 53A~53D Insulating sidewall 55. Bottom insulating layer 56. Top insulating layer 57 Interlayer insulating layer 58 First insulating layer 59 Second insulating layer 60 Second Functional Device 61 Seal conductor 62 Device Area 63 Outer area 64 Seal plug conductor 65 Sea via conductor 66 1st medial area 67 Second medial area 71 Through-wiring 72 Low-voltage connection wiring 73 Pull-out wiring 74 First connecting plug electrode 75 Second connecting plug electrode 76 Pad plug electrodes 77 Circuit board plug electrodes 78 1st electrode layer 79 Second electrode layer 80 Wiring plug electrodes 81 High-potential connection wiring 82 Pad plug electrodes 85 Dummy Patterns 86 High-Potential Dummy Pattern 87. First High-Potential Dummy Pattern 88. Second High-Potential Dummy Pattern 89 First area 90 Second area 91 Third area 92 First connection section 93 Pattern 1 94 Pattern 2 95 Pattern 3 96 First outer line 97 Second outer perimeter line 98 First Intermediate Line 99 First connection line 100 slits 101 First drawer section 102 Second drawer section 103 Third Outer Line 104 Second Intermediate Line 105 Second connection line 106 slits 107 Third drawer section 108 Fourth drawer section 109 Fourth outer perimeter line 110 Third Intermediate Line 111 Third connection line 112 slits 113 Fifth drawer section 114. Sixth drawer section 115 Second connection section 116A~116F High-potential line 117 Slits 121 Floating Dummy Pattern 122A~122F Floating Line 130 Separation structure 130A inner end 130B Outer end 130C Main body 131 Field Insulating Film 132 Connection part 140 Inorganic insulating layer 141 First Inorganic Insulating Layer 142 Second Inorganic Insulating Layer 143 Low-potential pad opening 144 High-potential pad opening 145 Organic insulating layer 146 Part 1 147 Part 2 148 Low potential terminal opening 149 High potential terminal opening 200 Signal transmission device 200p primary circuit system 200s Secondary circuit system 210 Controller chip (first chip) 211 Pulse transmission circuit (pulse generator) 212, 213 buffers 220 Driver chip (second chip) 221, 222 buffers 223 Pulse receiving circuit (RS flip-flop) 224 drivers 230 Transchip (Third Chip) 230a 1st wiring layer (lower layer) 230b 2nd wiring layer (upper layer) 231, 232 transformers 231p, 232p primary coil 231s, 232s Secondary coil 300 Transchips 301 First Transformer 302 Second Transformer 303 Third Transformer 304 4th Transformer 305 First Guard Ring 306 Second Guard Ring 401 Gate Driver 402 Power Element (IGBT) 410 Gate drive circuit 411 First gate drive unit 4111 Constant current source 412 Second gate drive unit 4121 Switch 4122 resistor 413 Logic Gates (AND Gates) 420 Drive capability switching circuit 421 High-Pass Filter 4211 Capacitor 4212 resistor 422 Comparator 423 Latch (RS Flip-Flop) 424 Delay section a1~a8 Pads (corresponding to the first current supply pads) b1~b8 Pads (corresponding to the first voltage measurement pads) c1~c4 pads (corresponding to the second current supply pads) d1~d4 pads (corresponding to the second voltage measurement pads) e1, e2 pads L1p, L2p, L3p, L4p Primary coil L1s, L2s, L3s, L4s secondary coils T1 External terminal T21, T22, T23, T24, T25, T26 External terminals X 1st direction X21, X22, X23 internal terminals Y Second direction Y21, Y22, Y23 wiring Z normal direction Z21, Z22, Z23 Via

Claims

1. A gate drive circuit configured to generate a gate drive signal for a power element in response to a gate control signal, A drive capability switching circuit is configured to increase the gate drive capability of the gate drive circuit when the time-varying signal obtained by passing the gate drive signal during the ON transition period of the power element through a high-pass filter becomes smaller than a threshold, It has, The aforementioned drive capability switching circuit is The high-pass filter is configured to extract frequency components higher than the cutoff frequency from the gate drive signal to generate the time-varying signal, A comparator configured to generate a comparison signal by comparing the time-varying signal with the threshold, An RS flip-flop configured to receive the gate control signal and the comparison signal as inputs and generate a drive capability switching signal for the gate drive circuit, A delay unit configured to delay the gate control signal and output it to the RS flip-flop, Includes, The RS flip-flop is a gate driver that enters a reset state when the gate control signal is at the logic level of the off state, and enters an unlocked state when the gate control signal is at the logic level of the on state.

2. The gate driver according to claim 1, wherein the high-pass filter is a first-order CR high-pass filter including a capacitor and a resistor.

3. The gate driver according to claim 1, wherein the threshold value is a variable value.

4. The gate drive circuit is, First gate drive unit and The second gate drive unit and A logic gate configured to switch the enable / disable status of the second gate drive unit in response to an instruction from the drive capability switching circuit, The gate driver according to claim 1, including the gate driver according to claim 1.

5. The gate driver according to claim 4, wherein the first gate drive unit is configured to charge the gate capacitance of the power element using a constant current drive method, and the second gate drive unit is configured to charge the gate capacitance of the power element using a voltage drive method.

6. The gate driver according to claim 5, wherein the first gate drive unit includes a constant current source, the constant current source is configured to be connected between the power supply terminal and the gate of the power element, and the second gate drive unit includes a switch and a resistor, the switch and the resistor are configured to be connected in series between the power supply terminal and the gate of the power element.

7. The gate drive circuit is, First gate drive unit and A second gate drive unit is configured to have a different driving capability from the first gate drive unit, Includes, The gate driver according to claim 1, wherein the first gate drive unit and the second gate drive unit are exclusively switched on or off in response to an instruction from the drive capability switching circuit.

8. The gate driver according to any one of claims 1 to 7, wherein both the gate drive circuit and the drive capability switching circuit are integrated into a semiconductor device.

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