Signal transmission device and isolation chip

Abstract

A transformer chip of this signal transmission device comprises a substrate, an element insulation layer, and a first transformer and a second transformer provided within the element insulation layer. The first transformer is provided with a first coil, and a second coil which is disposed facing the first coil in a z direction. The second transformer is provided with a first coil, and a second coil which is disposed facing the first coil in the z direction. The second coil of the first transformer and the second coil of the second transformer are electrically connected. The substrate includes a body part, and a substrate insulation layer formed on the surface of the body part. The element insulation layer is layered on the surface of the substrate insulation layer.

Description

[[TECHNICAL FIELD]]

[0001] The present disclosure relates to a signal transmission device and an insulating chip. [[BACKGROUND ART]]

[0002] As an example of a signal transmission device, an insulated gate driver that applies a gate voltage to the gate of a switching element such as a transistor is known. For example, Patent Document 1 describes a semiconductor integrated circuit as an insulated gate driver including a transformer having a primary first coil and a secondary second coil. [[PRIOR ART DOCUMENTS]] [[PATENT DOCUMENTS]]

[0003] [[Patent Document 1]] Japanese Patent Application Laid-Open No. 2013-51547 [[SUMMARY OF THE INVENTION]] [[Problem to be Solved by the Invention]]

[0004] A gate driver includes an insulating element such as a transformer used to insulate a primary-side circuit from a secondary-side circuit. In such a gate driver, improvement of the withstand voltage may be required. Such a problem is not limited to gate drivers, and can similarly occur in signal transmission devices and insulating chips that insulate a primary-side circuit and a secondary-side circuit and transmit signals therebetween. [[Means for Solving the Problem]]

[0005] A signal transmission device according to one aspect of the present disclosure comprises: a first chip including a first circuit; a first die pad on which the first chip is mounted; an insulating chip; a second chip including a second circuit configured to transmit and receive signals with the first circuit via the insulating chip; and a second die pad on which the second chip is mounted, wherein the insulating chip comprises: a substrate; an element insulating layer having a surface and a back surface opposite to the surface and closer to the substrate than the surface; and a first insulating element and a second insulating element provided within the element insulating layer for transmitting the signal, wherein the first insulating element has a first surface located within the element insulating layer closer to the surface than the back surface. The second insulating element comprises a side conductive portion and a first back-side conductive portion located closer to the back surface than the front surface within the element insulating layer and facing the first front-side conductive portion in the thickness direction of the element insulating layer, the second insulating element comprises a second front-side conductive portion located closer to the front surface than the back surface within the element insulating layer and a second back-side conductive portion located closer to the back surface than the front surface within the element insulating layer and facing the second front-side conductive portion in the thickness direction of the element insulating layer, the first back-side conductive portion and the second back-side conductive portion are electrically connected, the substrate includes a main body and a substrate insulating layer formed on the surface of the main body, and the element insulating layer is laminated on the surface of the substrate insulating layer.

[0006] An insulating chip according to one aspect of the present disclosure comprises a substrate, an element insulating layer having a surface and a back surface opposite to the surface and closer to the substrate than the surface, and a first insulating element and a second insulating element provided within the element insulating layer, wherein the first insulating element comprises a first surface-side conductive portion located closer to the surface than the back surface within the element insulating layer, and a first back-side conductive portion located closer to the back surface than the surface within the element insulating layer and facing the first surface-side conductive portion in the thickness direction of the element insulating layer, wherein the second insulating element comprises a second surface-side conductive portion located closer to the surface than the back surface within the element insulating layer, and a second back-side conductive portion located closer to the back surface than the surface within the element insulating layer and facing the second surface-side conductive portion in the thickness direction of the element insulating layer, the first back-side conductive portion and the second back-side conductive portion are electrically connected, and the substrate includes a main body and a substrate insulating layer formed on the surface of the main body, the element insulating layer is laminated on the surface of the substrate insulating layer. [Effects of the Invention]

[0007] The above-described signal transmission device and insulating chip make it possible to improve the dielectric strength. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a schematic circuit diagram showing the circuit configuration of the signal transmission device of the first embodiment. [Figure 2] Figure 2 is a schematic cross-sectional view showing the cross-sectional structure of the signal transmission device shown in Figure 1. [Figure 3] Figure 3 is a schematic plan view showing the planar structure of the transformer chip of the signal transmission device shown in Figure 2. [Figure 4] Figure 4 is a schematic cross-sectional view of the trans-chip shown in Figure 3, cut in a plane perpendicular to the thickness direction of the trans-chip. [Figure 5] Figure 5 is a schematic cross-sectional view showing the cross-sectional structure of the transformer chip shown in Figure 3, along line 5-5. [Figure 6]Figure 6 is a schematic cross-sectional view showing the 6-6 line cross-sectional structure of the transformer chip shown in Figure 3. [Figure 7] Figure 7 is a schematic cross-sectional view showing the cross-sectional structure of the transformer chip shown in Figure 3, specifically the section 7-7. [Figure 8] Figure 8 is a schematic cross-sectional view showing the 8-8 line cross-sectional structure of the transformer chip shown in Figure 3. [Figure 9] Figure 9 is an explanatory diagram illustrating an example of the manufacturing process of a transchip. [Figure 10] Figure 10 is an explanatory diagram illustrating an example of the manufacturing process of a transchip. [Figure 11] Figure 11 is an explanatory diagram illustrating an example of the manufacturing process of a transchip. [Figure 12] Figure 12 is a schematic circuit diagram showing the circuit configuration of the signal transmission device of the second embodiment. [Figure 13] Figure 13 is a schematic cross-sectional view showing the cross-sectional structure of the signal transmission device shown in Figure 12. [Figure 14] Figure 14 is a schematic plan view showing the planar structure of the capacitor chip of the signal transmission device shown in Figure 13. [Figure 15] Figure 15 is a schematic cross-sectional view showing the cross-sectional structure of the capacitor chip shown in Figure 14, cut by a plane perpendicular to the thickness direction of the capacitor chip. [Figure 16] Figure 16 is a schematic cross-sectional view showing the cross-sectional structure of the capacitor chip shown in Figure 14, specifically the 16-16 line cross-section. [Figure 17] Figure 17 is a schematic cross-sectional view showing the cross-sectional structure of the capacitor chip shown in Figure 14, along line 17-17. [Figure 18] Figure 18 is a schematic cross-sectional view showing the 18-18 cross-sectional structure of the capacitor chip shown in Figure 14. [Figure 19] Figure 19 is a schematic cross-sectional view showing the cross-sectional structure of the capacitor chip shown in Figure 14, along line 19-19. [Figure 20] Figure 20 is a schematic cross-sectional view showing the cross-sectional structure of the transformer chip in the modified signal transmission device. [Figure 21] FIG. 21 is a cross-sectional view schematically showing a cross-sectional structure of a transformer chip in a modified example of the signal transmission device. [Figure 22] FIG. 22 is a cross-sectional view schematically showing a cross-sectional structure, taken along a plane orthogonal to the thickness direction of the transformer chip, in a modified example of the signal transmission device. [Figure 23] FIG. 23 is a plan view schematically showing a planar structure of the transformer chip in the signal transmission device of FIG. 22. [Figure 24] FIG. 24 is a cross-sectional view schematically showing a cross-sectional structure, taken along a plane orthogonal to the thickness direction of the transformer chip, in a modified example of the signal transmission device. DESCRIPTION OF EMBODIMENTS

[0009] Hereinafter, embodiments of a signal transmission device and an insulating chip will be described with reference to the drawings. The embodiments described below exemplify configurations and methods for embodying the technical idea, and are not intended to limit the material, shape, structure, arrangement, dimensions, etc. of each component to those described below. It should be noted that, for the sake of simple and clear description, components shown in the drawings are not necessarily drawn to a constant scale. Furthermore, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings merely exemplify embodiments of the present disclosure, and should not be construed as limiting the present disclosure.

[0010] [First Embodiment] The signal transmission device 10 according to the first embodiment will be described with reference to FIGS. 1 to 11. FIG. 1 is a simplified diagram showing an example of a circuit configuration of the signal transmission device 10.

[0011] As shown in Figure 1, the signal transmission device 10 is a device that transmits pulse signals while electrically isolating the primary terminal 11 and the secondary terminal 12. The signal transmission device 10 is a digital isolator, and one example of such is a DC / DC converter. The signal transmission device 10 includes a signal transmission circuit 10A having a primary circuit 13 electrically connected to the primary terminal 11, a secondary circuit 14 electrically connected to the secondary terminal 12, and a transformer 15 that electrically connects the primary circuit 13 and the secondary circuit 14. In this embodiment, the primary circuit 13 corresponds to the "first circuit" and the secondary circuit 14 corresponds to the "second circuit".

[0012] The primary circuit 13 is a circuit configured to operate when a first voltage is applied. The primary circuit 13 is electrically connected to, for example, an external control device (not shown).

[0013] The secondary circuit 14 is a circuit configured to operate when a second voltage different from the first voltage is applied. The second voltage is, for example, higher than the first voltage. Both the first and second voltages are DC voltages. The secondary circuit 14 is electrically connected to, for example, a drive circuit controlled by a control device. An example of a drive circuit is a switching circuit.

[0014] The signal transmission device 10 is configured such that when a control signal from the control device is input to the primary circuit 13 via the primary terminal 11, the signal is transmitted from the primary circuit 13 to the secondary circuit 14 via the transformer 15, and the signal is output from the secondary circuit 14 to the drive circuit via the secondary terminal 12.

[0015] As described above, the signal transmission circuit 10A is electrically isolated between the primary circuit 13 and the secondary circuit 14 by the transformer 15. More specifically, the transformer 15 restricts the transmission of DC voltage between the primary circuit 13 and the secondary circuit 14, while allowing the transmission of pulse signals.

[0016] In other words, the state in which the primary circuit 13 and the secondary circuit 14 are isolated means that the transmission of DC voltage between the primary circuit 13 and the secondary circuit 14 is blocked, while the transmission of pulse signals from the primary circuit 13 to the secondary circuit 14 is permitted. Thus, the secondary circuit 14 is configured to receive signals from the primary circuit 13.

[0017] The dielectric strength of the signal transmission device 10 is, for example, 2500 Vrms or more and 7500 Vrms or less. In this embodiment, the dielectric strength of the signal transmission device 10 is approximately 5700 Vrms. However, the specific value of the dielectric strength of the signal transmission device 10 is not limited to this and is arbitrary. In this embodiment, the ground of the primary circuit 13 and the ground of the secondary circuit 14 are provided independently.

[0018] Next, the detailed configuration of the signal transmission device 10 will be described. The signal transmission device 10 of this embodiment includes two transformers 15 to correspond to the transmission of two types of signals from the primary circuit 13 to the secondary circuit 14. More specifically, the signal transmission device 10 includes a transformer 15 used for transmitting a first signal from the primary circuit 13 to the secondary circuit 14, and a transformer 15 used for transmitting a second signal from the primary circuit 13 to the secondary circuit 14. In this embodiment, the first signal is a signal that includes rising edge information of an external signal input to the signal transmission device 10, and the second signal is a signal that includes falling edge information of an external signal. A pulse signal is generated by the first signal and the second signal.

[0019] For the sake of explanation, the transformer 15 used for transmitting the first signal will be referred to as "transformer 15A," and the transformer 15 used for transmitting the second signal will be referred to as "transformer 15B." In this embodiment, transformer 15A corresponds to the "first signal transformer," and transformer 15B corresponds to the "second signal transformer."

[0020] The signal transmission device 10 includes a primary signal line 16A connecting the primary circuit 13 and the transformer 15A, a primary signal line 16B connecting the primary circuit 13 and the transformer 15B, a secondary signal line 17A connecting the transformer 15A and the secondary circuit 14, and a secondary signal line 17B connecting the secondary circuit 14 and the transformer 15B. The primary signal line 16A transmits a first signal from the primary circuit 13 to the transformer 15A, and the primary signal line 16B transmits a second signal from the primary circuit 13 to the transformer 15B. The secondary signal line 17A transmits a first signal from the transformer 15A to the secondary circuit 14, and the secondary signal line 17B transmits a second signal from the transformer 15B to the secondary circuit 14. Thus, the first signal is transmitted from the primary circuit 13 to the secondary circuit 14 via the primary signal line 16A, the transformer 15A, and the secondary signal line 17A in that order. The second signal is transmitted from the primary circuit 13 to the secondary circuit 14 via the primary signal line 16B, the transformer 15B, and the secondary signal line 17B in that order.

[0021] Transformer 15A transmits the first signal from the primary circuit 13 to the secondary circuit 14, while electrically isolating the primary circuit 13 and the secondary circuit 14. Transformer 15A has a first transformer 21A and a second transformer 22A connected in series with each other. In this embodiment, the first transformer 21A corresponds to the "first insulating element," and the second transformer 22A corresponds to the "second insulating element."

[0022] The signal transmission device 10 includes a pair of connecting signal lines 18A and 19A that connect the first transformer 21A and the second transformer 22A. The pair of connecting signal lines 18A and 19A are signal lines through which the first signal is transmitted.

[0023] In this embodiment, the dielectric strength of each transformer 21A and 22A is, for example, 2500 Vrms or more and 7500 Vrms or less. However, the dielectric strength of each transformer 21A and 22A may be 2500 Vrms or more and 5700 Vrms or less. However, the specific values ​​of the dielectric strength of each transformer 21A and 22A are not limited to these and are arbitrary.

[0024] The first transformer 21A includes a first coil 31A and a second coil 32A that is electrically insulated from the first coil 31A and magnetically coupled to it. The second transformer 22A includes a first coil 33A and a second coil 34A that is electrically insulated from the first coil 33A and magnetically coupled to it.

[0025] The first coil 31A is connected to the primary circuit 13 by the primary signal line 16A, while also being connected to the ground of the primary circuit 13. In other words, the first end of the first coil 31A is electrically connected to the primary circuit 13, and the second end of the first coil 31A is electrically connected to the ground of the primary circuit 13.

[0026] The second coil 32A is connected to the second coil 34A by a pair of connecting signal lines 18A and 19A. In one example, the second coil 32A and the second coil 34A are connected to each other in an electrically floating state. The first end of the second coil 32A and the first end of the second coil 34A are connected by connecting signal line 18A, and the second end of the second coil 32A and the second end of the second coil 34A are connected by connecting signal line 19A. In this way, the second coil 32A and the second coil 34A act as relay coils that relay the transmission of the first signal between the first coil 31A and the first coil 33A.

[0027] The first coil 33A is connected to the secondary circuit 14 by the secondary signal line 17A, while also being connected to the ground of the secondary circuit 14. In other words, the first end of the first coil 33A is electrically connected to the secondary circuit 14, and the second end of the first coil 33A is electrically connected to the ground of the secondary circuit 14.

[0028] Transformer 15B transmits a second signal from the primary circuit 13 to the secondary circuit 14, while electrically isolating the primary circuit 13 and the secondary circuit 14. Transformer 15B has a first transformer 21B and a second transformer 22B connected in series with each other. In this embodiment, the first transformer 21B corresponds to the "first insulating element," and the second transformer 22B corresponds to the "second insulating element."

[0029] The signal transmission device 10 includes a pair of connecting signal lines 18B and 19B that connect the first transformer 21B and the second transformer 22B. The pair of connecting signal lines 18B and 19B are signal lines that transmit the second signal.

[0030] The first transformer 21B includes a first coil 31B and a second coil 32B that is electrically insulated from the first coil 31B and magnetically coupled to it. The second transformer 22B includes a first coil 33B and a second coil 34B that is electrically insulated from the first coil 33B and magnetically coupled to it. The dielectric strength of the first transformer 21B is the same as that of the first transformer 21A, and the dielectric strength of the second transformer 22B is the same as that of the second transformer 22A. The connection configuration of the first transformer 21B and the second transformer 22B is the same as that of the first transformer 21A and the second transformer 22A, so a detailed explanation is omitted.

[0031] In a signal transmission device 10 with this configuration, the first signal output from the primary circuit 13 is transmitted to the secondary circuit 14 via the first transformer 21A and the second transformer 22A. The second signal output from the primary circuit 13 is transmitted to the secondary circuit 14 via the first transformer 21B and the second transformer 22B.

[0032] Figure 2 shows an example of a schematic cross-sectional structure illustrating a part of the internal configuration of the signal transmission device 10. As shown in Figure 2, the signal transmission device 10 is a semiconductor device in which multiple semiconductor chips are packaged together. Although not shown, the package format of the signal transmission device 10 is, for example, SO (Small Outline) type, and in this embodiment, it is SOP (Small Outline Package). Note that the package format of the signal transmission device 10 can be changed as needed.

[0033] The signal transmission device 10 includes a first chip 40, a second chip 50, and a transformer chip 60 as semiconductor chips. The signal transmission device 10 also includes a primary die pad 70 on which the first chip 40 is mounted, a secondary die pad 80 on which the second chip 50 is mounted, and a sealing resin 90 that seals each die pad 70, 80 and each chip 40, 50, 60. In this embodiment, the transformer chip 60 corresponds to an "insulating chip," the primary die pad 70 corresponds to a "first die pad," and the secondary die pad 80 corresponds to a "second die pad."

[0034] The sealing resin 90 is made of an electrically insulating material, for example, a black epoxy resin. The sealing resin 90 is formed in the shape of a rectangular plate with the z-direction as the thickness direction.

[0035] Both the primary die pad 70 and the secondary die pad 80 are formed from a conductive material. In this embodiment, each die pad 70, 80 is formed from a material containing Cu (copper). However, each die pad 70, 80 may be formed from other metallic materials such as Al (aluminum). Furthermore, the materials constituting each die pad 70, 80 are not limited to conductive materials. For example, each die pad 70, 80 may be formed from ceramics such as alumina. In other words, each die pad 70, 80 may be formed from an electrically insulating material.

[0036] Viewed from the z-direction, the primary die pad 70 and the secondary die pad 80 are arranged side by side, spaced apart from each other. Viewed from the z-direction, the arrangement direction of the primary die pad 70 and the secondary die pad 80 is defined as the x-direction. Viewed from the z-direction, the direction perpendicular to the x-direction is defined as the y-direction. Here, the x-direction corresponds to the "first direction," and the y-direction corresponds to the "second direction."

[0037] Both the primary die pad 70 and the secondary die pad 80 are formed in a flat plate shape. In this embodiment, the shape of each die pad 70, 80 as viewed from the z direction is rectangular, with the x direction being the shorter side and the y direction being the longer side. In this embodiment, the area of ​​the secondary die pad 80 as viewed from the z direction is larger than the area of ​​the primary die pad 70 as viewed from the z direction. Note that the shape of each die pad 70, 80 as viewed from the z direction can be arbitrarily changed. For example, the shape of each die pad 70, 80 as viewed from the z direction may be rectangular, with the x direction being the longer side and the y direction being the shorter side.

[0038] In this embodiment, the trans chip 60 is mounted on the secondary die pad 80. That is, both the trans chip 60 and the second chip 50 are mounted on the secondary die pad 80. The trans chip 60 and the second chip 50 are arranged on the secondary die pad 80 spaced apart from each other in the x direction. Therefore, it can be said that each chip 40, 50, and 60 are arranged spaced apart from each other in the x direction. In this embodiment, the chips 40, 50, and 60 are arranged in the order of first chip 40, trans chip 60, and second chip 50 as you move from the primary die pad 70 to the secondary die pad 80 in the x direction. In other words, the trans chip 60 is positioned between the first chip 40 and the second chip 50 in the x direction. In this embodiment, each die pad 70 and 80 is not exposed from the sealing resin 90.

[0039] In order to set the dielectric strength of the signal transmission device 10 to a preset dielectric strength, the die pads 70 and 80 need to be spaced apart from each other. In this embodiment, when viewed from the z direction, the distance in the x direction between the primary die pad 70 and the secondary die pad 80 is greater than the distance in the x direction between the second chip 50 and the transformer chip 60. Therefore, when viewed from the z direction, the distance in the x direction between the first chip 40 and the transformer chip 60 is greater than the distance in the x direction between the second chip 50 and the transformer chip 60. In other words, the transformer chip 60 is positioned closer to the second chip 50 than to the first chip 40.

[0040] When viewed from the z-direction, the first chip 40 has a rectangular shape with a short side and a long side. When viewed from the z-direction, the first chip 40 is mounted on the primary die pad 70 such that its short side is aligned with the x-direction and its long side is aligned with the y-direction.

[0041] The first chip 40 includes a first substrate 43 on which a primary circuit 13 is formed. The first substrate 43 is, for example, a semiconductor substrate. An example of a semiconductor substrate is a substrate formed from a material containing Si (silicon). A wiring layer 44 is formed on the first substrate 43. The wiring layer 44 has a plurality of insulating films stacked in the z direction and a metal layer provided between adjacent insulating films in the z direction. The metal layer constitutes the wiring pattern of the first chip 40. The metal layer is electrically connected to, for example, the primary circuit 13.

[0042] The first chip 40 has a chip main surface 40s and a chip back surface 40r that face opposite each other in the z direction. The first substrate 43 constitutes the chip back surface 40r, and the wiring layer 44 constitutes the chip main surface 40s. The chip back surface 40r faces the primary die pad 70. On the chip main surface 40s side of the first chip 40, there are a plurality of first electrode pads 41 and a plurality of second electrode pads 42. More specifically, each electrode pad 41, 42 is provided so as to be exposed from the chip main surface 40s. Each electrode pad 41, 42 is electrically connected to the primary circuit 13, for example, by the wiring layer 44.

[0043] Multiple first electrode pads 41 are positioned on the chip main surface 40s on the opposite side from the transformer chip 60 to the center of the chip main surface 40s in the x-direction. Although not shown, the multiple first electrode pads 41 are spaced apart from each other in the y-direction. As shown in Figure 2, multiple second electrode pads 42 are positioned on the chip main surface 40s on the side closer to the transformer chip 60 to the center of the chip main surface 40s in the x-direction. Although not shown, the multiple second electrode pads 42 are spaced apart from each other in the y-direction.

[0044] As shown in Figure 2, the first chip 40 is bonded to the primary die pad 70 by a first bonding material 101. More specifically, the first bonding material 101 is interposed between the back surface 40r of the chip and the primary die pad 70. The first bonding material 101 bonds the back surface 40r of the chip to the primary die pad 70. The first bonding material 101 is a conductive bonding material such as solder or Ag (silver) paste. Here, in this embodiment, the first bonding material 101 corresponds to the "first conductive bonding material".

[0045] The first bonding material 101 bonds the first substrate 43 of the first chip 40 to the primary side die pad 70. This electrically connects the first substrate 43 and the primary side die pad 70. Therefore, the primary side circuit 13 is electrically connected to the primary side die pad 70 via the first bonding material 101. The primary side die pad 70 constitutes the ground. Therefore, it can also be said that the primary side circuit 13 is electrically connected to the ground.

[0046] When viewed from the z-direction, the shape of the second chip 50 is rectangular, with a short side and a long side. When viewed from the z-direction, the second chip 50 is mounted on the secondary die pad 80 such that its short side is aligned with the x-direction and its long side is aligned with the y-direction.

[0047] As shown in Figure 2, the second chip 50 includes a second substrate 53 on which the secondary circuit 14 is formed. The second substrate 53 is, for example, a semiconductor substrate. An example of a semiconductor substrate is a Si substrate. A wiring layer 54 is formed on the second substrate 53. The wiring layer 54 has a plurality of insulating films stacked in the z direction and a metal layer provided between adjacent insulating films in the z direction. The metal layer constitutes the wiring pattern of the second chip 50. The metal layer is electrically connected to, for example, the secondary circuit 14.

[0048] The second chip 50 has a chip main surface 50s and a chip back surface 50r that face opposite each other in the z direction. The second substrate 53 constitutes the chip back surface 50r, and the wiring layer 54 constitutes the chip main surface 50s. The chip back surface 50r faces the secondary die pad 80. The chip back surface 50r faces the same side as the chip back surface 40r of the first chip 40, and the chip main surface 50s faces the same side as the chip main surface 40s of the first chip 40. On the chip main surface 50s side of the second chip 50, there are a plurality of first electrode pads 51 and a plurality of second electrode pads 52. More specifically, each electrode pad 51, 52 is provided so as to be exposed from the chip main surface 50s. Each electrode pad 51, 52 is electrically connected to the secondary circuit 14, for example, by the wiring layer 54.

[0049] Multiple first electrode pads 51 are positioned on the main surface 50s of the chip, closer to the transformer chip 60 relative to the center of the chip main surface 50s in the x-direction. Although not shown in the figure, the multiple first electrode pads 51 are spaced apart from each other in the y-direction. Multiple second electrode pads 52 are positioned on the main surface 50s of the chip, opposite to the transformer chip 60 relative to the center of the chip main surface 50s in the x-direction. Although not shown in the figure, the multiple second electrode pads 52 are spaced apart from each other in the y-direction.

[0050] As shown in Figure 2, the second chip 50 is bonded to the secondary die pad 80 by a second bonding material 102. More specifically, the second bonding material 102 is interposed between the back surface 50r of the chip and the secondary die pad 80. The second bonding material 102 bonds the back surface 50r of the chip to the secondary die pad 80. The second bonding material 102 is a conductive bonding material such as solder or Ag paste. In this embodiment, for example, the second bonding material 102 is made of the same material as the first bonding material 101. Here, in this embodiment, the second bonding material 102 corresponds to the "second conductive bonding material".

[0051] The second bonding material 102 bonds the second substrate 53 of the second chip 50 to the secondary die pad 80. This electrically connects the second substrate 53 and the secondary die pad 80. Therefore, the secondary circuit 14 is electrically connected to the secondary die pad 80 via the second bonding material 102. The secondary die pad 80 constitutes the ground. Thus, it can also be said that the secondary circuit 14 is electrically connected to the ground.

[0052] The transformer chip 60 includes both transformers 15A and 15B (see Figure 1). The shape of the transformer chip 60, as viewed from the z direction, is rectangular with a short side and a long side. In this embodiment, as viewed from the z direction, the transformer chip 60 is mounted on the secondary die pad 80 such that the long side is aligned with the y direction and the short side is aligned with the x direction.

[0053] The transformer chip 60 has a chip main surface 60s and a chip back surface 60r that face opposite each other in the z direction. The chip back surface 60r faces the secondary die pad 80. In other words, the chip back surface 60r faces the same side as the chip back surface 50r of the second chip 50, and the chip main surface 60s faces the same side as the chip main surface 50s of the second chip 50.

[0054] The transchip 60 comprises a plurality of first electrode pads 61 and a plurality of second electrode pads 62. Each first electrode pad 61 and each second electrode pad 62 is provided on the side of the chip main surface 60s. More specifically, when viewed from the z direction, each electrode pad 61, 62 is provided so as to be exposed from the chip main surface 60s.

[0055] Multiple first electrode pads 61 are positioned closer to the first chip 40 with respect to the center of the chip main surface 60s in the x-direction. Multiple second electrode pads 62 are positioned closer to the second chip 50 with respect to the center of the chip main surface 60s in the x-direction.

[0056] Multiple wires W are connected to each of the first chip 40, the transformer chip 60, and the second chip 50. Each wire W is a bonding wire formed by a wire bonding apparatus and is made of a conductor such as Au (gold), Al, or Cu.

[0057] Multiple first electrode pads 41 of the first chip 40 are individually connected to multiple primary leads (not shown) by multiple wires W. The primary leads are components that make up the primary terminal 11 in Figure 1. This electrically connects the primary circuit 13 and the primary terminal 11.

[0058] In this embodiment, the primary lead is formed from the same material as the primary die pad 70. The primary lead and the primary die pad 70 may be formed integrally. The primary lead is positioned at a distance from the primary die pad 70 on the opposite side from the secondary die pad 80 and is formed across the sealing resin 90. In other words, the primary lead has a portion that protrudes outward from the sealing resin 90. The portion of the primary lead that protrudes outward from the sealing resin 90 constitutes the external terminal of the signal transmission device 10.

[0059] Multiple second electrode pads 42 of the first chip 40 are individually connected to multiple first electrode pads 61 of the transformer chip 60 by multiple wires W. This electrically connects the primary circuit 13 to each transformer 21A, 21B (see Figure 1). In other words, the wiring layer 44 of the first chip 40, the multiple second electrode pads 42, the multiple wires W, and the multiple first electrode pads 61 each constitute a part of the primary signal lines 16A, 16B (see Figure 1).

[0060] Multiple second electrode pads 62 of the transformer chip 60 are individually connected to multiple first electrode pads 51 of the second chip 50 by multiple wires W. This electrically connects each transformer 22A, 22B to the secondary circuit 14 (see Figure 1). In other words, the multiple second electrode pads 62, the multiple wires W, and the multiple first electrode pads 51 of the second chip 50 each constitute a part of the secondary signal lines 17A, 17B (see Figure 1).

[0061] Multiple second electrode pads 52 of the second chip 50 are individually connected to multiple secondary leads (not shown) by multiple wires W. The secondary leads are components that make up the secondary terminals 12 in Figure 1. This electrically connects the secondary circuit 14 and the secondary terminals 12.

[0062] In this embodiment, the secondary lead is formed from the same material as the secondary die pad 80. The secondary lead and the secondary die pad 80 may be formed integrally. The secondary lead is positioned at a distance from the secondary die pad 80 on the opposite side from the primary die pad 70 and is formed across the sealing resin 90. In other words, the secondary lead has a portion that protrudes outward from the sealing resin 90. The portion of the secondary lead that protrudes outward from the sealing resin 90 constitutes the external terminal of the signal transmission device 10.

[0063] An example of the internal structure of the transchip 60 will be described with reference to Figures 3 to 8. Figure 3 is a schematic plan view showing the planar structure of the transchip 60. Figure 4 is a schematic cross-sectional view showing the cross-sectional structure of the inside of the transchip 60 cut in the xy plane. In Figure 4, hatching lines are omitted for the sake of readability. Figures 5 and 6 are schematic cross-sectional views showing the cross-sectional structure of the transchip 60 cut in the yz plane when the transchip 60 is mounted on the secondary die pad 80. Figures 7 and 8 are schematic cross-sectional views showing the cross-sectional structure of the transchip 60 cut in the xz plane when the transchip 60 is mounted on the secondary die pad 80. Figures 5 to 8 are schematic cross-sectional structures of the transchip 60, and the number of stacked element insulating layers 64, which will be described later, is not limited to the number of stacked element insulating layers 64 shown in Figures 5 to 8. Furthermore, the coils 31A, 31B, 32A, 32B, 33A, 33B, 34A, and 34B in Figures 5 to 8 are shown schematically and therefore do not correspond to the configuration of the coils 31A, 31B, 32A, 32B, 33A, 33B, 34A, and 34B in Figure 3. Also, the first end 36, which will be described later, is omitted in Figures 5 to 8.

[0064] In the following explanation, the direction from the back surface 60r of the transformer chip 60 toward the main surface 60s of the chip will be considered upward, and the direction from the main surface 60s toward the back surface 60r of the chip will be considered downward.

[0065] As shown in Figures 3 and 4, the transformer chip 60 integrates both transformers 15A and 15B into a single chip. In other words, the transformer chip 60 is a separate chip dedicated to both transformers 15A and 15B, distinct from the first chip 40 and the second chip 50.

[0066] As shown in Figures 3 and 4, when viewed from the z direction, both transformers 15A and 15B are spaced apart from each other in the y direction. When viewed from the z direction, the first transformer 21A of transformer 15A and the first transformer 21B of transformer 15B are each positioned closer to the first chip 40 (see Figure 2) than the center of the transformer chip 60 in the x direction. When viewed from the z direction, the second transformer 22A of transformer 15A and the second transformer 22B of transformer 15B are each positioned closer to the second chip 50 (see Figure 2) than the center of the transformer chip 60 in the x direction. The first transformers 21A and 21B are aligned with each other in the x direction and spaced apart from each other in the y direction. The second transformers 22A and 22B are aligned with each other in the x direction and spaced apart from each other in the y direction. The first transformer 21A and the second transformer 22A are aligned with each other in the y direction and spaced apart from each other in the x direction. The first transformer 21B and the second transformer 22B are aligned in the y-direction and spaced apart in the x-direction. In other words, the first transformer 21A (21B) and the second transformer 22A (22B) are spaced apart in the direction of the alignment of the two die pads 70 and 80.

[0067] From the arrangement of the transformers 21A, 21B, 22A, and 22B described above, the first coil 31A of the first transformer 21A and the first coil 33A of the second transformer 22A are arranged with a gap between them in the x-direction. Similarly, the first coil 31B of the first transformer 21B and the first coil 33B of the second transformer 22B are arranged with a gap between them in the x-direction. In other words, the first coil 31A(31B) of the first transformer 21A(21B) and the first coil 33A(33B) of the second transformer 22A(22B) are also arranged with a gap between them in the direction of arrangement of both die pads 70 and 80.

[0068] Furthermore, the first coil 31A of the first transformer 21A and the first coil 31B of the first transformer 21B are arranged with a gap in between in the y-direction. The first coil 33A of the second transformer 22A and the first coil 33B of the second transformer 22B are arranged with a gap in between in the y-direction. In other words, it can be said that the first coil 31A of the first transformer 21A and the first coil 31B of the first transformer 21B are arranged with a gap in between in a direction perpendicular to the arrangement direction of both die pads 70 and 80 when viewed from the z-direction. Also, it can be said that the first coil 33A of the second transformer 22A and the first coil 33B of the second transformer 22B are arranged with a gap in a direction perpendicular to the arrangement direction of both die pads 70 and 80 when viewed from the z-direction.

[0069] As shown in Figures 3, 5, and 6, the first coils 31A, 31B, 33A, and 33B are positioned aligned with each other in the z-direction. Each coil 31A, 31B, 33A, and 33B is appropriately made from one or more of the following materials: Ti (titanium), TiN (titanium nitride), Ta (tantalum), TaN (tantalum nitride), Au, Ag, Cu, Al, and W (tungsten). In this embodiment, each coil 31A, 31B, 33A, and 33B is formed from a material containing Cu.

[0070] As shown in Figure 3, in this embodiment, each coil 31A, 31B, 33A, and 33B has the same shape. Each coil 31A, 31B, 33A, and 33B has a spirally formed coil portion 35, a first end portion 36 drawn inward from the inner circumference of the coil portion 35, and a second end portion 37 drawn outward from the outer circumference of the coil portion 35. The first end portion 36 of each coil 31A and 31B is the end that is electrically connected to the primary circuit 13 (see Figure 1), and the second end portion 37 of each coil 31A and 31B is the end that is electrically connected to the ground of the primary circuit 13. The first end portion 36 of each coil 33A and 33B is the end that is electrically connected to the secondary circuit 14 (see Figure 1), and the second end portion 37 of each coil 33A and 33B is the end that is electrically connected to the ground of the secondary circuit 14.

[0071] As shown in Figure 3, the multiple (three in this embodiment) first electrode pads 61 are individually electrically connected to the first coils 31A and 31B. The multiple first electrode pads 61 are arranged spaced apart from each other in the y-direction. When viewed from the y-direction, the multiple first electrode pads 61 are positioned to overlap with the coil portions 35 of the first coils 31A and 31B. For convenience, in the following description, the three first electrode pads 61 will be referred to as first electrode pads 61A, 61B, and 61C. Here, in this embodiment, the first electrode pads 61A and 61B correspond to the "first pad," and the first electrode pad 61C corresponds to the "third pad."

[0072] Viewed from the z-direction, the first electrode pad 61A is positioned inward from the coil portion 35 of the first coil 31A. More specifically, the first electrode pad 61A is positioned inward from the inner peripheral edge of the coil portion 35 of the first coil 31A, with a gap in between. It can also be said that the coil portion 35 of the first coil 31A is formed to surround the first electrode pad 61A. Alternatively, it can be said that the first electrode pad 61A is positioned inside the first coil 31A. The first end portion 36 of the first coil 31A is electrically connected to the first electrode pad 61A.

[0073] The first electrode pad 61A is positioned so as to overlap with the first end 36 of the first coil 31A when viewed from the y-direction. When viewed from the z-direction, the first electrode pad 61A is positioned offset from the center of the first coil 31A. When viewed from the z-direction, it can also be said that the first electrode pad 61A is positioned so as not to overlap with the center of the first coil 31A. Here, the center of the first coil 31A is the center of the coil portion 35 of the first coil 31A. In other words, the center of the first coil 31A can also be said to be the winding center of the coil portion 35 of the first coil 31A. In this embodiment, the first electrode pad 61A is positioned offset in the y-direction from the center of the coil portion 35 of the first coil 31A. More specifically, the first electrode pad 61A is positioned in the y-direction offset from the center of the coil portion 35 of the first coil 31A towards the first coil 31B. This arrangement of the first electrode pad 61A reduces the eddy currents generated in the first electrode pad 61A due to the magnetic flux generated from the first coil 31A.

[0074] Viewed from the z-direction, the first electrode pad 61B is positioned inward from the coil portion 35 of the first coil 31B. More specifically, the first electrode pad 61B is positioned inward from the inner peripheral edge of the coil portion 35 of the first coil 31B, with a gap in between. It can also be said that the coil portion 35 of the first coil 31B is formed to surround the first electrode pad 61B. Alternatively, it can be said that the first electrode pad 61B is positioned inside the first coil 31B. The first end portion 36 of the first coil 31B is electrically connected to the first electrode pad 61B.

[0075] The first electrode pad 61B is positioned so as to overlap with the first end 36 of the first coil 31B when viewed from the y-direction. When viewed from the z-direction, the first electrode pad 61B is positioned offset from the center of the first coil 31B. When viewed from the z-direction, it can also be said that the first electrode pad 61B is positioned so as not to overlap with the center of the first coil 31B. Here, the center of the first coil 31B is the center of the coil portion 35 of the first coil 31B. In other words, the center of the first coil 31B can also be said to be the winding center of the coil portion 35 of the first coil 31B. In this embodiment, the first electrode pad 61B is positioned offset in the y-direction from the center of the coil portion 35 of the first coil 31B. More specifically, the first electrode pad 61B is positioned in the y-direction offset from the center of the coil portion 35 of the first coil 31B, closer to the first coil 31A. This arrangement of the first electrode pad 61B reduces the eddy currents generated in the first electrode pad 61B due to the magnetic flux generated from the first coil 31B.

[0076] Viewed from the z-direction, the first electrode pad 61C is positioned between the coil portion 35 of the first coil 31A and the coil portion 35 of the first coil 31B in the y-direction. In other words, viewed from the z-direction, the first electrode pad 61C is positioned outward from the coil portions 35 of the first coils 31A and 31B. Viewed from the z-direction, it can also be said that the first electrode pad 61C is positioned between the first electrode pad 61A and the first electrode pad 61B in the y-direction. The second end 37 of the first coil 31A and the second end 37 of the first coil 31B are electrically connected to the first electrode pad 61C.

[0077] Multiple (three in this embodiment) second electrode pads 62 are individually electrically connected to the first coils 33A and 33B. The multiple second electrode pads 62 are positioned so as to overlap with the coil portions 35 of the first coils 33A and 33B when viewed from the y-direction. Each electrode pad 61, 62 is formed from a material including, for example, Al. For convenience, in the following description, the three second electrode pads 62 will be referred to as second electrode pads 62A, 62B, and 62C. Here, in this embodiment, second electrode pads 62A and 62B correspond to the "second pad," and second electrode pad 62C corresponds to the "fourth pad."

[0078] Viewed from the z-direction, the second electrode pad 62A is positioned inward from the coil portion 35 of the first coil 33A. More specifically, the second electrode pad 62A is positioned inward from the inner peripheral edge of the coil portion 35 of the first coil 33A, with a gap in between. It can also be said that the coil portion 35 of the first coil 33A is formed to surround the second electrode pad 62A. Alternatively, it can be said that the second electrode pad 62A is positioned inside the first coil 33A. The first end portion 36 of the first coil 33A is electrically connected to the second electrode pad 62A.

[0079] The second electrode pad 62A is positioned so as to overlap with the first end 36 of the first coil 33A when viewed from the y-direction. When viewed from the z-direction, the second electrode pad 62A is positioned offset from the center of the first coil 33A. When viewed from the z-direction, it can also be said that the second electrode pad 62A is positioned so as not to overlap with the center of the first coil 33A. Here, the center of the first coil 33A is the center of the coil portion 35 of the first coil 33A. In other words, the center of the first coil 33A can also be said to be the winding center of the coil portion 35 of the first coil 33A. In this embodiment, the second electrode pad 62A is positioned offset in the y-direction from the center of the coil portion 35 of the first coil 33A. More specifically, the second electrode pad 62A is positioned in the y-direction offset from the center of the coil portion 35 of the first coil 33A towards the first coil 33B. This arrangement of the second electrode pad 62A reduces the eddy currents generated in the second electrode pad 62A due to the magnetic flux generated from the first coil 33A.

[0080] Viewed from the z-direction, the second electrode pad 62B is positioned inward from the coil portion 35 of the first coil 33B. More specifically, the second electrode pad 62B is positioned inward from the inner peripheral edge of the coil portion 35 of the first coil 33B, with a gap in between. It can also be said that the coil portion 35 of the first coil 33B is formed to surround the second electrode pad 62B. Alternatively, it can be said that the second electrode pad 62B is positioned inside the first coil 33B. The first end portion 36 of the first coil 33B is electrically connected to the second electrode pad 62B.

[0081] The second electrode pad 62B is positioned so as to overlap with the first end 36 of the first coil 33B when viewed from the y-direction. When viewed from the z-direction, the second electrode pad 62B is positioned offset from the center of the first coil 33B. When viewed from the z-direction, it can also be said that the second electrode pad 62B is positioned so as not to overlap with the center of the first coil 33B. Here, the center of the first coil 33B is the center of the coil portion 35 of the first coil 33B. In other words, the center of the first coil 33B can also be said to be the winding center of the coil portion 35 of the first coil 33B. In this embodiment, the second electrode pad 62B is positioned offset in the y-direction from the center of the coil portion 35 of the first coil 33B. More specifically, the second electrode pad 62B is positioned in the y-direction offset from the center of the coil portion 35 of the first coil 33B, closer to the first coil 33A. This arrangement of the second electrode pad 62B reduces the eddy currents generated in the second electrode pad 62B due to the magnetic flux generated from the first coil 33B.

[0082] Viewed from the z-direction, the second electrode pad 62C is positioned between the coil portion 35 of the first coil 33A and the coil portion 35 of the first coil 33B in the y-direction. In other words, viewed from the z-direction, the second electrode pad 62C is positioned outward from the coil portions 35 of the first coils 33A and 33B. Viewed from the z-direction, it can also be said that the second electrode pad 62C is positioned between the second electrode pad 62A and the second electrode pad 62B in the y-direction. The second electrode pad 62C is electrically connected to the second end 37 of the first coil 33A and the second end 37 of the first coil 33B.

[0083] The arrangement of the first electrode pads 61A-61C and the second electrode pads 62A-62C is not limited to the arrangement shown in Figure 3, but can be changed as desired. For example, when viewed from the z direction, the first electrode pad 61A may be positioned offset in the x direction from the center of the coil portion 35 of the first coil 31A. The same changes can be made for the first electrode pad 61B and the second electrode pads 62A and 62B. Also, in another example, when viewed from the z direction, the first electrode pad 61A may be positioned to overlap with the coil portion 35 of the first coil 31A. The same changes can be made for the first electrode pad 61B and the second electrode pads 62A and 62B.

[0084] As shown in Figures 3 and 4, the second coil 32A of the first transformer 21A is positioned to overlap with the first coil 31A of the first transformer 21A when viewed from the z direction. The second coil 32B of the first transformer 21B is positioned to overlap with the first coil 31B of the first transformer 21B when viewed from the z direction. The second coil 34A of the second transformer 22A is positioned to overlap with the first coil 33A of the second transformer 22A when viewed from the z direction. The second coil 34B of the second transformer 22B is positioned to overlap with the first coil 33B of the second transformer 22B when viewed from the z direction.

[0085] From the arrangement of the coils 31A-34A and 31B-34B, the second coil 32A and the second coil 34A are arranged with a gap between them in the x-direction. Similarly, the second coil 32B and the second coil 34B are arranged with a gap between them in the x-direction. In other words, the second coil 32A (32B) of the first transformer 21A (21B) and the second coil 34A (34B) of the second transformer 22A (22B) are also arranged with a gap between them in the direction of arrangement of both die pads 70 and 80.

[0086] Furthermore, the second coil 32A and the second coil 32B are arranged with a gap between them in the y-direction. The second coil 34A and the second coil 34B are arranged with a gap between them in the y-direction. In other words, the second coil 32A of the first transformer 21A and the second coil 32B of the first transformer 21B are arranged with a gap between them in a direction perpendicular to the arrangement direction of both die pads 70 and 80 when viewed from the z-direction. Also, the second coil 34A of the second transformer 22A and the second coil 34B of the second transformer 22B are arranged with a gap between them in a direction perpendicular to the arrangement direction of both die pads 70 and 80 when viewed from the z-direction.

[0087] The first end 36 of the second coil 32A and the first end 36 of the second coil 34A are connected to each other, and the second end 37 of the second coil 32A and the second end 37 of the second coil 34A are connected to each other. The first end 36 of the second coil 32B and the first end 36 of the second coil 34B are connected to each other, and the second end 37 of the second coil 32B and the second end 37 of the second coil 34B are connected to each other.

[0088] As shown in Figure 7, both the first end 36 of the second coil 32A and the first end 36 of the second coil 34A are provided on an element insulating layer 64 that is different from the coil portion 35 of the second coils 32A and 34A among the multiple element insulating layers 64. In this embodiment, the first end 36 of the second coils 32A and 34A is provided on an element insulating layer 64 that is closer to the substrate 63 than the coil portion 35 of the second coils 32A and 34A among the multiple element insulating layers 64. On the other hand, both the second end 37 of the second coil 32A and the second end 37 of the second coil 34A are provided on the same element insulating layer 64 as the coil portion 35 of the second coils 32A and 34A among the multiple element insulating layers 64.

[0089] As shown in Figure 8, both the first end 36 of the second coil 32B and the first end 36 of the second coil 34B are provided on a different element insulating layer 64 from the coil portion 35 of the second coils 32B and 34B among the multiple element insulating layers 64. On the other hand, both the second end 37 of the second coil 32B and the second end 37 of the second coil 34B are provided on the same element insulating layer 64 as the coil portion 35 of the second coils 32B and 34B among the multiple element insulating layers 64. The arrangement of the first end 36 and the second end 37 of the second coils 32B and 34B is the same as the arrangement of the first end 36 and the second end 37 of the second coils 32A and 34A.

[0090] In this embodiment, the number of turns of the first coil 31A is the same as the number of turns of the second coil 32A. Also in this embodiment, the outer diameter of the coil portion 35 of the first coil 31A is the same as the outer diameter of the coil portion 35 of the second coil 32A. The same relationship applies to the first coil 31B and the second coil 32B, the first coil 33A and the second coil 34A, and the first coil 33B and the second coil 34B as to the first coil 31A and the second coil 32A.

[0091] As shown in Figure 3, in this embodiment, the winding direction of the coil portion 35 of the first coil 31A is the same as the winding direction of the coil portion 35 of the first coil 31B. The winding direction of the coil portion 35 of the first coil 33A is the same as the winding direction of the coil portion 35 of the first coil 33B. Therefore, as shown in Figure 3, the first coil 31A and the first coil 31B are arranged to be point-symmetric with respect to the first electrode pad 61C. Also, the first coil 33A and the first coil 33B are arranged to be point-symmetric with respect to the second electrode pad 62C.

[0092] As shown in Figures 5 to 8, the transformer chip 60 has a substrate 63 and an element insulating layer 64 formed on the substrate 63. The substrate 63 is formed of, for example, a semiconductor substrate. In one example, the substrate 63 is a semiconductor substrate formed of a material containing Si. The substrate 63 may be a wide-bandgap semiconductor or a compound semiconductor. Alternatively, instead of a semiconductor substrate, the substrate 63 may be an insulating substrate formed of a material containing glass, or an insulating substrate formed of a material containing ceramics such as alumina.

[0093] A wide-bandgap semiconductor is a semiconductor substrate having a bandgap of 2.0 eV or greater. The wide-bandgap semiconductor may be SiC (silicon carbide). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may contain at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0094] The substrate 63 includes a main body 63A and a substrate insulating layer 63B. The substrate 63 has a substrate surface 63s and a substrate back surface 63r that face opposite each other in the z direction. The substrate surface 63s faces the same side as the surface 64s of the element insulating layer 64, and the substrate back surface 63r faces the same side as the back surface 64r of the element insulating layer 64.

[0095] The main body portion 63A has a front surface 63As and a back surface 63Ar that face opposite each other in the z direction. The front surface 63As faces the same side as the front surface 64s of the element insulating layer 64, and the back surface 63Ar faces the same side as the back surface 64r of the element insulating layer 64. The back surface 63Ar of the main body portion 63A constitutes the back surface 63r of the substrate 63.

[0096] In this embodiment, an SOI (Silicon on Insulator) substrate is used as the substrate 63. Therefore, the main body 63A includes a first semiconductor layer 63AA, a second semiconductor layer 63AB, and an oxide film 63AC. The first semiconductor layer 63AA and the second semiconductor layer 63AB are formed from a material containing, for example, Si. The oxide film 63AC is a silicon oxide film. The oxide film 63AC is positioned between the first semiconductor layer 63AA and the second semiconductor layer 63AB in the z direction. The first semiconductor layer 63AA constitutes the surface 63As of the main body 63A, and the second semiconductor layer 63AB constitutes the back surface 63Ar of the main body 63A (the back surface 63r of the substrate 63).

[0097] The substrate insulating layer 63B has a surface 63Bs and a back surface 63Br that face opposite each other in the z direction. The surface 63Bs faces the same side as the surface 63As of the main body 63A, and the back surface 63Br faces the same side as the back surface 63Ar of the main body 63A. The substrate insulating layer 63B is laminated on the main body 63A. In this embodiment, the substrate insulating layer 63B is formed on the surface 63As of the main body 63A. Therefore, the back surface 63Br of the substrate insulating layer 63B is in contact with the surface 63As of the main body 63A. It can also be said that the substrate insulating layer 63B is formed on the first semiconductor layer 63AA. Therefore, the back surface 63Br of the substrate insulating layer 63B is in contact with the first semiconductor layer 63AA. The surface 63Bs of the substrate insulating layer 63B constitute the substrate surface 63s of the substrate 63.

[0098] The substrate insulating layer 63B includes an oxide film. In this embodiment, the substrate insulating layer 63B is an LP (Low Pressure)-TEOS (tetraethyl orthosilicate) oxide film. The TEOS oxide film is a silicon oxide film formed by the reaction of an organic TEOS gas and an oxygen-based gas using a reduced-pressure CVD (Chemical Vapor Deposition) method.

[0099] Multiple element insulating layers 64 are stacked in the z direction on the surface 63Bs of the substrate insulating layer 63B. In other words, the z direction can also be said to be the thickness direction of the element insulating layer 64. In this embodiment, the total thickness of the multiple element insulating layers 64 is greater than the thickness of the substrate 63. However, the number of stacked element insulating layers 64 is set according to the dielectric strength required for the transformer chip 60. Therefore, depending on the number of stacked element insulating layers 64, the total thickness of the multiple element insulating layers 64 may be less than the thickness of the substrate 63. Here, the thickness of the substrate 63 is the distance in the z direction between the surface 63Bs of the substrate insulating layer 63B and the back surface 63Ar of the main body 63A.

[0100] The element insulating layer 64 has a first insulating film 64A and a second insulating film 64B formed on the first insulating film 64A. The first insulating film 64A is, for example, an etching stopper film and is formed from a material containing SiN (silicon nitride), SiC, SiCN (nitrogen-doped silicon carbide), etc. The first insulating film 64A also has a function of preventing the diffusion of Cu, for example. In other words, the first insulating film 64A can also be said to be a Cu diffusion prevention film. In this embodiment, the first insulating film 64A is formed from a material containing SiN. The second insulating film 64B is, for example, an interlayer insulating film and is an oxide film formed from a material containing SiO2 (silicon oxide). As shown in Figures 5 and 6, the thickness of the second insulating film 64B is greater than the thickness of the first insulating film 64A. The thickness of the first insulating film 64A may be 50 nm or more and less than 1000 nm. The thickness of the second insulating film 64B may be 500 nm or more and 5000 nm or less. In this embodiment, the thickness of the first insulating film 64A is, for example, about 300 nm, and the thickness of the second insulating film 64B is, for example, about 2000 nm.

[0101] The surface 64s of the element insulating layer 64 is provided with a first electrode pad 61 and a second electrode pad 62. The surface 64s of the element insulating layer 64 is the surface of the uppermost element insulating layer 64 among a plurality of element insulating layers 64 stacked in the z direction.

[0102] The back surface 64r of the element insulating layer 64 faces away from the front surface 64s of the element insulating layer 64 and faces the substrate surface 63s of the substrate 63. In this embodiment, the back surface 64r of the element insulating layer 64 is in contact with the substrate surface 63s of the substrate 63. The back surface 64r of the element insulating layer 64 is the back surface of the bottommost element insulating layer 64 among the multiple element insulating layers 64 stacked in the z direction.

[0103] The transchip 60 further comprises a protective film 65 formed on the surface 64s of the element insulating layer 64, and a passivation film 66 formed on the protective film 65. The protective film 65 is a film that protects the element insulating layer 64 and is formed of, for example, a silicon oxide film. The passivation film 66 is a surface protective film of the transchip 60 and is formed of, for example, a silicon nitride film. The passivation film 66 constitutes the main chip surface 60s of the transchip 60.

[0104] The first electrode pad 61 and the second electrode pad 62 are covered by a protective film 65 and a passivation film 66. On the other hand, the protective film 65 and the passivation film 66 have openings that expose the first electrode pad 61 and the second electrode pad 62. As a result, each electrode pad 61, 62 has an exposed surface for connecting the wire W.

[0105] As shown in Figure 5, the first transformers 21A and 21B are provided within the element insulating layer 64. In other words, the first coil 31A and the second coil 32A of the first transformer 21A, and the first coil 31B and the second coil 32B of the first transformer 21B are each provided within the element insulating layer 64.

[0106] The first coil 31A and the second coil 32A of the first transformer 21A are positioned opposite each other in the z direction. The first coil 31A and the second coil 32A are positioned spaced apart from each other in the z direction. One or more element insulating layers 64 are interposed between the first coil 31A and the second coil 32A in the z direction. The first coil 31A is positioned closer to the surface 64s than the surface 64r within the element insulating layer 64, and the second coil 32A is positioned closer to the surface 64r than the surface 64s within the element insulating layer 64. In other words, the first coil 31A is positioned closer to the surface 64s of the multiple element insulating layers 64 relative to the second coil 32A. To put it another way, the second coil 32A is positioned closer to the surface 64r of the multiple element insulating layers 64 relative to the first coil 31A.

[0107] The first coil 31B and the second coil 32B of the first transformer 21B are positioned opposite each other in the z direction. The first coil 31B and the second coil 32B are positioned spaced apart from each other in the z direction. One or more element insulating layers 64 are interposed between the first coil 31B and the second coil 32B in the z direction. The first coil 31B is positioned closer to the surface 64s than the surface 64r within the element insulating layer 64, and the second coil 32B is positioned closer to the surface 64r than the surface 64s within the element insulating layer 64. In other words, the first coil 31B is positioned closer to the surface 64s of the multiple element insulating layers 64 relative to the second coil 32B. To put it another way, the second coil 32B is positioned closer to the surface 64r of the multiple element insulating layers 64 relative to the first coil 31B.

[0108] The first coils 31A and 31B are positioned aligned with each other in the z-direction. In other words, the first coils 31A and 31B are located on the same element insulating layer 64 among the multiple element insulating layers 64. The second coils 32A and 32B are positioned aligned with each other in the z-direction. In other words, the second coils 32A and 32B are located on the same element insulating layer 64 among the multiple element insulating layers 64. The second coils 32A and 32B are spaced apart from the back surface 64r of the element insulating layer 64 in the z-direction. That is, one or more element insulating layers 64 are interposed between the second coils 32A and 32B and the back surface 64r of the element insulating layer 64.

[0109] The first coils 31A and 31B are provided penetrating the single-layer element insulating layer 64 in the z-direction. In other words, openings for forming the first coils 31A and 31B are provided in both the first insulating film 64A and the second insulating film 64B of the single-layer element insulating layer 64. The first coils 31A and 31B are formed by embedding conductive members made of a Cu-containing material into these openings. The second coils 32A and 32B are also formed in the same way as the first coils 31A and 31B, by embedding conductive members made of a Cu-containing material into their openings.

[0110] The second coils 32A and 32B may be made of a different material than the first coils 31A and 31B. The second coils 32A and 32B may be formed by embedding a conductive member made of a material including, for example, Al, within the opening.

[0111] As shown in Figure 6, the first coil 33A and the second coil 34A of the second transformer 22A are positioned opposite each other in the z direction. The first coil 33A and the second coil 34A are spaced apart from each other in the z direction. One or more element insulating layers 64 are interposed between the first coil 33A and the second coil 34A in the z direction. The first coil 33A is positioned closer to the surface 64s than the surface 64r within the element insulating layer 64, and the second coil 34A is positioned closer to the surface 64r than the surface 64s within the element insulating layer 64. In other words, the first coil 33A is positioned closer to the surface 64s than the second coil 34A among the multiple element insulating layers 64. To put it another way, the second coil 34A is positioned closer to the surface 64r than the first coil 33A among the multiple element insulating layers 64.

[0112] The first coil 33B and the second coil 34B of the second transformer 22B are positioned opposite each other in the z direction. The first coil 33B and the second coil 34B are positioned spaced apart from each other in the z direction. One or more element insulating layers 64 are interposed between the first coil 33B and the second coil 34B in the z direction. The first coil 33B is positioned closer to the surface 64s than the surface 64r within the element insulating layer 64, and the second coil 34B is positioned closer to the surface 64r than the surface 64s within the element insulating layer 64. In other words, the first coil 33B is positioned closer to the surface 64s than the second coil 34B among the multiple element insulating layers 64. To put it another way, the second coil 34B is positioned closer to the surface 64r than the first coil 33B among the multiple element insulating layers 64.

[0113] The first coils 33A and 33B are positioned aligned with each other in the z-direction. In other words, the first coils 33A and 33B are located on the same element insulating layer 64 among the multiple element insulating layers 64. The second coils 34A and 34B are positioned aligned with each other in the z-direction. In other words, the second coils 34A and 34B are located on the same element insulating layer 64 among the multiple element insulating layers 64. The second coils 34A and 34B are spaced apart from the back surface 64r of the element insulating layer 64 in the z-direction. That is, one or more element insulating layers 64 are interposed between the second coils 34A and 34B and the back surface 64r of the element insulating layer 64. In this embodiment, as shown in Figures 5 to 8, the first coils 33A and 33B and the first coils 31A and 31B are positioned aligned with each other in the z-direction. The second coils 34A and 34B and the second coils 32A and 32B are positioned at the same location in the z-direction.

[0114] In this embodiment, the first coils 31A and 31B correspond to the "first surface-side conductive part" and the "first surface-side coil," and the second coils 32A and 32B correspond to the "first back-side conductive part" and the "first back-side coil." The first coils 33A and 33B correspond to the "second surface-side conductive part" and the "second surface-side coil," and the second coils 34A and 34B correspond to the "second back-side conductive part" and the "second back-side coil."

[0115] As shown in Figures 3 and 5, the first end 36 of the first coil 31A has a portion that faces the first electrode pad 61A in the z direction. The first end 36 of the first coil 31A is connected to the first electrode pad 61A by a connecting wire 67A. The connecting wire 67A is a via that penetrates the element insulating layer 64 in the z direction and is appropriately selected from, for example, one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W. Preferably, the connecting wire 67A is formed of W, Ti, or TiN. Viewed from the z direction, the connecting wire 67A is positioned to overlap both the first end 36 of the first coil 31A and the first electrode pad 61A, and extends in the z direction to connect the first end 36 and the first electrode pad 61A.

[0116] The first end 36 of the first coil 31B has a portion that faces the first electrode pad 61B in the z-direction. The first end 36 of the first coil 31B is connected to the first electrode pad 61B by a connecting wire 67B. As shown in Figure 5, the material and connection method of the connecting wire 67B are the same as those of the connecting wire 67A.

[0117] The second end 37 of the first coil 31A and the second end 37 of the first coil 31B have portions that face the first electrode pad 61C in the z direction. The second end 37 of the first coils 31A and 31B are connected to the first electrode pad 61C by a connecting wire 68A. The connecting wire 68A is a via that penetrates the element insulating layer 64 in the z direction, similar to, for example, the connecting wire 67A, and is made of one or more of the following materials as appropriate: Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W. In this embodiment, the connecting wire 68A is made of the same material as the connecting wire 67A. Viewed from the z direction, the connecting wire 68A is positioned to overlap with both the second end 37 of the first coils 31A and 31B and the first electrode pad 61C, and extends in the z direction to connect these second end 37s to the first electrode pad 61C.

[0118] As shown in Figures 3 and 6, the first end 36 of the first coil 33A has a portion that faces the second electrode pad 62A in the z-direction. The first end 36 of the first coil 33A is connected to the second electrode pad 62A by a connecting wire 67C. As shown in Figure 6, the material and connection configuration of the connecting wire 67C are the same as those of the connecting wire 67A (see Figure 5).

[0119] The first end 36 of the first coil 33B has a portion that faces the second electrode pad 62B in the z-direction. The first end 36 of the first coil 33B is connected to the second electrode pad 62B by a connecting wire 67D. As shown in Figure 6, the material and connection method of the connecting wire 67D are the same as those of the connecting wire 67A.

[0120] The second end 37 of the first coil 33A and the second end 37 of the first coil 33B have portions that face the second electrode pad 62C in the z direction. The second end 37 of the first coils 33A and 33B are connected to the second electrode pad 62C by a connecting wire 68B. As shown in Figure 6, the material and connection configuration of the connecting wire 68B are the same as those of the connecting wire 68A (see Figure 5).

[0121] The transchip 60 is bonded to the secondary die pad 80 by a third bonding material 103. More specifically, the third bonding material 103 is interposed between the back surface 63Ar (chip back surface 60r) of the main body portion 63A of the substrate 63 and the secondary die pad 80. The third bonding material 103 bonds the back surface 63Ar (chip back surface 60r) of the main body portion 63A to the secondary die pad 80. In this embodiment, the third bonding material 103 is in contact with the entire surface of the back surface 63Ar (chip back surface 60r) of the main body portion 63A. The third bonding material 103 is an insulating bonding material such as epoxy resin. In other words, the third bonding material 103 is made of a different material from the first bonding material 101 and the second bonding material 102 (both see Figure 2). Here, in this embodiment, the third bonding material 103 corresponds to the "bonding material".

[0122] Next, an example of the dimensional relationships in the signal transmission device 10 will be described with reference to Figures 2, 5, and 6. As shown in Figure 2, the thickness TC3 of the trans tip 60 is greater than the thickness TC1 of the first tip 40 and the thickness TC2 of the second tip 50. Here, the thickness TC3 of the trans tip 60 is the distance in the z direction between the main surface 60s and the back surface 60r of the trans tip 60. The thickness TC1 of the first tip 40 is the distance in the z direction between the main surface 40s and the back surface 40r of the first tip 40. The thickness TC2 of the second tip 50 is the distance in the z direction between the main surface 50s and the back surface 50r of the second tip 50.

[0123] The thickness TS3 of the third bonding material 103 is equal to the thickness TS1 of the first bonding material 101 and the thickness TS2 of the second bonding material 102. Here, in this embodiment, the thickness TS3 of the third bonding material 103 corresponds to the "thickness of the bonding material". The thickness TS3 of the third bonding material 103 is the distance in the z direction between the secondary die pad 80 and the back surface 60r of the trans chip 60.

[0124] The thickness TS1 of the first bonding material 101 is the distance in the z direction between the primary die pad 70 and the back surface 40r of the first chip 40. The thickness TS2 of the second bonding material 102 is the distance in the z direction between the secondary die pad 80 and the back surface 50r of the second chip 50. Furthermore, if the difference between the thickness TS3 of the third bonding material 103 and the thickness TS1 of the first bonding material 101 is, for example, within 20% of the thickness TS3 of the third bonding material 103, then it can be said that the thickness TS3 of the third bonding material 103 and the thickness TS1 of the first bonding material 101 are equal. Also, if the difference between the thickness TS3 of the third bonding material 103 and the thickness TS2 of the second bonding material 102 is, for example, within 20% of the thickness TS3 of the third bonding material 103, then it can be said that the thickness TS3 of the third bonding material 103 and the thickness TS2 of the second bonding material 102 are equal.

[0125] Thus, the height position of the main surface 60s of the transformer chip 60 is higher than both the height position of the main surface 40s of the first chip 40 and the height position of the main surface 50s of the second chip 50.

[0126] As shown in Figure 2, the thickness of the first substrate 43 of the first chip 40 is equal to the thickness TB of the substrate 63 (see Figure 5). The thickness of the second substrate 53 of the second chip 50 is equal to the thickness TB of the substrate 63.

[0127] As shown in Figures 5 and 6, in this embodiment, the thickness TB of the substrate 63 is thinner than the thickness TT of the multiple element insulating layers 64. In this embodiment, the thickness TB of the substrate 63 is thicker than the distance D1 between the first coil 31A (31B) and the second coil 32A (32B) in the z direction.

[0128] The distance D1 between the first coil 31A (31B) and the second coil 32A (32B) in the z-direction is greater than the distance D2 between the second coil 32A (32B) and the back surface 64r of the element insulating layer 64 in the z-direction. It should also be said that distance D2 is the distance between the second coil 32A (32B) and the substrate surface 63s of the substrate 63 in the z-direction.

[0129] The distance D1 between the first coil 31A (31B) and the second coil 32A (32B) in the z-direction is greater than the distance D3 between the first coil 31A (31B) and the surface 64s of the element insulating layer 64 in the z-direction.

[0130] Since the first coil 33A(33B) is located in the same position as the first coil 31A(31B) in the z direction, and the second coil 34A(34B) is located in the same position as the second coil 32A(32B) in the z direction, the distance between the first coil 33A(33B) and the second coil 34A(34B) in the z direction is equal to the above-mentioned distance D1. Also, the distance between the second coil 34A(34B) and the back surface 64r of the element insulating layer 64 in the z direction is equal to the above-mentioned distance D2. Also, the distance between the first coil 33A(33B) and the surface 64s of the element insulating layer 64 in the z direction is equal to the above-mentioned distance D3.

[0131] The thickness TZ of the substrate insulating layer 63B of the transchip 60 is thicker than the thickness TA of one layer of the element insulating layer 64, but thinner than the total thickness TT of multiple element insulating layers 64. Here, the thickness TZ of the substrate insulating layer 63B is the distance in the z direction between the surface 63Bs and the back surface 63Br of the substrate insulating layer 63B. The thickness TA of one layer of the element insulating layer 64 is the distance in the z direction between the back surface of the first insulating film 64A and the surface of the second insulating film 64B of one layer of element insulating layer 64. The total thickness TT of multiple element insulating layers 64 is the distance in the z direction between the surface 64s and the back surface 64r of the element insulating layer 64. Furthermore, since the thickness TA of one layer of the element insulating layer 64 is equal to the respective thicknesses of each coil 31A~34A and 31B~34B, it can also be said that the thickness TZ of the substrate insulating layer 63B is thicker than the respective thicknesses of each coil 31A~34A and 31B~34B.

[0132] The thickness TZ of the substrate insulating layer 63B is greater than or equal to the distance D2 in the z-direction between the second coil 32A (32B) and the back surface 64r of the element insulating layer 64. In one example, the thickness TZ of the substrate insulating layer 63B is 2 μm or more and 4 μm or less. The distance D2 in the z-direction between the second coil 32A (32B) and the back surface 64r of the element insulating layer 64 is 0.5 μm or more and 2 μm or less. In this embodiment, the thickness TZ of the substrate insulating layer 63B is greater than the distance D2 in the z-direction between the second coil 32A (32B) and the back surface 64r of the element insulating layer 64. The thickness TZ of the substrate insulating layer 63B is greater than or equal to the distance D3 in the z-direction between the first coil 31A (31B) and the surface 64s of the element insulating layer 64. The thickness TZ of the substrate insulating layer 63B is less than the distance D1 in the z-direction between the first coil 31A (31B) and the second coil 32A (32B).

[0133] The thickness TZ of the substrate insulating layer 63B is thinner than the thickness T4 of the main body 63A. The thickness T4 of the main body 63A is the distance in the z direction between the front surface 63As and the back surface 63Ar of the main body 63A. The thickness TZ of the substrate insulating layer 63B is less than half the thickness T4 of the main body 63A. The thickness TZ of the substrate insulating layer 63B is less than one-third the thickness T4 of the main body 63A.

[0134] In the main body 63A, the thickness T1 of the first semiconductor layer 63AA is greater than the thickness T2 of the second semiconductor layer 63AB and the thickness T3 of the oxide film 63AC. The thickness T2 of the second semiconductor layer 63AB is greater than the thickness T3 of the oxide film 63AC. Here, the thickness T1 of the first semiconductor layer 63AA is the distance in the z direction between the surface of the first semiconductor layer 63AA that is in contact with the substrate insulating layer 63B and the back surface that is in contact with the oxide film 63AC. The thickness T2 of the second semiconductor layer 63AB is the distance in the z direction between the surface of the second semiconductor layer 63AB that is in contact with the oxide film 63AC and the back surface that faces the opposite direction in the z direction from this surface. The thickness T3 of the oxide film 63AC is the distance in the z direction between the surface of the oxide film 63AC that is in contact with the first semiconductor layer 63AA and the back surface that is in contact with the second semiconductor layer 63AB.

[0135] The thickness TZ of the substrate insulating layer 63B is thinner than the thickness T1 of the first semiconductor layer 63AA. The thickness TZ of the substrate insulating layer 63B is thinner than the thickness T2 of the second semiconductor layer 63AB. The thickness TZ of the substrate insulating layer 63B is equal to the thickness T3 of the oxide film 63AC. Here, if the difference between the thickness TZ of the substrate insulating layer 63B and the thickness T3 of the oxide film 63AC is, for example, within 20% of the thickness TZ of the substrate insulating layer 63B, then it can be said that the thickness TZ of the substrate insulating layer 63B is equal to the thickness T3 of the oxide film 63AC.

[0136] The thickness TZ of the substrate insulating layer 63B is greater than or equal to the thickness TC of the protective film 65. Also, the thickness TZ of the substrate insulating layer 63B is less than or equal to the thickness TD of the passivation film 66. Here, the thickness of the protective film 65 is the distance in the z direction between the front and back surfaces of the protective film 65. The front surface of the protective film 65 is the surface in contact with the passivation film 66, and the back surface of the protective film 65 is the surface in contact with the element insulating layer 64. Also, the thickness of the passivation film 66 is the distance in the z direction between the front and back surfaces of the passivation film 66. The front surface of the passivation film 66 is the surface that constitutes the main chip surface 60s of the transformer chip 60, and the back surface of the passivation film 66 is the surface in contact with the protective film 65.

[0137] In this embodiment, the thickness TZ of the substrate insulating layer 63B is thinner than the thickness TS3 of the third bonding material 103. The thickness TS3 of the third bonding material 103 is less than 10 μm (approximately 5 μm). Since the thickness TS3 of the third bonding material 103 is equal to the thickness TS1 of the first bonding material 101 and the thickness TS2 of the second bonding material 102, it can be said that the thickness TZ of the substrate insulating layer 63B is thinner than the thickness TS1 of the first bonding material 101, and that the thickness TZ of the substrate insulating layer 63B is thinner than the thickness TS2 of the second bonding material 102.

[0138] (Manufacturing method) An overview of an example of a method for manufacturing the signal transmission device 10 will be described. The manufacturing method for the signal transmission device 10 includes a preparation step of preparing the transformer chip 60, the first chip 40, the second chip 50, the primary die pad 70, and the secondary die pad 80.

[0139] The transchip 60 is manufactured, for example, as follows. As shown in Figure 9, first an SOI wafer 630 is prepared as a semiconductor wafer. The SOI wafer 630 constitutes the main body 63A of the substrate 63. The SOI wafer 630 has a wafer surface 630s and a wafer back surface 630r that face opposite each other in the thickness direction. Next, an insulating film 631 is formed on the outer surface of the SOI wafer 630. The insulating film 631 is formed by a reaction between an organic TEOS gas and an oxygen-based gas, for example, using a reduced-pressure CVD method. The insulating film 631 formed on the wafer surface 630s of the SOI wafer 630 constitutes the substrate insulating layer 63B. Thus, the manufacturing method of the transchip 60 includes a substrate insulating layer formation step. Figure 9 shows the step of forming a substrate insulating layer (insulating film 631) on both sides of the semiconductor wafer (SOI wafer 630) as part of the substrate insulating layer formation step. Thus, even if the thickness of the insulating film 631 is increased by forming the insulating film 631 on both sides of the semiconductor wafer (SOI wafer 630), the warping of the semiconductor wafer (SOI wafer 630) can be suppressed.

[0140] Next, as shown in Figure 10, an element insulating layer 640, first transformers 21A, 21B, and second transformers 22A, 22B are formed on the insulating film 631 formed on the wafer surface 630s of the SOI wafer 630. The element insulating layer 640 is an insulating layer that constitutes the element insulating layer 64 of the transformer chip 60, and is formed over the entire surface of the insulating film 631 formed on the wafer surface 630s of the SOI wafer 630, for example. In one example, multiple element insulating layers 640 are stacked on the insulating film 631, and second openings are formed in the element insulating layer 640 where the second coils 32A, 32B, 34A, 34B of each transformer 21A, 21B, 22A, 22B are placed. The element insulating layer 640 is formed, for example, by plasma CVD. Since the element insulating layer 640 is deposited by plasma CVD, its film quality differs from that of the insulating film 631 which is deposited by reduced pressure CVD. Then, by providing a second conductive material in the second opening, the second coils 32A, 32B, 34A, and 34B are formed. In this embodiment, Cu is used as the second conductive material. However, Al may be used as the second conductive material, for example. Next, the element insulating layer 640 is laminated again so as to cover the second coils 32A, 32B, 34A, and 34B, and a first opening is formed in the element insulating layer 640 where the first coils 31A, 31B, 33A, and 33B are arranged. Then, by providing a first conductive material in the first opening, the first coils 31A, 31B, 33A, and 33B are formed. In this embodiment, Cu is used as the first conductive material. Next, the element insulating layer 640 is laminated so as to cover the first coils 31A, 31B, 33A, and 33B.

[0141] Thus, the method for manufacturing the transformer chip 60 includes a step of laminating an element insulating layer 640 containing both insulating elements (both transformers 21A, 21B, 22A, 22B) onto the surface of a substrate insulating layer (insulating film 631).

[0142] Next, a plurality of first electrode pads 61 and a plurality of second electrode pads 62 are formed on the surface of the element insulating layer 640. Subsequently, a protective film 650 and a passivation film 660 are laminated on the surface of the element insulating layer 640 in that order. The protective film 650 is a film that constitutes the protective film 65 of the transchip 60 and is formed, for example, over the entire surface of the element insulating layer 640. The passivation film 660 is a film that constitutes the passivation film 66 of the transchip 60 and is formed, for example, over the entire surface of the protective film 650. Here, the protective film 650 and the passivation film 660 are formed with, for example, a mask covering a portion of each first electrode pad 61 and a portion of each second electrode pad 62. Then the mask is removed. As a result, each electrode pad 61, 62 is exposed.

[0143] Next, as shown in Figure 11, the SOI wafer 630 is ground so that its thickness falls within a predetermined range. The insulating film 631 formed on the back surface 630r of the SOI wafer 630 is ground away. This removes the insulating film 631 formed on the back surface 630r of the SOI wafer 630. Here, the back surface 630r of the SOI wafer 630 may also be ground away. This makes the sum of the thickness of the SOI wafer 630 and the thickness of the insulating film 631 equal to the thickness TB of the substrate 63. Figure 11 shows the step of removing the substrate insulating layer (insulating film 631) from the back surface (back surface 630r) of the semiconductor wafer (SOI wafer 630) as part of the substrate insulating layer formation process. In other words, in this embodiment, the step of removing the substrate insulating layer (insulating film 631) from the back surface (back surface 630r) of the semiconductor wafer (SOI wafer 630) is performed after the stacking of the element insulating layer 640.

[0144] Next, the SOI wafer 630, on which the element insulating layer 640, protective film 650, and passivation film 660 are formed, is cut along the z-direction to separate the transchip 60 into individual pieces. This forms the substrate 63, element insulating layer 64, protective film 65, and passivation film 66. Through these steps, the transchip 60 is manufactured.

[0145] Furthermore, the method for forming the substrate insulating layer in the substrate insulating layer formation process can be arbitrarily changed. For example, the substrate insulating layer (insulating film 631) may be formed by thermal oxidation of the semiconductor wafer (SOI wafer 630). Even by thermal oxidation, the substrate insulating layer (insulating film 631) is formed on both sides of the semiconductor wafer (SOI wafer 630), so warping of the semiconductor wafer (SOI wafer 630) can be suppressed. In this case as well, the insulating film 631 has a different film quality from the element insulating layer 640.

[0146] Furthermore, in the substrate insulating layer formation process, the order of the steps for removing the substrate insulating layer (insulating film 631) from the back surface (wafer back surface 630r) of the semiconductor wafer (SOI wafer 630) can be arbitrarily changed.

[0147] The manufacturing method for the signal transmission device 10 includes the steps of mounting the first chip 40 on the primary die pad 70 and mounting both the transformer chip 60 and the second chip 50 on the secondary die pad 80. In one example, the first chip 40 is mounted on the primary die pad 70 by die bonding, and both the second chip 50 and the transformer chip 60 are mounted on the secondary die pad 80 by die bonding. Specifically, first, a first bonding material 101 is applied to the primary die pad 70, a second bonding material 102 is applied to the area on the secondary die pad 80 where the second chip 50 will be mounted, and a third bonding material 103 is applied to the area on the secondary die pad 80 where the transformer chip 60 will be mounted. Subsequently, the first chip 40 is placed on the first bonding material 101, the second chip 50 is placed on the second bonding material 102, and the transformer chip 60 is placed on the third bonding material 103. Then, each of the bonding materials 101 to 103 is solidified. Note that conductive bonding materials are used for both the first bonding material 101 and the second bonding material 102, and insulating bonding material is used for the third bonding material 103. Therefore, the solidification method for the first bonding material 101 and the second bonding material 102 is different from the solidification method for the third bonding material 103. For example, when solder is used for the first bonding material 101 and the second bonding material 102, the first bonding material 101 and the second bonding material 102 are solidified by heating and cooling them, respectively. When the third bonding material 103 is formed from a material containing epoxy resin, the third bonding material 103 is solidified by, for example, mixing a hardening agent with the epoxy resin.

[0148] Here, for example, the first chip 40 may be mounted on the primary die pad 70, the second chip 50 on the secondary die pad 80, and then the transformer chip 60 may be mounted on the secondary die pad 80. In one example, first, the first bonding material 101 is applied to the primary die pad 70, and the second bonding material 102 is applied to the area on the secondary die pad 80 where the second chip 50 will be mounted. Next, the first chip 40 is placed on the first bonding material 101, and the second chip 50 is placed on the second bonding material 102. Then the first bonding material 101 and the second bonding material 102 are solidified. Next, the third bonding material 103 is applied to the area on the secondary die pad 80 where the transformer chip 60 will be mounted. Next, the transformer chip 60 is placed on the third bonding material 103. Then the third bonding material 103 is solidified.

[0149] The manufacturing method for the signal transmission device 10 includes a step of forming wires W. The wires W are formed by a wire bonding apparatus. More specifically, wires W are formed to individually connect a plurality of first electrode pads 41 and a plurality of primary leads of the first chip 40. Wires W are formed to individually connect a plurality of second electrode pads 52 and a plurality of secondary leads of the second chip 50. Wires W are formed to individually connect a plurality of second electrode pads 42 of the first chip 40 and a plurality of first electrode pads 61 of the transformer chip 60, and wires W are formed to individually connect a plurality of second electrode pads 62 of the transformer chip 60 and a plurality of first electrode pads 51 of the second chip 50.

[0150] The manufacturing method for the signal transmission device 10 includes a step of forming a sealing resin 90. The sealing resin 90 is formed, for example, by transfer molding. This seals each of the chips 40, 50, 60, each of the die pads 70, 80, and each of the wires W. Each of the primary and secondary leads is provided such that a portion of them protrudes from the side surface of the sealing resin 90.

[0151] The manufacturing method for the signal transmission device 10 involves forming the external terminals of the signal transmission device 10 by bending the portions of the multiple primary leads that protrude from the sealing resin 90 and the portions of the multiple secondary leads that protrude from the sealing resin 90. The signal transmission device 10 is manufactured through the above process. Although the above description describes the manufacturing method for one signal transmission device 10, it is not limited to this, and multiple signal transmission devices 10 may be manufactured simultaneously.

[0152] (action) To improve the dielectric strength of the transformer chip, for example, the distance D1 between the first coil 31A (31B) and the second coil 32A (32B) of the transformer 21A (21B) in the z-direction can be increased. In this case, the thickness TT of the element insulating layer 64 provided on the substrate 63 of the transformer chip 60 will increase. However, if the thickness TT of the element insulating layer 64 increases, a problem may arise in which the semiconductor wafer constituting the substrate 63 warps during the manufacturing of the transformer chip 60. For this reason, there is a limit to how much the thickness TT of the element insulating layer 64 can be increased.

[0153] Therefore, the transformer chip 60 of this embodiment includes a first transformer 21A (21B) and a second transformer 22A (22B) connected in series with each other. This makes it possible to improve the dielectric strength of the transformer chip 60 without excessively increasing both the distance D1 in the z-direction between the first coil 31A (31B) and the second coil 32A (32B) of the first transformer 21A (21B) and the distance D1 in the z-direction between the first coil 33A (33B) and the second coil 34A (34B) of the second transformer 22A (22B).

[0154] Incidentally, in such a transformer chip 60, the first transformer 21A (21B) is electrically connected to the primary circuit 13 via wire W, and the second transformer 22A (22B) is electrically connected to the secondary circuit 14 via wire W. Therefore, when the transformer chip 60 is mounted on a conductive secondary die pad 80, it is necessary to electrically isolate each transformer 21A (21B), 22A (22B) from the secondary die pad 80.

[0155] The dielectric strength between each transformer 21A(21B), 22A(22B) and the secondary die pad 80 is mainly determined by the distance in the z-direction between each second coil 32A(32B), 34A(34B) of each transformer 21A(21B), 22A(22B) and the secondary die pad 80. In other words, as the distance in the z-direction between each second coil 32A(32B), 34A(34B) and the secondary die pad 80 increases, the dielectric strength between each transformer 21A(21B), 22A(22B) and the secondary die pad 80 increases.

[0156] The distance in the z-direction between each second coil 32A(32B) and 34A(34B) of each transformer 21A(21B) and 22A(22B) and the secondary die pad 80 is determined by the sum of the distance between each second coil 32A(32B) and 34A(34B) and the main body portion 63A of the substrate 63, the thickness of the substrate 63, and the thickness TS3 of the bonding material 103.

[0157] Here, for example, in order to increase the distance between each second coil 32A(32B), 34A(34B) and the main body portion 63A of the substrate 63, it is conceivable to increase the number of layered element insulating layers 64 that are below each second coil 32A(32B), 34A(34B) and close to the substrate 63. In other words, it is conceivable to increase the distance D2 between the second coil 32A(32B), 34A(34B) and the back surface 64r of the element insulating layer 64. However, increasing the distance D2 will increase the thickness TT of the element insulating layer 64.

[0158] In this embodiment, the substrate 63 of the transformer chip 60 includes a substrate insulating layer 63B formed on the surface 63As of the main body portion 63A. As a result, both the element insulating layer 64 and the substrate insulating layer 63B are interposed between each second coil 32A(32B), 34A(34B) and the main body portion 63A of the substrate 63. Therefore, it is possible to avoid increasing the number of layered element insulating layers 64 that are lower than each second coil 32A(32B), 34A(34B) and close to the substrate 63 in order to increase the distance between each second coil 32A(32B), 34A(34B) and the main body portion 63A of the substrate 63. In other words, the distance in the z-direction between the main body portion 63A and each second coil 32A(32B), 34A(34B) can be increased without increasing the distance D2 between the second coil 32A(32B), 34A(34B) and the back surface 64r of the element insulating layer 64. This makes it possible to increase the distance D4 in the z-direction between each second coil 32A (32B), 34A (34B) and the secondary die pad 80.

[0159] (effect) The signal transmission device 10 of this embodiment provides the following advantages. (1-1) The signal transmission device 10 includes a first chip 40 including a primary circuit 13, a primary die pad 70 on which the first chip 40 is mounted, a transformer chip 60, a second chip 50 including a secondary circuit 14 configured to receive signals from the primary circuit 13 via the transformer chip 60, and a secondary die pad 80 on which the second chip 50 is mounted. The transformer chip 60 includes a substrate 63, an element insulating layer 64 having a surface 64s and a back surface 64r on the opposite side of the surface 64s and closer to the substrate 63 than the surface 64s, and a first transformer 21A (21B) and a second transformer 22A (22B) provided within the element insulating layer 64 for transmitting signals. The first transformer 21A (21B) includes a first coil 31A (31B) positioned closer to the surface 64s than the back surface 64r within the element insulating layer 64, and a second coil 32A (32B) positioned closer to the back surface 64r than the surface 64s within the element insulating layer 64. The second transformer 22A (22B) includes a first coil 33A (33B) positioned closer to the surface 64s than the back surface 64r within the element insulating layer 64, and a second coil 34A (34B) positioned closer to the back surface 64r than the surface 64s within the element insulating layer 64. The second coils 32A (32B) and 34A (34B) are electrically connected. The substrate 63 includes a main body 63A and a substrate insulating layer 63B formed on the surface 63As of the main body 63A. The element insulating layer 64 is laminated on the surface 63Bs of the substrate insulating layer 63B.

[0160] In this configuration, both the element insulating layer 64 and the substrate insulating layer 63B are interposed between the main body 63A and the second coils 32A(32B) and 34A(34B). This avoids the need to increase the number of layered element insulating layers 64 closer to the substrate 63 below each of the second coils 32A(32B) and 34A(34B) in order to increase the distance between each of the second coils 32A(32B) and 34A(34B) and the main body 63A of the substrate 63. In other words, the distance in the z-direction between the main body 63A and each of the second coils 32A(32B) and 34A(34B) can be increased without increasing the distance D2 between the second coils 32A(32B) and 34A(34B) and the back surface 64r of the element insulating layer 64. This allows the distance D4 between each second coil 32A(32B), 34A(34B) and the secondary die pad 80 in the z-direction to be increased without increasing the distance D2 between the second coil 32A(32B), 34A(34B) and the back surface 64r of the element insulating layer 64. Therefore, the dielectric strength between each second coil 32A(32B), 34A(34B) and the secondary die pad 80 in the z-direction can be improved. Consequently, the dielectric strength of the signal transmission device 10 can be improved.

[0161] (1-2) The thickness TZ of the substrate insulating layer 63B is thinner than the thickness T4 of the main body 63A. With this configuration, the substrate insulating layer 63B can be formed more easily compared to the case where the thickness TZ of the substrate insulating layer 63B is greater than or equal to the thickness T4 of the main body 63A. In other words, the formation time of the substrate insulating layer 63B can be shortened. Therefore, the manufacturing cost of the transformer chip 60 can be reduced.

[0162] (1-3) The main body 63A is an SOI substrate having a first semiconductor layer 63AA in contact with the element insulating layer 64, an oxide film 63AC provided on the side of the first semiconductor layer 63AA opposite to the element insulating layer 64, and a second semiconductor layer 63AB provided on the side of the oxide film 63AC opposite to the first semiconductor layer 63AA.

[0163] With this configuration, compared to a configuration in which the main body 63A is formed from a single-layer semiconductor substrate, the dielectric breakdown voltage between each second coil 32A (32B), 34A (34B) and the secondary die pad 80 in the z-direction is improved. Therefore, the dielectric breakdown voltage of the signal transmission device 10 can be improved.

[0164] (1-4) The thickness T1 of the first semiconductor layer 63AA is greater than both the thickness T3 of the oxide film 63AC and the thickness T2 of the second semiconductor layer 63AB. The thickness TZ of the substrate insulating layer 63B is less than the thickness T1 of the first semiconductor layer 63AA.

[0165] With this configuration, the substrate insulating layer 63B can be formed more easily compared to the case where the thickness TZ of the substrate insulating layer 63B is greater than or equal to the thickness T1 of the first semiconductor layer 63AA. In other words, the formation time of the substrate insulating layer 63B can be shortened. Therefore, the manufacturing cost of the trans chip 60 can be reduced.

[0166] (1-5) The thickness T2 of the second semiconductor layer 63AB is greater than the thickness T3 of the oxide film 63AC. The thickness TZ of the substrate insulating layer 63B is less than the thickness T2 of the second semiconductor layer 63AB. With this configuration, the substrate insulating layer 63B can be formed more easily compared to the case where the thickness TZ of the substrate insulating layer 63B is greater than or equal to the thickness T2 of the second semiconductor layer 63AB. In other words, the formation time of the substrate insulating layer 63B can be shortened. Therefore, the manufacturing cost of the trans chip 60 can be reduced.

[0167] (1-6) The thickness TZ of the substrate insulating layer 63B is greater than or equal to the distance D2 between the second coils 32A (32B), 34A (34B) and the back surface 64r of the element insulating layer 64 in the z direction. The substrate insulating layer 63B is a TEOS oxide film.

[0168] This configuration allows for an increase in the z-direction distance between the second coils 32A (32B), 34A (34B) and the secondary die pad 80 without increasing the distance D2. The TEOS oxide film is formed on both sides of the semiconductor wafer (SOI wafer 630) constituting the main body 63A during the manufacturing process of the transchip 60. Therefore, an increase in the thickness TT of the element insulating layer 64 can be suppressed, and the occurrence of warping of the semiconductor wafer (SOI wafer 630) constituting the substrate 63 can be suppressed during the manufacturing of the transchip 60.

[0169] (1-7) The thickness TZ of the substrate insulating layer 63B is thinner than the thickness TS3 of the third bonding material 103. With this configuration, the substrate insulating layer 63B can be formed more easily compared to the case where the thickness TZ of the substrate insulating layer 63B is equal to or greater than the thickness TS3 of the third bonding material 103. In other words, the formation time of the substrate insulating layer 63B can be shortened. Therefore, the manufacturing cost of the transformer chip 60 can be reduced.

[0170] (1-8) If the third bonding material that joins the transformer chip 60 to the secondary die pad 80 is conductive, then electrical insulation will be required between the third bonding material and the secondary die pad 80, as electrical insulation will be required between the third bonding material and the second coils 32A (32B) and 34A (34B).

[0171] In this embodiment, the third bonding material 103 has electrical insulating properties. As a result, there is no electrical conductivity between the third bonding material 103 and the secondary die pad 80. Therefore, in order to improve the dielectric strength of the transformer chip 60, electrical insulation is required between the second coils 32A(32B), 34A(34B) and the secondary die pad 80, rather than between the second coils 32A(32B), 34A(34B) and the third bonding material 103. Consequently, the dielectric strength of the transformer chip 60 can be easily improved.

[0172] (1-9) The thickness TZ of the substrate insulating layer 63B is thinner than the thickness TS1 of the first bonding material 101. With this configuration, the substrate insulating layer 63B can be formed more easily compared to the case where the thickness TZ of the substrate insulating layer 63B is greater than or equal to the thickness TS1 of the first bonding material 101. In other words, the formation time of the substrate insulating layer 63B can be shortened. Therefore, the manufacturing cost of the transformer chip 60 can be reduced.

[0173] Furthermore, the thickness TZ of the substrate insulating layer 63B is thinner than the thickness TS2 of the second bonding material 102. With this configuration, the substrate insulating layer 63B can be formed more easily compared to the case where the thickness TZ of the substrate insulating layer 63B is greater than or equal to the thickness TS2 of the second bonding material 102. In other words, the formation time of the substrate insulating layer 63B can be shortened. Therefore, the manufacturing cost of the transformer chip 60 can be reduced.

[0174] (1-10) The thickness TZ of the substrate insulating layer 63B is less than the distance D1 between the first coil 31A (31B) and the second coil 32A (32B) in the z direction. In other words, the distance D1 between the first coil 31A (31B) and the second coil 32A (32B) is greater than the thickness TZ of the substrate insulating layer 63B. The thickness TZ of the substrate insulating layer 63B is less than the distance D1 between the first coil 33A (33B) and the second coil 34A (34B) in the z direction. In other words, the distance D1 between the first coil 33A (33B) and the second coil 34A (34B) in the z direction is greater than the thickness TZ of the substrate insulating layer 63B.

[0175] With this configuration, both the distance D1 between the first coil 31A (31B) and the second coil 32A (32B), and the distance D1 between the first coil 33A (33B) and the second coil 34A (34B) can be increased, thereby improving the dielectric strength of the transformer tip 60.

[0176] (1-11) The distance D1 between the first coil 31A(31B) and the second coil 32A(32B) in the z direction is equal to the distance D1 between the first coil 33A(33B) and the second coil 34A(34B) in the z direction.

[0177] If the dielectric strength of the first transformer and the dielectric strength of the second transformer are different, the total dielectric strength of the first and second transformers connected in series may be lower than the sum of the dielectric strength of the first and second transformers.

[0178] In this respect, according to the configuration of this embodiment, the dielectric strength of the first transformer 21A (21B) and the dielectric strength of the second transformer 22A (22B) are equal to each other. Therefore, the total dielectric strength of the first transformer 21A (21B) and the second transformer 22A (22B) connected in series is approximately equal to the sum of the dielectric strength of the first transformer 21A (21B) and the dielectric strength of the second transformer 22A (22B). Thus, compared to the case where the dielectric strength of the first transformer 21A (21B) and the dielectric strength of the second transformer 22A (22B) are different, the dielectric strength of the transformer chip 60 can be improved.

[0179] (1-12) The second coil 32A (32B) and the second coil 34A (34B) are positioned at the same location relative to each other in the z-direction. With this configuration, since the second coils 32A (32B) and 34A (34B) connected to each other are not formed with a misalignment in the z direction, the second coils 32A (32B) and 34A (34B) connected to each other can be easily formed within the element insulating layer 64.

[0180] (1-13) The first coil 31A (31B) and the first coil 33A (33B) are spaced apart from each other in the x-direction, and the second coil 32A (32B) and the second coil 34A (34B) are spaced apart from each other in the x-direction. The first coil 31A (33A) and the first coil 31B (33B) are spaced apart from each other in the y-direction, and the second coil 32A (34A) and the second coil 32B (34B) are spaced apart from each other in the y-direction. The first coil 31A (31B), which is electrically connected to the primary circuit 13, is located near the first chip 40 in the x-direction, and the first coil 33A (33B), which is electrically connected to the secondary circuit 14, is located near the second chip 50 in the x-direction.

[0181] With this configuration, the first chip 40, which includes the primary circuit 13, and the first coil 31A (31B) can be easily connected by wire W. Also, the second chip 50, which includes the secondary circuit 14, and the first coil 33A (33B) can be easily connected by wire W.

[0182] (1-14) When viewed from the z direction, the first electrode pad 61A is positioned inside the coil portion 35 of the first coil 31A, and the first electrode pad 61B is positioned inside the coil portion 35 of the first coil 31B. When viewed from the y direction, the first electrode pad 61C is positioned to overlap with the first coil 31A (31B) in the x direction. When viewed from the z direction, the second electrode pad 62A is positioned inside the coil portion 35 of the first coil 33A, and the second electrode pad 62B is positioned inside the coil portion 35 of the first coil 33B. When viewed from the y direction, the second electrode pad 62C is positioned to overlap with the first coil 33A (33B) in the x direction.

[0183] With this configuration, for example, when viewed from the z-direction, the first electrode pads 61A to 61C are positioned closer to the first chip 40 than the first coil 31A (31B), and the second electrode pads 62A to 62C are positioned closer to the second chip 50 than the first coil 33A (33B). This configuration allows for miniaturization of the transformer chip 60 in the x-direction.

[0184] (1-15) The transformer chip 60 includes a substrate 63, an element insulating layer 64 having a surface 64s and a back surface 64r opposite to the surface 64s and closer to the substrate 63 than the surface 64s, and a first transformer 21A (21B) and a second transformer 22A (22B) provided within the element insulating layer 64 for transmitting signals. The first transformer 21A (21B) includes a first coil 31A (31B) positioned closer to the surface 64s than the back surface 64r within the element insulating layer 64, and a second coil 32A (32B) positioned closer to the back surface 64r than the surface 64s within the element insulating layer 64. The second transformer 22A (22B) includes a first coil 33A (33B) positioned closer to the surface 64s than the back surface 64r within the element insulating layer 64, and a second coil 34A (34B) positioned closer to the back surface 64r than the surface 64s within the element insulating layer 64. The second coil 32A (32B) and the second coil 34A (34B) are electrically connected. The substrate 63 includes a main body 63A and a substrate insulating layer 63B formed on the surface 63As of the main body 63A. The element insulating layer 64 is laminated on the surface 63Bs of the substrate insulating layer 63B.

[0185] With this configuration, the substrate insulating layer 63B is interposed between the main body 63A and the second coils 32A(32B) and 34A(34B), allowing the distance in the z-direction between the main body 63A and each of the second coils 32A(32B) and 34A(34B) to be increased without increasing the thickness TT of the element insulating layer 64. As a result, the distance in the z-direction between each of the second coils 32A(32B) and 34A(34B) and the back surface 60r of the transformer chip 60 can be increased without increasing the thickness TT of the element insulating layer 64. Therefore, when the transformer chip 60 is mounted on a metal frame, the distance in the z-direction between each of the second coils 32A(32B) and 34A(34B) and the frame can be increased, thereby improving the dielectric strength of the transformer chip 60.

[0186] (1-16) The method for manufacturing the transformer chip 60 includes a substrate insulating layer formation step of forming a substrate insulating layer (insulating film 631) on the wafer surface 630s of the semiconductor wafer (SOI wafer 630) constituting the main body 63A, and a step of laminating an element insulating layer 640 including both transformers 21A, 21B, 22A, and 22B on the surface of the insulating film 631. The substrate insulating layer formation step includes a step of forming an insulating film 631 on both the wafer surface 630s and the wafer back surface 630r of the SOI wafer 630, and a step of removing the insulating film 631 from the wafer back surface 630r of the SOI wafer 630.

[0187] With this configuration, since the insulating film 631 is formed on both the wafer surface 630s and the wafer back surface 630r of the SOI wafer 630, warping of the SOI wafer 630 can be suppressed even if the thickness of the insulating film 631 is increased. In addition, since the insulating film 631 prevents the thickness of the element insulating layer 640 from increasing, warping of the SOI wafer 630 can be reduced even if the element insulating layer 640 is stacked.

[0188] [Second Embodiment] The signal transmission device 10 of the second embodiment will be described with reference to Figures 12 to 19. The signal transmission device 10 of this embodiment differs from the signal transmission device 10 of the first embodiment mainly in that it includes a capacitor chip 120, which includes a capacitor 110, instead of a transformer chip 60. In the following description, the differences from the first embodiment will be described in detail, and components common to the first embodiment will be denoted by the same reference numerals and their descriptions will be omitted.

[0189] Figure 12 is a schematic circuit diagram of the signal transmission device 10 of this embodiment. As shown in Figure 12, the signal transmission circuit 10A of the signal transmission device 10 includes a capacitor 110 as an insulating structure that electrically insulates the primary circuit 13 and the secondary circuit 14. The capacitor 110 has a capacitor 110A connected to the signal line that transmits the first signal, and a capacitor 110B connected to the signal line that transmits the second signal. Both capacitors 110A and 110B are provided between the primary circuit 13 and the secondary circuit 14. The first signal and the second signal are the same as the first signal and the second signal of the first embodiment. Here, in this embodiment, capacitor 110A corresponds to the "capacitor for the first signal", and capacitor 110B corresponds to the "capacitor for the second signal".

[0190] The signal transmission circuit 10A includes a connecting signal line 20A as a signal line for transmitting a first signal, and a connecting signal line 20B as a signal line for transmitting a second signal. The connecting signal line 20A is provided between the primary signal line 16A and the secondary signal line 17A. The connecting signal line 20B is provided between the primary signal line 16B and the secondary signal line 17B. In other words, the signal lines for transmitting the first signal include the primary signal line 16A, the secondary signal line 17A, and the connecting signal line 20A. The signal lines for transmitting the second signal include the primary signal line 16B, the secondary signal line 17B, and the connecting signal line 20B.

[0191] Capacitor 110A has a first capacitor 111A and a second capacitor 112A connected in series with each other via a connecting signal line 20A. The first capacitor 111A is electrically connected to the primary circuit 13, and the second capacitor 112A is electrically connected to the secondary circuit 14. More specifically, the first capacitor 111A has a first electrode 113A and a second electrode 114A, and the second capacitor 112A has a first electrode 115A and a second electrode 116A. The first electrode 113A of the first capacitor 111A is connected to the primary circuit 13 by a primary signal line 16A, and the second electrode 114A is connected to the second electrode 116A of the second capacitor 112A via a connecting signal line 20A. The first electrode 115A of the second capacitor 112A is connected to the secondary circuit 14 by a secondary signal line 17A. Therefore, the primary circuit 13 and the secondary circuit 14 transmit the first signal via the first capacitor 111A and the second capacitor 112A, which are connected in series with each other.

[0192] Capacitor 110B has a first capacitor 111B and a second capacitor 112B connected in series with each other via a connecting signal line 20B. The first capacitor 111B has a first electrode 113B and a second electrode 114B, and the second capacitor 112B has a first electrode 115B and a second electrode 116B. The configuration of capacitor 110B and the connection configuration between capacitor 110B and the primary circuit 13 and secondary circuit 14 are the same as those of capacitor 110A, so a detailed explanation is omitted. The primary circuit 13 and the secondary circuit 14 transmit the second signal via the first capacitor 111B and the second capacitor 112B connected in series with each other. In this embodiment, the first capacitors 111A and 111B correspond to the "first insulating element," and the second capacitors 112A and 112B correspond to the "second insulating element."

[0193] Figure 13 is a schematic cross-sectional view of a part of the signal transmission device 10 of this embodiment. Note that in Figure 13, hatching lines have been omitted for the sake of readability. As shown in Figure 13, the signal transmission device 10 includes a capacitor chip 120 instead of the transformer chip 60 (see Figure 2) of the first embodiment. The capacitor chip 120 is positioned between the first chip 40 and the second chip 50 in the x-direction, similar to the transformer chip 60 of the first embodiment. Similar to the transformer chip 60 of the first embodiment, in this embodiment, the distance between the capacitor chip 120 and the second chip 50 in the x-direction is smaller than the distance between the capacitor chip 120 and the first chip 40 in the x-direction.

[0194] In this embodiment, the capacitor chip 120 is mounted on the secondary die pad 80. Similar to the first embodiment, the capacitor chip 120 is bonded to the secondary die pad 80 by a third bonding material 103. Similar to the first embodiment, the third bonding material 103 is an electrically insulating bonding material. Here, in this embodiment, the capacitor chip 120 corresponds to an "insulating chip".

[0195] Referring to Figures 13 to 19, an example of the internal configuration of the capacitor chip 120 will be described. Figure 14 is a schematic plan view showing the planar structure of the capacitor chip 120. Figure 15 is a schematic cross-sectional view showing the cross-sectional structure of the inside of the capacitor chip 120 cut in the xy plane. In Figure 15, hatching lines are omitted for the sake of readability. Figures 16 to 19 show the cross-sectional structure of the capacitor chip 120 when it is mounted on the secondary die pad 80. Figures 16 to 19 are schematic cross-sectional structures of the capacitor chip 120, and the number of layers of element insulating layer 64 is not limited to the number of layers of element insulating layer 64 shown in Figures 16 to 19. Also, in Figures 16 to 19, the first end portion 36 is omitted.

[0196] As shown in Figure 13, the capacitor chip 120 has a main chip surface 120s and a back chip surface 120r that face opposite each other in the z direction. The main chip surface 120s faces the same side as the main chip surface 40s of the first chip 40, and the back chip surface 120r faces the same side as the back chip surface 40r of the first chip 40. In the following description, the direction from the back chip surface 120r of the capacitor chip 120 toward the main chip surface 120s will be considered upward, and the direction from the main chip surface 120s toward the back chip surface 120r will be considered downward.

[0197] As shown in Figures 14 and 15, the capacitor chip 120 includes both capacitors 110A and 110B, and more specifically, both capacitors 110A and 110B are integrated into a single chip. In other words, the capacitor chip 120 is a separate chip dedicated to both capacitors 110A and 110B, distinct from the first chip 40 and the second chip 50.

[0198] Both capacitors 110A and 110B are arranged spaced apart in the y-direction. Viewed from the z-direction, the first capacitor 111A of capacitor 110A and the first capacitor 111B of capacitor 110B are each positioned closer to the first chip 40 (see Figure 13) than the center of the capacitor chip 120 in the x-direction. Viewed from the z-direction, the second capacitor 112A of capacitor 110A and the second capacitor 112B of capacitor 110B are each positioned closer to the second chip 50 (see Figure 13) than the center of the capacitor chip 120 in the x-direction. The first capacitors 111A and 111B are arranged aligned in the x-direction and spaced apart in the y-direction. The second capacitors 112A and 112B are arranged aligned in the x-direction and spaced apart in the y-direction. The first capacitor 111A and the second capacitor 112A are arranged aligned in the y-direction and spaced apart in the x-direction. The first capacitor 111B and the second capacitor 112B are aligned with each other in the y-direction and spaced apart from each other in the x-direction. In other words, the first capacitor 111A (111B) and the second capacitor 112A (112B) are spaced apart in the direction of the alignment of both die pads 70 and 80.

[0199] From the arrangement of the capacitors 111A, 111B, 112A, and 112B described above, the first electrode plate 121A of the first capacitor 111A and the first electrode plate 123A of the second capacitor 112A are arranged with a gap between them in the x-direction. Similarly, the first electrode plate 121B of the first capacitor 111B and the first electrode plate 123B of the second capacitor 112B are arranged with a gap between them in the x-direction. In other words, the first electrode plate 121A(121B) of the first capacitor 111A(111B) and the first electrode plate 123A(123B) of the second capacitor 112A(112B) are also arranged with a gap between them in the arrangement direction of both die pads 70 and 80.

[0200] Furthermore, the first electrode plate 121A of the first capacitor 111A and the first electrode plate 121B of the first capacitor 111B are arranged with a gap in between in the y-direction. The first electrode plate 123A of the second capacitor 112A and the first electrode plate 123B of the second capacitor 112B are arranged with a gap in between in the y-direction. In other words, the first electrode plate 121A of the first capacitor 111A and the first electrode plate 121B of the first capacitor 111B can also be said to be arranged with a gap in between in a direction perpendicular to the arrangement direction of both die pads 70 and 80 when viewed from the z-direction. Furthermore, the first electrode plate 123A of the second capacitor 112A and the first electrode plate 123B of the second capacitor 112B can also be said to be arranged with a gap in a direction perpendicular to the arrangement direction of both die pads 70 and 80 when viewed from the z-direction.

[0201] As shown in Figures 15, 17, and 18, the first electrode plates 121A, 121B, 123A, and 123B are positioned aligned with each other in the z-direction. Each of the first electrode plates 121A, 121B, 123A, and 123B is appropriately selected from one or more of Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W (tungsten). In this embodiment, each of the first electrode plates 121A, 121B, 123A, and 123B is formed from a material containing Cu.

[0202] In this embodiment, each of the first electrode plates 121A, 121B, 123A, and 123B has the same shape. In one example, each of the first electrode plates 121A, 121B, 123A, and 123B is formed in a plate shape with the z direction as the thickness direction. When viewed from the z direction, each of the first electrode plates 121A, 121B, 123A, and 123B has a rectangular shape with the x direction as the shorter side and the y direction as the longer side.

[0203] As shown in Figure 14, the capacitor chip 120 comprises a plurality (two in this embodiment) of first electrode pads 131 and a plurality (two in this embodiment) of second electrode pads 132.

[0204] Multiple first electrode pads 131 are individually electrically connected to first capacitors 111A and 111B. The multiple first electrode pads 131 are arranged spaced apart from each other in the y-direction. For convenience, in the following description, the two first electrode pads 131 will be referred to as first electrode pads 131A and 131B. Here, first electrode pads 131A and 131B correspond to the "first pad".

[0205] Viewed from the z-direction, the first electrode pad 131A is positioned to overlap with the first electrode plate 121A, and the first electrode pad 131B is positioned to overlap with the first electrode plate 121B. In this embodiment, viewed from the z-direction, the first electrode pad 131A is positioned to overlap with the center of the first electrode plate 121A in the x and y directions. Viewed from the z-direction, the first electrode pad 131B is positioned to overlap with the center of the first electrode plate 121B in the x and y directions. The first electrode pad 131A is electrically connected to the first electrode plate 121A, and the first electrode pad 131B is electrically connected to the first electrode plate 121B.

[0206] Multiple second electrode pads 132 are individually electrically connected to second capacitors 112A and 112B. The multiple second electrode pads 132 are arranged spaced apart from each other in the y-direction. For convenience, in the following description, the two second electrode pads 132 will be referred to as second electrode pads 132A and 132B. Here, second electrode pads 132A and 132B correspond to the "second pad".

[0207] Viewed from the z-direction, the second electrode pad 132A is positioned to overlap with the first electrode plate 123A, and the second electrode pad 132B is positioned to overlap with the first electrode plate 123B. In this embodiment, viewed from the z-direction, the second electrode pad 132A is positioned to overlap with the center of the first electrode plate 123A in the x and y directions. Viewed from the z-direction, the second electrode pad 132B is positioned to overlap with the center of the first electrode plate 123B in the x and y directions. The second electrode pad 132A is electrically connected to the first electrode plate 123A, and the second electrode pad 132B is electrically connected to the first electrode plate 123B.

[0208] As shown in Figures 14 and 15, the second electrode plate 122A of the first capacitor 111A is positioned to overlap with the first electrode plate 121A of the first capacitor 111A when viewed from the z direction. The second electrode plate 122B of the first capacitor 111B is positioned to overlap with the first electrode plate 121B of the first capacitor 111B when viewed from the z direction. The second electrode plate 124A of the second capacitor 112A is positioned to overlap with the first electrode plate 123A of the second capacitor 112A when viewed from the z direction. The second electrode plate 124B of the second capacitor 112B is positioned to overlap with the first electrode plate 123B of the second capacitor 112B when viewed from the z direction.

[0209] From the arrangement of the electrode plates 121A-124A and 121B-124B, the second electrode plate 122A and the second electrode plate 124A are arranged with a gap between them in the x-direction. Similarly, the second electrode plate 122B and the second electrode plate 124B are arranged with a gap between them in the x-direction. In other words, the second electrode plate 122A (122B) of the first capacitor 111A (111B) and the second electrode plate 124A (124B) of the second capacitor 112A (112B) are also arranged with a gap between them in the direction of arrangement of both die pads 70 and 80.

[0210] Furthermore, the second electrode plates 122A and 122B are arranged with a gap between them in the y-direction. The second electrode plates 124A and 124B are also arranged with a gap between them in the y-direction. In other words, the second electrode plate 122A of the first capacitor 111A and the second electrode plate 122B of the first capacitor 111B are arranged with a gap between them in a direction perpendicular to the arrangement direction of both die pads 70 and 80 when viewed from the z-direction. Also, the second electrode plate 124A of the second capacitor 112A and the second electrode plate 124B of the second capacitor 112B are arranged with a gap between them in a direction perpendicular to the arrangement direction of both die pads 70 and 80 when viewed from the z-direction.

[0211] The second electrode plate 122A and the second electrode plate 124A are electrically connected to each other. More specifically, the second electrode plate 122A and the second electrode plate 124A are connected by a connecting wire 140A. The connecting wire 140A is provided between the second electrode plate 122A and the second electrode plate 124A in the x-direction and extends along the x-direction. The connecting wire 140A is provided in the same element insulating layer 64 on which the second electrode plates 122A and 124A are provided, among the multiple element insulating layers 64.

[0212] The second electrode plate 122B and the second electrode plate 124B are electrically connected to each other. More specifically, the second electrode plate 122B and the second electrode plate 124B are connected by a connecting wire 140B. The connecting wire 140B is provided between the second electrode plate 122B and the second electrode plate 124B in the x-direction and extends along the x-direction. The connecting wire 140B is provided in the same element insulating layer 64 on which the second electrode plates 122B and 124B are provided, among the multiple element insulating layers 64. The connecting wires 140A and 140B are formed of a material containing Al, for example. However, the connecting wires 140A and 140B are not limited to Al and can be made of any conductive material.

[0213] As shown in Figures 16 to 19, the capacitor chip 120 has a substrate 63 and an element insulating layer 64, similar to the transformer chip 60 of the first embodiment. The configuration of the substrate 63 and the element insulating layer 64 is the same as in the first embodiment. The capacitor chip 120 also has a protective film 65 and a passivation film 66, similar to the transformer chip 60 of the first embodiment. The configuration of the protective film 65 and the passivation film 66 is the same as in the first embodiment. The first electrode pad 131 and the second electrode pad 132 are exposed in the z direction from the protective film 65 and the passivation film 66, similar to in the first embodiment.

[0214] The first capacitors 111A and 111B and the second capacitors 112A and 112B are each provided within the element insulating layer 64. In other words, the first electrode plate 121A and the second electrode plate 122A of the first capacitor 111A, the first electrode plate 121B and the second electrode plate 122B of the first capacitor 111B, the first electrode plate 123A and the second electrode plate 124A of the second capacitor 112A, and the first electrode plate 123B and the second electrode plate 124B of the second capacitor 112B are each provided within the element insulating layer 64.

[0215] The first electrode plate 121A and the second electrode plate 122A of the first capacitor 111A are arranged opposite each other in the z direction. The first electrode plate 121A and the second electrode plate 122A are spaced apart in the z direction. One or more element insulating layers 64 are interposed between the first electrode plate 121A and the second electrode plate 122A. The first electrode plate 121A is positioned closer to the surface 64s of the element insulating layer 64 than to the surface 64r, and the second electrode plate 122A is positioned closer to the back surface 64r of the element insulating layer 64 than to the surface 64s. In other words, the first electrode plate 121A is positioned closer to the surface 64s of the element insulating layer 64 than to the second electrode plate 122A. To put it another way, the second electrode plate 122A is positioned closer to the back surface 64r of the element insulating layer 64 than to the first electrode plate 121A.

[0216] The first electrode plates 121A and 121B are positioned aligned with each other in the z-direction. In other words, the first electrode plates 121A and 121B are located on the same element insulating layer 64 among the multiple element insulating layers 64. The second electrode plates 122A and 122B are positioned aligned with each other in the z-direction. In other words, the second electrode plates 122A and 122B are located on the same element insulating layer 64 among the multiple element insulating layers 64. The second electrode plates 122A and 122B are spaced apart from the back surface 64r of the element insulating layer 64 in the z-direction. That is, one or more element insulating layers 64 are interposed between the second electrode plates 122A and 122B and the back surface 64r of the element insulating layer 64.

[0217] The first electrode plates 121A and 121B are provided penetrating the single-layer element insulating layer 64 in the z-direction. In other words, openings for forming the first electrode plates 121A and 121B are provided in both the first insulating film 64A and the second insulating film 64B of the single-layer element insulating layer 64. The first electrode plates 121A and 121B are formed by embedding conductive members made of a Cu-containing material into these openings. The second electrode plates 122A and 122B are formed in the same manner as the first electrode plates 121A and 121B.

[0218] The first electrode plate 123A and the second electrode plate 124A of the second capacitor 112A are positioned opposite each other in the z direction. The first electrode plate 123A and the second electrode plate 124A are positioned spaced apart from each other in the z direction. One or more element insulating layers 64 are interposed between the first electrode plate 123A and the second electrode plate 124A in the z direction. The first electrode plate 123A is positioned closer to the surface 64s than the surface 64r within the element insulating layer 64, and the second electrode plate 124A is positioned closer to the back surface 64r than the surface 64s within the element insulating layer 64. In other words, the first electrode plate 123A is positioned closer to the surface 64s of the multiple element insulating layers 64 relative to the second electrode plate 124A. To put it another way, the second electrode plate 124A is positioned closer to the back surface 64r of the multiple element insulating layers 64 relative to the first electrode plate 123A.

[0219] The first electrode plate 123B and the second electrode plate 124B of the second capacitor 112B are positioned opposite each other in the z direction. The first electrode plate 123B and the second electrode plate 124B are positioned spaced apart from each other in the z direction. One or more element insulating layers 64 are interposed between the first electrode plate 123B and the second electrode plate 124B in the z direction. The first electrode plate 123B is positioned closer to the surface 64s than the surface 64r within the element insulating layer 64, and the second electrode plate 124B is positioned closer to the back surface 64r than the surface 64s within the element insulating layer 64. In other words, the first electrode plate 123B is positioned closer to the surface 64s of the multiple element insulating layers 64 relative to the second electrode plate 124B. To put it another way, the second electrode plate 124B is positioned closer to the back surface 64r of the multiple element insulating layers 64 relative to the first electrode plate 123B.

[0220] The first electrode plates 123A and 123B are positioned aligned with each other in the z-direction. In other words, the first electrode plates 123A and 123B are positioned on the same element insulating layer 64 among the multiple element insulating layers 64. The second electrode plates 124A and 124B are positioned aligned with each other in the z-direction. In other words, the second electrode plates 124A and 124B are positioned on the same element insulating layer 64 among the multiple element insulating layers 64. The second electrode plates 124A and 124B are positioned spaced apart from the back surface 64r of the element insulating layer 64 in the z-direction. That is, one or more element insulating layers 64 are interposed between the second electrode plates 124A and 124B and the back surface 64r of the element insulating layer 64.

[0221] Furthermore, the first electrode plates 123A, 123B and the first electrode plates 121A, 121B are positioned aligned with each other in the z-direction. The second electrode plates 124A, 124B and the second electrode plates 122A, 122B are positioned aligned with each other in the z-direction. The first electrode plates 123A, 123B and the second electrode plates 124A, 124B are formed in the same manner as the first electrode plates 121A, 121B and the second electrode plates 122A, 122B.

[0222] In this embodiment, the first electrode plates 121A and 121B correspond to the "first surface-side conductive portion" and the "first surface-side electrode plate," and the second electrode plates 122A and 122B correspond to the "first back-side conductive portion" and the "first back-side electrode plate." The first electrode plates 123A and 123B correspond to the "second surface-side conductive portion" and the "second surface-side electrode plate," and the second electrode plates 124A and 124B correspond to the "second back-side conductive portion" and the "second back-side electrode plate."

[0223] The first electrode plate 121A and the first electrode pad 131A are connected by a connecting wire 141A. The first electrode plate 121B and the first electrode pad 131B are connected by a connecting wire 141B. The first electrode plate 123A and the second electrode pad 132A are connected by a connecting wire 142A. The first electrode plate 123B and the second electrode pad 132B are connected by a connecting wire 142B. Each connecting wire 141A, 141B, 142A, and 142B is a via that penetrates the element insulating layer 64 in the z direction, and one or more of the following materials are appropriately selected: for example, Ti, TiN, Au, Ag, Cu, Al, and W (tungsten).

[0224] The substrate 63 of the capacitor chip 120 includes a substrate insulating layer 63B provided on the surface 63As of the main body portion 63A of the substrate 63, similar to the transformer chip 60 of the first embodiment. The capacitor chip 120 is also bonded to the secondary side die pad 80 by a third bonding material 103, similar to the transformer chip 60 of the first embodiment. The dimensional relationships in the signal transmission device 10 of this embodiment are the same as those in the signal transmission device 10 of the first embodiment. However, distance D1 is the distance in the z direction between the first electrode plate 121A (121B) and the second electrode plate 122A (122B), and the distance in the z direction between the first electrode plate 123A (123B) and the second electrode plate 124A (124A). Distance D2 is the distance in the z direction between the second electrode plate 122A (122B, 124A, 124B) and the back surface 64r of the element insulating layer 64. With this configuration of the signal transmission device 10, effects similar to those of the first embodiment can be obtained.

[0225] [Example of changes] The embodiments described above are illustrative of possible forms of the signal transmission device and isolation chip according to this disclosure, and are not intended to limit their forms. The signal transmission device and isolation chip according to this disclosure may take forms different from those illustrated in the embodiments described above. For example, these may be forms in which some of the configurations of the embodiments described above are replaced, modified, or omitted, or in which new configurations are added to the embodiments described above. Furthermore, the following modifications can be combined with each other as long as they do not technically contradict each other. In the following modifications, parts common to the embodiments described above are denoted by the same reference numerals as in the embodiments described above, and their descriptions are omitted.

[0226] In the first embodiment, the configuration of the substrate 63 of the transchip 60 can be arbitrarily changed. For example, as shown in Figure 20, the main body portion 63A of the substrate 63 may be a single-layer semiconductor substrate instead of an SOI substrate. The thickness TZ of the substrate insulating layer 63B is thinner than the thickness T4 of the main body portion 63A.

[0227] In the first embodiment, as shown in Figure 21, the trans chip 60 may include a back surface insulating layer 69 provided on the back surface 63Ar of the main body portion 63A of the substrate 63 (the side of the second semiconductor layer 63AB that is opposite to the oxide film 63AC in the z direction). In this embodiment, the back surface insulating layer 69 is formed over the entire surface of the back surface 63Ar of the main body portion 63A. The back surface insulating layer 69 has a surface 69s and a back surface 69r that face opposite each other in the z direction. The surface 69s of the back surface insulating layer 69 is in contact with the back surface 63Ar of the main body portion 63A. The back surface 69r of the back surface insulating layer 69 constitutes the chip back surface 60r of the trans chip 60.

[0228] The back insulating layer 69 is formed of an electrically insulating material. In this embodiment, the back insulating layer 69 is formed of a layer containing SiO, for example. The back insulating layer 69 is formed by, for example, applying a thermosetting organic siloxane polymer solution having siloxane bonds (Si-O-Si) as the main chain to the back surface 63r of the substrate and allowing it to solidify. The back insulating layer 69 may also be formed of a layer containing a resin, for example. Examples of resins include epoxy resin, phenolic resin, and polyimide resin.

[0229] The transformer chip 60 is bonded to the secondary die pad 80 by a third bonding material 103. More specifically, the third bonding material 103 is interposed between the back surface 69r (chip back surface 60r) of the back surface insulating layer 69 and the secondary die pad 80. The third bonding material 103 bonds the back surface 69r (chip back surface 60r) of the back surface insulating layer 69 to the secondary die pad 80. In this embodiment, the third bonding material 103 is in contact with the entire surface 69r (chip back surface 60r) of the back surface insulating layer 69.

[0230] The thickness TR of the back surface insulating layer 69 is greater than the thickness TA of one layer of the element insulating layer 64, but less than the total thickness TT of multiple element insulating layers 64. Here, the thickness TR of the back surface insulating layer 69 is the distance in the z direction between the surface 69s and the back surface 69r of the back surface insulating layer 69. Also, since the thickness TA of one layer of the element insulating layer 64 is equal to the respective thicknesses of each coil 31A~34A and 31B~34B, it can be said that the thickness TR of the back surface insulating layer 69 is greater than the respective thicknesses of each coil 31A~34A and 31B~34B.

[0231] The thickness TR of the back insulating layer 69 is greater than the distance D2 in the z direction between the second coil 32A (32B) and the back surface 64r of the element insulating layer 64. The thickness TR of the back insulating layer 69 is greater than the distance D3 in the z direction between the first coil 31A (31B) and the surface 64s of the element insulating layer 64. The thickness TR of the back insulating layer 69 is less than the distance D1 in the z direction between the first coil 31A (31B) and the second coil 32A (32B). The thickness TR of the back insulating layer 69 is less than the thickness T4 of the substrate 63.

[0232] The thickness TR of the back surface insulating layer 69 is greater than the thickness TC of the protective film 65. Also, the thickness TR of the back surface insulating layer 69 is greater than the thickness TD of the passivation film 66. Here, the thickness TC of the protective film 65 is the distance in the z direction between the front and back surfaces of the protective film 65. The front surface of the protective film 65 is the surface in contact with the passivation film 66, and the back surface of the protective film 65 is the surface in contact with the element insulating layer 64. Also, the thickness TD of the passivation film 66 is the distance in the z direction between the front and back surfaces of the passivation film 66. The front surface of the passivation film 66 is the surface that constitutes the main chip surface 60s of the transformer chip 60, and the back surface of the passivation film 66 is the surface in contact with the protective film 65.

[0233] In this embodiment, the thickness TR of the back insulating layer 69 is greater than the thickness TS3 of the third bonding material 103. In one example, the thickness TR of the back insulating layer 69 is 5 μm or more and 100 μm or less. Since the thickness TS3 of the third bonding material 103 is equal to the thickness TS1 of the first bonding material 101 and the thickness TS2 of the second bonding material 102, it can be said that the thickness TR of the back insulating layer 69 is greater than the thickness TS1 of the first bonding material 101, and that the thickness TR of the back insulating layer 69 is greater than the thickness TS2 of the second bonding material 102.

[0234] With this configuration, the distance in the z-direction between the second coil 32A (32B) and the secondary die pad 80 can be increased compared to a transformer chip without a back surface insulating layer 69. Therefore, the dielectric strength between the transformer chip 60 and the secondary die pad 80 can be improved, and thus the dielectric strength of the signal transmission device 10 can be improved. Similarly, in the modified example shown in Figure 20, the transformer chip 60 may also be provided with a back surface insulating layer 69 on the back surface 63Ar of the main body portion 63A of the substrate 63.

[0235] In the first embodiment, the positions of the first electrode pads 61A and 61B of the transformer tip 60 can be arbitrarily changed when viewed from the z direction. For example, the first electrode pad 61A may be positioned outside the coil portion 35 of the first coil 31A. In this case, the first electrode pad 61A may be positioned so as to overlap with the coil portion 35 of the first coil 31A in the x direction when viewed from the y direction. Alternatively, the first electrode pad 61A may be positioned so as to be closer to the first tip 40 or the second tip 50 in the x direction than the coil portion 35 of the first coil 31A when viewed from the z direction. In other words, the first electrode pad 61A may be positioned so as to be opposite to the first coil 33A in the x direction relative to the first coil 31A when viewed from the z direction. The first electrode pad 61B may be positioned outside the coil portion 35 of the first coil 31B. In this case, the first electrode pad 61B may be positioned so as to overlap with the coil portion 35 of the first coil 31B in the x direction when viewed from the y direction. Furthermore, the first electrode pad 61B may be positioned closer to the first tip 40 or the second tip 50 in the x-direction than the coil portion 35 of the first coil 31B when viewed from the z-direction. In other words, the first electrode pad 61B may be positioned on the opposite side of the first coil 33B in the x-direction from the first coil 31B when viewed from the z-direction.

[0236] In another example, the first electrode pad 61A may be positioned so as to overlap with the coil portion 35 of the first coil 31A when viewed from the z direction. Similarly, the first electrode pad 61B may be positioned so as to overlap with the coil portion 35 of the first coil 31B when viewed from the z direction.

[0237] In another example, the first electrode pad 61A may be positioned so as to coincide with the center of the first coil 31A when viewed from the z direction. Similarly, the first electrode pad 61B may be positioned so as to coincide with the center of the first coil 31B when viewed from the z direction.

[0238] In the first embodiment, the positions of the second electrode pads 62A and 62B of the transformer tip 60 can be arbitrarily changed when viewed from the z direction. For example, the second electrode pad 62A may be positioned outside the coil portion 35 of the first coil 33A. In this case, the second electrode pad 62A may be positioned so as to overlap with the coil portion 35 of the first coil 33A in the x direction when viewed from the y direction. Alternatively, the second electrode pad 62A may be positioned so as to be closer to the first tip 40 or the second tip 50 in the x direction than the coil portion 35 of the first coil 33A when viewed from the z direction. In other words, the second electrode pad 62A may be positioned so as to be opposite to the first coil 31A in the x direction relative to the first coil 33A when viewed from the z direction. The second electrode pad 62B may be positioned outside the coil portion 35 of the first coil 33B. In this case, the second electrode pad 62B may be positioned so as to overlap with the coil portion 35 of the first coil 33B in the x direction when viewed from the y direction. Furthermore, the second electrode pad 62B may be positioned closer to the first tip 40 or closer to the second tip 50 in the x-direction than the coil portion 35 of the first coil 33B when viewed from the z-direction. In other words, the second electrode pad 62B may be positioned on the opposite side of the first coil 31B in the x-direction from the first coil 33B when viewed from the z-direction.

[0239] In another example, the second electrode pad 62A may be positioned so as to overlap with the coil portion 35 of the first coil 33A when viewed from the z direction. Similarly, the second electrode pad 62B may be positioned so as to overlap with the coil portion 35 of the first coil 33B when viewed from the z direction.

[0240] In another example, the second electrode pad 62A may be positioned so as to coincide with the center of the first coil 33A when viewed from the z direction. Similarly, the second electrode pad 62B may be positioned so as to coincide with the center of the first coil 33B when viewed from the z direction.

[0241] In the first embodiment, the shapes of the first coils 31A, 31B, 33A, and 33B as viewed from the z direction can be arbitrarily changed. For example, as viewed from the z direction, at least one of the coil portions 35 of the first coils 31A, 31B, 33A, and 33B may be formed in an annular shape.

[0242] In the first embodiment, the shapes of the second coils 32A, 32B, 34A, and 34B as viewed from the z direction can each be arbitrarily changed. In one example, when viewed from the z-direction, at least one of the coil portions 35 of the second coils 32A, 32B, 34A, and 34B may be formed in an annular shape.

[0243] In another example, the second coil 32A and the second coil 34A may be formed integrally. More specifically, as shown in Figure 22, the second coil 32A and the second coil 34A are formed as a first coil 38A integrated with each other. More specifically, the first coil 38A has a first loop-shaped conductive portion 39A, a second loop-shaped conductive portion 39B, a third loop-shaped conductive portion 39C, and a fourth loop-shaped conductive portion 39D. The first loop-shaped conductive portion 39A, the second loop-shaped conductive portion 39B, the third loop-shaped conductive portion 39C, and the fourth loop-shaped conductive portion 39D are similar in shape to each other. The second loop-shaped conductive portion 39B is arranged to surround the first loop-shaped conductive portion 39A, the third loop-shaped conductive portion 39C is arranged to surround the second loop-shaped conductive portion 39B, and the fourth loop-shaped conductive portion 39D is arranged to surround the third loop-shaped conductive portion 39C. In this embodiment, the number of loop-shaped conductive parts was four, as shown in the first to fourth loop-shaped conductive parts 39A to 39D, but this is not limited to this. The number of loop-shaped conductive parts can be arbitrarily changed.

[0244] The first loop-shaped conductive portion 39A has a first opposing portion 39p, a second opposing portion 39q, and a connecting portion 39r. The first opposing portion 39p, the second opposing portion 39q, and the connecting portion 39r are integrated. The integrated first opposing portion 39p, the second opposing portion 39q, and the connecting portion 39r form a loop shape. The first opposing portion 39p and the second opposing portion 39q are aligned with each other in the y-direction and spaced apart from each other in the x-direction.

[0245] The first opposing portion 39p is positioned opposite the first coil 31A in the z direction and constitutes the second coil 32A. The shape of the first opposing portion 39p, as viewed from the z direction, is formed as an annular shape that opens relative to the second opposing portion 39q in the x direction.

[0246] The second opposing portion 39q is positioned opposite the first coil 33A in the z direction and constitutes the second coil 34A. The shape of the second opposing portion 39q, as viewed from the z direction, is formed as an annular shape that opens relative to the first opposing portion 39p in the x direction. Thus, as viewed from the z direction, the first opposing portion 39p and the second opposing portion 39q are formed as open annular shapes that open to each other.

[0247] The connecting portion 39r connects the first opposing portion 39p and the second opposing portion 39q. The connecting portion 39r includes the first connecting portion 39ra and the second connecting portion 39rb. The first connecting portion 39ra connects the first open end, which is the first open annular end of the first opposing portion 39p, and the first open end, which is the first open annular end of the second opposing portion 39q. The second connecting portion 39rb connects the second open end, which is the second open annular end of the first opposing portion 39p, and the second open end, which is the second open annular end of the second opposing portion 39q. In other words, the connecting portion 39r connects the open ends of both opposing portions 39p and 39q. Each connecting portion 39ra and 39rb is formed in a straight line extending along the x-direction. Similarly, the second to fourth loop-shaped conductive portions 39B to 39D also have a first opposing portion 39p, a second opposing portion 39q, and a connecting portion 39r.

[0248] The second coils 32B and 34B are formed as a single integrated second coil 38B. The second coil 38B has the same shape as the first coil 38A. For this reason, a detailed description of the second coil 38B is omitted. The second coils 32A, 32B, 34A, and 34B are made of one or more of the following materials as appropriate: Ti, TiN, Ta, TaN, Au, Ag, Cu, Al, and W. In this embodiment, the second coils 32A, 32B, 34A, and 34B are made of a material containing Al.

[0249] In this embodiment, the number of turns of the first coil 31A and the number of turns of the second coil 32A (number of first opposing portions 39p) are the same. Also in this embodiment, the outer diameter of the coil portion 35 of the first coil 31A and the outer diameter of the second coil 32A are equal. Here, the outer diameter of the second coil 32A is the outer diameter of the first opposing portion 39p (see Figure 4) of the fourth loop-shaped conductive portion 39D. The same relationship applies to the first coil 31B and the second coil 32B as to the first coil 31A and the second coil 32A.

[0250] With this configuration, since the second coils 32A (32B) and 34A (34B) connected to each other are not formed with a misalignment in the z direction, the second coils 32A (32B) and 34A (34B) connected to each other can be easily formed within the element insulating layer 64.

[0251] The second electrode plate 122A and the second electrode plate 124A of the second embodiment may also be formed integrally in the same manner. Similarly, the second electrode plate 122B and the second electrode plate 124B may also be formed integrally in the same manner.

[0252] In the first embodiment, either the signal path that transmits the first signal from the primary circuit 13 to the secondary circuit 14, or the signal path that transmits the second signal from the primary circuit 13 to the secondary circuit 14, may be omitted. As an example, Figures 23 and 24 show the configuration of the transformer chip 60 when the signal path that transmits the second signal from the primary circuit 13 to the secondary circuit 14 is omitted.

[0253] As shown in Figures 23 and 24, the transformer chip 60 is a single-chip version of the transformer 15A. In other words, the element insulating layer 64 of the transformer chip 60 has the first coil 31A and the second coil 32A of the first transformer 21A, and the first coil 33A and the second coil 34A of the second transformer 22A embedded within it.

[0254] As shown in Figure 23, the first coil 31A of the first transformer 21A and the first coil 33A of the second transformer 22A are arranged so that they are aligned in the y-direction when viewed from the z-direction, and spaced apart in the x-direction. The first coils 31A and 33A are positioned aligned with each other in the z-direction. As shown in Figures 23 and 24, the arrangement of each coil 31A to 34A is the same as in the first embodiment.

[0255] As shown in Figure 23, the transformer tip 60 has two first electrode pads 61A, 61C and two second electrode pads 62A, 62C. The first electrode pad 61A is located inside the coil portion 35 of the first coil 31A, and the first electrode pad 61C is located outside the coil portion 35 of the first coil 31A. The first end 36 of the first coil 31A is connected to the first electrode pad 61A, and the second end 37 of the first coil 31A is connected to the first electrode pad 61C. The second electrode pad 62A is located inside the coil portion 35 of the first coil 33A, and the second electrode pad 62C is located outside the coil portion 35 of the first coil 33A. The first end 36 of the first coil 33A is connected to the second electrode pad 62A, and the second end 37 of the first coil 33A is connected to the second electrode pad 62C. The second embodiment can be similarly modified.

[0256] In the modification example shown in Figure 24, the second coils 32A and 34A may be changed to the first coil 38A shown in Figure 22. In the first embodiment, the trans tip 60 may include a dummy pattern. The dummy pattern includes, for example, a first dummy pattern provided in an annular shape to surround both the second coils 32A and 34A when viewed from the z direction, and a second dummy pattern provided in an annular shape to surround the second coils 32B and 34B. The dummy pattern also includes, for example, a third dummy pattern provided in an annular shape to surround the first coil 33A (33B) when viewed from the z direction.

[0257] In the first and second embodiments, the first coils 31A, 31B, 33A, and 33B may be formed from a Cu-containing material, and the second coils 32A, 32B, 34A, and 34B may be formed from an Al-containing material.

[0258] With this configuration, the first coils 31A, 31B, 33A, and 33B, through which relatively large currents flow, are formed from a Cu-containing material, allowing current to flow smoothly through them. On the other hand, the second coils 32A, 32B, 34A, and 34B are formed from an Al-containing material, making them cheaper to manufacture compared to the case where the second coils 32A, 32B, 34A, and 34B are formed from a Cu-containing material.

[0259] In the second embodiment, the positions of the multiple first electrode pads 131 of the capacitor chip 120 can be arbitrarily changed when viewed from the z direction. For example, the first electrode pad 131A may be positioned so as not to overlap with the first electrode plate 121A when viewed from the z direction. The first electrode pad 131B may be positioned so as not to overlap with the first electrode plate 121B when viewed from the z direction.

[0260] In the second embodiment, the positions of the multiple second electrode pads 132 of the capacitor chip 120 can be arbitrarily changed when viewed from the z direction. For example, the second electrode pad 132A may be positioned so as not to overlap with the first electrode plate 123A when viewed from the z direction. The second electrode pad 132B may be positioned so as not to overlap with the first electrode plate 123B when viewed from the z direction.

[0261] In each embodiment, the thickness TZ of the substrate insulating layer 63B can be arbitrarily changed. In one example, the thickness TZ of the substrate insulating layer 63B may be greater than or equal to the thickness T4 of the main body 63A. The thickness TZ of the substrate insulating layer 63B may be greater than or equal to the thickness T3 of the oxide film 63AC of the main body 63A. The thickness TZ of the substrate insulating layer 63B may be greater than or equal to the thickness T2 of the second semiconductor layer 63AB of the main body 63A. The thickness TZ of the substrate insulating layer 63B may be greater than or equal to the thickness T1 of the first semiconductor layer 63AA of the main body 63A.

[0262] In another example, the thickness TZ of the substrate insulating layer 63B may be thinner than the distance D2 between the second coils 32A(32B), 34A(34B) and the back surface 64r of the element insulating layer 64 in the z direction. Also, the thickness TZ of the substrate insulating layer 63B may be thinner than the distance D2 between the second electrode plates 122A(122B), 124A(124B) and the back surface 64r of the element insulating layer 64 in the z direction.

[0263] In another example, the thickness TZ of the substrate insulating layer 63B may be greater than or equal to the thickness TS3 of the third bonding material 103. The thickness TZ of the substrate insulating layer 63B may be greater than or equal to the thickness TS1 of the first bonding material 101. The thickness TZ of the substrate insulating layer 63B may be greater than or equal to the thickness TS2 of the second bonding material 102.

[0264] In another example, the thickness TZ of the substrate insulating layer 63B may be greater than or equal to the distance D1 between the first coil 31A (31B) and the second coil 32A (32B) in the z direction. The thickness TZ of the substrate insulating layer 63B may be greater than or equal to the distance D1 between the first coil 33A (33B) and the second coil 34A (34B) in the z direction. Furthermore, the thickness TZ of the substrate insulating layer 63B may be greater than or equal to the distance D1 between the first electrode plate 121A (121B) and the second electrode plate 122A (122B) in the z direction. The thickness TZ of the substrate insulating layer 63B may be greater than or equal to the distance D1 between the first electrode plate 123A (123B) and the second electrode plate 124A (124B) in the z direction.

[0265] In each embodiment, the thickness relationship between the first semiconductor layer 63AA, the second semiconductor layer 63AB, and the oxide film 63AC of the main body 63A can be arbitrarily changed. For example, the thickness T1 of the first semiconductor layer 63AA may be less than or equal to the thickness T2 of the second semiconductor layer 63AB. The thickness T2 of the second semiconductor layer 63AB may be less than or equal to the thickness T3 of the oxide film 63AC.

[0266] In each embodiment, at least one of the protective film 65 and the passivation film 66 may be omitted. In each embodiment, the third bonding material 103 can be arbitrarily changed. For example, the third bonding material 103 may be a conductive bonding material such as the first bonding material 101 and the second bonding material 102.

[0267] In each embodiment, the transformer chip 60 (capacitor chip 120) may be mounted on the primary die pad 70. In this case, the transformer chip 60 (capacitor chip 120) is bonded to the primary die pad 70 by the third bonding material 103.

[0268] ·In each embodiment, the transformer chip 60 (capacitor chip 120) may be mounted on an intermediate die pad different from the primary die pad 70 and the secondary die pad 80. The intermediate die pad is arranged between the primary die pad 70 and the secondary die pad 80 in the x direction. In this case, the transformer chip 60 (capacitor chip 120) is bonded to the intermediate die pad by the third bonding material 103.

[0269] ·In each embodiment, the sealing resin 90 may be omitted from the signal transmission device 10. ·In each embodiment, as the configuration of the element insulating layer 64, the transformer chip 60 (capacitor chip 120) may include a resin layer composed of one layer or a plurality of layers. A material containing any one of polyimide resin, phenol resin, and epoxy resin may be used as the resin layer.

[0270] ·The transformer chip 60 (capacitor chip 120) is applicable to devices other than the signal transmission device 10 of each embodiment. The transformer chip 60 (capacitor chip 120) may be applied to, for example, a primary-side circuit module. That is, the primary-side circuit module includes a first chip 40, the transformer chip 60 (capacitor chip 120), and a sealing resin that seals these chips 40, 60 (120). The primary-side circuit module also includes a primary die pad 70 on which both the first chip 40 and the transformer chip 60 (capacitor chip 120) are mounted. The first chip 40 is bonded to the primary die pad 70 by the first bonding material 101, and the transformer chip 60 (capacitor chip 120) is bonded to the primary die pad 70 by the third bonding material 103. In this case, the primary-side circuit 13 (see FIG. 1) included in the first chip 40 corresponds to the "signal transmission circuit", and the first chip 40 corresponds to the "circuit chip". The primary-side circuit module corresponds to the "insulation module".

[0271] The transformer chip 60 (capacitor chip 120) may be applied, for example, to a secondary circuit module. That is, the secondary circuit module comprises a second chip 50, a transformer chip 60 (capacitor chip 120), and a sealing resin that seals these chips 50, 60 (120). The secondary circuit module also comprises a secondary die pad 80 on which both the second chip 50 and the transformer chip 60 (capacitor chip 120) are mounted. The second chip 50 is bonded to the secondary die pad 80 by a second bonding material 102, and the transformer chip 60 (capacitor chip 120) is bonded to the secondary die pad 80 by a third bonding material 103. In this case, the secondary circuit 14 (see Figure 1) included in the second chip 50 corresponds to a "signal transmission circuit," and the second chip 50 corresponds to a "circuit chip." The secondary circuit module corresponds to an "isolation module."

[0272] In each embodiment, the configuration of the signal transmission device 10 can be arbitrarily changed. In one example, the signal transmission device 10 may include the primary side circuit module and the second chip 50. In this case, the second chip 50 may be mounted on the secondary side die pad 80, and both the secondary side die pad 80 and the second chip 50 may be configured as a module sealed with a sealing resin.

[0273] In another example, the signal transmission device 10 may include the secondary circuit module and the first chip 40. In this case, the first chip 40 may be mounted on the primary die pad 70, and both the primary die pad 70 and the first chip 40 may be contained in a module sealed with a sealing resin.

[0274] In each embodiment, the direction of signal transmission in the signal transmission device 10 can be arbitrarily changed. In one example, the signal transmission device 10 may be configured to transmit signals from the secondary circuit 14 to the primary circuit 13 via the transformer 15. More specifically, when a signal (e.g., a feedback signal) from a drive circuit electrically connected to the secondary circuit 14 via the secondary terminal 12 is input to the secondary terminal 12, the signal is transmitted from the secondary circuit 14 to the primary circuit 13 via the transformer 15. The signal from the primary circuit 13 is then output to a control device electrically connected to the primary circuit 13 via the primary terminal 11. Alternatively, the signal transmission device 10 may be configured to transmit signals bidirectionally between the primary circuit 13 and the secondary circuit 14. In short, the signal transmission device 10 may include a primary circuit 13 and a secondary circuit 14 configured to transmit and receive signals to the primary circuit 13 via the transformer 15.

[0275] As used in this disclosure, the term “on / above” includes the meanings of “on / above” and “above / beyond” unless the context clearly indicates otherwise. Therefore, the expression “A is formed on B” is intended to mean that in each of the above embodiments, A may be in contact with B and directly positioned on B, but as a modified example, A may be positioned above B without contact with B. In other words, the term “on / above” does not preclude structures in which other members are formed between A and B.

[0276] The z-direction used in this disclosure does not necessarily have to be vertical, nor does it have to coincide perfectly with the vertical. Therefore, the various structures described herein are not limited to the z-direction "up" and "down" being the same as the z-direction "up" and "down" being the same as the vertical. For example, the x-direction may be vertical, or the y-direction may be vertical.

[0277] In this specification, the phrase "at least one of A and B" should be understood to mean "A only, or B only, or both A and B." [Note] The technical concepts that can be understood from each of the above embodiments and their respective modifications are described below. The reference numerals for the components of the embodiments corresponding to the components described in each appendix are shown in parentheses. These reference numerals are provided as examples to aid understanding, and the components described in each appendix should not be limited to those indicated by these reference numerals.

[0278] (Note 1) A first chip (40) including the first circuit (13), The first die pad (70) on which the first chip (40) is mounted, Insulating tip (60), A second chip (50) includes a second circuit (14) configured to transmit and receive signals to the first circuit (13) via the insulating chip (60), The second die pad (80) on which the second chip (50) is mounted, A signal transmission device (10) equipped with, The insulating tip (60) is Circuit board (63) and An element insulating layer (64) having a surface (64s) and a back surface (64r) opposite to the surface (64s) and closer to the substrate (63) than the surface (64s), The element insulating layer (64) includes a first insulating element (21A, 21B) and a second insulating element (22A, 22B) that transmit the signal, It has, The first insulating element (21A, 21B) is A first surface-side conductive portion (31A, 31B) is located within the element insulating layer (64) and is positioned closer to the surface (64s) than the back surface (64r), The element insulating layer (64) is located closer to the back surface (64r) than the surface (64s), and the first surface-side conductive portion (31A, 31B) and the first back surface-side conductive portion (32A, 32B) are arranged opposite each other in the thickness direction (z direction) of the element insulating layer (64), Equipped with, The second insulating element (22A, 22B) is a second surface-side conductive portion (33A, 33B) disposed closer to said front surface (64s) than said back surface (64r) in said element insulating layer (64); a second back-side conductive portion (34A, 34B) disposed closer to said back surface (64r) than said front surface (64s) in said element insulating layer (64), and disposed opposite to said second surface-side conductive portion (33A, 33B) in the thickness direction (z-direction) of said element insulating layer (64); comprising: said first back-side conductive portion (32A, 32B) and said second back-side conductive portion (34A, 34B) are electrically connected to each other, said substrate (63) comprises: a main body portion (63A), and a substrate insulating layer (63B) formed on a surface (63As) of said main body portion (63A), including said element insulating layer (64) is laminated on a surface (63Bs) of said substrate insulating layer (63B) A signal transmission device.

[0279] (Supplementary Note 2) said substrate insulating layer (63B) includes an oxide film The signal transmission device according to Supplementary Note 1.

[0280] (Supplementary Note 3) said oxide film is a TEOS oxide film The signal transmission device according to Supplementary Note 2.

[0281] (Supplementary Note 4) a thickness (TZ) of said substrate insulating layer (63B) is thinner than a thickness (T4) of said main body portion (63A) The signal transmission device according to any one of Supplementary Notes 1 to 3.

[0282] (Supplementary Note 5) said main body portion (63A) comprises: a first semiconductor layer (63AA) in contact with said element insulating layer (63B), and an oxide film (63AC) provided on a side opposite to said element insulating layer (63B) with respect to said first semiconductor layer (63AA), A second semiconductor layer (63AB) is provided on the opposite side of the oxide film (63AC) from the first semiconductor layer (63AA), It is an SOI substrate having A signal transmission device as described in any one of the appendices 1 to 4.

[0283] (Note 6) The thickness (T1) of the first semiconductor layer (63AA) is greater than both the thickness (T3) of the oxide film (63AC) and the thickness (T2) of the second semiconductor layer (63AB). The thickness (TZ) of the substrate insulating layer (63B) is thinner than the thickness (T1) of the first semiconductor layer (63AA). The signal transmission device described in Appendix 5.

[0284] (Note 7) The thickness (T2) of the second semiconductor layer (63AB) is greater than the thickness (T3) of the oxide film (63AC). The thickness (TZ) of the substrate insulating layer (63B) is thinner than the thickness (T2) of the second semiconductor layer (63AB). The signal transmission device described in Appendix 6.

[0285] (Note 8) The thickness (TZ) of the substrate insulating layer (63B) is equal to the thickness (T3) of the oxide film (63AC). The signal transmission device described in Appendix 7.

[0286] (Note 9) Both the first back-side conductive portion (32A, 32B) and the second back-side conductive portion (34A, 34B) are arranged spaced apart from the back surface (64r) of the element insulating layer (64) in the thickness direction (z direction) of the element insulating layer (64). The thickness (TZ) of the substrate insulating layer (63B) is greater than or equal to the distance (D2) between the first back-side conductive portion (32A, 32B) and the back surface (64r) of the element insulating layer (64) in the thickness direction (z direction) of the element insulating layer (64). A signal transmission device as described in any one of the appendices 1 to 8.

[0287] (Note 10) The insulating tip (60) is bonded to the first die pad (70) or the second die pad (80) by a bonding material (103). The thickness (TZ) of the substrate insulating layer (63B) is thinner than the thickness (TS3) of the bonding material (103). A signal transmission device as described in any one of the appendices 1 to 9.

[0288] (Note 11) The aforementioned bonding material (103) is an insulating bonding material. The signal transmission device described in Appendix 10.

[0289] (Note 12) The first chip (40) is bonded to the first die pad (70) by the first conductive bonding material (101). The second chip (50) is bonded to the second die pad (80) by a second conductive bonding material (102). The signal transmission device described in Appendix 10 or 11.

[0290] (Note 13) The thickness (TZ) of the substrate insulating layer (63B) is thinner than the thickness (TS1) of the first conductive bonding material (101). The signal transmission device described in Appendix 12.

[0291] (Note 14) The thickness (TZ) of the substrate insulating layer (63B) is thinner than the thickness (TS2) of the second conductive bonding material (102). The signal transmission device described in Appendix 12 or 13.

[0292] (Note 15) The thickness (TZ) of the substrate insulating layer (63B) is 2 μm or more and 4 μm or less. A signal transmission device as described in any one of the appendices 1 to 14.

[0293] (Note 16) The thickness (TZ) of the substrate insulating layer (63B) is thinner than the distance (D1) between the first surface-side conductive portion (31A, 31B) and the first back-side conductive portion (32A, 32B) in the thickness direction (z direction) of the element insulating layer (63). A signal transmission device as described in any one of the appendices 1 to 15.

[0294] (Note 17) The first surface-side conductive portion is a first surface-side coil (31A, 31B) formed in a spiral or annular shape. The first back-side conductive portion is a first back-side coil (32A, 32B) formed in a spiral or annular shape. The second surface-side conductive portion is a second surface-side coil (33A, 33B) formed in a spiral or annular shape. The second back-side conductive portion is a second back-side coil (34A, 34B) formed in a spiral or annular shape. A signal transmission device as described in any one of the appendices 1 to 16.

[0295] (Note 18) The signal transmission device (10) transmits signals from the first circuit (13) to the second circuit (14) via a transformer (15A, 15B) having the first insulating element (21A, 21B) and the second insulating element (22A, 22B). The transformer includes a first signal transformer (15A) and a second signal transformer (15B), The signal transmitted via the transformer (15A, 15B) includes a first signal and a second signal. The first signal is transmitted from the first circuit (13) to the second circuit (14) via the first signal transformer (15A). The second signal is transmitted from the first circuit (13) to the second circuit (14) via the second signal transformer (15B). The signal transmission device described in Appendix 17.

[0296] (Note 19) The first surface-side conductive portion is a first surface-side electrode plate (121A, 121B) formed in a flat plate shape. The first back-side conductive portion is a first back-side electrode plate (122A, 122B) formed in a flat plate shape. The second surface-side conductive portion is a second surface-side electrode plate (123A, 123B) formed in a flat plate shape. The second back-side conductive portion is a second back-side electrode plate (124A, 124B) formed in a flat plate shape. A signal transmission device as described in any one of the appendices 1 to 16.

[0297] (Note 20) Circuit board (63) and An element insulating layer (64) having a surface (64s) and a back surface (64r) opposite to the surface (64s) and closer to the substrate (63) than the surface (64s), The first insulating element (21A, 21B) and the second insulating element (22A, 22B) are provided within the element insulating layer (64), It has, The first insulating element (21A, 21B) is A first surface-side conductive portion (31A, 31B) is located within the element insulating layer (64) and is positioned closer to the surface (64s) than the back surface (64r), The element insulating layer (64) is located closer to the back surface (64r) than the surface (64s), and the first surface-side conductive portion (31A, 31B) and the first back surface-side conductive portion (32A, 32B) are arranged opposite each other in the thickness direction (z direction) of the element insulating layer (64), Equipped with, The second insulating element (22A, 22B) is A second surface-side conductive portion (33A, 33B) is located within the element insulating layer (64) and is positioned closer to the surface (64s) than the back surface (64r), The element insulating layer (64) is located closer to the back surface (64r) than to the front surface (64s), and the second front surface conductive portion (33A, 33B) and the second back surface conductive portion (34A, 34B) are arranged opposite each other in the thickness direction (z direction) of the element insulating layer (64), Equipped with, The first back-side conductive portion (32A, 32B) and the second back-side conductive portion (34A, 34B) are electrically connected. The aforementioned substrate (63) is The main unit (63A) and A substrate insulating layer (63B) formed on the surface (63As) of the main body portion (63A), Includes, The element insulating layer (64) is laminated on the surface (63Bs) of the substrate insulating layer (63B). Insulating tip (60).

[0298] (Note 21) A back surface insulating layer (69) is provided on the substrate (63) on the side opposite to the substrate insulating layer (63B). A signal transmission device as described in any one of the appendices 1 to 19.

[0299] (Note 22) The thickness (TR) of the back surface insulating layer (69) is greater than the thickness (TZ) of the substrate insulating layer (63B). The signal transmission device described in Appendix 21.

[0300] (Note 23) The thickness (TR) of the back surface insulating layer (69) is thinner than the thickness (TB) of the substrate (63). The signal transmission device described in Appendix 21 or 22.

[0301] (Note 24) The aforementioned back surface insulating layer (69) contains resin A signal transmission device as described in any one of the appendices 21 to 23.

[0302] (Note 25) The surface 64s of the element insulating layer (64) is provided with first pads (61A, 61B) and second pads (62A, 62B). Viewed from the thickness direction (z direction) of the element insulating layer (64), the first pads (61A, 61B) are positioned offset from the center of the first surface coils (31A, 31B). Viewed from the thickness direction (z direction) of the element insulating layer (64), the second pads (62A, 63B) are offset from the center of the second surface coils (33A, 33B). The signal transmission device described in Appendix 17.

[0303] (Note 26) Viewed from the thickness direction (z direction) of the element insulating layer (64), the first pads (61A, 61B) are arranged inside the first surface coils (31A, 31B). Viewed from the thickness direction (z direction) of the element insulating layer (64), the second pads (62A, 62B) are positioned inside the second surface coils (33A, 33B). The signal transmission device described in Appendix 25.

[0304] (Note 27) The first back-side coils (32A, 32B) and the second back-side coils (34A, 34B) are arranged at the same position in the thickness direction (z direction) of the element insulating layer (64). The insulating chip (60) includes a first loop-shaped conductive portion (39A) and a second loop-shaped conductive portion (39B) provided within the element insulating layer (64), The first loop-shaped conductive portion (39A) is An open annular first opposing part (39p) and a second opposing part (39q) that are open and facing each other, The two opposing parts (39p, 39q) are connected by a connecting part (39r) that connects their open ends, forming a loop shape. The first opposing portion (39p) is positioned opposite the first surface coil (31A, 31B) in the thickness direction (z direction) of the element insulating layer (64), and constitutes the first back surface coil (32A, 32B). The second opposing portion (39q) is positioned opposite the second surface coil (33A, 33B) in the thickness direction (z direction) of the element insulating layer (64), and constitutes the second back surface coil (34A, 34B). The second loop-shaped conductive portion (39B) is It is formed in a manner similar to the first loop-shaped conductive portion (39A), and is arranged to surround the first loop-shaped conductive portion (39A) when viewed from the thickness direction (z direction) of the element insulating layer (64). The signal transmission device described in Appendix 17.

[0305] (Note 28) Both the first surface coil (31A, 31B) and the second surface coil (33A, 33B) are formed from a copper-containing material. Both the first back-side coil (32A, 32B) and the second back-side coil (34A, 34B) are formed from a material containing aluminum. The signal transmission device described in Appendix 17.

[0306] (Note 29) Viewed from the thickness direction (z direction) of the element insulating layer (64), the first die pad (70) and the second die pad (80) are arranged with a gap in between. The first chip (40), the second chip (50), and the insulating chip (60) are arranged with a gap between them in the first direction (x direction), which is the arrangement direction of the first die pad (70) and the second die pad (80). The first surface coils (31A, 31B) and the second surface coils (33A, 33B) are arranged with a gap between them in the first direction (x direction). The first back-side coils (32A, 32B) and the second back-side coils (34A, 34B) are arranged with a gap between them in the first direction (x direction). The first surface coil (31A) of the first signal transformer (15A) and the first surface coil (31B) of the second signal transformer (15B) are arranged with a gap between them in a second direction (y direction) that is perpendicular to the first direction (x direction) when viewed from the thickness direction (z direction) of the element insulating layer (64). The second surface coil (33A) of the first signal transformer (15A) and the second surface coil (33B) of the second signal transformer (15B) are arranged with a gap between them in the second direction (y direction). The first rear-side coil (32A) of the first signal transformer (15A) and the first rear-side coil (32B) of the second signal transformer (15B) are arranged with a gap between them in the second direction (y-direction). The second rear-side coil (34A) of the first signal transformer (15A) and the second rear-side coil (34B) of the second signal transformer (15B) are arranged with a gap between them in the second direction (y-direction). The signal transmission device described in Appendix 18.

[0307] (Note 30) A third pad (61C) and a fourth pad (62C) are formed on the surface (64s) of the element insulating layer (64). The third pad (61C) is positioned between the first surface coil (31A) of the first signal transformer (15A) and the first surface coil (31B) of the second signal transformer (15B), as viewed from the thickness direction (z direction) of the element insulating layer (64), and is electrically connected to the first surface coil (31A) of the first signal transformer (15A) and the first surface coil (31B) of the second signal transformer (15B). The fourth pad (62C) is positioned between the second surface coil (33A) of the first signal transformer (15A) and the second surface coil (33B) of the second signal transformer (15B), as viewed from the thickness direction (z direction) of the element insulating layer (64), and is electrically connected to the second surface coil (33A) of the first signal transformer (15A) and the second surface coil (33B) of the second signal transformer (15B). The signal transmission device described in Appendix 29.

[0308] (Note 31) The signal transmission device (10) transmits signals from the first circuit (13) to the second circuit (14) via capacitors (110A, 110B) having the first insulating elements (111A, 111B) and the second insulating elements (112A, 112B). The capacitor includes a first signal capacitor (110A) and a second signal capacitor (110B), The signal transmitted through the capacitors (110A, 110B) includes a first signal and a second signal. The first signal is transmitted from the first circuit (13) to the second circuit (14) via the first signal capacitor (110A). The second signal is transmitted from the first circuit (13) to the second circuit (14) via the second signal capacitor (110B). The signal transmission device described in Appendix 19.

[0309] (Note 32) Viewed from the thickness direction (z direction) of the element insulating layer (64), the first die pad (70) and the second die pad (80) are arranged with a gap in between. The first chip (40), the second chip (50), and the insulating chip (120) are arranged with a gap between them in the first direction (x direction), which is the arrangement direction of the first die pad (70) and the second die pad (80). The first surface electrode plates (131A, 131B) and the second surface electrode plates (133A, 133B) are arranged with a gap between them in the first direction (x direction). The first back-side electrode plates (132A, 132B) and the second back-side electrode plates (134A, 134B) are arranged with a gap between them in the first direction (x direction). The first surface electrode plate (131A) of the first signal capacitor (110A) and the first surface electrode plate (131B) of the second signal capacitor (110B) are arranged with a gap between them in a second direction (y direction) that is perpendicular to the first direction (x direction) when viewed from the thickness direction (z direction) of the element insulating layer (64). The second surface electrode plate (133A) of the first signal capacitor (110A) and the second surface electrode plate (133B) of the second signal capacitor (110B) are arranged with a gap between them in the second direction (y direction). The first back-side electrode plate (132A) of the first signal capacitor (110A) and the first back-side electrode plate (132B) of the second signal capacitor (110B) are arranged with a gap between them in the second direction (y direction). The second back-side electrode plate (134A) of the first signal capacitor (110A) and the second back-side electrode plate (134B) of the second signal capacitor (110B) are arranged with a gap between them in the second direction (y-direction). The signal transmission device described in Appendix 31.

[0310] (Note 33) The surface (64s) of the element insulating layer (64) is provided with first pads (131A, 131B) and second pads (132A, 132B). The first pads (131A, 131B) are positioned so as to overlap with the first surface electrode plate (121A) of the first signal capacitor (110A) and the first surface electrode plate (121B) of the second signal capacitor (110B) when viewed from the second direction (y direction). The second pads (132A, 132B) are positioned so as to overlap with the second surface electrode plate (123A) of the first signal capacitor (110A) and the second surface electrode plate (123B) of the second signal capacitor (110B) when viewed from the second direction (y direction). The signal transmission device described in Appendix 32.

[0311] (Note 34) The insulating chip (60) described in Appendix 20, A circuit chip (40 / 50) including a signal transmission circuit (13 / 14) electrically connected to the insulating chip (60), Equipped with Insulation module.

[0312] (Note 35) A circuit board (63) having a main body (63A), An element insulating layer (64) having a surface (64s) and a back surface (64r) opposite to the surface (64s) and closer to the substrate (63) than the surface (64s), The first insulating element (21A, 21B) and the second insulating element (22A, 22B) are provided within the element insulating layer (64), A method for manufacturing an insulating chip (60) equipped with, The first insulating element (21A, 21B) is A first surface-side conductive portion (31A, 31B) is located within the element insulating layer (64) and is positioned closer to the surface (64s) than the back surface (64r), The element insulating layer (64) is located closer to the back surface (64r) than the surface (64s), and the first surface-side conductive portion (31A, 31B) and the first back surface-side conductive portion (32A, 32B) are arranged opposite each other in the thickness direction (z direction) of the element insulating layer (64), Equipped with, The second insulating element (22A, 22B) is A second surface-side conductive portion (33A, 33B) is located within the element insulating layer (64) and is positioned closer to the surface (64s) than the back surface (64r), The element insulating layer (64) is located closer to the back surface (64r) than to the front surface (64s), and the second front surface conductive portion (33A, 33B) and the second back surface conductive portion (34A, 34B) are arranged opposite each other in the thickness direction (z direction) of the element insulating layer (64), Equipped with, The first back-side conductive portion (32A, 32B) and the second back-side conductive portion (34A, 34B) are electrically connected. The method for manufacturing the insulating chip (60) is as follows: A substrate insulating layer formation step is performed to form a substrate insulating layer (631) on the surface (630s) of the semiconductor wafer (630) that constitutes the main body (63A), A step of laminating the element insulating layer (640) containing both insulating elements (21A, 21B, 22A, 22B) onto the surface of the substrate insulating layer (631), A method for manufacturing insulating chips, including the method described above.

[0313] (Note 36) The substrate insulating layer formation step includes the step of forming the substrate insulating layer (631) on both sides (630s, 630r) of the semiconductor wafer (630). The method for manufacturing an insulating chip as described in Appendix 35.

[0314] (Note 37) The substrate insulating layer formation step includes a step of removing the substrate insulating layer (631) on the back surface (630r) of the semiconductor wafer (630) after the element insulating layer (640) has been laminated. The method for manufacturing an insulating chip as described in Appendix 36.

[0315] (Note 38) In the process of laminating the element insulating layer (640) and the process of forming the substrate insulating layer (631), the method of forming the element insulating layer (640) and the direction of forming the substrate insulating layer (631) are different from each other. A method for manufacturing an insulating chip as described in any one of appendices 35 to 37.

[0316] (Note 39) In the process of laminating the element insulating layer (640), the element insulating layer (640) is formed by plasma CVD. The method for manufacturing an insulating chip as described in Appendix 38.

[0317] (Note 40) In the process of forming the substrate insulating layer (631) on both sides (630s, 630r) of the semiconductor wafer (630), the substrate insulating layer (631) is formed by thermal oxidation of the semiconductor wafer (630). A method for manufacturing an insulating chip as described in Appendix 38 or 39.

[0318] (Note 41) In the process of forming the substrate insulating layer (631) on both sides (630s, 630r) of the semiconductor wafer (630), the substrate insulating layer (631) is formed by a reduced-pressure CVD method using TEOS gas. A method for manufacturing an insulating chip as described in Appendix 38 or 39.

[0319] (Note 42) The process includes cutting the semiconductor wafer (630) together with the element insulating layer (640) to separate it into a plurality of insulating chips (60). A method for manufacturing an insulating chip as described in any one of the appendices 35 to 41.

[0320] (Note 43) The semiconductor wafer (630) is made of SOI wafer. A method for manufacturing an insulating chip as described in any one of the appendices 35 to 42.

[0321] The above description is for illustrative purposes only. Those skilled in the art will recognize that many more possible combinations and substitutions are possible beyond the components and methods (manufacturing processes) enumerated for the purpose of illustrating the technology of this disclosure. This disclosure is intended to encompass all alternatives, variations, and modifications included within the scope of this disclosure, including the claims and appendices. [Explanation of symbols]

[0322] 10... Signal transmission device 10A...Signal transmission circuit 11…Primary side terminal 12…Secondary side terminal 13…Primary side circuit (1st circuit) 14…Secondary side circuit (second circuit) 15…Trans 15A…Transformer (Transformer for the first signal) 15B…Transformer (Transformer for the second signal) 16A,16B…Primary side signal line 17A, 17B…Secondary side signal line 18A, 18B, 19A, 19B, 20A, 20B… Connection signal lines 21A, 21B... First transformer (first insulating element) 22A, 22B... Second transformer (second insulating element) 31A, 31B... First coil (first surface-side conductive part, first surface-side coil) 33A, 33B... First coil (Second surface side conductive part, second surface side coil) 32A, 32B... Second coil (first back side conductive part, first back side coil) 34A, 34B... Second coil (Second back side conductive part, Second back side coil) 35... Coil section 36...First end 37…Second end 38A…First coil 38B... Second coil 39A...First loop-shaped conductive part 39B...Second loop-shaped conductive part 39C...Third loop-shaped conductive part 39D...Fourth loop-shaped conductive part 39p...1st opposing part 39q...Second opposing section 39r…Connection part 39ra...1st connection part 39rb…Second connection part 40…First chip 40s… Main surface of the chip 40r…back of the chip 41…First electrode pad 42...Second electrode pad 43... Circuit board 44...Wiring layer 50…Second chip 50s… Main surface of the chip 50r…back of the chip 51…First electrode pad 52...Second electrode pad 53... Circuit board 54...Wiring layer 60…Transformer chip (isolation chip) 60s... Main surface of the chip 60r…back of the chip 61…First electrode pad 61A, 61B... First electrode pad (first pad) 61C…First electrode pad (third pad) 62...Second electrode pad 62A, 62B... Second electrode pad (second pad) 62C…Second electrode pad (fourth pad) 63... Circuit board 63s…Substrate surface 63r...backside of the circuit board 63A...Main unit 63As…Surface 63Ar…Back side 63AA…First semiconductor layer 63AB...Second semiconductor layer 63AC…Oxide film 63B...Insulating layer of the substrate 63Bs…Surface 63Br... Reverse side 64... Element insulating layer 64s…Surface 64r…Back side 64A...First insulating film 64B...Second insulating film 65...Protective film 66... ​​Passivation membrane 67A~67D...Connecting wires 68A, 68B…connecting wires 69…Insulating layer on the back 69s…Surface 69r…back side 70... Primary side die pad (first pad) 80...Secondary die pad (second pad) 90...Sealing resin 101...First bonding material (first conductive bonding material) 102...Second bonding material (second conductive bonding material) 103...Third bonding material (bonding material, insulating bonding material) 110...Capacitor 110A…Capacitor (Capacitor for the first signal) 110B...Capacitor (Capacitor for the second signal) 111A, 111B... First capacitor (first insulating element) 112A, 112B... Second capacitor (second insulating element) 113A, 113B, 115A, 115B…1st electrode 114A,114A,116A,116B…Second electrode 120... Capacitor chip (insulating chip) 120s... Main surface of the chip 120r…back of the chip 121A, 121B...First electrode plate (first surface side conductive part, first surface side electrode plate) 123A, 123B...First electrode plate (second surface side conductive part, second surface side electrode plate) 122A, 122B...Second electrode plate (first back side conductive part, first back side electrode plate) 124A, 124B...Second electrode plate (second back side conductive part, second back side electrode plate) 131, 131A, 131B... First electrode pad (first pad) 132, 132A, 132B... Second electrode pad (second pad) 141A, 141B, 142A, 142B…connecting wires 630…SOI wafer (semiconductor wafer) 630s…Surface 630r…back side 631… Insulating film 640... Element insulating layer 650…Protective film 660... Passivation membrane W...wire TC1…Thickness of the first chip TC2…Thickness of the second chip TC3... Thickness of the transformer chip (capacitor chip) TS1... Thickness of the first bonding material TS2…Thickness of the second bonding material TS3...Thickness of the third bonding material TA...Thickness of one layer of the element's insulating layer TB... Thickness of the circuit board TC... thickness of the protective film TD... Thickness of the passivation film TR...Thickness of the insulating layer on the back side TT...Total thickness of the element's insulating layer TZ...Thickness of the insulating layer on the substrate T1...Thickness of the first semiconductor layer T2…Thickness of the second semiconductor layer T3...Oxide film thickness T4…Thickness of the main body of the circuit board D1…Distance between the first coil and the second coil D2…Distance between the second coil and the back surface of the element's insulating layer D3…Distance between the first coil and the surface of the element's insulating layer D4…Distance between the second coil and the primary die pad

Claims

1. A first chip including the first circuit, The first die pad on which the first chip is mounted, Insulating chip and, A second chip includes the first circuit via the insulating chip and a second circuit configured to transmit and receive at least one of signals, The second die pad on which the second chip is mounted, A signal transmission device equipped with, The aforementioned insulating chip is circuit board and An element insulating layer having a surface and a back surface opposite to the surface and closer to the substrate than the surface, The device comprises a first insulating element and a second insulating element provided within the element insulating layer for transmitting the signal, The first insulating element is, A first surface-side conductive portion is provided within the element insulating layer, positioned closer to the surface than the back surface, The element insulating layer comprises a first surface-side conductive portion and a first back-side conductive portion, which is positioned closer to the back surface than the front surface within the element insulating layer, and which is positioned opposite the first surface-side conductive portion in the thickness direction of the element insulating layer. The second insulating element is, A second surface-side conductive portion is provided within the element insulating layer, positioned closer to the surface than the back surface, The element insulating layer comprises a second surface-side conductive portion and a second back-side conductive portion, which is positioned closer to the back surface than the front surface within the element insulating layer and is opposed to the second surface-side conductive portion in the thickness direction of the element insulating layer. The first back-side conductive portion and the second back-side conductive portion are electrically connected. The aforementioned substrate is The main body and A substrate insulating layer formed on the surface of the main body, Includes, The element insulating layer is laminated on the surface of the substrate insulating layer. A signal transmission device.

2. The substrate insulating layer includes an oxide film. The signal transmission device according to claim 1.

3. The oxide film is a TEOS oxide film. The signal transmission device according to claim 2.

4. The thickness of the substrate insulating layer is thinner than the thickness of the main body. The signal transmission device according to claim 1.

5. The main body is, A first semiconductor layer in contact with the aforementioned element insulating layer, An oxide film provided on the side opposite to the element insulating layer with respect to the first semiconductor layer, A second semiconductor layer is provided on the side opposite to the first semiconductor layer relative to the oxide film, It is a sharp SOI substrate. The signal transmission device according to claim 1.

6. The thickness of the first semiconductor layer is greater than both the thickness of the oxide film and the thickness of the second semiconductor layer. The thickness of the substrate insulating layer is thinner than the thickness of the first semiconductor layer. The signal transmission device according to claim 5.

7. The thickness of the second semiconductor layer is greater than the thickness of the oxide film. The thickness of the substrate insulating layer is thinner than the thickness of the second semiconductor layer. The signal transmission device according to claim 6.

8. The thickness of the substrate insulating layer is equal to the thickness of the oxide film. The signal transmission device according to claim 7.

9. Both the first back-side conductive portion and the second back-side conductive portion are arranged spaced apart from the back surface of the element insulating layer in the thickness direction of the element insulating layer. The thickness of the substrate insulating layer is greater than or equal to the distance between the first back-side conductive portion and the back surface of the element insulating layer in the thickness direction of the element insulating layer. The signal transmission device according to claim 1.

10. The insulating chip is bonded to the first die pad or the second die pad by a bonding material. The thickness of the substrate insulating layer is thinner than the thickness of the bonding material. The signal transmission device according to claim 1.

11. The aforementioned bonding material is an insulating bonding material. The signal transmission device according to claim 10.

12. The first chip is bonded to the first die pad by a first conductive bonding material. The second chip is bonded to the second die pad by a second conductive bonding material. The signal transmission device according to claim 10.

13. The thickness of the substrate insulating layer is thinner than the thickness of the first conductive bonding material. The signal transmission device according to claim 12.

14. The thickness of the substrate insulating layer is thinner than the thickness of the second conductive bonding material. The signal transmission device according to claim 12.

15. The thickness of the substrate insulating layer is 2 μm or more and 4 μm or less. The signal transmission device according to claim 1.

16. The thickness of the substrate insulating layer is thinner than the distance between the first surface-side conductive portion and the first back-side conductive portion in the thickness direction of the element insulating layer. The signal transmission device according to claim 1.

17. The first surface-side conductive portion is a first surface-side coil formed in a spiral or annular shape, The first back-side conductive portion is a first back-side coil formed in a spiral or annular shape, The second surface-side conductive portion is a second surface-side coil formed in a spiral or annular shape, The second back-side conductive portion is a second back-side coil formed in a spiral or annular shape. A signal transmission device according to any one of claims 1 to 16.

18. The signal transmission device transmits signals from the first circuit to the second circuit via a transformer having the first insulating element and the second insulating element. The transformer includes a first signal transformer and a second signal transformer. The signal transmitted through the transformer includes a first signal and a second signal. The first signal is transmitted from the first circuit to the second circuit via the first signal transformer. The second signal is transmitted from the first circuit to the second circuit via the second signal transformer. The signal transmission device according to claim 17.

19. The first surface-side conductive portion is a first surface-side electrode plate formed in a flat plate shape, The first back-side conductive portion is a first back-side electrode plate formed in a flat plate shape, The second surface-side conductive portion is a second surface-side electrode plate formed in a flat plate shape, The second back-side conductive portion is a second back-side electrode plate formed in a flat plate shape. A signal transmission device according to any one of claims 1 to 16.

20. circuit board and An element insulating layer having a surface and a back surface opposite to the surface and closer to the substrate than the surface, A first insulating element and a second insulating element are provided within the element insulating layer, It has, The first insulating element is, A first surface-side conductive portion is provided within the element insulating layer, positioned closer to the surface than the back surface, The element insulating layer comprises a first surface-side conductive portion and a first back-side conductive portion, which is positioned closer to the back surface than the front surface within the element insulating layer, and which is positioned opposite the first surface-side conductive portion in the thickness direction of the element insulating layer. The second insulating element is, A second surface-side conductive portion is provided within the element insulating layer, positioned closer to the surface than the back surface, The element insulating layer comprises a second surface-side conductive portion and a second back-side conductive portion, which is positioned closer to the back surface than the front surface within the element insulating layer and is opposed to the second surface-side conductive portion in the thickness direction of the element insulating layer. The first back-side conductive portion and the second back-side conductive portion are electrically connected. The aforementioned substrate is The main body and A substrate insulating layer formed on the surface of the main body, Includes, The element insulating layer is laminated on the surface of the substrate insulating layer. Insulating chip.

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