Parts for semiconductor manufacturing equipment

Abstract

The present invention relates to a component for a semiconductor manufacturing apparatus and a heat-resistant material. The component for a semiconductor manufacturing apparatus according to the present invention includes a plurality of layers of steps on a cross section, and the plurality of layers include a first surface exposed to plasma and a second surface placed on the semiconductor manufacturing apparatus.

Description

Technical Field

[0001] The present invention relates to a component for semiconductor manufacturing equipment Product . Background Art

[0002] In general, dry etching used in semiconductor manufacturing processes includes plasma etching which uses gas-phase etching gas and plasma. In this process, after an etching gas is introduced into a reaction vessel and ionized, it is accelerated at the surface of a wafer to physically and chemically remove the uppermost layer of the wafer surface. It is widely used because etching adjustment is easy, productivity is high, and fine patterns at a level of tens of nanometers can be formed.

[0003] Actually, from the perspective of the wafer to be etched, it is essential to apply uniform high frequency with a uniform energy distribution over the entire surface of the wafer. The application of such uniform energy distribution when applying high frequency cannot be achieved only by adjusting the high frequency output. To solve this problem, it is greatly affected by the forms of the stage and anode serving as a high-frequency electrode used to apply high frequency to the wafer, as well as the etch ring that substantially functions to fix the wafer. The etch ring serves to prevent diffusion of plasma in the reaction chamber of a dry etching apparatus under severe conditions where plasma exists, and to confine plasma around the wafer on which etching processing is performed.

[0004] Generally, when producing a material by the CVD method, the material is produced by laminating a plurality of deposited layers. Although this material has superior plasma resistance compared to a material produced by a sintering method that contains compact pores, it has the problem of reduced processability.

[0005] In particular, for complex shapes with a plurality of steps, precise processing is difficult, which causes problems such as increased processing time, reduced productivity, and increased cost.

[0006] Furthermore, when the boundaries between multiple vapor-deposited layers are exposed during processing, problems arise such as uneven plasma etching at the layer boundaries, which can induce the generation of particles.

[0007] Therefore, among the semiconductor manufacturing processes, the technology to minimize particle generation used in the plasma etching process, particularly in the manufacturing of etch rings, and to improve the processability of the product remains a core area requiring development in order to lower the production cost of semiconductor products. [Overview of the project] [Problems that the invention aims to solve]

[0008] The present invention aims to solve the above-mentioned problems, and the object of the present invention is a semiconductor manufacturing equipment part that can minimize the time-consuming processing steps in manufacturing semiconductor manufacturing equipment parts and improve productivity. items The objective is to provide a solution. Another objective of the present invention is to prevent the generation of particles by ensuring that the interface is not exposed during the plasma etching process.

[0009] However, the problems that this invention aims to solve are not limited to those mentioned above, and further problems not mentioned can be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0010] The semiconductor manufacturing apparatus component of the present invention includes a plurality of stepped layers on its cross-section, wherein each of the plurality of layers includes a first surface exposed to plasma and a second surface placed on the semiconductor manufacturing apparatus.

[0011] The first surface may be the same stacking surface.

[0012] The plasma resistance of the first surface is greater than that of the second surface, and the laminated surface may be formed by stacking the surfaces with a cross-section aligned with the first surface.

[0013] The same surface of the aforementioned multiple layers may contain grains whose size deviation is ±10% from the average value.

[0014] The first surface may be an inclined surface exposed to the plasma, and the second surface may be a base surface.

[0015] The first surface may be a CVD substrate surface, and the second surface may be a CVD growth surface.

[0016] The aforementioned part was formed by CVD growth from the first surface.

[0017] Grains on the same surface among the aforementioned multiple layers can have a size within ±10% of the average grain size.

[0018] The grain size of the first surface may be smaller than the grain size of the second surface.

[0019] The semiconductor manufacturing equipment component is an etch ring, and the first surface may include a step and may be a wafer mounting surface.

[0020] The aforementioned component may be made of SiC or B4C material as the plasma-resistant material.

[0021] The aforementioned component may be one in which the boundary of the deposited layer is not exposed to the plasma.

[0022] The present invention provides a method for manufacturing a component for semiconductor manufacturing equipment, comprising the steps of: preparing a base material; forming a vapor-deposited layer containing SiC or B4C so as to surround the base material; processing the vapor-deposited layer; and removing the base material to obtain a component for semiconductor manufacturing equipment containing at least one SiC or B4C.

[0023] The aforementioned base material may contain carbon-based materials.

[0024] The vapor deposition layer may be formed by CVD growth from a first surface in contact with the base material to a second surface which is the surface to be processed.

[0025] The plasma resistance of said first surface is greater than the plasma resistance of said second surface.

[0026] Said first surface may be an inclined surface exposed to plasma, and said second surface may be a base surface.

[0027] The grain size of said first surface is smaller than the grain size of said second surface.

[0028] Said base material has a vertically symmetrical shape, and said component for a semiconductor manufacturing apparatus containing one or more of SiC or B4C may have the same shape.

[0029] Said component for a semiconductor manufacturing apparatus is an etch ring, and said base material may include steps on an upper surface and a lower surface.

Effects of the Invention

[0030] The component for a semiconductor manufacturing apparatus according to one embodiment of the present invention is excellent in plasma resistance because the surface exposed to plasma is formed on the same surface even when laminated by the CVD method, so that the etching rate caused by plasma can be reduced. Accordingly, since the service life of the component for a semiconductor manufacturing apparatus is extended and the replacement cycle of the component is increased, the replacement cost of the component for a semiconductor manufacturing apparatus can be reduced.

[0031] Furthermore, since the replacement cycle of the component for a semiconductor manufacturing apparatus is prolonged, interruption of the etching process can be reduced, and the productivity of the semiconductor plasma etching process can be improved.

[0032] A method for manufacturing semiconductor manufacturing equipment components according to one embodiment of the present invention improves processability and ultimately reduces the production cost of semiconductor products by eliminating some of the conventional processing steps in the manufacturing process of semiconductor manufacturing equipment components. Furthermore, since at least one or more semiconductor manufacturing equipment components can be obtained in a single process, the manufacturing process is shortened, and it is expected that the production efficiency of semiconductor manufacturing equipment components will be improved.

[0033] Furthermore, according to one embodiment of the present invention, the effect of not generating particles can be obtained by not exposing the interface surface during the plasma etching process. [Brief explanation of the drawing]

[0034] [Figure 1] This is a cross-sectional view of a component for semiconductor manufacturing equipment according to one embodiment of the present invention. [Figure 2] This is an illustrative cross-sectional view showing the lamination surface of a semiconductor manufacturing equipment component according to one embodiment of the present invention. [Figure 3] This is a cross-sectional view illustrating the grain sizes of the first and second surfaces according to one embodiment of the present invention. [Figure 4] This is a schematic diagram showing the manufacturing process of semiconductor manufacturing equipment components related to one embodiment of the present invention. [Figure 5] This is a schematic diagram showing the manufacturing process of semiconductor manufacturing equipment components related to one embodiment of the present invention. [Figure 6] This is a schematic diagram showing the manufacturing process of semiconductor manufacturing equipment components related to one embodiment of the present invention. [Figure 7] This is a schematic diagram showing the manufacturing process of semiconductor manufacturing equipment components related to one embodiment of the present invention. [Figure 8] This is a schematic diagram showing the manufacturing process of a component for semiconductor manufacturing equipment according to another embodiment of the present invention. [Figure 9] This is a schematic diagram showing the manufacturing process of a component for semiconductor manufacturing equipment according to another embodiment of the present invention. [Figure 10] This is a schematic diagram showing the manufacturing process of a component for semiconductor manufacturing equipment according to another embodiment of the present invention. [Figure 11] This is a schematic diagram showing the manufacturing process of a component for semiconductor manufacturing equipment according to another embodiment of the present invention. [Modes for carrying out the invention]

[0035] Embodiments of the present invention will be described in detail below with reference to the attached drawings. In the description of the present invention, if a specific description of a relevant prior art function or configuration is deemed to unnecessarily obscure the gist of the invention, such detailed description will be omitted. Furthermore, the terms used herein are those used to appropriately express preferred embodiments of the present invention, and these may vary depending on the intent of the user, operator, or the conventions of the art to which the invention belongs. Accordingly, the definitions of these terms must be based on the content throughout this specification. The same reference numerals shown in each drawing indicate the same component.

[0036] Throughout the specification, when any member is located "on top of" another member, this includes not only cases where the member is in contact with another member, but also cases where there is an additional member between the two members.

[0037] When any part of the specification "includes" any component, this means that it further includes other components, rather than excluding them.

[0038] The semiconductor manufacturing equipment component and its manufacturing method of the present invention will be described in detail below with reference to embodiments and drawings. However, the present invention is not limited to such embodiments and drawings.

[0039] The semiconductor manufacturing apparatus component of the present invention includes multiple layers (between multiple layers) of steps in its cross-section, and each of the multiple layers includes a first surface exposed to plasma and a second surface placed on the semiconductor manufacturing apparatus.

[0040] The semiconductor manufacturing equipment component of the present invention relates not to the semiconductor itself, but to a part of the equipment used to manufacture semiconductors. In other words, it relates to a component of semiconductor manufacturing equipment.

[0041] A semiconductor manufacturing equipment component according to one embodiment of the present invention has excellent plasma resistance, which reduces the etching rate caused by plasma etching. Therefore, the lifespan of the semiconductor manufacturing equipment component can be extended, reducing the replacement cost of the semiconductor manufacturing equipment component, and the interruption of the etching process associated with the semiconductor manufacturing equipment component can be reduced, thereby improving the productivity of the etching process. Furthermore, according to the present invention, since the interface surface is not exposed during the plasma etching process, no particles are generated, thus eliminating process problems caused by particles.

[0042] Figure 1 is a cross-sectional view of a component for semiconductor manufacturing equipment according to one embodiment of the present invention.

[0043] Referring to Figure 1, part 100 according to one embodiment of the present invention includes a first surface 110 and a second surface 120.

[0044] According to one embodiment, the first surface 110 and the second surface 120 have different plasma resistance properties of SiC, and this difference results in a difference in the tendency to etch with respect to plasma. Therefore, the first surface 110, which is the periphery of a wafer that is etched in the reaction chamber of a semiconductor manufacturing apparatus under harsh conditions where plasma is present, for example, a dry etching apparatus, has greater plasma resistance than the second surface 120, and the lifespan of the semiconductor manufacturing apparatus components can be extended.

[0045] According to one embodiment, the first surface may be the same laminated surface. If the first surface exposed to the plasma environment is not the same laminated surface (same deposition surface) and includes a laminate boundary, particles may be generated from the laminate boundary. In contrast, the semiconductor manufacturing equipment component of the present invention has a first surface exposed to the plasma environment that is the same laminated surface (same deposition surface) and does not include a laminate boundary, thus reducing the generation of particles or defects and further improving plasma resistance.

[0046] The first surface 110 may be an inclined surface exposed to the plasma, and the second surface 120 may be a base surface. The inclined surface exposed to the plasma means the surface on which the component 100 is mounted and exposed to the plasma generated in the semiconductor manufacturing apparatus. The base surface is the surface on which the component 100 is processed after being grown by chemical vapor deposition (CVD) and mounted in the manufacturing apparatus.

[0047] In particular, since component 100 is formed by a chemical vapor deposition process, it has sufficient corrosion resistance and strength, and can have a homogeneous surface without pore formation. Furthermore, component 100 can be made of SiC (Silicon carbide) or B4C (Boron Carbide) as a plasma-resistant material. Materials are also acceptable.

[0048] According to one embodiment, the first surface may be an inclined surface exposed to plasma, the second surface may be a base surface, the first surface may be a CVD substrate surface, and the second surface may be a CVD growth surface.

[0049] The CVD substrate surface is the surface on which the deposition of the component 100 is initiated by CVD. The CVD growth surface is the surface on which the material grows through the deposition of the component 100 by CVD.

[0050] According to one embodiment, the part 100 is formed by CVD growth from the first surface 110.

[0051] According to one embodiment, the first surface 110 is an unformed surface that has not undergone any processing to substantially alter its shape (in particular, a surface that does not form a shape as intended). The unformed surface means that some processing, such as flattening, is performed, but there is no processing to substantially change its shape.

[0052] The first surface 110 may be an unshaped surface that has not been shaped, as it is the surface on which vapor deposition is initiated by CVD.

[0053] The plasma resistance of the first surface is greater than that of the second surface, and the laminated surface may include a cross-section formed by stacking along the first surface.

[0054] Figure 2 is an illustrative cross-sectional view showing the lamination surface of a semiconductor manufacturing equipment component according to one embodiment of the present invention.

[0055] Referring to Figure 2, the semiconductor manufacturing equipment component according to one embodiment of the present invention is formed by stacking SiC along the first surface 110, and the multiple stacking boundaries 130, 130', and 130'' on the cross-section show stacking lines that are curved according to the shape of the first surface.

[0056] The laminated surface of the semiconductor manufacturing equipment component may be arranged so that each layer is parallel to the laminated surface of the semiconductor manufacturing equipment component.

[0057] Referring to Figure 2, since the plasma-resistant surface is formed on the same deposition surface, it has uniform etching characteristics, resulting in a uniform degree of etching. When the boundary where different deposition surfaces meet is exposed, particles are easily generated at the boundary by the plasma, and if the area is relatively etched, sustained etching concentration occurs, triggering an overall deterioration of physical properties. However, according to the present invention, since there is no boundary of the deposition surface on the plasma-resistant surface, the generation of particles, etching concentration, and acceleration described above can be prevented.

[0058] In this invention, the same vapor-deposited surface refers to a vapor-deposited surface exhibiting the same degree of transmittance. Transmittance is defined as the degree to which light passes through the material layer, and is the value obtained by dividing the intensity of the light that has passed through the material layer by the intensity of the light incident on the material layer. Transmittance can be measured by various methods, but in this case, a test specimen was prepared with a thickness of 3 mm, and the measurement was taken using a light source with a luminous intensity of 150 Lux or more, with the distance between the test specimen and the light source being 7 cm or less.

[0059] The test specimens were manufactured to a thickness of 2 mm, and these 2 mm specimens were verified using photographs and videos. When this is done, a clearly identical deposition surface can be confirmed. The test specimens are manufactured to a thickness of 1 mm, and when examined with the naked eye, a clearly identical deposition surface can be confirmed for 1 mm thick test specimens. Since transmittance can change depending on the thickness, light source, and the distance between the test specimen and the light source, it is considered as a relative value for the same thickness.

[0060] According to one embodiment, the laminated surface may include a curved surface.

[0061] According to one embodiment, the same surface of the multiple layers may contain grains whose size deviation is ±10% from the average value. The grain size is the average diameter of the grains. As you move from the first surface 110 to the second surface 120, the grain size gradually increases or becomes more similar.

[0062] According to one embodiment, the same surface of the multiple layers may contain grains whose size deviation is ±10% from the average value, and according to one embodiment, the grain size of the first surface 110 is smaller than the grain size of the second surface 120.

[0063] Since each layer is formed by the same deposition process, the surfaces of each layer may contain grains whose size deviation is ±10% from the average value.

[0064] Figure 3 is a cross-sectional view illustrating the grain sizes of the first and second surfaces according to one embodiment of the present invention.

[0065] Referring to Figure 3, the grain size of the first surface 110 becomes relatively smaller and more compact as the raw material is deposited by the CVD method and the component material begins to grow. As more deposition occurs, that is, as you move towards the second surface 120, the SiC grain size gradually increases. Therefore, the component 100 has multiple laminated surfaces that are repeatedly formed, and the grain size is the same for all of the same laminated surfaces.

[0066] In one embodiment, the first surface 110 and the second surface 120 have different SiC grain sizes, resulting in a difference in their etching tendency to plasma. The first surface 110, which has a smaller and more compact SiC grain size and is the periphery of the wafer being etched in the reaction chamber of a semiconductor manufacturing apparatus, such as a dry etching apparatus, can reduce the etching rate by plasma compared to the second surface 120. That is, the smaller the grain size, the greater the plasma resistance, and the larger the grain size, the less plasma resistance.

[0067] According to one embodiment, the semiconductor manufacturing equipment component is an etch ring, the first surface includes a step, and is the wafer mounting surface. The etch ring fixes the wafer in the reaction chamber of the semiconductor manufacturing equipment to prevent plasma diffusion and concentrates the plasma around the wafer where the etching process is performed. The first surface 110 of the etch ring, which has a small grain size, is exposed to the plasma, thereby reducing the etching rate at which the etch ring is etched by the plasma. Consequently, the lifespan of the etch ring can be extended, the cost of replacing the etch ring can be reduced, and the interruption of the etching process due to the replacement of the etch ring can be reduced, thereby improving the productivity of the etching process.

[0068] According to one embodiment, the semiconductor manufacturing equipment component may be an electrode in addition to an etch ring. The electrode is used in a plasma etching apparatus and is provided with multiple holes that evenly disperse the etching gas supplied externally to the inside of the plasma etching apparatus and supply it inside the plasma etching apparatus. On the lower side of the electrode, the supplied etching gas is plasma-activated and etches a specific thin film on the substrate. Therefore, the bottom of the electrode Since the surface is in contact with the plasma, when using an electrode according to one embodiment of the present invention, the etching rate of the electrode due to the plasma can be reduced, thereby extending the lifespan of the electrode.

[0069] The aforementioned component may be made of SiC or B4C as a plasma-resistant material. According to one embodiment, the semiconductor manufacturing equipment component is used not only for etch rings and electrodes, but also for various susceptors and other components containing SiC or B4C that are exposed to plasma, and is applied to the formation of various components in a dry etching apparatus for semiconductor manufacturing. Furthermore, the aforementioned component is one in which the boundary of the deposited layer is not exposed to plasma.

[0070] The present invention provides a method for manufacturing a component for semiconductor manufacturing equipment, comprising the steps of: preparing a base material; forming a vapor-deposited layer containing SiC or B4C surrounding the base material; processing the vapor-deposited layer; and removing the base material to obtain a component for semiconductor manufacturing equipment containing at least one SiC or B4C.

[0071] A method for manufacturing semiconductor manufacturing equipment components according to one embodiment of the present invention allows for the omission of some of the conventional processing steps in the manufacturing process of semiconductor manufacturing equipment components, thereby improving processability and ultimately reducing the production cost of semiconductor products. Furthermore, since at least one or more semiconductor manufacturing equipment components can be obtained in a single process, the manufacturing process is shortened, and an improvement in the production efficiency of semiconductor manufacturing equipment components can be expected.

[0072] Figures 4 to 7 are schematic diagrams showing the manufacturing process of semiconductor manufacturing equipment components according to one embodiment of the present invention. Referring to Figures 4 to 7, the manufacturing process of semiconductor manufacturing equipment components according to one embodiment of the present invention includes a base material preparation step (Figure 4), a vapor deposition layer formation step (Figure 5), a vapor deposition layer processing step (Figure 6), and a component acquisition step (Figure 7).

[0073] Referring to Figure 4, the base material preparation step is a step of preparing the base material 200.

[0074] According to one embodiment, the base material 200 includes a carbon-based material. The base material 200 may include, for example, graphite, carbon black, etc. The base material is not limited as long as it is a carbon-based material on which a vapor-deposited material such as SiC or B4C is uniformly and well deposited on its surface. Preferably, it is a material that can be easily separated from the vapor-deposited layer of a material such as SiC or B4C.

[0075] According to one embodiment, the shape of the base material 200 is not particularly limited, as long as a homogeneous deposition layer of a deposition material such as SiC or B4C can be formed on its upper and lower surfaces. However, when considering the structure of a deposition chamber on which a deposition material such as SiC or B4C can be deposited, the base material may be formed in a ring shape in order to form a homogeneous deposition layer of a deposition material such as SiC or B4C on the base material.

[0076] Referring to Figure 5, the vapor deposition layer formation step is a step in which the SiC or B4C vapor deposition layer 100a is formed so that it surrounds the base material 200. A homogeneous SiC or B4C vapor deposition layer can be formed not only on the top and bottom of the base material 200, but also on the sides.

[0077] According to one embodiment, when the vapor-deposited layer 100a is SiC, the raw material gas is a gas containing at least one selected from the group consisting of CH3SiCl3, (CH3)2SiCl2, (CH3)3SiCl, (CH3)4Si and CH3SiHCl2, or the SiCl4 gas contains at least one selected from the group consisting of CH4, C3H8, C6H14, C7H8 and CCl4. When the vapor-deposited layer 100a is B4C, the raw material gas is a gas from the group consisting of BCl3, B2H6, BF3, CH4, C2H6 and C3H8. It may include at least one of the following.

[0078] According to one embodiment, the step of forming the vapor-deposited layer can be performed at a vapor deposition temperature of 1000°C to 1900°C, and the film deposition rate can be 20 μm / h to 400 μm / h.

[0079] According to one embodiment, if the temperature of the vapor deposition layer formation step is less than 1000°C, the temperature is extremely low, causing the presence of an amorphous phase, which leads to a rapid decrease in plasma resistance and a decrease in the vapor deposition layer formation rate, resulting in productivity problems. If the temperature of the vapor deposition layer formation step exceeds 1900°C, problems arise in the quality of the vapor deposition, such as delamination of the vapor deposition layer. If the film deposition rate is less than 20 μm / hour, the low vapor deposition layer formation rate results in productivity problems, and if the film deposition rate exceeds 400 μm / hour, the excessively high rate leads to problems such as the presence of pores between the base material and the vapor deposition layer, resulting in homogeneous vapor deposition.

[0080] According to one embodiment, the vapor-deposited layer is formed by growth of chemical vapor deposition (CVD) from a first surface in contact with the base material to a second surface which is the surface to be processed. The first and second surfaces are the same as the first surface 110 and the second surface 120 shown in Figure 1, a cross-sectional view of a semiconductor manufacturing equipment component 100 according to one embodiment of the present invention. Since the SiC or B4C vapor-deposited layer is formed by chemical vapor deposition, it can have a homogeneous surface without the occurrence of pores. Therefore, due to the chemical properties of SiC and B4C materials, it has excellent strength and corrosion resistance, and due to the excellent surface homogeneity of the manufacturing method, it has the characteristic of having a low etching rate to plasma.

[0081] Referring to Figure 6, the deposition layer 100a processing step is intended to easily secure the SiC or B4C deposition layer 100a surrounding the base material 200 as a component for semiconductor manufacturing equipment, and is processed into the shape of a component.

[0082] Referring to Figure 7, the part acquisition step allows for the removal of the base material 200 and the acquisition of semiconductor manufacturing equipment parts 100 containing one or more SiC or B4C. After the SiC or B4C vapor-deposited layer surrounding the base material is processed, the base material and the semiconductor manufacturing equipment parts can be easily separated.

[0083] According to one embodiment, when the base material 200 is removed, one surface of the base material is formed to correspond to the shape of the part. Therefore, the SiC or B4C surface that is in contact with and laminated on the base material becomes the shape of one surface of the part, thus eliminating the need for processing steps to change the shape and reducing the total number of processing steps for the part. In other words, the shape of the surface is determined during the vapor deposition process onto the base material, and there is no need to change its shape through additional processing.

[0084] According to one embodiment, the plasma resistance of the first surface may be greater than that of the second surface. There is a difference in the plasma resistance of SiC or B4C between the first and second surfaces, and this difference can result in a difference in the tendency to etch with respect to plasma. Therefore, the first surface, which is the periphery of a wafer undergoing etching in the reaction chamber of a semiconductor manufacturing apparatus under harsh conditions where plasma is present, has greater plasma resistance than the second surface, thereby extending the lifespan of semiconductor manufacturing apparatus components.

[0085] According to one embodiment, the first surface may be an inclined surface exposed to plasma, and the second surface may be a base surface. The inclined surface exposed to plasma may be a surface near the surface on which a wafer or the like is placed, as it is the surface to which the plasma generated in the semiconductor manufacturing apparatus is exposed. The base surface is a surface that is processed after SiC or B4C has grown by chemical vapor deposition (CVD).

[0086] The first surface is a CVD substrate surface, and the second surface is a CVD growth surface. The component is formed by CVD growth from the first surface.

[0087] The grains on the same laminated surface may have a size within ±10% of the average grain size.

[0088] According to one embodiment, the grain size of the first surface may be smaller than the grain size of the second surface. The grain sizes of the first surface and the second surface are as described with reference to Figure 2. The grain size of the first surface is relatively small as the SiC or B4C begins to grow and is deposited compactly, and the grain size of the SiC or B4C increases as deposition continues, i.e., as it moves towards the second surface. The difference in the grain size of the SiC or B4C between the first and second surfaces results in a difference in the etching tendency to plasma. In semiconductor manufacturing equipment, for example, in the reaction chamber of a dry etching apparatus, the first surface, which is the periphery of a wafer where etching is performed, has a smaller grain size and is more compact than the second surface, and the etching rate etched by the plasma can be reduced. That is, the smaller the grain size, the greater the plasma resistance, and the larger the grain size, the less the plasma resistance.

[0089] According to one embodiment, the size of the crystal grains is measured using the Scherrer equation with respect to the full width at half maximum (FWHM) of the preferred growth peak in X-ray diffraction analysis.

[0090] The aforementioned full width at half maximum (FWHM) refers to the FWHM of the preferred growth peak that appeared in the X-ray diffraction analysis, and the Scherrer equation refers to the equation shown in Equation 1.

[0091] [Formula 1] Scherrer equation: grain size (nm) = 0.9 × (λ(B × cosθ))

[0092] Here, λ is the measurement wavelength for X-ray diffraction analysis, B is the full width at half maximum (rad) of the preferred growth peak, and θ is the angle value (rad) of the preferred growth peak.

[0093] According to one embodiment, the base material has a vertically symmetrical shape, and the semiconductor manufacturing equipment component containing one or more SiC or B4C has the same shape. The base material has a vertically symmetrical shape of the semiconductor manufacturing equipment component to be obtained, and can form a semiconductor manufacturing equipment component containing one or more SiC or B4C after processing of a SiC or B4C vapor deposition layer surrounding the base material.

[0094] According to one embodiment, the surface of the semiconductor manufacturing equipment component exposed after removing the base material is not processed. The surface exposed after removing the base material has a small grain size, which gives it excellent plasma resistance, and it can be used without processing.

[0095] According to one embodiment, the step of processing the vapor-deposited layer allows for processing the surface of the vapor-deposited layer that is not in contact with the base material. Since the surface of the vapor-deposited layer that is not in contact with the base material has a larger grain size, processing it is not a problem because its plasma resistance is slightly reduced compared to the surface with a smaller grain size.

[0096] According to one embodiment, the semiconductor manufacturing equipment component is an etch ring, the base material includes steps on its upper and lower surfaces, the semiconductor manufacturing equipment component is an etch ring, the first surface includes steps, and is the wafer mounting surface.

[0097] The aforementioned semiconductor manufacturing equipment components can be used not only for edge rings but also for various electrodes and susceptors, and can be applied to the formation of various components in dry etching equipment for semiconductor manufacturing that is exposed to plasma containing SiC or B4C.

[0098] Figures 8 to 11 are schematic diagrams showing the manufacturing process of semiconductor manufacturing equipment components according to another embodiment of the present invention. Referring to Figures 8 to 11, semiconductor manufacturing equipment components of the present invention can be manufactured in the same manner using a non-symmetrical base material. This is the same method as described with reference to Figures 4 to 7, but as shown in Figures 4 to 7, the base material is not located between the two components, so it is not possible to obtain components on both sides of the base material. However, the same advantages can be expected by removing the base material and using the unformed processed surface as an inclined surface directly exposed to plasma.

[0099] As described above, although embodiments have been described by limited embodiments and drawings, a person with ordinary skill in the art can make various modifications and variations from the above description. For example, the described techniques may be performed in a different order than described, and / or the described components may be combined or combined in a different manner than described, or substituted or replaced by other components or equivalents, and still achieve appropriate results. Accordingly, the scope of the present invention is not limited to the disclosed embodiments, but is defined by the claims and equivalents thereof.

Claims

1. A component for semiconductor manufacturing equipment, The aforementioned part is formed by stacking multiple layers in a cross-sectional view, creating steps. It includes a first surface exposed to plasma and a second surface placed on the semiconductor manufacturing apparatus, The first surface is a laminated surface exhibiting the same transparency, The plasma resistance of the first surface is greater than that of the second surface. The cross-section includes a laminated surface formed by stacking along the first surface, The same surface of the aforementioned multiple layers contains grains whose size deviation is ±10% from the average value. Components for semiconductor manufacturing equipment.

2. The semiconductor manufacturing apparatus component according to claim 1, wherein the first surface is an inclined surface exposed to plasma, and the second surface is a base surface.

3. The semiconductor manufacturing apparatus component according to claim 1, wherein the first surface is a CVD substrate surface and the second surface is a CVD growth surface.

4. The semiconductor manufacturing apparatus component according to claim 1, wherein the grains on the same surface among the multiple layers have a size within ±10% of the average grain size.

5. The semiconductor manufacturing apparatus component according to claim 1, wherein the grain size of the first surface is smaller than the grain size of the second surface.

6. The aforementioned semiconductor manufacturing equipment component is an etching ring. The semiconductor manufacturing apparatus component according to claim 1, wherein the first surface includes a step and is a wafer mounting surface.

7. The component for semiconductor manufacturing equipment according to claim 1, wherein the component is made of SiC or B4C material as a plasma-resistant material.

8. The component for semiconductor manufacturing apparatus according to claim 1, wherein the component is a component in which the boundary of the vapor-deposited layer is not exposed to the plasma.

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