Semiconductor equipment

Abstract

To provide a semiconductor device capable of suppressing degradation in electrical characteristics associated with miniaturization.SOLUTION: In a semiconductor device, a transistor 100 includes: stacked layers formed of a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 in this order on an insulating surface of a substrate 100; and a third oxide semiconductor layer 133 formed so as to cover a part of the surface of the stacked layer. The third oxide semiconductor layer has a first layer in contact with the stacked layers and a second layer on the first layer. The first layer is formed of a microcrystalline layer, and the second layer is formed of a crystalline layer in which its c-axis is oriented in a vertical direction with respect to the surface of the first layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device using an oxide semiconductor.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The invention disclosed in this specification and the like The technical field of one aspect relates to an article, a method, or a manufacturing method. Alternatively, the present invention one aspect relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, as a more specific technical field of the present invention disclosed in this specification, examples of the technical field of one aspect include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, power storage devices, memory devices, driving methods thereof, or manufacturing methods thereof, which can be given as examples can be mentioned.

[0003] Note that in this specification and the like, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics in general. A transistor and a semiconductor circuit are one aspect of a semiconductor device. In addition, a memory device, a display device, and an electronic device may include a semiconductor device. Background Art

[0004] A technique for forming a transistor (also referred to as a thin film transistor (TFT)) using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (display devices). Although silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have attracted attention as other materials. technique for forming a transistor (also referred to as a thin film transistor (TFT)) has attracted attention. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (display devices). silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have attracted attention as other materials. Although silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have attracted attention as other materials.

[0005] For example, indium (In), gallium (Ga), and as the active layer of a transistor. A transistor using an amorphous oxide semiconductor containing zinc (Zn) is disclosed in Patent Document 1. Yes, they are. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2006-165528 [Overview of the project] [Problems that the invention aims to solve]

[0007] Miniaturization of transistors is an essential technology for increasing the density of integrated circuits. Miniaturization of transistors can worsen their electrical characteristics and increase the likelihood of variations. It is known that the yield of integrated circuits will decrease due to the miniaturization of transistors. The ball is more likely to decrease.

[0008] Therefore, one aspect of the present invention provides a structure that can suppress the deterioration of electrical characteristics that becomes significant with miniaturization. One of the objectives is to provide semiconductor devices that meet the requirements of miniaturization. One of the objectives is to provide a semiconductor device having a structure that can hold down the lower part. Alternatively, one of the objectives is to provide a semiconductor device with a high degree of integration. One of the objectives is to provide semiconductor devices that reduce degradation. Alternatively, low power consumption semiconductor devices. One of the objectives is to provide a conductive device, or to provide a highly reliable semiconductor device. One of the objectives is to retain data even when the power is cut off. One of the objectives is to provide, or to provide a novel semiconductor device. Let's make it one.

[0009] Furthermore, the description of these problems does not preclude the existence of other problems. The approach does not need to solve all of these problems. This will become clear from the description in the specification, drawings, claims, etc., and the specification, drawings It is possible to extract other issues from the descriptions in the surfaces, claims, etc. [Means for solving the problem]

[0010] One aspect of the present invention relates to a semiconductor device having stacked oxide semiconductor layers.

[0011] One aspect of the present invention involves forming a first oxide semiconductor layer and a second oxide semiconductor layer on an insulating surface in that order. The resulting laminate, and a portion of the side surface, a portion of the top surface, and a portion of the side surface opposite to the said side It has a third oxide semiconductor layer formed to cover it, and the third oxide semiconductor layer is stacked It has a first layer in contact with and a second layer on the first layer, the first layer being formed of a microcrystalline layer. The second layer is formed of a crystalline layer in which the c-axis is oriented perpendicular to the surface of the first layer. This semiconductor device is characterized by having [a certain feature].

[0012] Another aspect of the present invention is a first oxide semiconductor layer and a second oxide semiconductor layer on an insulating surface. A stack formed in a layered order, and a source electrode layer and a drain electrode layer in contact with a part of the stack. And so that it comes into contact with a portion of the insulating surface, the laminate, the source electrode layer, and the drain electrode layer. A third oxide semiconductor layer formed thereon, and a gate insulating layer formed on the third oxide semiconductor layer. A film, a gate electrode layer formed on the gate insulating film, a source electrode layer, a drain electrode layer, The third oxide semiconductor layer has an insulating layer formed on the gate electrode layer, and the third oxide semiconductor layer is in contact with the stack. It has a first layer and a second layer on the first layer, and the first layer is formed of a microcrystalline layer. The second layer is formed of a crystalline layer in which the c-axis is oriented perpendicular to the surface of the first layer. This semiconductor device is characterized by the following features.

[0013] In this specification, ordinal numbers such as "the first," "the second," etc., are used to avoid confusion of constituent elements. It should be noted that this is added for the purpose of providing a numerical limit, and is not intended to limit the number of items.

[0014] The first oxide semiconductor layer described above has a crystalline layer oriented along the c axis perpendicular to the insulating surface. The second oxide semiconductor layer described above is oriented along the c-axis perpendicular to the upper surface of the first oxide semiconductor layer. It is preferable to have a crystalline layer.

[0015] Furthermore, in the region where the above stacking and the third oxide semiconductor layer are in contact, the second oxide semiconductor layer The surface preferably has a curved shape.

[0016] Furthermore, the first oxide semiconductor layer and the third oxide semiconductor layer are more efficient than the second oxide semiconductor layer. Furthermore, the energy at the lower end of the conduction band is close to the vacuum level in the range of 0.05 eV to 2 eV. preferable.

[0017] Furthermore, the first to third oxide semiconductor layers are In-M-Zn oxide layers (M (These are Al, Ti, Ga, Y, Zr, La, Ce, Nd or Hf), and the first oxide half The conductive layer and the third oxide semiconductor layer have an atomic ratio of M to In that is the same as that of the second oxide semiconductor. It is preferable that it be larger than the layer. [Effects of the Invention]

[0018] By using one aspect of the present invention, the decrease in electrical characteristics that becomes significant with miniaturization can be suppressed. A semiconductor device with the following configuration can be provided. Alternatively, the yield reduction associated with miniaturization can be suppressed. A semiconductor device having a structure that can achieve high integration can be provided. A semiconductor device can be provided. Alternatively, a semiconductor device with reduced on-current degradation can be provided. We can provide it. Or, we can provide a low-power semiconductor device. This can provide highly reliable semiconductor devices. Alternatively, even if the power supply is cut off, data can be stored. It is possible to provide a semiconductor device in which a data object is held. Or, it is possible to provide a novel semiconductor device. It is possible.

[0019] Furthermore, the description of these effects does not preclude the existence of other effects. The embodiment does not necessarily have to have all of these effects. Furthermore, other effects are... This will become clear from the description in the specification, drawings, claims, etc., and the specification, drawings Furthermore, it is possible to extract other effects from the descriptions in the claims and other documents. [Brief explanation of the drawing]

[0020] [Figure 1] Top view and cross-sectional view of a transistor. [Figure 2] Cross-section of a transistor. [Figure 3] A diagram illustrating the band structure of an oxide semiconductor layer. [Figure 4] A diagram illustrating the crystal structure in a portion of the stacked oxide semiconductor layers. [Figure 5] Magnified cross-sectional view of a transistor. [Figure 6] Cross-section of a transistor. [Figure 7] A diagram illustrating the method for manufacturing transistors. [Figure 8] A diagram illustrating the method for manufacturing transistors. [Figure 9] Cross-sectional view and circuit diagram of a semiconductor device. [Figure 10] Circuit diagram of a semiconductor device. [Figure 11] Circuit diagrams and cross-sectional views of semiconductor devices. [Figure 12] Circuit diagram of a semiconductor device. [Figure 13] A diagram illustrating electronic devices to which semiconductor devices can be applied. [Figure 14] Cross-sectional view of a sample used to observe the stacking state of oxide semiconductor layers. [Figure 15] Cross-sectional TEM image of an oxide semiconductor layer. [Modes for carrying out the invention]

[0021] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Without departing from the spirit and scope of the present invention, its form and details may be changed in various ways. Those skilled in the art will readily understand that further improvements are possible. Therefore, the present invention can be implemented as follows: The description of the form is not to be interpreted as being limited to the content of the description. Furthermore, the structure of the invention described below In this context, the same reference numeral is used for identical parts or parts having similar functions across different drawings. It is used in this way, and the explanation of its repetition may be omitted.

[0022] Furthermore, in this specification, etc., when it is explicitly stated that X and Y are connected, X When X and Y are electrically connected, and when X and Y are functionally connected, This includes the case where X and Y are directly connected. Here, X and Y are objects (for example) For example, it is assumed to be a device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc. Therefore And, not limited to predetermined connection relationships, for example, connection relationships shown in a diagram or text, but also including diagrams or This includes relationships other than those explicitly stated in the text.

[0023] One example of a case where X and Y are electrically connected is the ability to make an electrical connection between X and Y possible. Elements such as switches, transistors, capacitive elements, inductors, resistive elements, and dies. One or more devices (such as diodes, display elements, light-emitting elements, and loads) are connected between X and Y. Yes, it is possible. Furthermore, a switch has the function of being controlled to be on or off. In other words, a switch The switch can be in a conductive (on) or non-conductive (off) state, allowing current to flow. It has a function to control whether or not current flows. Alternatively, the switch selects the path through which current flows. It has a function to switch between modes.

[0024] One example of a functional connection between X and Y is enabling a functional connection between X and Y. Circuits that perform this function (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signal transformers) Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (electric (Source circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of a signal, etc.) Voltage source, current source, switching circuit, amplification circuit (which can increase signal amplitude or current amount, etc.) Circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc., signal generation One or more circuits (such as memory circuits and control circuits) can be connected between X and Y. For example, even if another circuit is placed between X and Y, the signal output from X If the signal is transmitted to Y, then X and Y are assumed to be functionally connected.

[0025] Note that if it is explicitly stated that X and Y are connected, it means that X and Y are electrically connected. If this is the case (i.e., if X and Y are connected with another element or circuit in between) (when X and Y are functionally connected) and when X and Y are functionally connected (i.e., when there is no other circuit between X and Y) (When they are functionally connected with a sash in between) and when X and Y are directly connected (that is (including cases where X and Y are connected without another element or circuit in between) Therefore, if you explicitly state that they are electrically connected, then simply state that they are connected. This is equivalent to the case where it is explicitly stated only that it is.

[0026] Note that, in circuit diagrams, independent components are shown as being electrically connected to each other. Even in such cases, one component may possess the functions of multiple components. For example, if part of the wiring also functions as an electrode, one conductive film will function as the wiring, and It possesses the functions of both components of the electrode. Therefore, in this specification Electrically connected means that a single conductive film combines the functions of multiple components. This also falls under that category.

[0027] For example, if the source (or first terminal, etc.) of the transistor is connected via Z1 (or via (In short), electrically connected to X, the drain (or second terminal, etc.) of the transistor is connected to Z. If Y is electrically connected via (or without) 2, or if the transistor source (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. They are directly connected, with the transistor's drain (or second terminal, etc.) directly connected to a portion of Z2. If it is connected to and another part of Z2 is directly connected to Y, it can be expressed as follows: It is possible to do so.

[0028] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal) of the transistor." The terminals (such as the X terminal) are electrically connected to each other, and X is the source (or the X terminal) of the transistor. The electrical connections are in the following order: terminal 1, the drain of the transistor (or terminal 2, etc.), and Y. It can be expressed as "It is connected." Or, "The source (or the source) of the transistor." Terminal 1 (or terminal 2) is electrically connected to X, and the drain (or terminal 2) of the transistor is connected to X. (d) is electrically connected to Y, X is the source of the transistor (or the first terminal, etc.), and the transistor The drain (or second terminal, etc.) of the converter, Y, is electrically connected in this order. It can be expressed as "X is the source (or first terminal) of the transistor." Alternatively, "X is the source (or first terminal) of the transistor." Y is electrically connected to X via the drain (or second terminal, etc.) and X, the transistor The source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.) ), Y is provided in this connection order. By using a specific method of expression to define the order of connections in the circuit configuration, Distinguish between the source (or first terminal, etc.) and drain (or second terminal, etc.) of the zista. This allows us to determine the technical scope. Note that these expressions are just examples, and The method of representation is not limited to these. Here, X, Y, Z1, and Z2 are the object (e.g., the device). (This refers to elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.)

[0029] Furthermore, in this specification, transistors can be formed using various substrates. The type of substrate is not limited to a specific one. One example of such a substrate is a semiconductor. Substrates (e.g., single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, We have plastic substrates, metal substrates, stainless steel substrates, and stainless steel foil. Substrates, tungsten substrates, substrates having tungsten foil, flexible substrates, laminated Examples include laminated films, paper containing fibrous materials, or base films. One of the glass substrates. Examples include barium borosilicate glass, aluminoborosilicate glass, or soda fountains. Examples include glass. One example of a flexible substrate is polyethylene terephthalate (PET). ), represented by polyethylene naphthalate (PEN) and polyethersulfone (PES) These include flexible plastics or synthetic resins such as acrylic. Examples of films include polypropylene, polyester, polyvinyl fluoride, or poly Examples include polyvinyl chloride. Examples of base films include polyester, polyamide, and polyvinyl chloride. These include reimide, inorganic vapor-deposited films, or paper. In particular, semiconductor substrates, single crystal substrates, Alternatively, by manufacturing transistors using SOI substrates, characteristics, size, and Alternatively, it can manufacture transistors with less variation in shape, high current capacity, and small size. This is possible. When a circuit is constructed using such transistors, the circuit consumes less power. This allows for increased power output or higher integration of circuits.

[0030] Furthermore, even if a flexible substrate is used as the substrate and transistors are formed directly on the flexible substrate, That's fine. Alternatively, a release layer may be provided between the substrate and the transistor. The release layer is half a layer on top of it. After partially or completely completing the conductive device, it is separated from the circuit board and transferred to another circuit board. It can be used. In this case, the transistor can be mounted on substrates with poor heat resistance or flexible substrates. Yes, it is possible. The aforementioned release layer may include, for example, an inorganic film consisting of a tungsten film and a silicon oxide film. This involves using a layered structure configuration, or a configuration in which an organic resin film such as polyimide is formed on the substrate. It is possible.

[0031] In other words, a transistor is formed using one substrate, and then the transistor is transferred to another substrate. The transistor may be placed on one of the substrates on which the transistor is transposed. Examples include, in addition to the substrates on which the transistors described above can be formed, paper substrates, cellophane Fan substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates Board (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or (This includes regenerated fibers (acetate, cupro, rayon, recycled polyester, etc.), leather These include leather substrates and rubber substrates. By using these substrates, a tiger with good characteristics can be produced. Formation of transistors, formation of low-power transistors, manufacturing of durable devices, heat resistance This allows for the addition of features, weight reduction, or thinning of the material.

[0032] (Embodiment 1) In this embodiment, a semiconductor device according to one aspect of the present invention will be described with reference to the drawings.

[0033] Figures 1(A), (B), and (C) are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. Yes. Figure 1(A) is a top view, and the cross section of the dashed line A1-A2 shown in Figure 1(A) is shown in Figure 1( This corresponds to B). Also, Figure 1(C) is a cross-sectional view of the dashed line A3-A4 shown in Figure 1(A). Yes. Note that in the top view of Figure 1(A), some elements have been omitted for clarity. It is. Also, the direction of the dashed line A1-A2 is the channel length direction, and the direction of the dashed line A3-A4 is the channel length direction. This is sometimes referred to as the width direction of the panel.

[0034] The transistor 100 shown in Figures 1(A), (B), (C) and 2 is formed on the substrate 110. The formed underlayer insulating film 120 and the first oxide semiconductor layer 1 formed on the underlayer insulating film 31. A stack formed in the order of a second oxide semiconductor layer 132, and a part of the stack that is in contact with the stack A source electrode layer 140 and a drain electrode layer 150 are formed in such a manner, and a base insulating film 120, The laminate, the source electrode layer 140 and the drain electrode layer 150, each in contact with a portion of the laminate. 3 oxide semiconductor layer 133 and gate insulating film 1 formed on the third oxide semiconductor layer 60, a gate electrode layer 170 formed on the gate insulating film, a source electrode layer 140, It has a rain electrode layer 150 and an insulating layer 180 formed on the gate electrode layer 170.

[0035] Here, the first oxide semiconductor layer 131 is positioned along the c-axis perpendicular to the surface of the underlying insulating film 120. The second oxide semiconductor layer 132 has an oriented crystalline layer and is located on top of the first oxide semiconductor layer 131. It is preferable to have a crystalline layer that is c-oriented perpendicular to the plane.

[0036] Furthermore, the third oxide semiconductor layer 133 is in contact with the first layer and on the first layer It is formed to have a second layer. The first layer is a microcrystalline layer, and the second layer is It is formed of a crystalline layer in which the c-axis is oriented perpendicular to the surface of the first layer.

[0037] Furthermore, an insulating layer 185 made of oxide may be formed on the insulating layer 180. The insulating layer 185 may be provided as needed, and another insulating layer may be formed on top of it. i. Also, the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third acid The oxide semiconductor layer 133 is collectively referred to as the oxide semiconductor layer 130.

[0038] Furthermore, the "source" and "drain" functions of a transistor are related to transistors with different polarities. When adopting a circuit, or when the direction of current changes during circuit operation, the configuration may be reversed. Therefore, in this specification, the terms "source" and "drain" are interchangeable. It may be used.

[0039] Furthermore, a transistor according to one aspect of the present invention includes an oxide semiconductor layer (first oxide semiconductor layer 131 and the source electrode layer 140 or drain electrode layer overlapping the second oxide semiconductor layer 132) At 150, from one end of the oxide semiconductor layer shown in the top view of Figure 1(A), to the source electrode layer 1 The distance (ΔW) to one end of the 40 or drain electrode layer 150 is preferably 50 nm or less. The wavelength should be 25 nm or less. By reducing ΔW, the oxygen contained in the underlying insulating film 120 is reduced. - Suppress the amount of diffusion into the metal material that constitutes the electrode layer 140 or the drain electrode layer 150. Therefore, oxygen contained in the substrate insulating film 120, especially in excess, can be obtained. Unnecessary release of oxygen can be suppressed, and the underlying insulating film 120 can be applied to the oxide semiconductor layer. Oxygen can be supplied efficiently from there.

[0040] Next, the components of a transistor 100 according to one embodiment of the present invention will be described in detail.

[0041] The substrate 110 is not merely a support substrate, but also has other devices such as transistors formed on it. A substrate may also be used. In this case, the gate electrode layer 170 of transistor 100 and the source electrode At least one of layer 140 and drain electrode layer 150 is electrically connected to the other devices mentioned above. It may be connected to the target.

[0042] The underlying insulating film 120 has the role of preventing the diffusion of impurities from the substrate 110, as well as oxidation It can play a role in supplying oxygen to the semiconductor layer 130. Therefore, the underlying insulating film 1 20 is preferably an insulating film containing oxygen, and is an insulating film containing more oxygen than the stoichiometric composition. It is more preferable that it be a film. Also, as mentioned above, the substrate 110 is formed on other devices. In the case of a substrate, the underlying insulating film 120 also functions as an interlayer insulating film. CMP (Chemical Mechanical Polishing) to make the surface flat It is preferable to perform a planarization treatment using methods such as the shing method.

[0043] Furthermore, in the region where the channel of transistor 100 is formed, the oxide semiconductor layer 130 From the substrate 110 side, the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third It has a structure in which oxide semiconductor layers 133 are stacked. Also, the channel width in Figure 1(C) As shown in the cross-sectional view, in the channel formation region, the third oxide semiconductor layer 133 is Side and top surfaces of a stack consisting of a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 , formed to cover the side opposite to the side in question. Therefore, in the channel formation region The second oxide semiconductor layer 132 is connected to the first oxide semiconductor layer 131 and the third oxide semiconductor layer The structure is surrounded by a conductive layer 133.

[0044] Here, as an example, the second oxide semiconductor layer 132 has the first oxide semiconductor layer 131 and electron affinity (from vacuum level to the lower edge of the conduction band) is greater than that of the third oxide semiconductor layer 133. A high-energy oxide semiconductor is used. The electron affinity is between the vacuum level and the top of the valence band. From the energy difference (ionization potential), the energy between the lower end of the conduction band and the upper end of the valence band can be calculated. It can be calculated by subtracting the difference (energy gap).

[0045] The first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 are made of the second oxide semiconductor The layer 132 contains one or more metallic elements, for example, the energy at the lower end of the conduction band is second Compared to oxide semiconductor layer 132, the values ​​are 0.05 eV, 0.07 eV, 0.1 eV, and 0.15 eV. One or more of the following, and within the range of 2eV, 1eV, 0.5eV, or 0.4eV. It is preferable to form it with an oxide semiconductor that is close to the vacuum level in the surrounding environment.

[0046] In such a structure, when an electric field is applied to the gate electrode layer 170, the oxide semiconductor layer 13 Among the 0s, the second oxide semiconductor layer 132, which has the lowest energy at the lower end of the conduction band, has a channel. A second oxide semiconductor layer is formed between the second oxide semiconductor layer 132 and the gate insulating film 160. Because the oxide semiconductor layer 133 is formed, the channel of the transistor is This structure does not come into contact with the insulating film.

[0047] Furthermore, the first oxide semiconductor layer 131 contains the metal elements that make up the second oxide semiconductor layer 132. Because it is composed of one or more of these, the second oxide semiconductor layer 132 and the underlying insulating film 120 come into contact Compared to the interface in the case of the second oxide semiconductor layer 132 and the first oxide semiconductor layer 131 It becomes difficult to form interface states at the interface. These interface states can form channels. Therefore, the threshold voltage of the transistor may fluctuate. By providing layer 131, variations in electrical characteristics such as the threshold voltage of the transistor can be reduced. This can reduce the noise level. Furthermore, it can improve the reliability of the transistor.

[0048] Furthermore, the third oxide semiconductor layer 133 is composed of the metal elements that make up the second oxide semiconductor layer 132. Because it is composed of one or more of these, the second oxide semiconductor layer 132 and the gate insulating film 160 Compared to the interface when in contact, the second oxide semiconductor layer 132 and the third oxide semiconductor layer 13 Carrier scattering becomes less likely at the interface with 3. Therefore, the third oxide semiconductor layer By providing 133, the field-effect mobility of the transistor can be increased.

[0049] First oxide semiconductor layer 131, second oxide semiconductor layer 132, third oxide semiconductor layer 13 3 contains at least indium, zinc, and M(Al, Ti, Ga, Ge, Y, Zr, Sn When the In-M-Zn oxide layer contains metals such as La, Ce, or Hf, the first acid In or Zn in the oxide semiconductor layer 131 and the third oxide semiconductor layer 133 The atomic ratio of M is preferably higher than that of the second oxide semiconductor layer 132. Specifically, the ratio of atoms should be 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more. Assuming the above, M bonds more strongly to oxygen than In or Zn, so oxygen vacancies are present in oxide semiconductors. It has a function to suppress the occurrence in the layer. That is, the first oxide semiconductor layer 131 and The third oxide semiconductor layer 133 is less prone to oxygen vacancies than the second oxide semiconductor layer 132. It can be said that...

[0050] Furthermore, the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor Layer 133 contains at least indium, zinc, and M(Al, Ti, Ga, Ge, Y, Zr When it is an In-M-Zn oxide layer containing metals such as Sn, La, Ce, or Hf, the The first oxide semiconductor layer 131 is In:M:Zn=x1:y1:z1 [atomic ratio], and the second acid The oxide semiconductor layer 132 is In:M:Zn=x2:y2:z2 [atomic ratio], and the third oxide semiconductor If the conductive layer 133 is In:M:Zn=x3:y3:z3 [atomic ratio], then y1 / x1 It is preferable that y3 / x3 is greater than y2 / x2. x3 is 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more, than y2 / x2. In this case, if y2 is greater than or equal to x2 in the second oxide semiconductor layer 132, then The electrical characteristics of the inverter can be stabilized. However, if y2 is more than 3 times x2... Therefore, the field-effect mobility of the transistor decreases, so y2 is less than 3 times x2. This is preferable.

[0051] In this specification, the atomic ratio used to describe the composition of the oxide semiconductor layer refers to the number of atoms in the base material. It also includes the meaning of indicating a ratio. The oxide semiconductor material is targeted and film is deposited using the sputtering method. In that case, the type and ratio of sputtering gas, the density of the target, and the deposition conditions will affect the film deposition. The composition of the oxide semiconductor layer being created may differ from that of the target material. Therefore, in this specification, the atomic ratios used to describe the composition of the oxide semiconductor layer are the atomic ratios of the parent material. This shall be included. For example, when sputtering is used as the film deposition method, the atomic ratio is 1:1 A :1 In-Ga-Zn oxide film is an In-Ga-Zn oxide film with an atomic ratio of 1:1:1. This can be rephrased as an In-Ga-Zn oxide film deposited using the material as a target. .

[0052] Zn and O in the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 When removed, the atomic ratio of In to M is preferably less than 50 atomic%, and M is 50% or more, more preferably In is less than 25% and M is 75a The tomic percentage should be 1% or higher. Also, remove Zn and O from the second oxide semiconductor layer 132. In this case, the atomic ratio of In to M is preferably 25 atomic% or more for In and 7 atomic% for M. Less than 5 atomic%, more preferably In is 34 atomic% or more, and M is 66 at It should be less than omic%.

[0053] The thickness of the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 is 1 nm or more. The second oxide semiconductor layer is less than 00 nm, preferably between 3 nm and 50 nm. The thickness of 132 is 1 nm to 200 nm, preferably 3 nm to 100 nm. More preferably, the wavelength should be between 3 nm and 50 nm.

[0054] A first oxide semiconductor layer 131, a second oxide semiconductor layer 132, and a third oxide semiconductor For example, layer 133 may use an oxide semiconductor containing indium, zinc, and gallium. This is possible. In particular, when indium is included in the second oxide semiconductor layer 132, the carrier This is preferable because it increases mobility.

[0055] Therefore, the oxide semiconductor layer 130 is the first oxide semiconductor layer 131, and the second oxide semiconductor By creating a stacked structure of layer 132 and a third oxide semiconductor layer 133, the second oxide semiconductor layer Channels can be formed in 132, resulting in high field-effect mobility and stable electrical characteristics. It is possible to form transistors that possess this property.

[0056] First oxide semiconductor layer 131, second oxide semiconductor layer 132, third oxide semiconductor layer 13 In band structure 3, the energy at the lower end of the conduction band changes continuously. This is the first The oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer 133 This can also be understood from the fact that oxygen diffuses easily between them due to the similar composition. Therefore , first oxide semiconductor layer 131, second oxide semiconductor layer 132, third oxide semiconductor layer 1 Although 33 is a laminate of layers with different compositions, it can also be said to be continuous in terms of physical properties, as shown in the drawing. In this diagram, each interface of the laminate is represented by a dotted line.

[0057] The oxide semiconductor layers 130, which are stacked with a common main component, are not simply stacked one layer at a time. Continuous junctions (in this case, U-shaped junctions where the energy at the lower end of the conduction band changes continuously between each layer) The structure is fabricated so that a well structure is formed. That is, trap centers and recombination centers are formed at the interface of each layer. A layered structure is formed in such a way that no impurities that would form a defect level like a central one are present. If impurities are present between the layers of stacked oxide semiconductor layers, the energy band will change. Continuity is lost, and carriers are trapped or recombined at the interface, causing them to disappear.

[0058] For example, the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 contain In:Ga Zn=1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:6:4 or 1:9: 6 (atomic ratio), the second oxide semiconductor layer 132 has In:Ga:Zn=1:1:1, 5: Use In-Ga-Zn oxides such as 5:6 or 3:1:2 (atomic ratio). It is possible.

[0059] In the oxide semiconductor layer 130, the second oxide semiconductor layer 132 becomes a well, and acid In a transistor using an oxide semiconductor layer 130, the channel is the second oxide semiconductor layer 1 It is formed at 32. Furthermore, the oxide semiconductor layer 130 has a continuously changing energy at the lower end of the conduction band. Because of its shape, it can also be called a U-shaped well. A channel formed with this configuration can also be called an embedded channel.

[0060] Furthermore, the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133, and silicon oxide Trap levels can form near the interface with insulating films or other insulating materials due to impurities or defects. The presence of a first oxide semiconductor layer 131 and a third oxide semiconductor layer 133 means that The oxide semiconductor layer 132 of the second layer can be separated from the trap level.

[0061] However, the lower end of the conduction band of the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 In a field where the difference between the energy and the energy at the lower end of the conduction band of the second oxide semiconductor layer 132 is small In addition, electrons in the second oxide semiconductor layer 132 exceed the energy difference and reach the trap level. Sometimes, electrons are trapped in trap levels, creating a negative fixed charge at the insulating film interface. This occurs, causing the transistor's threshold voltage to shift in the positive direction.

[0062] Therefore, in order to reduce the fluctuation of the transistor threshold voltage, the first oxide semiconductor layer The energy at the lower end of the conduction band of 131 and the third oxide semiconductor layer 133, and the energy at the lower end of the conduction band of the second oxide semiconductor layer It is necessary to create a difference of a certain magnitude or more between the energy at the lower end of the conduction band of the conductor layer 132 and the energy at the lower end of the conduction band. The respective energy differences are preferably 0.1 eV or more, and more preferably 0.15 eV or more. preferable.

[0063] Furthermore, the first oxide semiconductor layer 131, the second oxide semiconductor layer 132 and the third oxide semiconductor The conductive layer 133 preferably contains a crystalline layer oriented along the c-axis. By using a film that can be filmed, stable electrical characteristics can be imparted to the transistor.

[0064] Furthermore, when using In-Ga-Zn oxide for the oxide semiconductor layer 130, the gate insulating of In is used. To prevent diffusion into the edge film, the third oxide semiconductor layer 133 is connected to the second oxide semiconductor layer 132 It is preferable to have a composition with less In than [a certain amount].

[0065] A transistor according to one aspect of the present invention, in addition to being an embedded channel as described above, is shown in Figure 2. As shown, the third oxide semiconductor layer 133 is connected to the first oxide semiconductor layer 131 and the second oxide semiconductor layer The lamination of the conductive layer 132 and the microcrystalline layer 133a in contact with the underlying insulating film 120, and the microcrystalline layer The structure has a crystalline layer 133b in which the c-axis is oriented perpendicular to the surface.

[0066] Details of the band structure of the oxide semiconductor layer (corresponding to the B1-B2 direction in Figure 2) in the said structure This is shown in Figure 3. Here, Evac is the energy of the vacuum level, and EcI1 and EcI2 are oxidation levels. The energy at the lower end of the conduction band of the silicon film, EcS1, is the conduction band of the first oxide semiconductor layer 131. The energy at the lower end, EcS2, is the energy at the lower end of the conduction band of the second oxide semiconductor layer 132. EcS3 is the energy at the lower end of the conduction band of the third oxide semiconductor layer 133.

[0067] The energy changes rapidly between EcS1 and EcS2, and between EcS3 and EcS2. However, at the beginning and end of the change, the slope changes gradually.

[0068] This is the interface between the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132, and the third At the interface between the first oxide semiconductor layer 133 and the second oxide semiconductor layer 132, the composition expands mutually. The composition between the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 is dispersed, or Forming a region that forms the composition between the third oxide semiconductor layer 133 and the second oxide semiconductor layer 132 It is for the purpose of achieving something.

[0069] Therefore, as shown in Figure 3, the channel formed in the second oxide semiconductor layer 132 is From the interface between the third oxide semiconductor layer 133 and the second oxide semiconductor layer 132, a small amount of material flows toward the center of the film. From a distanced position and from the interface between the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 It is formed in region 132b between a position slightly away from the center of the membrane. Even if defects or impurities are present at either interface, carrier trapping and recombination are suppressed. It is possible to obtain it.

[0070] Furthermore, in the third oxide semiconductor layer 133, the first oxide semiconductor layer 131 and the second oxide The region in contact with the stacking of the semiconductor layer 132 is a microcrystalline layer 133a, and the microcrystalline layer is located above it. Because the density is lower than that of the crystal layer 133b formed in the part, the second oxide semiconductor layer The composition of 132 becomes more likely to diffuse toward the third oxide semiconductor layer 133. Therefore, the third The region of composition between the first oxide semiconductor layer 133 and the second oxide semiconductor layer 132 increases. Therefore, the channel formed in the second oxide semiconductor layer 132 is the third oxide semiconductor layer A position further away from the interface between the body layer 133 and the second oxide semiconductor layer 132, towards the center of the film. This is formed in such a way that it more effectively suppresses problems that occur when there are defects or impurities at the aforementioned interface. It is possible.

[0071] Furthermore, the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 are oriented along the c axis in the crystal. When formed in layers, the microcrystalline layer 133a has a lower density than the crystalline layer, so It can be said that oxygen diffuses easily through this layer. Therefore, the microcrystalline layer 133a is used as a pass-through for the substrate insulation. To efficiently supply oxygen from the film 120 to the second oxide semiconductor layer 132 which will form a channel. This allows for the replenishment of oxygen in oxygen-deficient areas.

[0072] Furthermore, the crystalline layer 133b in the third oxide semiconductor layer 133 is on the surface of the microcrystalline layer 133a. It is oriented along the c-axis perpendicular to the curved surface. By forming it so that it has a c-axis oriented crystal, the channel of the second oxide semiconductor layer 132 It can densely cover the area.

[0073] Figure 4(A) shows a transistor formed to have a curved surface in the channel width direction. A second oxide semiconductor layer 132, a microcrystalline layer 133a covering the second oxide semiconductor layer, and the micro A schematic cross-sectional view of the crystal structure in a portion of the stacked crystal layer 133b formed on the crystal layer. Here, the second oxide semiconductor layer 132 is the first oxide semiconductor layer 131 (not shown). This is a crystalline layer oriented along the c-axis perpendicular to the surface of ).

[0074] As shown in the figure, the surface of the second oxide semiconductor layer 132 is formed to have a curved surface. , a dense crystalline layer oriented along the c axis perpendicular to the surface of the curved surface via the microcrystalline layer 133a A third oxide semiconductor layer 133 having 133b can be formed. Therefore, The effect of the oxide semiconductor layer 133 on suppressing oxygen desorption from the second oxide semiconductor layer 132. This can enhance the effect of trapping oxygen released from the underlying insulating film 120, This allows for efficient oxygen replenishment of oxygen vacancies in the second oxide semiconductor layer 132.

[0075] Note that if the surface of the second oxide semiconductor layer 132 is not formed to have a curved surface, see Figure 4. As shown in (B), in the third oxide semiconductor layer 133, the second oxide semiconductor layer 132 In the region where the crystalline layer 133b formed on the upper part and the crystalline layer 133b formed on the side intersect A region 233 with sparse crystals is formed. Therefore, the acid of the second oxide semiconductor layer 132 The oxygen supplied from the substrate insulating film 120 to the second oxide semiconductor layer 132 is in region 2 It becomes easier to release through 33. Therefore, oxygen vacancies in the second oxide semiconductor layer 132 This makes it impossible to efficiently replenish oxygen.

[0076] Furthermore, in order to impart stable electrical characteristics to transistors using an oxide semiconductor layer as the channel This involves reducing the impurity concentration in the oxide semiconductor layer and making the oxide semiconductor layer intrinsically or substantially intrinsically Making it true is effective. Here, essentially true means the carrier density of the oxide semiconductor layer. is 1×10 17 / cm 3 or less, preferably 1×10 15 / cm 3 or less , more preferably 1×10 13 / cm 3 or less.

[0077] Further, in an oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and metals other than the main component elements act as impurities. For example, hydrogen and nitrogen contribute to formation of donor levels and increase carrier density . In addition, silicon contributes to formation of impurity levels in the oxide semiconductor layer . The impurity levels serve as traps and may deteriorate the electrical characteristics of a transistor . Therefore, it is preferable to reduce the impurity concentration in the layers of the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer 133 and at the interfaces between the respective layers .

[0078] In order to make an oxide semiconductor layer intrinsic or substantially intrinsic, in SIMS (Secondary Ion Mass Spectrometry ) analysis, for example, the silicon concentration is set to 1×10 at a certain depth of the oxide semiconductor layer or in a certain region of the oxide semiconductor layer 1×10 19 atoms / cm 3 or less, preferably 5×10 18 atoms / cm 3 or less , more preferably 1×10 18 atoms / cm 3 or less in a portion of the oxide semiconductor layer is preferable. Further, the hydrogen concentration is, for example, at a certain depth of the oxide semiconductor layer or in a certain region of the oxide semiconductor layer, 2×10 at a certain depth of the oxide semiconductor layer or in a certain region of the oxide semiconductor layer, 2×10 20 atoms / cm3 The following are preferably 5 ×10 19 atoms / cm 3 More preferably 1 × 10 19 atoms / cm 3 Below Below, more preferably 5 × 10 18 atoms / cm 3 It has the following parts: This is preferable. Furthermore, the nitrogen concentration is, for example, at a certain depth in the oxide semiconductor layer, or In a region of the oxide semiconductor layer, 5 × 10 19 atoms / cm 3 Less than, preferably 5 x 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 It has the following parts This is preferable.

[0079] Furthermore, if the oxide semiconductor layer contains crystals, and if silicon or carbon is present in high concentrations, the oxide will be affected. This can reduce the crystallinity of the semiconductor layer. This includes, for example, a certain depth in the oxide semiconductor layer, or a certain region in the oxide semiconductor layer. In this case, the silicon concentration is 1 × 10⁻⁶ 19 atoms / cm 3 Less than 5 × 10 1 8 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Less than It is sufficient that it has a portion. Also, for example, at a certain depth in the oxide semiconductor layer, In a region of the oxide semiconductor layer, the carbon concentration is set to 1 × 10⁻⁶. 19atoms / cm 3 less than Preferably 5 × 10 18 atoms / cm 3 Less than 1 × 10 18 at oms / cm 3 It is sufficient to have a portion that is less than [a certain value].

[0080] Furthermore, as mentioned above, a transient using a highly purified oxide semiconductor layer in the channel formation region The off-current of the sta is extremely small. For example, if the voltage between the source and drain is 0.1V, 5 When set to V or approximately 10V, the off-current normalized by the transistor's channel width. This makes it possible to reduce the voltage to several yA / μm to several zA / μm.

[0081] Furthermore, silicon-containing insulating films are often used as gate insulating films for transistors. Therefore, for the reasons stated above, the region that becomes the channel of the oxide semiconductor layer is a transient in one aspect of the present invention. It can be said that a structure that does not come into contact with the gate insulating film, like a sta, is preferable. When a channel is formed at the interface between the insulating film and the oxide semiconductor layer, carrier scattering occurs at the interface. This can occur, and the field-effect mobility of the transistor may decrease. From this perspective as well It is preferable to keep the region that forms the channel of the oxide semiconductor layer away from the gate insulating film. .

[0082] The source electrode layer 140 and the drain electrode layer 150 use a conductive material that readily bonds with oxygen. It is preferable to use Al, Cr, Cu, Ta, Ti, Mo, W, etc. This is possible. Among the above materials, Ti, which is particularly prone to bonding with oxygen, and the subsequent process temperature can be compared. It is preferable to use W, which has a high melting point, as it can be used to achieve a high melting point. Conductive materials that readily bond also include materials that allow oxygen to diffuse easily.

[0083] When a conductive material that readily bonds with oxygen is brought into contact with an oxide semiconductor layer, oxygen in the oxide semiconductor layer However, a phenomenon occurs where the oxygen diffuses towards the conductive material side, which is more likely to combine with oxygen. This phenomenon is more pronounced at higher temperatures. This occurs very noticeably. Because the transistor manufacturing process involves a heating step, the above phenomenon occurs. Oxygen vacancies in the region near the source electrode layer or drain electrode layer of the oxide semiconductor layer that is in contact with it. This occurs, and the small amount of hydrogen contained in the membrane combines with the oxygen vacancy in that region, resulting in n It is then typed. Therefore, the n-typed region becomes the source or drain of the transistor. It can be made to work.

[0084] The above n-type region is a magnified cross-sectional view of the transistor in Figure 5 (part of the cross-section in the channel length direction). (Near the source electrode layer 140) is shown. In the first oxide semiconductor layer 131 and the second acid The boundary 135, indicated by a dotted line in the ionized semiconductor layer 132, is the boundary between the intrinsic semiconductor region and the n-type semiconductor region. This is the boundary between the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. The region in contact with the source electrode layer 140 becomes an n-type region. Note that boundary 135 This is a schematic representation and may not be clear in reality. Also, in Figure 5, the boundary A portion of 135 is positioned so as to extend laterally within the second oxide semiconductor layer 132. The state is shown, but the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 The entire region sandwiched between the electrode layer 140 and the underlying insulating film 120 may also become n-shaped in the thickness direction. ru.

[0085] Furthermore, when forming a transistor with an extremely short channel length, the above-mentioned oxygen vacancy occurs, resulting in n The shaped region may extend in the direction of the transistor's channel length. In this case, The electrical characteristics of a transistor allow for on / off control via threshold voltage shift and gate voltage. A non-conductive state (a state of conduction) appears. Therefore, a transistor with an extremely short channel length is formed. In such cases, conductive materials that readily bond with oxygen should be used for the source electrode layer and drain electrode layer. That is not necessarily desirable.

[0086] In such cases, the source electrode layer 140 and the drain electrode layer 150 are made of the material described above. It is also possible to use conductive materials that are less likely to bond with oxygen. For example, such conductive materials include For example, materials containing tantalum nitride, titanium nitride, gold, platinum, palladium, or ruthenium. This can be used. In this case, the source electrode layer 140 and the drain electrode layer 150 are made of the conductive material and the aforementioned oxygen A configuration in which conductive materials that readily bond with each other are laminated may also be used.

[0087] The gate insulating film 160 contains aluminum oxide, magnesium oxide, silicon oxide, and nitrogen oxide. Silicon oxide, silicon nitride, silicon nitride, gallium oxide, germanium oxide, oxide Yttrium, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and An insulating film containing one or more types of tantalum oxide can be used. Also, the gate insulating film 160 is The above materials may be laminated.

[0088] The gate electrode layer 170 contains Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru Conductive films such as Ag, Ta, and W can be used. Furthermore, the gate electrode layer is The above materials may be laminated. Furthermore, a conductive film containing nitrogen may be used for the gate electrode layer. It's okay to be there.

[0089] An insulating layer 180 is formed on the gate insulating film 160 and the gate electrode layer 170. It is preferable that aluminum oxide be used for the insulating layer. The nium film acts as a barrier, preventing the passage of both hydrogen, water, and other impurities, as well as oxygen. The effect is high. Therefore, the aluminum oxide film is used during the transistor fabrication process and during manufacturing. Later, oxides of impurities such as hydrogen and moisture, which become factors in the variation of the transistor's electrical characteristics, To prevent contamination of the semiconductor layer 130, and to prevent the presence of oxygen, which is the main component material constituting the oxide semiconductor layer 130. Effect of preventing emission from the oxide semiconductor layer and preventing unnecessary oxygen emission from the underlying insulating film 120. It is suitable for use as a protective film having the acid contained in the aluminum oxide film. It is also possible to diffuse the element into the oxide semiconductor layer.

[0090] Furthermore, it is preferable that an insulating layer 185 is formed on the insulating layer 180. This includes magnesium oxide, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride Cone, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, rayon oxide Using an insulating film containing one or more of tantalum, neodymium oxide, hafnium oxide, and tantalum oxide This is possible. Furthermore, the insulating layer may be a laminate of the above-mentioned materials.

[0091] Here, it is preferable that the insulating layer 185 has excess oxygen. An insulating layer containing excess oxygen is, This refers to an insulating layer that can release oxygen through heat treatment or other means. For example, if the surface temperature is 1 The heating treatment is carried out at a temperature of 00°C to 700°C, preferably 100°C to 500°C. Thermal desorption gas spectroscopy analysis revealed that the amount of oxygen released, converted to oxygen atoms, was 1.0 × 10⁻¹⁶. 19 at oms / cm 3 The film is as described above. The oxygen released from the insulating layer is the gate insulating film 16 Is it possible to diffuse into the channel formation region of the oxide semiconductor layer 130 via 0? Furthermore, even if an oxygen deficiency is formed in the channel formation region, oxygen can be replenished. Therefore, stable transistor electrical characteristics can be obtained.

[0092] Miniaturization of transistors is essential for highly integrating semiconductor devices. It is known that miniaturization degrades the electrical characteristics of transistors, particularly the channel width. The decrease in on-current, directly caused by the reduction in size, is significant.

[0093] However, in a transistor according to one aspect of the present invention, as described above, the second oxide semiconductor A third oxide semiconductor layer 133 is formed so as to cover the region in the body layer 132 where the channel is formed. The channel forming layer and the gate insulating film do not come into contact. This can suppress carrier scattering that occurs at the interface between the channel formation layer and the gate insulating film, and This allows for an increase in the field-effect mobility of the inverter.

[0094] Furthermore, a transistor according to one aspect of the present invention is as shown in the cross-sectional view in the channel width direction of Figure 2, Length of the upper surface of the second oxide semiconductor layer 132 in the channel width direction (W T ) is the oxide In a structure reduced to the same thickness as the semiconductor layer, particularly in order to improve electrical properties, It is possible.

[0095] For example, in a transistor as shown in Figure 2, W T If it is small as described above, The electric field applied from the electrode layer 170 to the side surface of the second oxide semiconductor layer 132 is the second oxide Because it extends across the entire semiconductor layer 132, it is also formed on the side surface and upper surface of the second oxide semiconductor layer 132. A channel equivalent to the one being formed is created.

[0096] W T For transistors with a small channel width, the channel width is W T and the second acid in the channel width direction Length of the side surface of the semiconductor layer 132 (W S1 , W S2 ) sum (W T +W S1 +W S2 ) and fixed This can be done, and an on-current corresponding to the channel width flows through the transistor. Ta, W T If it is extremely small, current will flow throughout the entire second oxide semiconductor layer 132. ru.

[0097] That is, W using one aspect of the present invention T In transistors with small size, carrier scattering is suppressed. Because it combines the effects of both increasing the channel width and expanding the channel width, it is more efficient than conventional transistors. The current can be increased.

[0098] Furthermore, W S1 =W S2 =W S In this case, the on-current of the transistor can be efficiently improved. 0.3W S ≤W T ≤3W S (W T 0.3W S The above 3W S The following applies. Also, preferred or W T / W S is 0.5 or more and 1.5 or less, more preferably W T / W S is 0.7 or more and 1.3 or less. When W T / W S >3, the S value and off-state current may increase.

[0099] Therefore, the transistor of one embodiment of the present invention can, even when the transistor is miniaturized , obtain a sufficiently high on-state current.

[0100] Further, in the transistor of one embodiment of the present invention, the second oxide semiconductor layer 132 is formed over the first oxide semiconduc tor layer 131, which provides an effect of making interface states less likely to be formed, and an effect that the second oxide semiconduc tor layer 132 serving as an intermediate layer of a three-layer structure can eliminate the influence of impurity contamination from above and below . Therefore, the second oxide semiconductor layer 132 has a structure surrounded by the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133. In addition to improving the on-state current of the aforementioned transistor , the threshold voltage can be stabilized and the S value can be reduced. Accordingly, Icut (current when the gate voltage VG is 0 V) can be reduced, and the power consumption of a semiconductor device can be reduced. Further, since the threshold voltage of the transistor is stabilized , the long-term reliability of the semiconductor device can be improved.

[0101] Further, as shown in FIG. 6, the transistor of one embodiment of the present invention may include a conductive film 172 between the oxide semiconductor layer 130 and a substra te 110. By using the conductive film as a second gate electrode , the on-state current can be further increased and the threshold voltage can be controlled. To increa se the on-state current, for example, the gate electrode layer 170 and the conductive film 172 are set to the same potential, and It can be driven as a dual-gate transistor. Also, to control the threshold voltage... This can be achieved by supplying a constant potential to the conductive film 172 that is different from that of the gate electrode layer 170.

[0102] This embodiment may be appropriately combined with other embodiments and examples shown herein. It is possible.

[0103] (Embodiment 2) In this embodiment, the method for manufacturing the transistor 100 shown in Figure 1, as described in Embodiment 1, is as follows: This will be explained using Figures 7 and 8.

[0104] The substrate 110 can be a glass substrate, ceramic substrate, quartz substrate, sapphire substrate, or the like. It is possible to also use single-crystal semiconductor substrates such as silicon and silicon carbide, and polycrystalline semiconductor substrates. Plates, compound semiconductor substrates such as silicon germanium, SOI (Silicon On I It is also possible to use substrates such as nsulators, and semiconductor elements can be placed on these substrates. You may use the one provided.

[0105] The underlayer insulating film 120 is made of aluminum oxide by plasma CVD or sputtering, etc. Magnesium oxide, silicon oxide, silicon nitride oxide, gallium oxide, germanium oxide Yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and oxide insulating films such as tantalum oxide, silicon nitride, silicon oxide nitride, aluminum nitride. Using a nitride insulating film such as nium or aluminum nitride oxide, or a film made by mixing the above materials It can be formed by lamination of the above materials, and at least oxide semiconductor The upper layer in contact with the body layer 130 contains excess oxygen that can serve as a source of oxygen for the oxide semiconductor layer 130. It is preferable to form it with a material containing [the specified element].

[0106] Furthermore, ion implantation, ion doping, and plasma immersion methods are applied to the underlying insulating film 120. Oxygen may be added using methods such as on-plantation. Therefore, the supply of oxygen from the underlying insulating film 120 to the oxide semiconductor layer 130 is further facilitated. It is possible.

[0107] Furthermore, the surface of the substrate 110 is an insulator, and impurities will spread to the oxide semiconductor layer 130 that will be provided later. If there is no scattering effect, the underlying insulating film 120 can be omitted.

[0108] Next, a first oxide semiconductor film 3, which will become the first oxide semiconductor layer 131, is placed on the underlying insulating film 120. 31 and the second oxide semiconductor film 332 which will become the second oxide semiconductor layer 132 are sputtered The film is deposited using the CVD method, MBE method, ALD method, or PLD method (see Figure 7(A)). see).

[0109] Next, the first oxide semiconductor film 331 and the second oxide semiconductor film 332 are selectively etched. By performing this process, a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132 are formed. (See Figure 7(B)). At this time, the underlying insulating film 120 is etched slightly excessively as shown in the figure. It may be done. By excessively etching the underlying insulating film 120, the gate that will be formed later will be affected. The electrodes can be used to easily cover the second oxide semiconductor layer 132. In the cross-section in the channel width direction, from the upper surface to the side of the second oxide semiconductor layer 132 The shape is designed to have curvature along its length.

[0110] Note that the first oxide semiconductor film 331 and the second oxide semiconductor film 332 are selectively etched ing. In this process, not only photoresist but also a hard mask such as a metal film may be used. In addition , an organic resin may be formed on the metal film. For example, a tungsten film with a thickness of approximately 5 nm or the like can be used as the metal film.

[0111] Further, as the etching method described above, it is preferable to use a dry etching method with which a difference in etching rate between the first oxide semiconductor film 331 and the second oxide semiconductor film 332 is small .

[0112] In order to form a continuous junction in the stacked layer of the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 , it is preferable to continuously stack each layer without exposure to the atmosphere using a multi-chamber type deposition apparatus including a load lock chamber (e.g., a sputtering apparatus) . It is preferable that each chamber in the sputtering apparatus is subjected to high vacuum evacuation using an adsorption-type vacuum exhaust pump such as a cryopump to remove as much as possible moisture or the like which becomes an impurity for an oxide semiconductor, such that the chamber can be evacuated to a pressure of approximately 5×10 Pa or higher and 1×10 -7 Pa or lower, and -4 a substrate to be deposited can be heated to 100° C. or higher, preferably 500° C. or higher. Alternatively, it is preferable that a combination of a turbomolecular pump and a cold trap is used to prevent backflow of gas containing moisture, carbon components, and the like from an exhaust system into the chamber. it is preferable to prevent gas containing moisture, carbon components, and the like from flowing back from the exhaust system into the chamber by combining a turbomolecular pump and a cold trap.

[0113] In order to obtain a high-purity intrinsic oxide semiconductor, not only high vacuum evacuation of the inside of a chamber but also high purification of a sputtering gas is required. For oxygen gas or argon gas used as a sputtering gas, high purification is also necessary. ​The dew point is -40°C or lower, preferably -80°C or lower, more preferably -100°C or lower. By using highly purified gas, the amount of moisture and other substances incorporated into the oxide semiconductor layer can be minimized. It can be prevented.

[0114] The first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the layer formed in a later step The third oxide semiconductor layer 133 can be made from the material described in Embodiment 1. For example, the first oxide semiconductor layer 131 has In:Ga:Zn=1:3:6, 1:3:4, In-Ga-Zn oxides in 1:3:3 or 1:3:2 [atomic ratio], second oxide semiconductors Body layer 132 contains In-G with an In:Ga:Zn ratio of 1:1:1 or 5:5:6 [atomic ratio]. α-Zn oxide, third oxide semiconductor layer 133: In:Ga:Zn=1:3:6, 1:3 Use In-Ga-Zn oxide in atomic ratios of 4, 1:3:3, or 1:3:2. It is possible.

[0115] Furthermore, the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide The oxide semiconductor that can be used as semiconductor layer 133 is at least indium (In It is preferable that it contains either in or zinc (Zn). Alternatively, it may contain both in and Zn. This is preferable. Furthermore, it reduces variations in the electrical characteristics of transistors using the oxide semiconductor. Therefore, it is preferable to include a stabilizer along with them.

[0116] Stabilizers include gallium (Ga), tin (Sn), hafnium (Hf), and aluminum. Examples include aluminum (Al) or zirconium (Zr). Also, other stabilizers... These are lanthanides: lanthanum (La), cerium (Ce), and praseodymium (P). r), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium ( Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium Examples include rhodium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu). .

[0117] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and in-Zn oxide. Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In- Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, I n-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al -Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn acid In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, I n-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy -Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn acid In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide Materials, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al -Zn oxide, In-Sn-Hf-Zn oxide, and In-Hf-Al-Zn oxide are used. It is possible.

[0118] For example, in-Ga-Zn oxide is a material whose main components are In, Ga, and Zn. It means an oxide containing In, Ga, and Zn. Good. Also, in this specification, a film composed of In-Ga-Zn oxide is referred to as an IGZO film. They also call them that.

[0119] Also, InMO3(ZnO) m Materials represented as (m>0, and m is not an integer) It may be included. Note that M is one selected from Ga, Y, Zr, La, Ce, or Nd. This indicates a metallic element or multiple metallic elements. Also, In2SnO5(ZnO) n (n>0, and You may also use materials represented by n (where n is an integer).

[0120] However, as described in detail in Embodiment 1, the first oxide semiconductor layer 131 and the third The oxide semiconductor layer 133 has a lower electron affinity than the second oxide semiconductor layer 132. Select the sea urchin ingredient.

[0121] Furthermore, it is preferable to use the sputtering method for depositing the oxide semiconductor layer. For this purpose, RF sputtering, DC sputtering, AC sputtering, etc., can be used.

[0122] First oxide semiconductor layer 131, second oxide semiconductor layer 132, third oxide semiconductor layer 13 When using In-Ga-Zn oxide as option 3, the atomic ratios of In, Ga, and Zn are as follows: For example, In:Ga:Zn=1:1:1, In:Ga:Zn=2:2:1, In:Ga: Zn=3:1:2, In:Ga:Zn=5:5:6, In:Ga:Zn=1:3:2, I n:Ga:Zn=1:3:3, In:Ga:Zn=1:3:4, In:Ga:Zn=1: 3:6, In:Ga:Zn=1:4:3, In:Ga:Zn=1:5:4, In:Ga: Zn=1:6:6, In:Ga:Zn=2:1:3, In:Ga:Zn=1:6:4, I n:Ga:Zn=1:9:6, In:Ga:Zn=1:1:4, In:Ga:Zn=1: Using either a 1:2 ratio of materials, the first oxide semiconductor layer 131 and the third oxide semiconductor The electron affinity of layer 133 should be smaller than that of the second oxide semiconductor layer 132. .

[0123] For example, if the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of an oxide with c=1 is such that the atomic ratio is In:Ga:Zn=A:B:C(A+B+C The composition of the oxide in the vicinity of (aA) = 1) means that a, b, and c are in the vicinity of (aA) 2 +(bB) 2 + (cC) 2 ≤r 2 This means satisfying the following condition. For example, r can be set to 0.05. The same applies to other oxides.

[0124] Furthermore, the second oxide semiconductor layer 132 is made of the first oxide semiconductor layer 131 and the third oxide It is desirable to increase the indium content compared to semiconductor layer 133. In oxide semiconductors, mainly The s orbitals of heavy metals contribute to carrier conduction, and by increasing the In content, Because more s orbitals overlap, oxides with a composition where In is more abundant than Ga have the same composition as Ga. Compared to oxides with equal or lesser composition, the mobility is higher. Therefore, the second oxide By using an oxide with a high indium content in the semiconductor layer 132, a high-mobility transistor can be formed. It is possible to realize ZISTA.

[0125] The structure of oxide semiconductor films will be described below.

[0126] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. This refers to the state in which something is positioned. Therefore, it also includes cases where the angle is between -5° and 5°. Also, "Perpendicular" refers to a state where two lines are positioned at an angle between 80° and 100°. Therefore, this also includes cases where the angle is between 85° and 95°.

[0127] Furthermore, in this specification, if a crystal is trigonal or rhombohedral, it will be represented as a hexagonal crystal system. .

[0128] Oxide semiconductor films are broadly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. A single-crystal oxide semiconductor film is a CAAC-OS (C Axis Aligned Crystals Polycrystalline oxide semiconductor film This refers to microcrystalline oxide semiconductor films, amorphous oxide semiconductor films, etc.

[0129] First, let's explain the CAAC-OS membrane.

[0130] CAAC-OS film is one of the oxide semiconductor films having multiple crystalline regions, and most of the bonds The crystal portion is small enough to fit within a cube with sides less than 100 nm. Therefore, CAAC -The crystalline portion contained in the OS film is cubic with sides less than 10 nm, less than 5 nm, or less than 3 nm. This also includes cases where the organism is small enough to fit inside the body.

[0131] CAAC-OS film is scanned using a transmission electron microscope (TEM). When observed with a microscope, clear boundaries between crystalline regions, i.e., bonds, can be seen. The grain boundaries (also called crystal grain boundaries) cannot be identified. Therefore, CA AC-OS films are less susceptible to the decrease in electron mobility caused by grain boundaries.

[0132] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). ) This confirms that metal atoms are arranged in layers in the crystalline region. Each layer has irregularities on the surface (also called the surface to be formed) or the upper surface that forms the CAAC-OS film. The shape reflects this, and the elements are arranged parallel to the surface or top surface of the CAAC-OS film.

[0133] On the other hand, the CAAC-OS film was observed by TEM from a direction roughly perpendicular to the sample surface (planar TEM). (M observation) In the crystalline region, metal atoms are arranged in a triangular or hexagonal shape. This can be confirmed. However, no regularity is observed in the arrangement of metal atoms between different crystalline regions. stomach.

[0134] Cross-sectional TEM observation and planar TEM observation revealed that the crystalline portion of the CAAC-OS film exhibits orientation. You can tell they are there.

[0135] X-ray diffraction (XRD) applied to the CAAC-OS film. When structural analysis is performed using this method, for example, a CAAC-OS film having InGaZnO4 crystals is found. In the out-of-plane analysis, the diffraction angle (2θ) shows a peak near 31°. This peak may appear. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is generally aligned with the surface to be formed or the upper surface. It can be confirmed that it is facing in a nearly vertical direction.

[0136] On the other hand, in-pl X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis. In analysis using the ANE method, a peak may appear when 2θ is around 56°. This peak is It is attributed to the (110) plane of the InGaZnO4 crystal. Single crystal oxidation of InGaZnO4 For a solid semiconductor film, fix 2θ to around 56°, and use the normal vector of the sample surface as the axis (φ axis). When the sample is rotated while the analysis (φ scan) is performed, the crystal plane equivalent to the (110) plane is found. Six attributed peaks are observed. In contrast, in the case of the CAAC-OS film, 2θ is set to 5 Even when fixed at approximately 6° and scanned using the φ scan function, no clear peak appears.

[0137] From the above, it can be concluded that in CAAC-OS films, the orientation of the a-axis and b-axis is inconsistent between different crystalline regions. It is a rule, but it has c-axis orientation and the c-axis is parallel to the normal vector of the surface to be formed or the upper surface. It can be seen that it is facing in a certain direction. Therefore, the layered structure confirmed by the aforementioned cross-sectional TEM observation is Each layer of metal atoms arranged in this manner is a plane parallel to the ab-plane of the crystal.

[0138] The crystalline portion is formed when the CAAC-OS film is deposited, or when crystallization treatment such as heat treatment is performed. It is formed when this occurs. As mentioned above, the c-axis of the crystal is the surface on which the CAAC-OS film is formed or It is oriented in a direction parallel to the normal vector of the upper surface. Therefore, for example, CAAC-OS film When the shape is altered by etching or other means, the c-axis of the crystal becomes the shape of the CAAC-OS film. The normal vector may not be parallel to the surface or top surface.

[0139] Furthermore, the degree of crystallinity in the CAAC-OS film does not need to be uniform. For example, the CAAC-OS film When the crystalline portion is formed by crystal growth from near the upper surface of the CAAC-OS film, the upper surface The nearby region may have a higher degree of crystallinity than the region near the surface being formed. Also, CAA When impurities are added to a C-OS film, the degree of crystallinity in the region where the impurities are added changes, and some areas Regions with different degrees of crystallinity may also be formed.

[0140] Furthermore, the out-of-plane method for CAAC-OS films containing InGaZnO4 crystals. Analysis revealed that in addition to a peak near 2θ = 31°, a peak also appeared near 2θ = 36°. In some cases, this may occur. Peaks near 36° 2θ indicate c-axis orientation in a portion of the CAAC-OS film. This indicates that it contains crystals that do not have [the specified characteristic]. The CAAC-OS film has 2θ near 31°. It is preferable that a peak is observed, and that no peak is observed near 36° for 2θ.

[0141] CAAC-OS films are oxide semiconductor films with low impurity concentrations. The impurities include hydrogen, carbon, These are elements other than silicon and transition metal elements, which are the main components of oxide semiconductor films. In particular, silicon Elements such as ions, which have a stronger bonding force with oxygen than the metal elements that make up oxide semiconductor films, By removing oxygen from the material semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. This is a contributing factor. Also, heavy metals such as iron and nickel, argon, and carbon dioxide have a certain atomic radius. Because of its large molecular radius, when it is contained within an oxide semiconductor film, the oxide semiconductor film This disrupts the atomic arrangement and reduces crystallinity. Furthermore, these impurities are present in oxide semiconductor films. Objects can sometimes act as carrier traps or carrier sources.

[0142] Furthermore, CAAC-OS films are oxide semiconductor films with a low defect level density. For example, oxide Oxygen vacancies in semiconductor films can act as carrier traps or capture hydrogen. It can be a source of carrier activity.

[0143] A low impurity concentration and low defect level density (few oxygen vacancies) is referred to as high-purity intrinsic or This is essentially called high-purity intrinsic. High-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film Because there are fewer carrier sources, the carrier density can be kept low. Therefore, The transistor using this oxide semiconductor film exhibits an electrical characteristic in which the threshold voltage becomes negative. Also called normally-on.) It rarely becomes high-purity intrinsic or substantially high-purity. Highly intrinsic oxide semiconductor films have few carrier traps. Transistors using body membranes exhibit less variation in electrical characteristics and are highly reliable. Furthermore, the charge trapped in the carrier trap of the oxide semiconductor film requires time to be released. It can remain dormant for a long time, behaving almost like a fixed charge. Therefore, the impurity concentration Transistors using oxide semiconductor films with high defect level density have unstable electrical properties. It can happen.

[0144] Furthermore, transistors using CAAC-OS films exhibit electrical characteristics under irradiation with visible light and ultraviolet light. The fluctuations are small.

[0145] Next, we will explain microcrystalline oxide semiconductor films.

[0146] In microcrystalline oxide semiconductor films, the crystalline regions can be clearly observed in TEM images. In some cases, this may not be the case. The crystalline portion contained in the microcrystalline oxide semiconductor film is between 1 nm and 100 nm in size. or are often between 1 nm and 10 nm in size. In particular, between 1 nm and 10 nm The following are nanocrystals (nc: nanocryst), which are microcrystalline structures between 1 nm and 3 nm in size. An oxide semiconductor film having al) is made nc-OS (nanocrystalline Ox It is called an IDE Semiconductor film. Also, an nc-OS film is, for example, TE In some cases, grain boundaries may not be clearly visible in images observed using M.

[0147] nc-OS films are used in minute regions (for example, regions between 1 nm and 10 nm, especially regions larger than 1 nm). The atomic arrangement has periodicity in the region of 3 nm or less. Also, the nc-OS film is different No regularity in crystal orientation is observed between the crystalline regions. Therefore, no orientation is observed throughout the entire film. Therefore, depending on the analytical method, nc-OS films may be indistinguishable from amorphous oxide semiconductor films. There are cases where this is not possible. For example, when using X-rays with a diameter larger than that of the crystalline region on an nc-OS film, XR When structural analysis is performed using instrument D, the out-of-plane method shows that the crystal plane No peaks indicating this are detected. Also, for the nc-OS film, probes larger than the crystalline region are detected. Electron diffraction (also called limited-field electron diffraction) uses an electron beam with a diameter (e.g., 50 nm or more). When this is done, a diffraction pattern resembling a halo pattern is observed on the nc-OS film. In contrast, the probe diameter is close to or smaller than the size of the crystal (for example, 1 nm to 30 nm). When electron diffraction (also called nanobeam electron diffraction) is performed using the following electron beams, the sponge A circular pattern is observed. Furthermore, when nanobeam electron diffraction is performed on the nc-OS film, a circular pattern is observed. In some cases, a region of high brightness (ring-shaped) may be observed in the nc-OS film. When nanobeam electron diffraction is performed, if multiple spots are observed within a ring-shaped region... There is.

[0148] nc-OS films are oxide semiconductor films with higher orderliness than amorphous oxide semiconductor films. Therefore, nc-OS films have a lower defect level density than amorphous oxide semiconductor films. However, In nc-OS films, no regularity is observed in the crystal orientation between different crystalline regions. Therefore, nc-O The S film has a higher defect level density compared to the CAAC-OS film.

[0149] Note that oxide semiconductor films include, for example, amorphous oxide semiconductor films, microcrystalline oxide semiconductor films, and CA The AC-OS film may be a multilayer film having two or more types.

[0150] CAAC-OS films are made, for example, using a polycrystalline oxide semiconductor sputtering target. The film can be deposited by sputtering. When ions collide with the sputtering target... As a result, the crystalline region contained in the sputtering target is cleaved from the ab plane and parallel to the ab plane. In this case, sputtered particles may peel off as flat or pellet-shaped particles with a smooth surface. In addition, the flat or pellet-shaped sputtered particles are charged and therefore aggregate in the plasma. Furthermore, it can reach the substrate while maintaining its crystalline state, allowing for the formation of a CAAC-OS film.

[0151] The second oxide semiconductor layer 132 is an In-M-Zn oxide layer (where M is Ga, Y, Zr, La, In the case of Ce or Nd, a sprue is used to form the second oxide semiconductor layer 132. In the target for the application, the atomic ratio of the metal elements is In:M:Zn = a1:b1:c1. Then 、 a1 / b1 is between 1 / 3 and 6, and moreover, between 1 and 6, and c1 / b1 is It is preferable that the ratio is between 1 / 3 and 6, and more preferably between 1 and 6. By setting the value between 1 and 6, a CAAC-OS film is formed as the second oxide semiconductor layer 132. This makes it easier to do so. A typical example of the atomic ratio of the target metal elements is In:M:Zn= Examples include 1:1:1, In:M:Zn=3:1:2, In:M:Zn=5:5:6, etc.

[0152] A first oxide semiconductor layer 131 and a third oxide semiconductor layer 133 are formed of an In-M-Zn oxide layer (M is Ga, Y, Zr, La, Ce, or Nd). In the sputtering target used for depositing the first oxide semiconductor layer 1 31 and the third oxide semiconductor layer 133 , when the atomic ratio of metal elements is In:M:Zn = a2:b2:c2 、 , a2 / b2 is less than a1 / b1, c2 / b2 is greater than or equal to 1 / 3 and less than or equal to 6, and more preferably greater than or equal to 1 and less than or equal to 6 . Setting c2 / b2 to be greater than or equal to 1 and less than or equal to 6 facilitates formation of a CAAC-OS film as the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 . Typical examples of the atomic ratio of metal elements in the target include In:M:Zn = 1:3:2, I n:M:Zn = 1:3:3, In:M:Zn = 1:3:4, and In:M:Zn = 1:3:6 , and the like.

[0153] After forming the second oxide semiconductor layer 132, first heat treatment may be performed. The first heat treatme nt is performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, in an inert gas atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or a reduced pressure atmosphere. Alternatively, the atmosphere for the first heat treatment may be such that after heat treatment in an inert gas atmosphere, heat treatment is performed in an atmosphere containing 10 ppm or more of an oxidizing gas to compensate for desorbed oxygen. The first heat treatment improves the crystallinity of the second oxide semiconductor layer 132, and further can remove impurities such as hydrogen and water from the base insulating film 120 and the first oxide semiconductor layer 131. Note that the first heating step may be performed before etching for forming the second oxide semiconductor layer 132. Note that the first heating step may be performed before etching for forming the second oxide semiconductor layer 132.

[0154] Next, a source electrode layer is placed on the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. A first conductive film is formed, which will become 140 and the drain electrode layer 150. This refers to alloy materials that are mainly composed of Al, Cr, Cu, Ta, Ti, Mo, W, or these materials. It can be used. For example, a 100 nm titanium film can be formed by sputtering. Alternatively, a tungsten film may be formed by the CVD method.

[0155] Next, the first conductive film is etched so as to divide it on the second oxide semiconductor layer 132. - An electrode layer 140 and a drain electrode layer 150 are formed (see Figure 7(C)). Excessive etching of the first conductive film causes a portion of the second oxide semiconductor layer 132 to etch. It may take on a chapping shape.

[0156] Next, the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the source electrode layer 140 And on the drain electrode layer 150, a third oxide semiconductor layer 133 is formed. A body film 333 is formed. At this time, the second oxide semiconductor layer of the third oxide semiconductor film 333 The area near the interface with 132 is a microcrystalline layer, and a c-axis oriented crystalline layer is formed on top of this microcrystalline layer.

[0157] Furthermore, the second heat treatment may be performed after the formation of the third oxide semiconductor film 333. The heat treatment can be carried out under the same conditions as the first heat treatment. The second heat treatment will result in Impurities such as hydrogen and water can be removed from the oxide semiconductor film 333. From the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132, hydrogen and water are further extracted. It can remove impurities.

[0158] Next, an insulating film 360, which will become the gate insulating film 160, is formed on the third oxide semiconductor film 333. The insulating film 360 contains aluminum oxide, magnesium oxide, silicon oxide, and nitridation. Silicon, silicon nitride, silicon nitride, gallium oxide, germanium oxide, gallium oxide Zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and acid Tantalum oxide and the like can be used. The insulating film 360 is a laminate of the above materials. The insulating film 360 can be made by sputtering, CVD, MBE, ALD, or PLD. It can be formed using [a specific method / tool].

[0159] Next, a second conductive film 370, which will become the gate electrode layer 170, is formed on the insulating film 360 (Figure 8). (See (A)). The second conductive film 370 can be Al, Ti, Cr, Co, Ni, Cu, Y Using Zr, Mo, Ru, Ag, Ta, W, or alloy materials with these as the main components. The second conductive film 370 can be formed by sputtering or CVD. It is possible. Furthermore, as the second conductive film 370, a conductive film containing nitrogen may be used, and the above material A laminate of a conductive film containing a material and a conductive film containing nitrogen may also be used.

[0160] Next, using a resist mask for forming the gate electrode layer 170, the second conductive film 37 The 0 is selectively etched to form a gate electrode layer 170.

[0161] Next, the insulating film 360 is selected using the above resist mask or gate electrode layer 170 as a mask. Selective etching is performed to form a gate insulating film 160.

[0162] Next, using the above-mentioned resist mask or gate electrode layer 170 as a mask, a third oxide semiconductor The body film 333 is etched to form a third oxide semiconductor layer 133 (see Figure 8(B)). .

[0163] Etching of the second conductive film 370, insulating film 360, and third oxide semiconductor film 333 as described above. The etching can be performed layer by layer or continuously. Also, the etching method is dry etching. Either etching or wet etching may be used, and an appropriate etching method may be used for each layer. You may choose this option.

[0164] Next, insulating material is placed on the source electrode layer 140, the drain electrode layer 150, and the gate electrode layer 170. Layer 180 and insulating layer 185 are formed (see Figure 8(C)). Insulating layer 180 and insulating layer 185 can be formed using the same materials and methods as the underlying insulating film 120. It is particularly preferable to use aluminum oxide for the insulating layer 180.

[0165] Furthermore, ion implantation, ion doping, and plasma immersion ions were applied to the insulating layer 180. Oxygen may be added using methods such as the implantation method. By adding oxygen... This makes it possible to further facilitate the supply of oxygen from the insulating layer 180 to the oxide semiconductor layer 130. Cut.

[0166] Next, a third heat treatment may be performed. The third heat treatment is performed under the same conditions as the first heat treatment. This can be done. The third heat treatment removes the underlying insulating film 120 and the gate insulating film 160. Excess oxygen is more easily released from the insulating layer 180, reducing oxygen vacancies in the oxide semiconductor layer 130. It can be reduced.

[0167] By following the above steps, the transistor 100 shown in Figure 1 can be manufactured.

[0168] This embodiment may be appropriately combined with other embodiments and examples shown herein. It is possible.

[0169] (Embodiment 3) In this embodiment, a transistor, which is one aspect of the present invention, is used in a state where no power is supplied. Moreover, a semiconductor device (memory device) that can retain its contents and has no limit on the number of write cycles An example of placement will be explained using a diagram.

[0170] Figure 9(A) shows a cross-sectional view of the semiconductor device, and Figure 9(B) shows a circuit diagram of the semiconductor device.

[0171] The semiconductor device shown in Figures 9(A) and 9(B) has a lower section using the first semiconductor material. It has a transistor 3200, and a transistor 3300 with a second semiconductor material on top, and It also has a capacitive element 3400. Note that the transistor 3300 is as in Embodiment 1 The transistor 100 described above can be used.

[0172] Furthermore, the capacitive element 3400 connects one electrode to the source electrode layer of the transistor 3300 or to the source electrode layer. The rain electrode layer, the other electrode being the gate electrode layer of transistor 3300, and the dielectric being the transistor The same materials are used for the gate insulating film 160 and the third oxide semiconductor layer 133 of the T3300. By adopting this structure, it can be formed simultaneously with transistor 3300.

[0173] Here, the first semiconductor material and the second semiconductor material are materials with different energy gaps. It is desirable to do so. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (silicone). The second semiconductor material is an oxide semiconductor as described in Embodiment 1. Yes, it is possible. Transistors using materials other than oxide semiconductors can easily operate at high speeds. Therefore, transistors using oxide semiconductors have low off-current electrical characteristics, allowing for long-term charge retention. Allows for retention.

[0174] The above explanation assumes that all transistors are n-channel transistors. However, it goes without saying that p-channel transistors can be used. Also, information To hold it, a transistor like the one shown in Embodiment 1, which uses an oxide semiconductor, is used. Other aspects include the materials used in semiconductor devices and the structure of semiconductor devices, as well as the specific configuration of semiconductor devices. It is not necessary to limit this to what is shown here.

[0175] In Figure 9(A), transistor 3200 is made of a semiconductor material (for example, crystalline silicon, etc.). A channel formation region is provided on the substrate 3000 including ), and the channel formation region is sandwiched between them The provided impurity region, the intermetallic compound region adjacent to the impurity region, and the channel formation region It has a gate insulating film provided on the gate insulating film and a gate electrode layer provided on the gate insulating film. Note that in the diagram, the source electrode layer and drain electrode layer may not be explicitly shown. For convenience, this state is sometimes also referred to as a transistor. To explain the connection relationships of the inverter, the source electrode layer includes the source region and drain region. It is sometimes referred to as the drain electrode layer. In other words, in this specification, the relationship between the source electrode layer and the drain electrode layer The description may include source code.

[0176] An element isolation insulating layer 3100 is provided on the substrate 3000 so as to surround the transistor 3200. An insulating layer 3150 is provided to cover the transistor 3200. The element isolation insulating layer 3100 is LOCOS (Local Oxidation of Si (licon) and STI (Shallow Trench Isolation) It can be formed using element isolation technology.

[0177] For example, when using a crystalline silicon substrate, the transistor 3200 can operate at high speed. Therefore, by using this transistor as a readout transistor, information It allows for high-speed reading of data.

[0178] A transistor 3300 is provided on the insulating layer 3150, and its source electrode layer or drain The wiring electrically connected to the electrode layer acts as one electrode of the capacitive element 3400. Furthermore, the wiring is electrically connected to the gate electrode layer of transistor 3200.

[0179] The transistor 3300 shown in Figure 9(A) has a channel formed in the oxide semiconductor layer. It is a gate-type transistor. Transistor 3300 has a small off-current, therefore By using this method, it is possible to retain memory content for a long period of time. Semiconductor memory that does not require refresh operations, or requires extremely infrequent refresh operations. Because it can be made into a device, power consumption can be significantly reduced.

[0180] Furthermore, an electrode 3250 is provided via an insulating layer 3150 so as to be superimposed on the transistor 3300. It is being used. By supplying an appropriate potential to the electrode as a second gate electrode, The threshold voltage of the transistor 3300 can be controlled. This can improve long-term reliability. Furthermore, the electrode can be used as the gate electrode of transistor 3300. By operating at the same potential, the on-current can be increased. Note that electrode 325 It is also possible to have a configuration that does not include zeros.

[0181] As shown in Figure 9(A), transistor 330 is formed on the substrate on which transistor 3200 is formed. Since 0 and capacitive elements 3400 can be formed, the integration density of semiconductor devices can be increased. It is possible.

[0182] An example of a circuit configuration corresponding to Figure 9(A) is shown in Figure 9(B).

[0183] In Figure 9(B), the first wiring 3001 is electrically connected to the source electrode layer of transistor 3200. The second wiring 3002 is electrically connected to the drain electrode layer of transistor 3200. They are connected. Also, the third wiring 3003 is connected to the source electrode layer of transistor 3300. It is electrically connected to one side of the drain electrode layer, and the fourth wiring 3004 is connected to transistor 330 It is electrically connected to the gate electrode layer of transistor 3200. The polar layer, and the other of the source electrode layer or drain electrode layer of transistor 3300, are capacitances. The fifth wiring 3005 is electrically connected to one of the electrodes of element 3400, and the capacitive element 3400 It is electrically connected to the other electrode. Note that the element corresponding to electrode 3250 is shown in the figure. not present.

[0184] In the semiconductor device shown in Figure 9(B), the potential of the gate electrode layer of transistor 3200 can be maintained. By utilizing its unique characteristics, it is possible to write, store, and read information in the following ways: ru.

[0185] This section will explain how to write and retain information. First, the potential of the fourth wiring 3004 is set to the traction control. The potential is set to the ON state for transistor 3300, thereby turning on transistor 3300. As a result, the potential of the third wiring 3003 becomes the gate electrode layer of transistor 3200, And is supplied to the capacitance element 3400. That is, to the gate electrode layer of transistor 3200 A predetermined charge is applied (written). Here, two different potential levels are given. A device to which either electric charge (hereinafter referred to as Low-level charge or High-level charge) is assigned. Then, the potential of the fourth wire 3004 is set so that transistor 3300 is in the off state. By setting the potential and turning off transistor 3300, transistor 3200 The charge applied to the gate electrode layer is retained (held).

[0186] Because the off-current of transistor 3300 is extremely small, the gate current of transistor 3200 The charge in the polar layers is retained for a long period of time.

[0187] Next, we will explain how to read the information. A predetermined potential (constant potential) is applied to the first wiring 3001. In this state, when an appropriate potential (readout potential) is applied to the fifth wiring 3005, the transistor Depending on the amount of charge held in the gate electrode layer of terminal 3200, the second wiring 3002 will have different powers. To take a position. Generally, if transistor 3200 is an n-channel type, then transistor 320 Apparent threshold voltage V when a high-level charge is applied to the terminal gate layer of 0 th_H This is because a low-level charge is applied to the gate electrode layer of transistor 3200. The apparent threshold voltage V in this case th_L This is because it becomes lower. Here, the apparent appearance The i-value voltage is the fifth wiring 30 required to turn on transistor 3200. This refers to the potential of 05. Therefore, the potential of the fifth wiring 3005 is V th_H and V th_L By setting the potential V0 between these points, the gate electrode layer of transistor 3200 is supplied. It is possible to distinguish the applied charge. For example, in writing, when a high-level charge is applied... If so, the potential of the fifth wiring 3005 is V0 (>V th_H ) If so, Transis TA3200 is in the "on state". If a low-level charge is applied, the fifth The potential of wiring 3005 is V0( <V th_L Even if this happens, transistor 3200 will be "off" It remains in the "state". Therefore, by determining the potential of the second wiring 3002, it is maintained. The information contained within can be retrieved.

[0188] When memory cells are arranged in an array, only the information of the desired memory cell is read. It becomes necessary to be able to output the information. If the information is not read in this way, the state of the gate electrode layer. Regardless, the potential at which transistor 3200 is in the "off state" is V th_ H A smaller potential should be applied to the fifth wiring 3005. Alternatively, the state of the gate electrode layer can be adjusted. Regardless, the potential at which transistor 3200 turns "on" is, that is, V th_L A higher potential should be applied to the fifth wiring 3005.

[0189] In the semiconductor device shown in this embodiment, an oxide semiconductor is used in the channel formation region for off-current By applying extremely small transistors, it is possible to retain memory contents for extremely long periods of time. This is possible. In other words, the refresh operation becomes unnecessary, or the refresh operation is eliminated. Because the frequency of operation can be made extremely low, power consumption can be significantly reduced. Furthermore, in the absence of power supply (however, it is desirable that the potential be fixed), However, it is possible to retain memory content over a long period of time.

[0190] Furthermore, the semiconductor device shown in this embodiment does not require a high voltage for writing information, and There are no issues with degradation of the child. For example, unlike conventional non-volatile memory, it does not use floating gates. Because there is no need to inject electrons into it or extract electrons from the floating gate, Problems such as degradation of the gate insulating film are less likely to occur. In other words, the semiconductor device according to the disclosed invention In this configuration, there is no limitation on the number of rewrite cycles, which is a problem with conventional non-volatile memory, and reliability The quality improves dramatically. Furthermore, the on and off states of the transistors allow for the processing of information. Because data is recorded, high-speed operation can be easily achieved.

[0191] As described above, semiconductors that achieve miniaturization and high integration while also possessing high electrical characteristics. We can provide the device.

[0192] This embodiment may be appropriately combined with other embodiments and examples shown herein. It is possible.

[0193] (Embodiment 4) In this embodiment, a transistor, which is one aspect of the present invention, is used in a state where no power is supplied. Furthermore, regarding semiconductor devices that can retain stored data and have no limitations on the number of write cycles... Next, we will describe a semiconductor device with a configuration different from that shown in Embodiment 3.

[0194] Figure 10 shows an example of the circuit configuration of a semiconductor device. In this semiconductor device, the first wiring 4 The source electrode layer of transistor 500 and transistor 4300 are electrically connected, and the second wiring 460 0 and the gate electrode layer of transistor 4300 are electrically connected, and transistor 4300 The drain electrode layer and the first terminal of the capacitive element 4400 are electrically connected. The transistor 4300 included in the semiconductor device is the transistor described in Embodiment 1. A generator 100 can be used. Note that the first wiring 4500 is a bit line, and the second wiring Line 4600 can function as a word line.

[0195] The semiconductor device (memory cell 4250) has a transistor 3300 and a capacitor as shown in Figure 9. It can be connected in the same way as element 3400. Therefore, the capacitive element 4400 is Similar to the capacitive element 3400 described in Embodiment 3, the manufacturing process of the transistor 4300 is as follows: They can be manufactured simultaneously.

[0196] Next, information is written to and stored in the semiconductor device (memory cell 4250) shown in Figure 10. Let me explain how to do it.

[0197] First, supply a potential to the second wiring 4600 that turns on transistor 4300, Turn on the inverter 4300. This will change the potential of the first wiring 4500 to the capacitance element The first terminal of child 4400 is supplied (written). Then, the potential of the second wiring 4600 is applied. This is the potential at which transistor 4300 turns off, and transistor 4300 is turned off. By maintaining this state, the potential of the first terminal of the capacitive element 4400 is maintained (held).

[0198] The 4300 transistor, which uses an oxide semiconductor, has the characteristic of having an extremely low off-current. Therefore, by turning off transistor 4300, the capacitive element 4400 The potential of the first terminal (or the charge stored in the capacitive element 4400) is maintained for an extremely long period of time. It is possible to hold it across.

[0199] Next, we will explain how to read the information. When transistor 4300 is turned ON, floating The first wiring 4500, which is in a idle state, and the capacitive element 4400 are electrically connected, and the first wiring 4500 and Charge is redistributed among the capacitive elements 4400. As a result, the potential of the first wiring 4500 changes. The change in potential of the first wiring 4500 is the potential of the first terminal of the capacitive element 4400. Alternatively, it takes on different values ​​depending on the charge stored in the capacitive element 4400.

[0200] For example, let V be the potential of the first terminal of the capacitive element 4400, C be the capacitance of the capacitive element 4400, and the first The capacitance component of wiring 4500 is CB, and the charge of the first wiring 4500 before redistribution is CB. If the potential is VB0, then the potential of the first wiring 4500 after charge redistribution is (CB × The formula becomes VB0 + C × V) / (CB + C). Therefore, the state of memory cell 4250 is Assuming the potential of the first terminal of the capacitive element 4400 takes on two states, V1 and V0 (V1 > V0), Then, the potential of the first wiring 4500 when the potential V1 is maintained is (=(CB × VB0 + C (×V1) / (CB+C)) is the potential of the first wiring 4500 when the potential V0 is maintained. It can be seen that this is higher than (=(CB×VB0+C×V0) / (CB+C)).

[0201] Then, by comparing the potential of the first wiring 4500 with a predetermined potential, the information is read out. It is possible.

[0202] Thus, the semiconductor device (memory cell 4250) shown in Figure 10 has a transistor 4300 Due to its extremely low off-current, the charge stored in the capacitive element 4400 remains for a long time. It can be retained over time. In other words, a refresh operation is unnecessary, or This allows for extremely low refresh frequency, significantly reducing power consumption. It is possible to store the stored information over a long period of time, even without a power supply. It is possible to hold it.

[0203] The memory cell 4250 shown in Figure 10 is a drive circuit for driving the memory cell 4250. It is preferable to stack substrates on which the following are formed. The memory cell 4250 and the drive circuit are stacked. This makes it possible to miniaturize semiconductor devices. The number of drive circuits is not limited.

[0204] The transistors included in the drive circuit use a different semiconductor material than transistor 4300. It is preferable to use silicon, germanium, silicon germanium, silicon carbide Cone or gallium arsenide can be used, and the use of a single-crystal semiconductor is more preferred. It is so. Transistors using such semiconductor materials are similar to transistors using oxide semiconductors. It enables faster operation than the previous model and is suitable for use in the configuration of the drive circuit for the memory cell 4250. They are doing it.

[0205] As described above, semiconductors that achieve miniaturization and high integration while also possessing high electrical characteristics. We can provide the device.

[0206] This embodiment may be appropriately combined with other embodiments and examples shown herein. It is possible.

[0207] (Embodiment 5) In this embodiment, an example of a circuit utilizing a transistor according to one aspect of the present invention is shown in the drawings. See the explanation below.

[0208] Figure 11(A) shows the circuit diagram of the semiconductor device, and Figures 11(C) and (D) show cross-sectional views of the semiconductor device. These are shown below. Figures 11(C) and (D) show the channels of transistor 2100 on the left side, respectively. The diagram shows a cross-sectional view in the longitudinal direction, and on the right, a cross-sectional view in the channel width direction. The circuit diagram also includes: To clearly indicate that it is a transistor using an oxide semiconductor, the designation "OS" is used. It is attached.

[0209] The semiconductor device shown in Figures 11(C) and (D) has a transistor using the first semiconductor material at the bottom. It has a 2200 transistor and a 2100 transistor made of a second semiconductor material on top. Here, as a transistor 2100 using a second semiconductor material, as exemplified in Embodiment 1, An example of applying transistor 100 will be explained.

[0210] Here, the first semiconductor material and the second semiconductor material are materials with different energy gaps. It is desirable to do so. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (silicone). Cone, germanium, silicon germanium, silicon carbide, or gallium arsenide, etc. ) and the second semiconductor material can be the oxide semiconductor described in Embodiment 1. Transistors using materials other than oxide semiconductors, such as single-crystal silicon, can operate at high speeds. It is easy. On the other hand, transistors using oxide semiconductors have low off-current.

[0211] Here, we will explain assuming that transistor 2200 is a p-channel type transistor. However, it goes without saying that different circuits can be constructed using n-channel transistors. Furthermore, other than using a transistor as shown in Embodiment 1 using an oxide semiconductor, This section describes the specific components of semiconductor devices, including the materials used and the structure of the semiconductor device. It is not necessary to limit it to what is shown.

[0212] The configurations shown in Figures 11(A), (C), and (D) consist of a p-channel transistor and an n-channel transistor. A so-called CMO is formed by connecting two transistors of type 1 in series and connecting their respective gates. An example of an S-circuit configuration is shown.

[0213] A transistor to which an oxide semiconductor according to one aspect of the present invention is applied has an increased on-current. Therefore, high-speed operation of the circuit becomes possible.

[0214] In the configuration shown in Figure 11(C), an insulating layer 2201 is placed on top of the transistor 2200. A transistor 2100 is provided. Also, transistors 2200 and 2 Multiple wirings 2202 are provided between 100. Also, multiple insulation layers are embedded in various insulating layers. The 2203 plugs electrically connect the wiring and electrodes located at the top and bottom, respectively. It is also provided with an insulating layer 2204 covering the transistor 2100, and on the insulating layer 2204 Wiring 2205 and Wiring 2 formed by processing the same conductive film as the pair of electrodes of the transistor. 206 and are provided.

[0215] In this way, stacking two transistors reduces the circuit footprint, Multiple circuits can be arranged at a high density.

[0216] Figure 11(C) shows either the source or drain of transistor 2100 and the transistor Either the source or drain of the 2200 is connected to the electrical wiring 2202 or plug 2203. They are connected precisely. Also, the gate of transistor 2100 is connected to wiring 2205 and wiring 22 06, via plug 2203 and wiring 2202, etc., the gateway of transistor 2200 It is electrically connected to the tortoise.

[0217] In the configuration shown in Figure 11(D), the plug 2203 is attached to the gate insulating film of transistor 2100. An opening for embedding is provided, and the gate of transistor 2100 and plug 2203 are The components are connected. This configuration makes it easy to integrate the circuits. Compared to the configuration shown in Figure 11(C), the number and length of wiring and plugs can be reduced. Therefore, the circuit can be operated at a higher speed.

[0218] Here, in the configuration shown in Figures 11(C) and (D), transistor 2100 and transistor By changing the connection configuration of the electrodes of the Ta2200, various circuits can be constructed. For example, as shown in Figure 11(B), the source and drain of each transistor are connected. By using a continuous circuit configuration, it can function as a so-called analog switch. Cut.

[0219] This embodiment may be appropriately combined with other embodiments and examples shown herein. It is possible.

[0220] (Embodiment 6) In this embodiment, an image is created to read information about an object using a transistor according to one aspect of the present invention. This document describes a semiconductor device that has a sensor function.

[0221] Figure 12 shows an example of an equivalent circuit of a semiconductor device having an image sensor function.

[0222] Photodiode 610 has one electrode connected to the photodiode reset signal line 661, and the other electrode connected to the photodiode reset signal line 661. One electrode is electrically connected to the gate of transistor 640. Transistor 640 Either the source or the drain is connected to the photosensor reference signal line 672, and the source or drain The other end of the input is electrically connected to either the source or the drain of transistor 650. Transistor 650 has its gate connected to the gate signal line 662, and its source or drain connected to the gate signal line 662. This is electrically connected to the photosensor output signal line 671.

[0223] The photodiode 610 includes, for example, a semiconductor layer having a p-type conductivity and a high-resistance (i A pin-type semiconductor layer having an n-type conductivity and a semiconductor layer having an n-type conductivity are stacked together. A photodiode can be applied.

[0224] By detecting the light incident on the photodiode 610, information about the detected object can be read. This is possible. Furthermore, when reading information about the detected object, a light source such as a backlight is used. It is also possible to do so.

[0225] Furthermore, transistors 640 and 650 are equipped with the oxidation shown in Embodiment 1. A transistor 100 in which a channel is formed in a solid semiconductor can be used. It was clearly determined that transistors 640 and 650 contain an oxide semiconductor. To make it easier to understand, the symbol for transistors is denoted with "OS". Transistor 640 The transistor 650 has a high on-current and is electrically stable with suppressed electrical characteristic fluctuations. It is a transistor. By including this transistor, the image sensor function shown in Figure 12 is achieved. As a semiconductor device, it can provide highly reliable semiconductor devices.

[0226] This embodiment may be appropriately combined with other embodiments and examples shown herein. It is possible.

[0227] (Embodiment 7) The transistors described in Embodiments 1 and 2 are used in display devices, memory devices, CPUs, and DSPs. (Digital Signal Processor), Custom LSI, PLD(P LSIs such as rogrammable logic devices, RF-ID (Rad io Frequency Identification), inverter, image sensor It can be applied to semiconductor devices such as sensors. In this embodiment, the above semiconductor device is Let's explain some examples of electronic devices.

[0228] Electronic devices having the above-mentioned semiconductor device include televisions, display devices such as monitors, lighting devices, and Personal computers, word processors, image playback devices, portable audio players Radio, tape recorder, stereo, telephone, cordless phone, mobile phone, car phone Transceivers, radios, game consoles, calculators, personal digital assistants, electronic organizers, ebooks, electronic translation devices. Translation devices, voice input devices, video cameras, digital still cameras, electric shavers, IC chips High-frequency heating devices such as microwave ovens, electric rice cookers, electric washing machines, electric vacuum cleaners, air conditioners Air conditioning equipment such as showers, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators Storage units, electric freezers, electric refrigerators / freezers, DNA storage freezers, radiation detectors, dialysis machines, X-ray machines. Examples include medical devices such as diagnostic equipment. Also, smoke detectors, heat detectors, gas alarm devices, etc. Other examples include alarm systems such as security alarms. Furthermore, guide lights, traffic lights, conveyor belts, Examples of industrial equipment include elevators, escalators, industrial robots, and power storage systems. In addition, it is propelled by an engine using fuel or by an electric motor using electricity from a non-aqueous secondary battery. Moving objects are also included in the category of electronic devices. Examples of such moving objects include, for example... Electric vehicles (EVs), hybrid electric vehicles (HEVs) that combine internal combustion engines and electric motors, plastic PHEVs, tracked vehicles that replace these tires and wheels with tracks, Motorized bicycles including electric assist bicycles, motorcycles, electric wheelchairs, golf carts, Small or large vessels, submarines, helicopters, aircraft, rockets, satellites, space probes Examples include planetary probes and spacecraft. Some specific examples of these electronic devices are shown in Figure 13.

[0229] The television device 8000 shown in Figure 13(A) has a display unit 8002 built into the housing 8001. It is integrated, and displays video via the display unit 8002 and outputs sound from the speaker unit 8003. It is possible to do so. A memory device having a transistor according to one aspect of the present invention has a display unit 80 It is possible to use 02 in the drive circuit for operation.

[0230] Furthermore, the television equipment 8000 includes a CPU 8004 for information communication and memory. It may be provided. The CPU 8004 and memory may have transistors according to one aspect of the present invention. A CPU and memory device can be used.

[0231] The alarm device 8100 shown in Figure 13(A) is a residential fire alarm, and it has a smoke or heat detection unit. This is an example of an electronic device using the 8102 and the 8101 microcomputer. Computer 8101 includes a memory device and CPU having transistors according to one aspect of the present invention. .

[0232] Furthermore, the air conditioner having an indoor unit 8200 and an outdoor unit 8204 as shown in Figure 13(A) The processor includes an electronic transistor, memory device, or CPU as shown in the previous embodiment. This is an example of equipment. Specifically, the indoor unit 8200 consists of the housing 8201, the air outlet 8202, and CP. It has U8203, etc. In Figure 13(A), CPU8203 is connected to indoor unit 8200. The example shows a case where it is provided, but the CPU 8203 is provided in the outdoor unit 8204. Alternatively, CPU 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. It may be used. A transistor according to one aspect of the present invention is used in the CPU of an air conditioner. This can lead to energy savings.

[0233] Furthermore, the electric refrigerator-freezer 8300 shown in Figure 13(A) is a transition as shown in the previous embodiment. This is an example of an electronic device including a starter, memory device, or CPU. Specifically, electric refrigeration The 8300 unit consists of the casing 8301, the refrigerator door 8302, the freezer door 8303, and the CPU 830. It has four components. In Figure 13(A), the CPU 8304 is located inside the enclosure 8301. A transistor according to one aspect of the present invention is used in the CPU 8304 of an electric refrigerator 8300. This will help to reduce power consumption.

[0234] Figures 13(B) and (C) show an example of an electronic device, specifically an electric vehicle. The 700 is equipped with a secondary battery 9701. The power of the secondary battery 9701 is supplied to circuit 97 The output is adjusted by 02 and supplied to the drive unit 9703. Circuit 9702 is shown in the figure. It is controlled by a processing unit 9704 having ROM, RAM, CPU, etc. By using one type of transistor in the CPU of the electric vehicle 9700, power saving is achieved. It can be done.

[0235] The drive unit 9703 consists of a DC motor or an AC motor alone, or a motor and an internal combustion engine. It is composed of a combination of these. The processing unit 9704 processes the driver's operation information of the electric vehicle 9700. Information (acceleration, deceleration, stopping, etc.) and driving information (information such as uphill and downhill slopes, and the driving force applied to the drive wheels) Based on input information (such as load information), a control signal is output to circuit 9702. Circuit 9702 The electrical energy supplied from the secondary battery 9701 is controlled by the control signal of the processing unit 9704. - Adjust to control the output of the drive unit 9703. If an AC motor is installed, see Figure Although not shown, it also has a built-in inverter that converts DC to AC.

[0236] This embodiment may be appropriately combined with other embodiments and examples shown herein. It is possible. [Examples]

[0237] In this embodiment, the results of observing the stacking state of the oxide semiconductor layer described in Embodiment 1 are as follows: I will explain the details.

[0238] Figure 14 is a cross-sectional view showing the structure of the sample used in this embodiment. The sample is made of substrate 4 10 an underlying insulating film 420, a first oxide semiconductor layer 431 and a second underlying insulating film A stack consisting of an oxide semiconductor layer 432, and a third oxide semiconductor formed on the stack It has a body layer 433. Furthermore, it has a first oxide semiconductor layer 431 and a second oxide semiconductor layer 432. , and the third oxide semiconductor layer 433 is the first oxide semiconductor layer 1 shown in Embodiment 1. 31 corresponds to the second oxide semiconductor layer 132 and the third oxide semiconductor layer 133, respectively. do.

[0239] Next, we will explain the method for preparing the sample shown in Figure 14.

[0240] First, a silicon wafer is used as the substrate 410, and the silicon wafer is subjected to thermal oxidation. A silicon oxide film was formed to serve as the underlying insulating film 420.

[0241] Next, the first In- Ga-Zn oxide film, In:Ga:Zn=1:1:1 (atomic ratio) second In-Ga A Zn oxide film was continuously deposited by sputtering. The first In-Ga-Zn oxide film The film thicknesses of the first and second In-Ga-Zn oxide films were set to 20 nm and 15 nm, respectively.

[0242] The deposition conditions for the first In-Ga-Zn oxide film are In:Ga:Zn=1:3:4 (number of atoms) Targeting a φ8 inch In-Ga-Zn oxide (ratio), with argon as the sputtering gas: Oxygen = 2:1 (flow ratio), film deposition pressure 0.4 Pa, input power 0.5 kW (DC), The distance between the get and the substrate was set to 60 mm, and the substrate temperature was set to 200°C.

[0243] Furthermore, the deposition conditions for the second In-Ga-Zn oxide film are In:Ga:Zn=1:1:1( A φ8 inch In-Ga-Zn oxide (atomic ratio) is targeted, and sputtering gas is applied. Gon:Oxygen = 2:1 (flow rate ratio), film deposition pressure 0.4 Pa, input power 0.5 kW (DC) The target-substrate distance was set to 60 mm, and the substrate temperature to 300°C.

[0244] Next, the first In-Ga-Zn oxide film and the second In-Ga-Zn oxide film are placed at 450 The material is heat-treated at 450°C in a nitrogen atmosphere for 1 hour, followed by another heat treatment at 450°C in an oxygen atmosphere for 1 hour. They did that.

[0245] Next, a 5 nm tungsten film and a 20 nm film are placed on the second In-Ga-Zn oxide film. A resin was formed, and a resist mask was created using electron beam lithography.

[0246] Then, using the resist mask as a mask, the organic resin and tungsten film are selectively processed. Etching was performed. The etching method used was a two-stage process with an inductively coupled dry etching apparatus. Etching was performed.

[0247] For the first etching stage, use 100% carbon tetrafluoride as the etching gas and a pressure of 0.67 Pa, input power 2000W, bias power 50W, substrate temperature -10℃, etching A time setting of 12 seconds was used. Additionally, for the second etching stage, a four-stage etching gas was used. Carbon dioxide:oxygen = 3:2 (flow rate ratio), pressure 2.0 Pa, input power 1000 W, substrate The following conditions were used: 25W power supply, -10°C substrate temperature, and 8 seconds etching time.

[0248] Next, using an organic resin and a tungsten film as a mask, the first In-Ga-Zn oxide film and selectively etch the second In-Ga-Zn oxide film and the first oxide semiconductor layer A stack of 431 and a second oxide semiconductor layer 432 was formed. Etching was performed using an inductively coupled method. Using a dry etching apparatus of the same type, the etching gas is methane:argon = 1:2 (flow rate ratio). ), pressure 1.0 Pa, input power 600 W, substrate bias power 100 W, substrate temperature The conditions used were 70°C and an etching time of 82 seconds.

[0249] Next, the organic resin and tungsten film were etched. Inductive coupling was used for the etching. Using a dry etching apparatus of the same type, the etching gas is carbon tetrafluoride:oxygen = 3:2 (flow rate) (Ratio), pressure 2.0 Pa, input power 1000 W, substrate bias power 25 W, substrate temperature The etching conditions used were -10°C and 6 seconds.

[0250] Then, 10 A third oxide semiconductor layer 433 with a size of nm was formed using the sputtering method.

[0251] The deposition conditions for the third oxide semiconductor layer 433 are In:Ga:Zn=1:3:4 (atomic ratio). The target is an 8-inch diameter In-Ga-Zn oxide, and the sputtering gas is argon:oxygen. =2:1 (flow rate ratio), deposition pressure 0.4 Pa, input power 0.5 kW (DC), target The distance between the to board and the substrate was set to 60 mm, and the substrate temperature was set to 200°C.

[0252] Figure 15(A) shows a cross-sectional TEM image of the region enclosed by the dotted line in Figure 14. In a region of several nanometers on the underlying insulating film 420 side of the semiconductor layer 431, the crystal lattice could not be confirmed. However, a grid pattern was observed in the upper part. Also, in the second oxide semiconductor layer 432, the first Similar lattice fringes were observed in the oxide semiconductor layer 431. That is, the first oxide semiconductor layer Most of 431 and the entirety of the second oxide semiconductor layer 432 are crystalline layers, and the orientation of the lattice fringes From this, it was determined that the CAAC-OS film is c-oriented perpendicular to the deposition surface. Ta.

[0253] Furthermore, the first oxide semiconductor layer 431 or the second oxide semiconductor layer of the third oxide semiconductor layer 433 In the conductive layer 432, no crystal lattice is observed in the region of a few nanometers, but a lattice is visible above it. A stripe was observed. That is, the third oxide semiconductor layer 433 consists of a microcrystalline layer 433a and a crystalline layer 4 It was confirmed to be 33b.

[0254] The lattice patterns observed in the crystalline layer 433b are located on the upper part of the second oxide semiconductor layer 432 and the first oxide The orientation differs on the side of the material semiconductor layer 431 or the second oxide semiconductor layer 432. It was found that the CAAC-OS film was c-axis oriented perpendicular to the deposition surface.

[0255] Furthermore, as is clear from Figure 15(B), which is an enlarged view of the dotted line frame in Figure 15(A), the second is On the curved edge region of the oxide semiconductor layer 432, via the microcrystalline layer 433a, Lattice fringes were observed in crystal layer 433b, which is oriented along the c axis perpendicular to the curved surface.

[0256] Based on the results of this embodiment, a laminated structure of oxide semiconductor layers according to one aspect of the present invention can be fabricated. It was confirmed that it was possible.

[0257] This embodiment can be appropriately combined with the embodiments shown in this specification. [Explanation of Symbols]

[0258] 100 transistors 110 circuit boards 120 Undercoat Insulating Film 130 Oxide semiconductor layer 131 First oxide semiconductor layer 132 Second oxide semiconductor layer 132b area 133 Third oxide semiconductor layer 133a Microcrystalline layer 133b Crystal layer 135 Boundary 140 Source electrode layer 150 Drain electrode layer 160 Gate Insulator 170 gate electrode layers 172 Conductive film 180 Insulating layer 185 Insulating layer 233 areas 331 First oxide semiconductor film 332 Second oxide semiconductor film 333 Third Oxide Semiconductor Film 360 insulating film 370 Second conductive film 410 circuit boards 420 Underlying insulating film 431 First oxide semiconductor layer 432 Second oxide semiconductor layer 433 Third oxide semiconductor layer 433a Microcrystalline layer 433b Crystal layer 610 Photodiode 640 transistors 650 transistors 661 Photodiode reset signal line 662 Gate signal line 671 Photosensor output signal line 672 Photosensor Reference Signal Line 2100 transistors 2200 transistors 2201 Insulating layer 2202 Wiring 2203 Plug 2204 Insulating layer 2205 Wiring 2206 Wiring 3000 circuit boards 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3100 Element isolation insulating layer 3150 Insulating layer 3200 transistors 3250 electrode 3300 transistors 3400 Capacitive element 4250 memory cells 4300 transistors 4400 Capacitive element 4500 wiring 4600 wiring 8000 Television equipment 8001 enclosure 8002 Display section 8003 Speaker section 8004 CPU 8100 Alarm device 8101 Microcomputer 8102 Detection Unit 8200 indoor unit 8201 enclosure 8202 Air outlet 8203 CPU 8204 Outdoor unit 8300 Electric Refrigerator / Freezer 8301 enclosure 8302 Refrigerator door 8303 Freezer door 8304 CPU 9700 Electric Vehicles 9701 Secondary battery 9702 Circuit 9703 Drive unit 9704 Processing Unit

Claims

1. A first conductive layer located on an insulating surface and functioning as the gate electrode of a transistor, A first insulating layer having a region located above the first conductive layer, An oxide semiconductor layer having a region located above the first insulating layer, A second conductive layer having a region in contact with the oxide semiconductor layer and functioning as either the source electrode or the drain electrode of the transistor, A third conductive layer having a region in contact with the oxide semiconductor layer and functioning as the other of the source electrode or drain electrode of the transistor, The oxide semiconductor layer comprises a first region arranged substantially parallel to the insulating surface, a second region overlapping the first region and also arranged substantially parallel to the insulating surface, and a third region arranged in a direction intersecting the insulating surface. In the first region, a grid pattern was observed in a cross-sectional photograph taken with a transmission electron microscope. In the second region, no crystal lattice was observed in the cross-sectional image taken with a transmission electron microscope. In the third region, a grid pattern was observed in a cross-sectional photograph taken with a transmission electron microscope. The orientation of the grid pattern in the first region and the orientation of the grid pattern in the third region are different from each other. A semiconductor device wherein the first region and the second region have different compositions.

2. A first conductive layer located on an insulating surface and functioning as the gate electrode of a transistor, A first insulating layer having a region located above the first conductive layer, An oxide semiconductor layer having a region located above the first insulating layer, A second conductive layer having a region in contact with the oxide semiconductor layer and functioning as either the source electrode or the drain electrode of the transistor, A third conductive layer having a region in contact with the oxide semiconductor layer and functioning as the other of the source electrode or drain electrode of the transistor, The oxide semiconductor layer comprises a first region arranged substantially parallel to the insulating surface, a second region overlapping the first region and also arranged substantially parallel to the insulating surface, and a third region arranged in a direction intersecting the insulating surface. In the first region, a grid pattern was observed in a cross-sectional photograph taken with a transmission electron microscope. The second region has crystalline portions with a size of 1 nm to 10 nm, In the third region, a grid pattern was observed in a cross-sectional photograph taken with a transmission electron microscope. The orientation of the grid pattern in the first region and the orientation of the grid pattern in the third region are different from each other. A semiconductor device wherein the first region and the second region have different compositions.

3. In claim 1 or 2, The aforementioned oxide semiconductor layer comprises indium, gallium, and zinc, and is a semiconductor device.

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