Contact structure and method for forming the same

Abstract

To provide a contact structure and a method of forming the same.SOLUTION: A semiconductor device includes a first die including a stack of a first layer in a first region on the reverse side of the first die and a stack of a second layer in a second region on the reverse side of the first die. The stack of the first layer has different layers less in number than the stack of the second layer. A contact structure is formed in the first region on the reverse side of the first die. The contact structure extends through the stack of the first layer, and a first conductive structure on the top side of the first die and a second conductive structure on the reverse side of the first die are conductively connected. The top side and reverse side are the opposite sides.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This application generally describes embodiments relating to semiconductor devices and manufacturing processes for semiconductor devices.

Background Art

[0002] A memory device typically includes a memory cell array and peripheral circuits. In some examples, the memory cell array can be formed on a first die, referred to as an array die, and the peripheral circuits are formed on a second die, referred to as a peripheral die. The array die and the peripheral die can be bonded to connect the peripheral circuits to the memory cell array.

Prior Art Literature

Patent Literature

[0003]

Patent Document 1

Summary of the Invention

Problem to be Solved by the Invention

[0004] Aspects of the present disclosure provide a semiconductor device having a contact structure and a method of forming the same.

Means for Solving the Problem

[0005] According to a first aspect, a semiconductor device is provided. The semiconductor device includes a first die. The first die includes a first layer stack in a first region on a back side of the first die and a second layer stack in a second region on the back side of the first die. The first layer stack has fewer different layers than the second layer stack. A contact structure is formed in the first region on the back side of the first die. The contact structure extends through the first layer stack and is configured to conductively connect a first conductive structure on a front side of the first die to a second conductive structure on the back side of the first die. The front side is opposite the back side.

[0006] In some embodiments, the first layer stack includes, in order, a first layer, a replacement layer, and a first insulating layer. The second layer stack includes, in order, a first layer, a second layer, a conductive layer, a replacement layer, and a first insulating layer.

[0007] In some embodiments, the first layer and the replacement layer have equivalent etching properties. The second layer and the first layer have different etching properties. The conductive layer and the second layer have different etching properties. In some embodiments, the first layer and the replacement layer contain the same conductive material. In some embodiments, the first layer contains doped silicon, and the replacement layer contains doped silicon.

[0008] In some embodiments, the contact structure includes a conductive portion and a sidewall portion. The conductive portion is configured to be electrically connected to a first conductive structure. The sidewall portion is configured to insulate the conductive portion from the stack of the first layer.

[0009] In some embodiments, the conductive portion includes at least one of tungsten or aluminum. In some embodiments, the sidewall portion includes at least one of silicon oxide, silicon nitride, zirconium oxide, hafnium oxide, aluminum oxide, or tantalum oxide.

[0010] In some embodiments, the semiconductor device further includes a memory cell on the front side of a first die and a second die bonded opposite the first die. The second die includes a substrate and a peripheral network formed on the front side of the substrate for the memory cell. In some embodiments, the memory cell includes a third stack of alternating gate layers and a second insulating layer on the front side of the first die and a plurality of channel structures extending through the third stack.

[0011] In some embodiments, the semiconductor device further includes a second die bonded opposite the first die. The second die includes memory cells formed on the front side of the second die. A peripheral network is formed on the front side of the first die for the memory cells.

[0012] A second aspect of this disclosure provides a method for fabricating a semiconductor device. The method includes replacing a multilayer in a stack of layers formed on the back side of a first die with a replacement layer in a first region and from the back side of the first die. A buffer layer is formed on the back side above the replacement layer. Contact holes are formed in the first region by etching the buffer layer and the replacement layer. The contact holes expose a first conductive structure formed on the front side of the first die. The front side is opposite to the back side.

[0013] In some embodiments, the step of replacing a multilayer in a stack of layers formed on the back of the first die with a replacement layer further includes forming a recess in the stack of layers in a first region such that the first etch stop layer is at the bottom of the recess. A replacement layer is deposited to fill the recess in the stack of layers and cover the stack of layers from the back of the first die.

[0014] In some embodiments, the multilayer within the stack of layers is replaced with a substitution layer having etching properties equivalent to the first etch-stop layer within the stack of layers. In some embodiments, the substitution layer and the first etch-stop layer are made of the same material.

[0015] In some embodiments, an insulating portion of the contact structure is formed on the side wall of the contact hole. A conductive portion of the contact structure is formed to fill the contact hole and connect to the first conductive structure.

[0016] In some embodiments, the step of forming an insulating portion of the contact structure on the sidewall of the contact hole further includes depositing insulating material on the sidewall and bottom of the contact hole. The insulating material is removed from the bottom of the contact hole.

[0017] In some embodiments, a second conductive structure is formed on the back side of the contact structure. The second conductive structure is electrically coupled to the first conductive structure via the contact structure.

[0018] In some embodiments, memory cells are formed on the front side of a first die. Peripheral circuitry for the memory cells is formed on the front side of a second die. The first die and the second die are bonded face-to-face.

[0019] According to a third aspect, a memory system is provided. The memory system includes a semiconductor device and a controller configured to control operation of the semiconductor device. The controller is connected to the semiconductor device. The semiconductor device includes a die including a contact structure provided on a back side of the die. A first conductive structure is provided on a front side of the die and connected to the contact structure from the front side of the die. The front side is a side opposite the back side. A second conductive structure is provided on the back side of the die and connected to the contact structure from the back side of the die. The contact structure is configured to conductively connect the first conductive structure to the second conductive structure.

[0020] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be increased or decreased for clarity of discussion. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] [Figure 1] It is a cross-sectional view of a semiconductor device in accordance with an illustrative embodiment of the present disclosure. [Figure 2A] It is a cross-sectional view of a semiconductor device at an intermediate manufacturing step in accordance with an illustrative embodiment of the present disclosure. [Figure 2B] It is a cross-sectional view of a semiconductor device at an intermediate manufacturing step in accordance with an illustrative embodiment of the present disclosure. [Figure 2C] It is a cross-sectional view of a semiconductor device at an intermediate manufacturing step in accordance with an illustrative embodiment of the present disclosure. [Figure 2D] It is a cross-sectional view of a semiconductor device at an intermediate manufacturing step in accordance with an illustrative embodiment of the present disclosure. [Figure 2E]It is a cross-sectional view of a semiconductor device at an intermediate manufacturing step, according to an exemplary embodiment of the present disclosure. [Figure 2F] It is a cross-sectional view of a semiconductor device at an intermediate manufacturing step, according to an exemplary embodiment of the present disclosure. [Figure 3] It is a flowchart of a process for manufacturing an exemplary semiconductor device, according to an embodiment of the present disclosure. [Figure 4] It shows a block diagram of a memory system device according to some examples of the present disclosure. DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

[0022] The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are in direct contact, but may also include embodiments where additional features are formed between the first and second features, such that the first and second features are not in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of brevity and clarity, and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0023] Further, to facilitate describing the relationship of one element or feature to another element or feature as illustrated in the figures, spatially relative terms such as "beneath", "below", "lower", "above", "upper", and the like may be used herein. Spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein may accordingly be interpreted accordingly.

[0024] A semiconductor device may include multiple dies that are bonded together. In some fabrication techniques, the dies can be bonded at the wafer level before the formation of a pad structure. For example, a first wafer containing multiple first dies (e.g., array dies) and a second wafer containing multiple second dies (peripheral dies) can be bonded facing each other. The bonded wafers are then further processed, for example, to form a pad structure on the back side of one of the wafers, and the pad structure is used to interface with an external network. In some examples, after the formation of the pad structure, the bonded wafers can be cut into chips, each chip may contain two dies that are bonded together (e.g., an array die and a peripheral die), and the pad structure is formed on the back side of one of the two dies.

[0025] While the pad structure is formed on the back side of one of the two dies, the pad structure can be connected to a circuit network formed on the front side of the two dies by a conductive structure. Some of the conductive structure is formed by machining steps acting on the front side of the dies before bonding, and some of the conductive structure is formed by machining steps acting on the back side of one of the two dies.

[0026] According to certain aspects of this disclosure, a contact structure can be formed from the back side of one of two dies, the contact structure can extend through various layers on the back side of the die, and can electrically connect to a conductive structure provided on the front side of the die (for example, the conductive structure is formed by a machining step acting on the front side of the die). In some examples, one of the various layers is a silicon layer, and the contact structure extending through the various layers is referred to as a through-silicon contact (TSC) structure. In the following description, the TSC structure is used as an example illustrating a technique for forming a contact structure, which can be used to form a contact structure extending through various layers without a silicon layer.

[0027] Generally, the memory cell array and other circuit networks, peripheral circuits, etc., are located on the front side of the die (sometimes referred to as the front in some cases), and the opposite side of the die is called the back side. The front side and the back side are opposite sides of the die.

[0028] For the sake of clarity, the end of the TSC structure that connects to the pad structure on the back of the die is referred to as the back side of the TSC structure, and the end of the TSC structure that connects to the conductive structure on the front side of the die is referred to as the front side of the TSC structure. The TSC structure can therefore function as a connecting structure.

[0029] To form a TSC structure, in some cases, through-holes (TSHs) in silicon are formed by etching through a stack of layers from the back of the die, usually before a conductive metallic material is deposited on the TSH. The stack of layers can contain different materials with different etching properties, such as different etch rates and etching directions. During the etching process that forms the TSH, due to differences in etching properties, the TSH may have non-flat sidewalls, for example, at the interface of two materials with different etching properties.

[0030] In some cases, TSHs typically have a high aspect ratio, and relatively smooth sidewalls are desirable for TSHs. Non-flat sidewalls of TSHs can be problematic for further processing. In some cases, due to other processing requirements, the stack of layers may have entirely different etching characteristics. For example, the stack of layers may include an insulating layer (first layer), a conductive layer (second layer), a second etch-stop layer for etching the conductive layer (third layer), a first etch-stop layer for etching the second etch-stop layer (fourth layer), etc. Generally, the etch-stop layers are selected to have relatively large differences in etching characteristics from the layers being etched. Therefore, the stack of layers includes three interfaces with relatively large differences in etching characteristics. Specifically, the first and second layers have relatively large differences in etching characteristics, the second and third layers have relatively large differences in etching characteristics, and the third and fourth layers have large differences in etching characteristics. Due to the differences in etching properties of the four different materials, the etching profiles around the three interfaces of the TSH sidewall can make it difficult to form a smooth TSH.

[0031] Aspects of this disclosure provide techniques for reducing the number of different materials in the stack of layers through which the TSC structure will extend, so that the TSC structure can be formed with a relatively smooth sidewall profile. In one example, the stack of layers through which the TSC structure will extend contains two different materials and has one interface. As a result, in some examples, the etching process for forming the TSH is simplified, and more importantly, it becomes easier to obtain a smooth etching profile of the TSH.

[0032] Figure 1 is a cross-sectional view of a semiconductor device 100 according to an illustrative embodiment of the present disclosure. As shown, the semiconductor device 100 may include a first die (or wafer) D1. The first die D1 has a back side and a front side opposite to the back side. The first die D1 may include a stack of first layers 101 in a first region 108 on the back side of the first die D1. The first die D1 may also include a stack of second layers 102 in a second region 109 on the back side of the first die D1. In some examples, the stack of second layers 102 is adjacent to the stack of first layers 101, and the stack of second layers 102 contains different material properties with more layers than the stack of first layers 101. The first die D1 may further include at least one through-silicon contact (TSC) structure 120 formed in the first region 108 on the back side of the first die D1 and extending through the stack of first layers 101. At least one TSC structure 120 is configured to electrically connect a first conductive structure 131 on the front side of the first die D1 to a second conductive structure 133 on the back side of the first die D1.

[0033] In some embodiments, the first layer stack 101 includes, in order, a first layer 111 (illustrated by 111a, also referred to as the first etch-stop layer), a replacement layer 116 (illustrated by 116a), and a first insulating layer 117 (illustrated by 117a). The second layer stack 102 includes, in order, a first layer 111 (illustrated by 111b), a second layer 112 (also referred to as the second etch-stop layer), a conductive layer 113, a replacement layer 116 (illustrated by 116b), and a first insulating layer 117 (illustrated by 117b). In some embodiments, the first layer 111 and the replacement layer 116 have equivalent (e.g., similar or identical) etching properties. The second layer 112 and the first layer 111 have different etching properties. The conductive layer 113 and the second layer 112 have different etching properties.

[0034] Referring further to Figure 1, the TSC structure 120 may include a conductive portion 121 and a sidewall portion 123 (also referred to as an insulating portion). The conductive portion 121 is configured to electrically connect to a first conductive structure 131 on the front side and a second conductive structure 133 on the back side. As a result, the second conductive structure 133 can be electrically coupled to the first conductive structure 131 via the TSC structure 120. In one example, the second conductive structure 133 is configured to be a pad-out structure, and the conductive portion 121 includes a conductive metallic material such as tungsten or aluminum. Note that in some examples, the first conductive structure 131 may extend into the conductive portion 121 to increase the contact area between the first conductive structure 131 and the conductive portion 121.

[0035] The sidewall portion 123 of the TSC structure 120 is configured to isolate the conductive portion 121 from the stack 101 of the first layer. In one example, the sidewall portion 123 is provided between the conductive portion 121 and the stack 101 of the first layer. The sidewall portion 123 can therefore function to electrically isolate the conductive portion 121 from the stack 101 of the first layer. Accordingly, the sidewall portion 123 may include insulating materials such as silicon oxide, silicon nitride, zirconium oxide, hafnium oxide, aluminum oxide, tantalum oxide, etc.

[0036] As illustrated in Figure 1, the TSC structure 120 extends through a stack 101 of first layers, including a first insulating layer 117, a replacement layer 116, and a first layer 111. In one embodiment, the replacement layer 116 and the first layer 111 contain different materials and have an interface between them. Thus, the TSC structure 120 extends through three layers of different materials and two interfaces. In another embodiment, the replacement layer 116 and the first layer 111 contain the same conductive material with no etching difference, so that etching does not cause a non-planar interface. Thus, the TSC structure 120 extends through two layers of different materials and one interface. For example, the same conductive material can be a silicon material (e.g., doped polysilicon, doped amorphous silicon, or doped nanosilicon) or a conductive metallic material.

[0037] Furthermore, in some embodiments, the semiconductor device 100 may include a shielding structure 125 formed on the back side of the first die D1. The shielding structure 125 extends through at least one of the first stack 101 or the second stack 102. In the example of Figure 1, the shielding structure 125 is located at the boundary between the first region 108 and the second region 109. As shown, the shielding structure 125 can have a high aspect ratio. In particular, in one example, the TSC structure 120 is wider than the shielding structure 125 in the XY plane. In addition, the shielding structure 125 may include insulating material to electrically isolate the second stack 102. In one example, the sidewall portions 123 of the shielding structure 125 and the TSC structure 120 may include the same insulating material.

[0038] Referring further to Figure 1, the semiconductor device 100 may further include memory cells formed on the front side of the first die D1. In some embodiments, the memory cells include 3D NAND memory cells. In non-limiting examples, a third stack 103 of alternating word line layers 141 (also referred to as gate layers) and a second insulating layer 143 is provided on the front side of the first die D1. The stack 103 of the third layers may include an array region in which at least one channel structure 150 is formed and extends through the third stack 103. The alternating word line layers 141 and the second insulating layer 143 and the channel structure 150 can form a stack of transistors, such as a vertical memory cell string. An array of alternating word line layers 141 and the second insulating layer 143 and the channel structure 150 can form an array of vertical memory cell strings. In some examples, the stack of transistors may include memory cells and selection transistors, such as one or more lower selection transistors, one or more upper selection transistors, and so on. In some examples, a stack of transistors may also include one or more dummy selection transistors.

[0039] The second insulating layer 143 may include one or more insulating materials such as silicon nitride, silicon oxide, etc. The word line layer 141 may include a gate stack of materials such as a high-k gate insulator layer, a metal gate electrode, etc. The channel structure 150 may include a channel layer 153 (e.g., polysilicon) and is surrounded by one or more third insulating layers 155, such as a tunneling layer (e.g., silicon oxide), a charge trap layer (e.g., silicon nitride), and a barrier layer (e.g., silicon oxide), which together form an oxide-nitride-oxide (ONO) structure surrounding the channel layer 153. The channel structure 150 may further include a space 151 within the channel layer 153. The space 151 may be a void or filled with insulating material.

[0040] In one embodiment, the first layer 111 (illustrated by 111b) in the second region 109 is configured to serve as a common source line or as a source connection layer that electrically connects the channel layer 153 to the source region of the semiconductor device 100. Accordingly, one or more portions of a third insulating layer 155 are removed so that the first layer 111 is in direct contact with the channel layer 153. This can be achieved, for example, by SWS technology as disclosed in the present applicant's concurrently pending U.S. Patent Application No. 17 / 113,662, filed December 7, 2020, entitled "TWO-STEP L-SHAPED SELECTIVE EPITAXIAL GROWTH," the entire content of which is incorporated herein by reference.

[0041] Furthermore, the third stack 103 may have a stepped region in which multiple gate contact structures 145 are formed. The gate contact structures 145 are connected to the word line layer 141.

[0042] Referring further to Figure 1, the semiconductor device 100 may include a second die (or wafer) D2 bonded to a first die D1 opposite each other via a junction interface 180 (the network side being the front and the substrate side being the back). Accordingly, the second die D2 also has a front side and a back side opposite the front side. The second die D2 includes a substrate 188 and peripheral networks (e.g., address decoders, drive circuits, sense amplifiers, etc.) formed on the front side of the substrate 188 for memory cells. Note that the first die D1 initially includes the substrate on which memory cells are formed. In some examples, the substrate of the first die D1 is removed before the formation of the TSC structure 120.

[0043] The structure in the first die D1 can be electrically coupled to the structure in the second die D2 via the contact structure in the first die D1, the metal layers in the first die D1 (e.g., shown as 171 and 172, 171a, 171n, 172a, 172n, etc.), the bonding structure 181 at the bonding interface 180 (e.g., shown as 181a, 181n, etc.), the metal layers in the second die D2 (e.g., shown as 191, 191a, 191n, etc.), and the contact structure in the second die D2 (not shown). For example, the channel structure 150 can be electrically connected to the structure of the peripheral network in the second D2 via the metal layers 171n and 172n, the bonding structure 181n, and the metal layer 191n. Similarly, the first conductive structure 131 can be electrically connected to other structures of the peripheral network in the second D2 (e.g., input / output circuits) via metal layers 171a and 172a, junction structure 181a, and metal layer 191a. As a result, in some examples, the second conductive structure 133 can be electrically connected to the input / output circuits via the TSC structure 120 and the first conductive structure 131.

[0044] In the example shown in Figure 1, the first die D1 contains a memory cell, and the second die D2 contains a peripheral network. Generally, the peripheral network of the second die D2 can interface the memory cell with an external network. For example, the peripheral network receives commands from the external network via the second conductive structure 133, provides control signals to the memory cell, receives data from the memory cell, and outputs data to the external network via the second conductive structure 133.

[0045] In some embodiments, the semiconductor device 100 may include multiple array dies (e.g., a first die D1) and CMOS dies (e.g., a second die D2). The multiple array dies and CMOS dies can be stacked and bonded together. Each array die is coupled to a CMOS die, and the CMOS dies can similarly drive the array dies individually or simultaneously. Furthermore, in some embodiments, the semiconductor device 100 includes at least a first wafer and a second wafer that are bonded opposite each other. The first die D1 is provided on the first wafer together with other array dies such as D1, and the second die D2 is provided on the second wafer together with other CMOS dies such as D2. The first wafer and the second wafer are bonded together such that the array dies on the first wafer are bonded to the corresponding CMOS dies on the second wafer.

[0046] In an alternative embodiment, the second die D2 may include a memory cell, and the first die D1 may include a peripheral network (not shown) for the memory cell. Similarly, the peripheral network may be coupled to the memory cell via contact structures in the first die, a junction interface between the first die and the second die, and contact structures in the second die. In particular, the second conductive structure 133 may also be provided on the back side of the first die D1 and coupled to the input / output circuits of the peripheral network via the first conductive structure 131.

[0047] Figures 2A, 2B, 2C, 2D, 2E, and 2F are cross-sectional views of semiconductor device 100' at various intermediate steps in manufacturing according to illustrative embodiments of the present disclosure. In some embodiments, semiconductor device 100' can ultimately become semiconductor device 100.

[0048] As illustrated, the embodiment of semiconductor device 100' in Figure 2A is similar to the embodiment of semiconductor device 100 in Figure 1. The description is provided above, and the explanation here will be given to highlight the differences. For example, semiconductor device 100' may include a fourth stack 104 of layers formed on the back side of the first die D1. The fourth stack 104 of layers includes a first etch stop layer 111, a second etch stop layer 112, and a conductive layer 113. The first conductive structure 131 may extend into the fourth stack 104 by a penetration depth. Specifically, in the example of Figure 2A, the first conductive structure 131 extends through the first etch stop layer 111 and the second etch stop layer 112 into the conductive layer 113. Note that the penetration depth of the first conductive structure 131 is related to the contact area with the future TSC structure (e.g., TSC structure 120 in Figure 1) and therefore may differ in other examples.

[0049] In some embodiments, a hard mask layer 114 can be formed on the back of the fourth stack 104. A photoresist layer 115 can be formed on the back of the hard mask layer 114. The photoresist layer 115 is patterned such that a portion of the hard mask layer 114 is exposed in the first region 108. In one example, the hard mask layer 114 comprises at least one of silicon oxide, silicon nitride, or carbon.

[0050] Figure 2B illustrates the semiconductor device 100' after the pattern has been transferred from the photoresist layer 115 to the hard mask layer 114. This pattern transfer can be achieved by etching a portion of the hard mask layer 114 exposed in the first region 108 using the photoresist layer 115 as an etching mask. The photoresist layer 115 is then removed. As a result, a portion of the conductive layer 113 is exposed in the first region 108.

[0051] Figure 2C illustrates the semiconductor device 100' after a portion of the conductive layer 113 exposed in the first region 108 has been removed. This can be achieved by etching a portion of the conductive layer 113 using a hard mask layer 114 as an etching mask and a second etch-stop layer 112 to determine the etching endpoint. As a result, a portion of the second etch-stop layer 112 is exposed in the first region 108, and a recess 107 is formed within the fourth stack 104. In the example of Figure 2C, the first conductive structure 131 is also exposed from the back side. As mentioned in Figure 2A, the penetration depth of the first conductive structure 131 can differ in other examples. Therefore, the first conductive structure 131 may or may not be exposed in other examples.

[0052] In Figure 2D, a portion of the second etch-stop layer 112 exposed in the first region 108 is etched away using the hard mask layer 114 as an etching mask, and the hard mask layer 114 is also removed. Note that the hard mask layer 114 can be etched during or after the etching of a portion of the second etch-stop layer 112. For example, the second etch-stop layer 112 may include silicon oxide, silicon nitride, etc. The hard mask layer 114 may include at least one of silicon oxide, silicon nitride, or carbon. In one embodiment, both the hard mask layer 114 and the second etch-stop layer 112 are made from silicon oxide so that portions of both the hard mask layer 114 and the second etch-stop layer 112 can be etched in the same etching process. In another embodiment, the hard mask layer 114 contains silicon oxide while the second etch-stop layer 112 contains silicon nitride. In one example, a portion of the second etch-stop layer 112 is etched before the hard mask layer 114 is etched.

[0053] Note that Figures 2A to 2D illustrate an example of forming a recess 107 in the fourth stack 104 in the first region 108. It should be understood that other patterning and / or etching processes can be designed and executed to form a recess 107 in the first region 108.

[0054] In Figure 2E, a replacement layer 116 is formed from the back side of the first die D1. The replacement layer 116 fills the recesses 107 and covers the fourth stack 104 from the back side of the first die D1. In one example, the replacement layer 116 can be planarized from the back side of the first die D1 by chemical mechanical polishing (CMP). In some embodiments, the replacement layer 116 includes a conductive material. For example, the conductive material can be selected such that the replacement layer 116 and the first etch-stop layer 111 have equivalent (e.g., similar or identical) etching properties. During the future etching process, a smooth etching profile can be obtained around the interface between the replacement layer 116 and the first etch-stop layer 111. In some embodiments, the replacement layer 116 and the first etch-stop layer 111 include the same conductive material and are formed without an interface between them. For example, the substitution layer 116 and the first etch-stop layer 111 may include a silicon material (e.g., doped polysilicon, doped amorphous silicon, or doped nanosilicon) or a conductive metal material.

[0055] Referring further to Figure 2E, a first insulating layer 117 (also called a buffer layer) is formed on the back side of the replacement layer 116. The first insulating layer 117 may contain an insulating material such as silicon oxide. The first insulating layer 117 can be used as a buffer layer during a future etching process to stabilize the etching conditions.

[0056] In Figure 2F, at least one silicon through-hole (TSH) 126 (also known as a contact hole) is formed in the first region 108. The at least one TSH 126 extends through the first etch-stop layer 111 of the stack 104 of the first insulating layer 117, the replacement layer 116, and the fourth layer. The TSH 126 exposes the first conductive structure 131 from the back side of the first die D1. In some embodiments, an opening 127 may also be formed in the first region 108. The TSH 126 and the opening 127 have a depth H. The TSH 126 has a width D1, and the opening 127 has a width D2. In some examples, D1 can be greater than D2. The TSH 126 and the opening 127 can be formed in the same patterning process using the photoresist layer 118 as a mask. Furthermore, the opening 127 can have a high aspect ratio in cross-section in the xz plane. The opening 127 may be a trench extending in the y-direction.

[0057] Although not shown, in some embodiments, through-silicon contact (TSC) structures, such as the TSC structure 120 in Figure 1, are formed on the TSH 126 and can contact the first conductive structure 131. In some embodiments, a sidewall portion 123 of the TSC structure 120 is formed on the sidewall 126' of the TSH 126, and a conductive portion 121 of the TSC structure 120 is formed to fill the TSH 126. For example, insulating material can be deposited on the sidewall 126' and bottom 126'' of the TSH 126. The insulating material is then removed from the bottom 126'' of the TSH 126 so that the insulating material on the sidewall 126' of the TSH 126 forms the sidewall portion 123 of the TSC structure 120. Note that the insulating material may cover a portion of the first conductive structure 131 and then be removed. Subsequently, conductive material is deposited to fill the TSH 126 and form the conductive portion 121 of the TSC structure 120. The conductive material may be overfilled with TSH126, and a CMP process can be used to remove the overfilled portion of the conductive material.

[0058] Furthermore, in some embodiments, a shielding structure, such as the shielding structure 125 in Figure 1, can be formed in the opening 127. In one embodiment, the sidewall portion 123 of the shielding structure 125 and the TSC structure 120 contain the same insulating material and are formed in the same deposition process (note that D1 can be greater than D2). In another embodiment, the sidewall portion 123 of the shielding structure 125 and the TSC structure 120 are formed in separate processes and may or may not contain the same material.

[0059] Note that in the example of Figure 2F, the opening 127 is formed in the first region 108, or more precisely, at the boundary between the first region 108 and the second region 109. In another example, the opening 127 can be formed in the first region 108 without being at the boundary. In yet another example, the opening 127 can be formed in the second region 109, whether at the boundary or not. Accordingly, the TSH 126 and the opening 127 can be formed in separate etching processes.

[0060] Figure 3 is a flowchart of a process 300 for manufacturing an exemplary semiconductor device, such as the semiconductor device 100 in Figure 1, according to an embodiment of the present disclosure.

[0061] Process 300 begins with step S310, in which a multilayer in the stack of layers formed on the back of the first die is replaced with a replacement layer in a first region and from the back of the first die. In some embodiments, a recess is formed in the stack of layers in a first region to replace the multilayer with a replacement layer (e.g., Figures 2A-2D). The first etch stop layer of the stack of layers can be the bottom of the recess. Then, a replacement layer is deposited to fill the recess in the stack of layers and cover the stack of layers from the back of the first die (e.g., Figure 2E).

[0062] In some embodiments, the layer stack includes a first etch-stop layer, a second etch-stop layer, and a conductive layer. In some embodiments, forming a recess involves etching a portion of the conductive layer and a portion of the second etch-stop layer from the back of the first die based on a mask, so that the first etch-stop layer is exposed. In some embodiments, the back of the replacement layer can be planarized, for example, by CMP. In some embodiments, the multilayer in the layer stack is replaced with a replacement layer having etching properties equivalent to (e.g., similar or identical) the first layer in the layer stack. In one example, the replacement layer and the first etch-stop layer are made of the same material (e.g., doped silicon).

[0063] Process 300 then proceeds to step S320 by forming a buffer layer on the back side of the replacement layer (e.g., Figure 2E). The buffer layer may contain insulating material. The buffer layer can be used to stabilize etching conditions by acting as a buffer layer during the subsequent etching process.

[0064] In step S330, contact holes are formed in the first region by etching the buffer layer and the replacement layer. The contact holes expose the first conductive structure formed on the front side of the first die. The front side is the opposite side from the back side. For example, a TSH can be formed in the first region (e.g., Figure 2F).

[0065] In some embodiments, a contact structure (e.g., a TSC structure) is formed in the contact hole. Specifically, an insulating portion (also referred to as the sidewall portion) of the contact structure is formed on the side wall of the TSH, and a conductive portion of the contact structure is formed that fills the TSH and comes into contact with the first conductive structure.

[0066] In some embodiments, insulating material is deposited on the side walls and bottom of the TSH. The insulating material is then removed from the bottom of the TSH so that the insulating material on the side walls of the TSH forms the side wall portion of the TSC structure. Conductive material is then deposited to fill the TSH and form the conductive portion of the TSC structure.

[0067] In some embodiments, a second conductive structure is formed on the back side of the TSC structure. The second conductive structure is electrically coupled to the first conductive structure via the TSC structure. The second conductive structure can be configured to include, for example, a pad-out structure.

[0068] In some embodiments, a shielding structure is formed extending through the buffer layer, the replacement layer, and the first etch-stop layer. The shielding structure may include an insulating material.

[0069] In some embodiments, memory cells are formed on the front side of a first die. A peripheral network for the memory cells is formed on the front side of a second die. In one example, the first die and the second die are joined facing each other such that a first junction structure connected to a first conductive structure in the first die is joined to a second junction structure connected to the input / output circuits of the peripheral network in the second die.

[0070] Please note that the semiconductor device 100 can be used appropriately in a memory system.

[0071] Figure 4 shows a block diagram of a memory system device 400 according to some examples of the present disclosure. The memory system device 400 includes one or more semiconductor memory devices, such as those illustrated by semiconductor memory devices 411, 412, 413, and 414, each configured similarly to semiconductor device 100. In some examples, the memory system device 400 is a solid-state drive (SSD).

[0072] The memory system device 400 may include other appropriate components. For example, the memory system device 400 may include an interface 401 and a master controller 402 coupled together as shown in Figure 4. The memory system device 400 may include a bus 420 that couples the master controller 402 with semiconductor memory devices 411-414. In addition, the master controller 402 is connected to the semiconductor memory devices 411-414, respectively, as illustrated by control lines 421, 422, 423, and 424.

[0073] Interface 401 is mechanically and electrically configured to connect the memory system device 400 and the host device, and can be used to transfer data between the memory system device 400 and the host device.

[0074] The master controller 402 is configured to connect each of the semiconductor memory devices 411-414 to interface 401 for data transfer. For example, the master controller 402 is configured to provide enable / disable signals to each of the semiconductor memory devices 411-414 in order to activate one or more semiconductor memory devices 411-414 for data transfer.

[0075] The master controller 402 is responsible for completing various instructions within the memory system device 400. For example, the master controller 402 can perform bad block management, error checking and correction, garbage collection, and the like.

[0076] In some embodiments, the master controller 402 is implemented using a processor chip. In some examples, the master controller 402 is implemented using multiple microcontroller units (MCUs).

[0077] As used herein, “device” or “semiconductor device” generally refers to any suitable device, such as a memory circuit, a semiconductor chip (or die) on which a memory circuit is formed, a semiconductor wafer on which multiple semiconductor dies are formed, a stack of semiconductor chips, or a semiconductor package containing one or more semiconductor chips assembled on a package substrate.

[0078] As used herein, “substrate” generally refers to an object processed according to the present invention. A substrate may include any material portion or structure of a device, in particular a semiconductor or other electronic device, such as a semiconductor wafer, a base substrate structure such as a reticle, or a layer on or above a base substrate structure, such as a thin film. Thus, a substrate is not limited to any particular, patterned or unpatterned base structure, lower layer or upper layer, but is intended to include any such layer or base structure, as well as any combination of layers and / or base structures. While the description may refer to certain types of substrates, this is for illustrative purposes only.

[0079] The substrate can be any suitable substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, and / or a silicon-on-insulator (SOI) substrate. The substrate may contain a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. The group IV semiconductor may contain Si, Ge, or SiGe. The substrate may be a bulk wafer or an epitaxial layer.

[0080] The above outlines some features of embodiments so that those skilled in the art may better understand aspects of the disclosure. Those skilled in the art should recognize that they may immediately use the disclosure as a basis for designing or modifying other processes and structures to carry out the same objectives and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also acknowledge that such equivalent structures will not depart from the spirit and scope of the disclosure, and that they may make various changes, substitutions and modifications within this specification without departing from the spirit and scope of the disclosure. [Explanation of Symbols]

[0081] 100 Semiconductor Devices 100' Semiconductor devices 101 First stack 102 Second stack 103 The third stack 104 The fourth stack 107 Recess 108 The first area 109 Second Domain 111, 111a, 111b First etch stop layer 112 Second Etch Stop Layer 113 Conductive layer 114 Hard Mask Layer 115 Photoresist layer 116, 116a, 116b substitution layer 117, 117a, 117b First insulating layer 118 Photoresist layer 120 Through-Silicon Contact (TSC) Structure 121 Conductive parts 123 Side wall part 125 Shielding structure 126 Silicone Through Hole (TSH) 126' side wall 126'' bottom 127 Opening 131 First conductive structure 133 Second conductive structure 141 Word Line Layer 143 Second insulating layer 145 Gate Contact Structure 150-channel structure 151 Space 153 channel layer 155 Third insulating layer 171, 171a, 171n, 172, 172a, 172n metal layer 180 Joint interface 181, 181a, 181n Joint Structure 188 circuit boards 191, 191a, 191n metal layer 400 memory system devices 401 Interface 402 Master Controller 411, 412, 413, 414 Semiconductor memory devices 420 bus 421, 422, 423, 424 control lines D1 First Die D2 The second die

Claims

1. It is a semiconductor device, A memory stack including alternating gate layers and a first insulating layer in a first direction, In the first direction, the first layer on the memory stack, A second layer located above the first layer in the first direction, A first conductive layer located on the second layer in the first direction, A channel structure extending through the memory stack in the first direction, The first conductive layer, the second layer, and the second insulating layer extending through the first layer Equipped with, A semiconductor device in which the first layer comprises a conductive material and the second layer comprises a silicon-based insulating material.

2. The semiconductor device according to claim 1, wherein the first layer comprises doped silicon or a conductive metal, and the second layer comprises silicon oxide or silicon nitride.

3. The second layer and the first layer have different etching characteristics. The first conductive layer and the second layer have different etching characteristics. The semiconductor device according to claim 1.

4. A first conductive structure extending beyond the memory stack in the first direction, wherein the first conductive structure is spaced apart from the memory stack in a second direction, and the second direction is different from the first direction. The semiconductor device according to claim 1, further comprising the above.

5. A contact structure located on the first conductive structure and electrically connected to the first conductive structure, the contact structure extending through the first layer The semiconductor device according to claim 4, further comprising the above.

6. The semiconductor device according to claim 5, wherein the contact structure comprises a conductive portion and an insulating portion, and the insulating portion is configured to insulate the conductive portion from the first layer.

7. A semiconductor device, A memory stack including alternating gate layers and a first insulating layer in a first direction, In the first direction, the first layer on the memory stack, A second layer located above the first layer in the first direction, A first conductive layer located on the second layer in the first direction, A channel structure extending through the memory stack in the first direction, A first conductive structure extending beyond the memory stack in the first direction, wherein the first conductive structure is spaced apart from the memory stack in a second direction, and the second direction is different from the first direction, and the first conductive structure is spaced apart from the memory stack in the second direction. A contact structure located on the first conductive structure and electrically connected to the first conductive structure, the contact structure extending through the first layer Equipped with, The first layer comprises a conductive material, and the second layer comprises a silicon-based insulating material. The contact structure comprises a conductive portion and an insulating portion, and the insulating portion is configured to insulate the conductive portion from the first layer. A semiconductor device in which the first conductive structure extends further beyond the first layer and into the conductive portion of the contact structure.

8. A second conductive layer located on the first conductive layer or the first layer in the first direction and in contact with the first conductive layer or the first layer. The semiconductor device according to claim 5, further comprising the above.

9. The second insulating layer extends further through the second conductive layer, The semiconductor device according to claim 8, wherein the second conductive layer, the first conductive layer, the second layer, and the first layer each have a first portion in the second direction, the second conductive layer and the first layer each have a second portion in the second direction, the second insulating layer is located between the first portion and the second portion, and the contact structure extends through the second portion.

10. The semiconductor device according to claim 9, wherein the second conductive layer of the second portion extends to the same depth as the first conductive layer and the second layer of the first portion, and the contact structure extends to the second conductive layer of the second portion.

11. The semiconductor device according to claim 9, wherein the second conductive layer of the second portion is located on the first layer of the second portion in the first direction.

12. A semiconductor device, A memory stack including alternating gate layers and a first insulating layer in a first direction, In the first direction, the first layer on the memory stack, A second layer located above the first layer in the first direction, A first conductive layer located on the second layer in the first direction, A channel structure extending through the memory stack in the first direction and Equipped with, The first layer comprises a conductive material, and the second layer comprises a silicon-based insulating material. A semiconductor device in which the channel structure extends further through the first layer, the second layer, and into the first conductive layer, and the channel structure includes a channel layer electrically connected to the first layer.

13. A peripheral circuit connected to the memory stack, wherein the memory stack is located between the peripheral circuit and the first layer. The semiconductor device according to claim 1, further comprising the above.

14. The semiconductor device according to claim 8, wherein the material of the second conductive layer and the material of the first layer are different.

15. A third insulating layer located on the second conductive layer in the first direction. The semiconductor device according to claim 8, further comprising the above.

16. A second conductive structure located on the contact structure in the first direction and in contact with the contact structure. The semiconductor device according to claim 5, further comprising the above.

17. A memory system comprising a semiconductor device and a controller, wherein the controller is configured to control the operation of the semiconductor device, and the controller is connected to the semiconductor device. The aforementioned semiconductor device is A memory stack including alternating gate layers and a first insulating layer in a first direction, In the first direction, the first layer on the memory stack, A second layer located above the first layer in the first direction, A first conductive layer located on the second layer in the first direction, A channel structure extending through the memory stack in the first direction, The first conductive layer, the second layer, and the second insulating layer extending through the first layer Equipped with, A memory system in which the first layer comprises a conductive material and the second layer comprises a silicon-based insulating material.

18. The aforementioned semiconductor device is A first conductive structure extending beyond the memory stack in the first direction, wherein the first conductive structure is spaced apart from the memory stack in a second direction, and the second direction is different from the first direction, and the first conductive structure is spaced apart from the memory stack in the second direction. A contact structure extending through the first layer and electrically connected to the first conductive structure The memory system according to claim 17, further comprising the following:

19. The aforementioned semiconductor device is A second conductive layer located on the first conductive layer or the first layer in the first direction and in contact with the first conductive layer or the first layer. The memory system according to claim 17, further comprising the following:

20. A method for fabricating semiconductor devices, The steps include forming a memory stack including alternating gate layers and a first insulating layer in a first direction, The steps of forming a first conductive structure, which extends beyond the memory stack in the first direction, wherein the first conductive structure is spaced apart from the memory stack in a second direction, and the second direction is different from the first direction; The steps of forming a first layer on the memory stack in the first direction, The steps include forming a second layer on the first layer in the first direction, The steps include forming a first conductive layer on the second layer in the first direction, The steps of forming the first conductive layer, the second layer, and the second insulating layer extending through the first layer, The steps include forming a contact structure that extends through the first layer and is electrically connected to the first conductive structure, and Includes, A method comprising the first layer comprising a conductive material and the second layer comprising a silicon-based insulating material.

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