Semiconductor equipment

Abstract

The present invention provides a semiconductor device that can improve the electrical properties of a structure containing SiC. [Solution] The semiconductor device 1 includes a SiC semiconductor layer 2 having a first main surface 3 and a second main surface 4, a semiconductor element formed on the first main surface 3, a group of raised portions 12 including a plurality of raised portions 11 formed on the second main surface 4 at intervals along a first direction X and a second direction Y, and an electrode 10 directly connected to the group of raised portions 12 on the second main surface 4.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background Art]

[0002] Patent Document 1 discloses a semiconductor device including a SiC substrate, a Schottky barrier diode formed on a front surface of the SiC substrate, and an ohmic electrode layer formed on a back surface of the SiC substrate. [Prior Art Literature] [Patent Literature]

[0003] [Patent Document 1] Japanese Patent Laid-Open No. 2011-198780 [Summary of the Invention] [Problem to be Solved by the Invention]

[0004] An embodiment provides a semiconductor device capable of improving electrical characteristics in a structure containing SiC. [Means for Solving the Problem]

[0005] An embodiment provides a semiconductor device including: a SiC semiconductor layer having a first main surface on one side and a second main surface on the other side; a semiconductor element formed on the first main surface; a ridge group including a plurality of ridges formed spaced apart from each other on the second main surface, wherein some of the plurality of ridges have first portions overlapping each other when viewed in a first direction that is one of the planar directions of the second main surface; and an electrode formed on the second main surface and connected to the ridge group.

[0006] One embodiment provides a semiconductor device comprising: a SiC semiconductor layer having a first main surface on one side and a second main surface on the other side; a semiconductor element formed on the first main surface; a group of raised portions including a plurality of raised portions formed on the second main surface at intervals from each other along a first direction and a second direction intersecting the first direction; and an electrode directly connected to the group of raised portions on the second main surface.

[0007] These semiconductor devices allow for an increase in the contact area of ​​the electrodes with respect to the second main surface through the use of raised sections. This improves the electrical characteristics.

[0008] The aforementioned or any other purposes, features, and effects will be made clearer by the following description of embodiments with reference to the attached drawings. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a perspective view showing a semiconductor device according to a first embodiment of the present invention. [Figure 2] Figure 2 is a top view of the semiconductor device shown in Figure 1. [Figure 3] Figure 3 is a bottom view of the semiconductor device shown in Figure 1, and is a bottom view showing a first example of the raised portion group. [Figure 4A] Figure 4A shows an example of the second morphology of the raised area. [Figure 4B] Figure 4B shows an example of the third morphology of the raised area. [Figure 4C] Figure 4C shows an example of the fourth morphology of the raised area. [Figure 4D] Figure 4D shows an example of the fifth morphology of the raised area. [Figure 5] Figure 5 is a cross-sectional view along the VV line shown in Figure 2. [Figure 6A] Figure 6A is a top view showing a semiconductor wafer used in the manufacture of the semiconductor device shown in Figure 1. [Figure 6B] Figure 6B is a bottom view of the semiconductor wafer shown in Figure 6A, after the grinding and annealing processes. [Figure 7] Figure 7 is a flowchart illustrating an example of a manufacturing method for the semiconductor device shown in Figure 1. [Figure 8A] Figure 8A is a cross-sectional view showing the manufacturing method of the semiconductor device shown in Figure 1. [Figure 8B] Figure 8B is a cross-sectional view showing a process that follows Figure 8A. [Figure 8C] Figure 8C is a cross-sectional view showing a process after Figure 8B. [Figure 8D] Figure 8D is a cross-sectional view showing a process after Figure 8C. [Figure 8E] Figure 8E is a cross-sectional view showing a process after Figure 8D. [Figure 8F] Figure 8F is a cross-sectional view showing a process that follows Figure 8E. [Figure 8G] Figure 8G is a cross-sectional view showing a process after Figure 8F. [Figure 8H] Figure 8H is a cross-sectional view showing a process after Figure 8G. [Figure 8I] Figure 8I is a cross-sectional view showing a process after Figure 8H. [Figure 8J] Figure 8J is a cross-sectional view showing a process after Figure 8I. [Figure 8K] Figure 8K is a cross-sectional view showing a process after Figure 8J. [Figure 8L] Figure 8L is a cross-sectional view showing a process after Figure 8K. [Figure 8M] Figure 8M is a cross-sectional view showing a process after Figure 8L. [Figure 8N] Figure 8N is a cross-sectional view showing a process after Figure 8M. [Figure 8O] Figure 8O is a cross-sectional view showing a process after Figure 8N. [Figure 8P] Figure 8P is a cross-sectional view showing a process that follows Figure 8O. [Figure 8Q] Figure 8Q is a cross-sectional view showing a process after Figure 8P. [Figure 8R] Figure 8R is a cross-sectional view showing a process after Figure 8Q. [Figure 9]Figure 9 is a graph showing the relationship between resistance and the thickness of the metal layer. [Figure 10] Figure 10 is a graph showing the relationship between resistance value and the amount of overlap at the laser irradiation position. [Figure 11] Figure 11 is a bottom view corresponding to Figure 2, and is a bottom view showing a semiconductor device according to a second embodiment of the present invention. [Figure 12] Figure 12 is a cross-sectional view corresponding to Figure 5, and shows a semiconductor device according to a third embodiment of the present invention. [Figure 13] Figure 13 is a cross-sectional view corresponding to Figure 5, and shows a semiconductor device according to a fourth embodiment of the present invention. [Figure 14] Figure 14 is a top view showing a semiconductor device according to a fifth embodiment of the present invention, in which the structure above the first main surface of the SiC semiconductor layer has been removed. [Figure 15] Figure 15 is a cross-sectional view along the line XV-XV shown in Figure 14. [Figure 16] Figure 16 is a top view showing a semiconductor device according to the sixth embodiment of the present invention, in which the structure above the first main surface of the SiC semiconductor layer has been removed. [Figure 17] Figure 17 is a cross-sectional view along the line XVII-XVII shown in Figure 16. [Figure 18] Figure 18 is a top view showing a semiconductor device according to the seventh embodiment of the present invention. [Figure 19] Figure 19 is a bottom view of the semiconductor device shown in Figure 18. [Figure 20] Figure 20 is an enlarged view of region XX shown in Figure 18, with the structure above the first main surface of the SiC semiconductor layer removed. [Figure 21] Figure 21 is a cross-sectional view along the line XXI-XXI in Figure 20. [Figure 22] Figure 22 is a cross-sectional view along the line XXII-XXII in Figure 20. [Figure 23] Figure 23 is an enlarged view of region XXIII in Figure 22. [Figure 24]Figure 24 is a graph illustrating sheet resistance. [Figure 25] Figure 25 is an enlarged view of the region corresponding to Figure 20, and is an enlarged view for illustrating the structure of a semiconductor device according to the eighth embodiment of the present invention. [Figure 26] Figure 26 is a cross-sectional view along the line XXVI-XXVI shown in Figure 25. [Figure 27] Figure 27 is a cross-sectional view of the region corresponding to Figure 21, and is a cross-sectional view illustrating the structure of a semiconductor device according to the ninth embodiment of the present invention. [Figure 28] Figure 28 is an enlarged view of the region corresponding to Figure 20, and is an enlarged view for illustrating the structure of a semiconductor device according to the 10th embodiment of the present invention. [Figure 29] Figure 29 is a cross-sectional view of the region corresponding to Figure 21, and is a plan view illustrating the structure of a semiconductor device according to the 11th embodiment of the present invention. [Modes for carrying out the invention]

[0010] Figure 1 is a perspective view showing a semiconductor device 1 according to a first embodiment of the present invention. Figure 2 is a top view of the semiconductor device 1 shown in Figure 1. Figure 3 is a bottom view of the semiconductor device 1 shown in Figure 1, and is a bottom view showing a first embodiment example of the raised portion group 12.

[0011] Referring to Figure 1, the semiconductor device 1 has a SiC semiconductor layer 2 containing a SiC (silicon carbide) single crystal. The SiC semiconductor layer 2 may also contain a 4H-SiC single crystal.

[0012] The SiC semiconductor layer 2 has an off-angle that is tilted at an angle of no more than 10° with respect to the [11-20] direction from the (0001) plane. More specifically, the off-angle is between 0° and 4° (for example, 2° or 4°). The off-angle may be greater than 0° and less than 4°. Typically, the off-angle is set to 2° or 4°, more specifically, in the range of 2° ± 10% or 4° ± 10%.

[0013] The SiC semiconductor layer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and sides 5A, 5B, 5C, and 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a rectangular shape when viewed in a plan view from the direction of their normals (hereinafter simply referred to as "plan view").

[0014] Side 5A faces side 5D. Side 5B faces side 5C. The four sides 5A to 5D each extend planarly along the normal direction of the first main surface 3 and the second main surface 4. The lengths of sides 5A to 5D may be between 1 mm and 10 mm (for example, between 2 mm and 5 mm).

[0015] Referring to Figures 1 and 2, an insulating layer 6, an electrode 7, an insulating layer 8, and a resin layer 9 are formed on the first main surface 3. An electrode 10 is formed on the second main surface 4. The structures of the insulating layer 6, electrode 7, insulating layer 8, resin layer 9, and electrode 10 will be described later.

[0016] Referring to Figure 3 and its enlarged view, the second main surface 4 has a group of raised areas 12, which includes a plurality of raised areas 11. The plurality of raised areas 11 are portions that are raised on the second main surface 4 along the direction normal to the second main surface 4.

[0017] The multiple raised portions 11 are formed spaced apart from each other along an arbitrary first direction X and a second direction Y that intersects the first direction X. The first direction X is one of the plane directions of the first main surface 3 of the SiC semiconductor layer 2.

[0018] In this configuration, the first direction X is set parallel to the sides 5B and 5D. More specifically, the second direction Y is perpendicular to the first direction X. In other words, in this configuration, the second direction Y is set parallel to the sides 5A and 5C.

[0019] The raised portion group 12 has a first portion 17 in which some of the raised portions 11 overlap with the first direction X in a first view from the first direction X. The raised portion group 12 has a second portion 18 in which some of the raised portions 11 are formed spaced apart from the first portion 17 and overlap with the first direction X in a first view.

[0020] The multiple raised portions 11 are formed continuously along the first direction X. More specifically, the multiple raised portions 11 have a dotted pattern, being spaced apart along the first direction X and the second direction Y.

[0021] The multiple raised portions 11 are formed continuously along the first direction X while maintaining this dotted pattern. In this configuration, the multiple raised portions 11 are formed from the periphery of one side surface 5A to the periphery of the other side surface 5C in a plan view.

[0022] The distances between the multiple raised portions 11 formed at intervals in the first direction X in the raised portion group 12 may be different from each other. The distances between the multiple raised portions 11 formed at intervals in the second direction Y in the raised portion group 12 may also be different from each other.

[0023] The multiple raised portions 11 may each be formed with non-uniform shapes, sizes, and thicknesses. The thickness of a raised portion 11 is the distance from the base to the top (tip) of the raised portion 11 with respect to the direction normal to the second main surface 4.

[0024] The multiple raised portions 11 may each have a size greater than 0 μm and less than or equal to 10 μm in a plan view. The thickness of each raised portion 11 may be greater than 0 μm and less than or equal to 2 μm, 2 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, or 8 μm to 10 μm.

[0025] The thickness of each raised portion 11 may be greater than 0 nm and less than or equal to 500 nm. The thickness of each raised portion 11 may be greater than 0 nm and greater than 1 nm, greater than or equal to 50 nm, greater than or equal to 50 nm, greater than or equal to 100 nm, greater than or equal to 100 nm, greater than or equal to 200 nm, greater than or equal to 200 nm, greater than or equal to 3400 nm, or greater than or equal to 500 nm.

[0026] The raised portion group 12 is formed on the second main surface 4 in an area narrower than the width of the side surfaces 5A to 5D (in this embodiment, side surfaces 5A and 5C). The raised portion group 12 may also be formed in an area of ​​1 / 1000 to 1 / 5 of the width of the side surfaces 5A to 5D (in this embodiment, side surfaces 5A and 5C).

[0027] The raised portion group 12 may be formed in a range of 1 / 1000 to 1 / 500, 1 / 500 to 1 / 100, 1 / 100 to 1 / 50, 1 / 50 to 1 / 100, or 1 / 10 to 1 / 50 of the width of the side surfaces 5A to 5D.

[0028] The raised portion group 12 may be formed in a range of 1 / 200 to 1 / 10 of the width of the side surfaces 5A to 5D (in this embodiment, side surfaces 5A and 5C). The raised portion group 12 may be formed in a range of 10 μm to 200 μm with respect to the second direction Y.

[0029] The raised portion group 12 may be formed in the range of 10 μm to 50 μm, 50 μm to 100 μm, 100 μm to 150 μm, or 150 μm to 200 μm with respect to the second direction Y. The raised portion group 12 may be formed in the range of 50 μm to 150 μm, or 80 μm to 120 μm with respect to the second direction Y.

[0030] The raised portion group 12 has a layout in which multiple raised portions 11 overlap in the first direction X when viewed from the first direction X. The raised portion group 12 forms a raised portion group region 13 that extends in a band shape along the first direction X, due to the aggregate pattern of multiple raised portions 11 that are continuously scattered along the first direction X.

[0031] In other words, the raised portion group region 13 includes a plurality of raised portions 11 (raised portion group 12) formed in a band-shaped region extending along the first direction X on the second main surface 4. Multiple raised portion groups 12 (raised portion group region 13) having this configuration are formed on the second main surface 4 at intervals along the second direction Y.

[0032] In other words, the scattered pattern of multiple raised areas 11 is formed intermittently in a second-direction view as seen from a second-direction Y. The distance between multiple groups of raised areas 12 may be between 1% and 25% of the area in which the groups of raised areas 12 are formed. The distance between multiple groups of raised areas 12 may be between 1% and 5%, 5% and 10%, 10% and 15%, 15% and 20%, or 20% and 25% of the area in which the groups of raised areas 12 are formed.

[0033] With respect to the second direction Y, the distance between multiple adjacent raised areas 12 may be greater than 0 μm and less than or equal to 100 μm. The distance between multiple raised areas 12 may be greater than 0 μm and less than or equal to 20 μm, 20 μm to 40 μm, 40 μm to 60 μm, 60 μm to 80 μm, or 80 μm to 100 μm. The distance between multiple raised areas 12 may be greater than or equal to 5 μm and less than or equal to 50 μm.

[0034] The first direction X may be set in the [11-20] direction, and the second direction Y may be set in the [1-100] direction. In other words, the raised portion group 12 may form a band-shaped raised portion group region 13 extending substantially parallel to or parallel to the [11-20] direction, and multiple such regions may be formed at intervals along the [1-100] direction.

[0035] The first direction X may be set in the [1-100] direction, and the second direction Y may be set in the [11-20] direction. In other words, the raised portion group 12 may form a band-shaped raised portion group region 13 extending substantially parallel or parallel to the [1-100] direction, and multiple such regions may be formed at intervals along the [11-20] direction.

[0036] In the second main surface 4, a space 14 is defined in the region between groups of raised portions 12 that are adjacent to each other in the second direction Y. The space 14 does not have a dotted pattern containing multiple raised portions 11.

[0037] Space 14 is divided into strips extending parallel to the first direction X by adjacent groups of raised areas 12 (regions of raised areas 13). As a result, a stripe pattern is formed on the second main surface 4, which includes groups of raised areas 12 and spaces 14 that are alternately formed along the second direction Y.

[0038] Multiple grooves 16 are formed on the second main surface 4. In Figure 3 and its enlarged view, the grooves 16 are indicated by lines. The grooves 16 are formed in the raised section group 12 and the space 14.

[0039] Multiple grooves 16 include grinding marks resulting from grinding the second wafer main surface 43 of the SiC semiconductor wafer 41, which will be described later. Therefore, the direction in which the grooves 16 extend differs depending on the position from which the SiC semiconductor layer 2 is cut from the SiC semiconductor wafer 41.

[0040] The groove 16 may extend substantially parallel to or parallel to each group of raised sections 12. The groove 16 may include portions that intersect with the group of raised sections 12. The groove 16 may extend along directions that intersect or are perpendicular to each group of raised sections 12. The groove 16 may extend in a straight line or in an arc shape.

[0041] Some of the multiple raised portions 11 included in each group of raised portions 12 are formed at intervals along the groove 16. In other words, each group of raised portions 12 includes a third portion 19 in which some of the multiple raised portions 11 are formed at intervals along the groove 16 when viewed from above.

[0042] Each group of raised portions 12 is formed, for example, by an annealing process. Multiple raised portions 11 may be laser processing marks formed by a laser annealing process.

[0043] Multiple raised portions 11 (the third portion 19 of the raised portion group 12) along the groove 16 may be formed by an annealing treatment method on the second main surface 4 (the second wafer main surface 43 of the SiC semiconductor wafer 41) that is demarcated by the groove 16.

[0044] Each raised section 12 can take on various forms by adjusting the annealing conditions (in this case, laser annealing conditions), as shown in Figures 4A to 4D.

[0045] Figure 4A shows an example of the second form of each of the ridge groups 12.

[0046] As shown in Figure 4A, the group of raised portions 12 may include convex, curved raised portions 11 that extend along a first direction X in a plan view and protrude along a second direction Y (towards the side surface 5B in Figure 4A). The raised portions 11 may be formed by a plurality of overlapping raised portions 11.

[0047] The distance between the two furthest points in the raised portion 11 may be between 1 μm and 200 μm (approximately 50 μm in this embodiment). With respect to the first direction X, the distance between multiple adjacent raised portions 11 is set to a value of 10% or more of the size of the raised portion 11. Multiple raised portions 11 are formed by shifting the laser irradiation positions of adjacent portions in the first direction X.

[0048] Figure 4B shows an example of the third morphology of the raised area group 12.

[0049] As shown in Figure 4B, the group of raised portions 12 may include a concave curved raised portion 11 that extends along the second direction Y in a plan view and is recessed along the first direction X. The raised portion 11 may be formed by a plurality of overlapping raised portions 11.

[0050] The distance between the two furthest points in each raised portion 11 may be between 1 μm and 200 μm (approximately 50 μm in this example). Multiple raised portions 11 are formed by overlapping the adjacent laser irradiation positions by 50% to 70%.

[0051] Figure 4C shows an example of the fourth morphology of the raised section group 12.

[0052] As shown in Figure 4C, the group of raised portions 12 may include line-shaped raised portions 11 that extend along the second direction Y in a plan view and are recessed along the first direction X. The raised portions 11 may have projections that protrude along the first direction X. The raised portions 11 may be formed by a plurality of overlapping raised portions 11.

[0053] The distance between the two furthest points in the raised portion 11 may be between 1 μm and 200 μm (approximately 50 μm in this example). Multiple raised portions 11 are formed by overlapping the laser irradiation positions of adjacent portions by 70% to 90%.

[0054] Figure 4D shows an example of the fifth morphology of the raised area group 12.

[0055] As shown in Figure 4D, the group of raised parts 12 may have a layout in which rows of raised parts, each containing a plurality of raised parts 11 arranged at intervals along the second direction Y, are formed at intervals along the first direction X.

[0056] The distance between the two furthest points in the raised portion 11 may be between 1 μm and 200 μm (approximately 5 μm in this example). Multiple raised portions 11 are formed by overlapping the laser irradiation positions of adjacent portions by 90% or more and less than 100%.

[0057] Figure 5 is a cross-sectional view along the VV line shown in Figure 3.

[0058] Referring to Figure 5, in this configuration, the SiC semiconductor layer 2 is n+ The structure has a laminated form including an n-type SiC semiconductor substrate 21 and an n-type SiC epitaxial layer 22. The SiC semiconductor substrate 21 forms a second main surface 4. The SiC epitaxial layer 22 forms a first main surface 3. The SiC semiconductor substrate 21 and the SiC epitaxial layer 22 form side surfaces 5A to 5D.

[0059] The thickness of the SiC semiconductor substrate 21 may be 5 μm or more and 400 μm or less. The thickness of the SiC semiconductor substrate 21 may be 5 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, 250 μm or more and 300 μm or less, 300 μm or more and 350 μm or less, or 350 μm or more and 400 μm or less.

[0060] The thickness of the SiC semiconductor substrate 21 is preferably 80 μm to 200 μm (for example, about 150 μm). By reducing the thickness of the SiC semiconductor substrate 21, the resistance can be reduced by shortening the current path.

[0061] The SiC epitaxial layer 22 forms part of the first main surface 3 and the side surfaces 5A to 5D. The thickness of the SiC epitaxial layer 22 may be between 1 μm and 100 μm.

[0062] The thickness of the SiC epitaxial layer 22 may be 1 μm to 25 μm, 25 μm to 50 μm, 50 μm to 75 μm, or 75 μm to 100 μm. Preferably, the thickness of the SiC epitaxial layer 22 is 5 μm to 15 μm (for example, about 10 μm).

[0063] The n-type impurity concentration in the SiC epitaxial layer 22 is less than or equal to the n-type impurity concentration in the SiC semiconductor substrate 21. The n-type impurity concentration in the SiC semiconductor substrate 21 is 1.0 × 10⁻⁶. 18 cm -3 The above 1.0 × 10 21 cm -3may be as follows. The n-type impurity concentration of the SiC epitaxial layer 22 is 1.0×10 15 cm -3 or more and 1.0×10 18 cm -3 or less.

[0064] Referring to FIG. 5 and the enlarged view of FIG. 5, the aforementioned raised portion group 12 and the groove 16 are formed in the SiC semiconductor substrate 21. A modified layer 4a obtained by modifying a part of SiC in the SiC semiconductor layer 2 (SiC semiconductor substrate 21) to have other properties is formed on the surface layer portion of the second main surface 4. The modified layer 4a is formed by an annealing treatment method for the second main surface 4.

[0065] The modified layer 4a contains Si atoms and C atoms. More specifically, the modified layer 4a has a carbon density lower than that of a region outside the modified layer 4a in the SiC semiconductor layer 2 (SiC semiconductor substrate 21).

[0066] The modified layer 4a has a silicon density exceeding the carbon density. In other words, the modified layer 4a includes a Si modified layer obtained by modifying SiC of the SiC semiconductor layer 2 (SiC semiconductor substrate 21) into Si. The modified layer 4a may be an Si amorphous layer.

[0067] The modified layer 4a may contain lattice defects resulting from modification of SiC. In other words, the modified layer 4a may include a lattice defect region having defect levels introduced due to the modification of SiC.

[0068] In this embodiment, the modified layer 4a is formed in a region along the raised portion group 12 in the surface layer portion of the second main surface 4. In each raised portion group 12, the plurality of raised portions 11 are formed by the modified layer 4a. In other words, the plurality of raised portions 11 include the modified layer 4a.

[0069] In this embodiment, the modified layer 4a is also formed in the space 14. The modified layer 4a extends from the raised portion group 12 to the space 14. In other words, the annealing treatment method for the second main surface 4 also extends to the space 14.

[0070] In the modified layer 4a, the thickness of the portion along the raised portion group 12 is greater than or equal to the thickness of the portion along the space 14 in the modified layer 4a, due to the presence of the raised portion 11. More specifically, the thickness of the portion along the raised portion group 12 in the modified layer 4a is greater than the thickness of the portion along the space 14 in the modified layer 4a.

[0071] The thickness of the modified layer 4a may be between 1 nm and 1000 nm. The thickness Ta of the region of the modified layer 4a that forms the raised portion 11 may be between 50 nm and 1000 nm. The thickness Tb of the region of the modified layer 4a outside the raised portion 11 may be between 1 nm and 300 nm.

[0072] The thickness Ta may be 50 nm to 100 nm, 100 nm to 200 nm, 200 nm to 300 nm, 300 nm to 400 nm, 400 nm to 500 nm, 500 nm to 600 nm, 600 nm to 700 nm, 700 nm to 800 nm, 800 nm to 900 nm, or 900 nm to 1000 nm.

[0073] The thickness Tb may be 1 nm to 10 nm, 10 nm to 50 nm, 50 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, or 250 nm to 300 nm.

[0074] The thickness Tb may be 1 / 2, 1 / 3, 1 / 4, 1 / 5, 1 / 6, 1 / 7, 1 / 8, 1 / 9, 1 / 10, 1 / 11, 1 / 12, 1 / 13, 1 / 14, 1 / 15, 1 / 16, 1 / 17, 1 / 18, 1 / 19, or 1 / 20 of the thickness Ta.

[0075] The resistance of the second main surface 4 when the group of raised parts 12 is absent is greater than the resistance of the second main surface 4 when the group of raised parts 12 is present. In other words, the multiple groups of raised parts 12 have an electrical characteristic of resistance less than or equal to the resistance of a single SiC crystal.

[0076] More specifically, the multiple raised portions 12 have a resistance value less than the resistance value of a single SiC crystal. Furthermore, the multiple raised portions 12 have a resistance value less than or equal to the resistance value of the space 14. More specifically, the multiple raised portions 12 have a resistance value less than the resistance value of the space 14.

[0077] The electrical resistance of the raised portion group 12 is reduced by the modified layer 4a. In other words, the resistance of the raised portion group 12 is less than or equal to the resistance of the SiC single crystal due to the modified layer 4a. The electrical resistance of the space 14 is also less than or equal to the resistance of the SiC single crystal due to the modified layer 4a.

[0078] The aforementioned electrode 10 is formed on the second main surface 4. The electrode 10 is directly connected to the second main surface 4. The electrode 10 covers the group of raised portions 12 on the second main surface 4. In this embodiment, the electrode 10 covers multiple groups of raised portions 12 collectively.

[0079] The electrode 10 is formed in a film-like manner, following the outer surface of the group of raised parts 12 (the outer surfaces of the multiple raised parts 11) and the inner surface of the groove 16. As a result, the portion of the outer surface of the electrode 10 that covers the group of raised parts 12 (the multiple raised parts 11) has a raised part 10a that is raised in a direction away from the second main surface 4. In addition, the portion of the outer surface of the electrode 10 that covers the groove 16 has a recessed portion 10b that is recessed toward the second main surface 4.

[0080] Electrode 10 forms ohmic contact with the second main surface 4. More specifically, electrode 10 forms ohmic contact with the group of raised portions 12. Even more specifically, electrode 10 forms ohmic contact with multiple groups of raised portions 12. In this embodiment, electrode 10 also forms ohmic contact with the space 14.

[0081] The electrode 10 has a laminated structure including a plurality of electrode layers stacked on the second main surface 4. In this embodiment, the electrode 10 has a four-layer structure including a Ti layer 31, a Ni layer 32, an Au layer 33, and an Ag layer 34 stacked in this order from the second main surface 4.

[0082] The Ti layer 31, Ni layer 32, Au layer 33, and Ag layer 34 are formed in a film-like manner, following the outer surface of the raised portion group 12 (the outer surface of the multiple raised portions 11) and the inner surface of the groove 16. The raised portion 10a and recessed portion 10b of the electrode 10 are formed on the outer surface of the Ag layer 34.

[0083] The Ti layer 31 is directly connected to the second main surface 4. The Ti layer 31 covers multiple groups of raised sections 12 collectively and forms ohmic contact with the second main surface 4. In this configuration, the Ti layer 31 also forms ohmic contact with the space 14.

[0084] The Ni layer 32 covers almost or entirely the Ti layer 31. The Au layer 33 covers almost or entirely the Ni layer 32. The Ag layer 34 covers almost or entirely the Au layer 33.

[0085] The thickness of the Ti layer 31 may be between 0.01 μm and 5 μm (for example, about 0.07 μm). The thickness of the Ni layer 32 may be between 0.1 μm and 40 μm (for example, about 1.2 μm).

[0086] The thickness of the Au layer 33 may be 0.1 μm or more and 40 μm or less (for example, about 0.07 μm). The thickness of the Ag layer 34 may be 0.1 μm or more and 40 μm or less (for example, about 0.3 μm). The electrode 10 may have a single-layer structure consisting of a Ti layer 31, a Ni layer 32, an Au layer 33, or an Ag layer 34.

[0087] Electrode 10 forms ohmic contact with the second main surface 4 without the need for a silicide layer, which is primarily composed of silicide. Electrode 10 also forms ohmic contact with the raised portion group 12 without the need for a silicide layer, which is primarily composed of silicide.

[0088] Electrode 10 forms ohmic contact with the second main surface 4 without the need for a carbon layer, which is primarily composed of carbon. Electrode 10 also forms ohmic contact with the raised portion group 12 without the need for a carbon layer, which is primarily composed of carbon.

[0089] Electrode 10 does not include any region in which a material mainly composed of silicide is formed in layers. Furthermore, electrode 10 does not include any region in which a material mainly composed of carbon is formed in layers.

[0090] The electrode 10 engages with the uneven surface defined by the group of raised parts 12 (multiple raised parts 11) and the multiple grooves 16. The contact area of ​​the electrode 10 with respect to the second main surface 4 is increased by the group of raised parts 12 (multiple raised parts 11). This increases the adhesion force of the electrode 10 to the second main surface 4. The contact area of ​​the electrode 10 with respect to the second main surface 4 is also increased by the multiple grooves 16.

[0091] An n-type diode region 23 is formed in the SiC epitaxial layer 22. A portion of the diode region 23 is exposed from the first main surface 3. In this configuration, the diode region 23 is formed using a portion of the SiC epitaxial layer 22.

[0092] The diode region 23 may be formed by introducing n-type impurities (donors) into the surface layer of the SiC epitaxial layer 22. In this case, the diode region 23 may have a higher n-type impurity concentration than the n-type impurity concentration of the SiC epitaxial layer 22.

[0093] The diode region 23 is formed in the central part of the first main surface 3 in a plan view. The diode region 23 is formed in a rectangular shape with four sides parallel to the sides 5A to 5D in a plan view. The diode region 23 may also be formed in a circular shape in a plan view.

[0094] In the surface layer of the SiC epitaxial layer 22, an impurity region 24 is formed around the diode region 23. The impurity region 24 is a region in which p-type impurities (acceptors) are introduced along the periphery of the diode region 23. The impurity region 24 has a higher p-type impurity concentration than the n-type impurity concentration of the SiC epitaxial layer 22.

[0095] In this configuration, the p-type impurities forming the impurity region 24 are not activated. The impurity region 24 is formed as a non-semiconductor region, not a p-type semiconductor region. The p-type impurities forming the impurity region 24 may be activated. In this case, the impurity region 24 becomes a p-type semiconductor region.

[0096] The impurity region 24 extends in a band-like shape along the periphery of the diode region 23. In this configuration, the impurity region 24 is formed in an endless (quadrilateral ring) shape surrounding the diode region 23. The impurity region 24 is also called the guard ring region. The inner periphery of the impurity region 24 defines the diode region 23.

[0097] The impurity region 24 may be exposed from the sides 5A to 5D. The impurity region 24 may be formed with gaps between it and the inner region from the sides 5A to 5D.

[0098] The aforementioned insulating layer 6 is formed on the first main surface 3. The insulating layer 6 may contain silicon oxide. The insulating layer 6 has an opening 25 that exposes the diode region 23. In this embodiment, the opening 25 also exposes the boundary between the diode region 23 and the impurity region 24. In a plan view, the opening 25 is formed in a rectangular shape with four sides parallel to the sides 5A to 5D.

[0099] On the first main surface 3, an electrode 7 is formed on the diode region 23. The electrode 7 forms a Schottky junction with the diode region 23. This forms a Schottky barrier diode D with electrode 7 as the anode and the diode region 23 as the cathode.

[0100] The peripheral edge of electrode 7 is formed with a gap extending inward from the sides 5A to 5D. The peripheral edge of electrode 7 may overlap with the impurity region 24 in a plan view. Electrode 7 is formed in a rectangular shape with four sides parallel to the sides 5A to 5D in a plan view.

[0101] The electrode 7 has a covering portion 26. The covering portion 26 extends from above the first main surface 3 onto the insulating layer 6 and covers a portion of the insulating layer 6. The width of the covering portion 26 may be greater than or equal to the line width of the raised portion group 12.

[0102] Electrode 7 comprises at least one of aluminum, copper, molybdenum, nickel, aluminum-copper alloy, aluminum-silicon alloy, and aluminum-silicon-copper alloy. In this embodiment, electrode 7 comprises an aluminum-copper alloy.

[0103] The aforementioned insulating layer 8 is formed on the insulating layer 6. In this embodiment, the insulating layer 8 contains silicon nitride. The insulating layer 8 may contain silicon oxide instead of or in addition to silicon nitride. The insulating layer 8 covers the electrode 7. The insulating layer 8 has a first opening 27 that exposes the electrode 7.

[0104] In this configuration, the first opening 27 covers the peripheral edge of the electrode 7, exposing the inner region of the electrode 7. In a plan view, the first opening 27 is formed in a rectangular shape with four sides parallel to the sides 5A to 5D.

[0105] The aforementioned resin layer 9 is formed on the insulating layer 8. In this embodiment, the resin layer 9 contains a photosensitive resin. The resin layer 9 may contain a negative-type or positive-type photosensitive resin.

[0106] In this embodiment, the resin layer 9 contains polybenzoxazole as an example of a positive-type photosensitive resin. The resin layer 9 may also contain polyimide as an example of a negative-type photosensitive resin.

[0107] The resin layer 9 is formed in a rectangular shape with four sides parallel to the sides 5A to 5D in a plan view. The peripheral edge of the resin layer 9 is formed with a gap inward from the sides 5A to 5D, exposing the first main surface 3. More specifically, the peripheral edge of the resin layer 9 exposes the insulating layer 8.

[0108] A second opening 28 is formed in the inner part of the resin layer 9. The second opening 28 communicates with the first opening 27 and exposes the electrode 7. The inner wall of the second opening 28 may be located outside the first opening 27. The inner wall of the second opening 28 may be located inside the first opening 27.

[0109] Figure 6A is a top view showing a SiC semiconductor wafer 41 used in the manufacture of the semiconductor device 1 shown in Figure 1. Figure 6B is a bottom view of the SiC semiconductor wafer 41 shown in Figure 6A, showing the state after grinding and annealing processes on the second wafer main surface 43 of the SiC semiconductor wafer 41.

[0110] Referring to Figures 6A and 6B, the SiC semiconductor wafer 41 is made of a disc-shaped plate-like SiC single crystal. The SiC semiconductor wafer 41 has a first wafer main surface 42 on one side, a second wafer main surface 43 on the other side, and a wafer side surface 44 connecting the first wafer main surface 42 and the second wafer main surface 43.

[0111] The SiC semiconductor wafer 41 may contain a 4H-SiC single crystal. The first wafer main surface 42 has an off-angle inclined at an angle of 10° or less with respect to the [11-20] direction from the (0001) plane. The off-angle may be 0° or more and 4° or less. The off-angle may be greater than 0° and less than 4°. Typically, the off-angle is set to 2° or 4°, more specifically in the range of 2°±10% or 4°±10%.

[0112] The SiC semiconductor wafer 41 includes one or more (one in this embodiment) orientation flats 45 formed on the wafer side surface 44. The orientation flats 45 are formed as an example of a marker indicating the crystal orientation. The orientation flats 45 include notches formed on the periphery of the SiC semiconductor wafer 41. In this embodiment, the orientation flats 45 extend linearly along the [11-20] direction.

[0113] The first wafer main surface 42 is an element formation surface on which semiconductor elements (Schottky barrier diodes D in this configuration) are formed. Multiple device formation regions 46, each corresponding to a semiconductor device 1, are set on the first wafer main surface 42.

[0114] In this embodiment, the multiple device formation regions 46 are arranged in a matrix along the [11-20] direction ([-1-120] direction) and the [1-100] direction ([-1100] direction).

[0115] Multiple device formation regions 46 are demarcated by a grid of dicing lines 47. The semiconductor device 1 is cut out by cutting the SiC semiconductor wafer 41 along the periphery (dicing lines 47) of the multiple device formation regions 46.

[0116] Referring to Figure 6B, after the grinding process and annealing treatment of the second wafer main surface 43, a plurality of raised areas 12 and a plurality of grinding marks 48 are formed on the second wafer main surface 43.

[0117] The multiple groups of raised sections 12 are formed in a stripe pattern that is substantially parallel or parallel to the orientation flat 45. The multiple groups of raised sections 12 may also be formed in a stripe pattern that intersects or is perpendicular to the orientation flat 45.

[0118] Multiple grinding marks 48 each extend in an arc shape from the center to the periphery of the SiC semiconductor wafer 41. The multiple grinding marks 48 generally include grinding marks 48 that intersect in the [11-20] direction and the [1-100] direction.

[0119] The multiple grinding marks 48 include grinding marks 48 that extend substantially parallel to or parallel to the [11-20] direction or the [1-100] direction in portions where the tangent of the arc is along the [11-20] direction or the [1-100] direction. The grooves 16 formed on the second main surface 4 of the SiC semiconductor layer 2 may be formed by a portion of the grinding marks 48.

[0120] Figure 7 is a flowchart illustrating an example of a manufacturing method for the semiconductor device 1 shown in Figure 1. Figures 8A to 8R are cross-sectional views showing the manufacturing method for the semiconductor device 1 shown in Figure 1. Figures 8A to 8R show only one device formation region 46.

[0121] Referring to Figure 8A, first, the aforementioned n + A SiC semiconductor wafer 41 of a specific type is prepared (step S1 in Figure 7). The SiC semiconductor wafer 41 will serve as the base for the SiC semiconductor substrate 21.

[0122] Next, referring to Figure 8B, an n-type SiC epitaxial layer 22 is formed on the first wafer main surface 42 (step S2 in Figure 7). The SiC epitaxial layer 22 is formed by growing SiC on the first wafer main surface 42 by an epitaxial growth method.

[0123] Next, referring to Figure 8C, the diode region 23 is set on the main surface of the SiC epitaxial layer 22. Then, the impurity region 24 is formed on the surface of the SiC epitaxial layer 22 so as to demarcate the diode region 23 (step S3 in Figure 7). In this step, p-type impurities are introduced into the surface of the SiC epitaxial layer 22 by ion implantation via an ion implantation mask 51.

[0124] Next, referring to Figure 8D, an insulating layer 6 is formed on the main surface of the SiC epitaxial layer 22 (step S4 in Figure 7). The insulating layer 6 may contain silicon oxide. The insulating layer 6 may be formed by a thermal oxidation treatment method or a CVD (Chemical Vapor Deposition) method.

[0125] Next, referring to Figure 8E, the unwanted portion of the insulating layer 6 is removed (step S5 in Figure 7). The unwanted portion of the insulating layer 6 may also be removed by an etching method (e.g., wet etching) through a mask 52 having a predetermined pattern. The mask 52 has openings 53 that expose the area in the insulating layer 6 where the openings 25 should be formed. This forms the openings 25 in the insulating layer 6.

[0126] Next, referring to Figure 8F, electrode 7 is formed on the main surface of the SiC epitaxial layer 22 (step S6 in Figure 7). Electrode 7 may contain an aluminum-copper alloy. Electrode 7 may be formed by sputtering or CVD.

[0127] Next, referring to Figure 8G, the unwanted portion of the electrode 7 is removed (step S7 in Figure 7). The unwanted portion of the electrode 7 may also be removed by an etching method (e.g., dry etching) through a mask 54 having a predetermined pattern. This patterns the electrode 7 into a predetermined shape.

[0128] Next, referring to Figure 8H, an insulating layer 8 is formed on the insulating layer 6 so as to cover the electrode 7 (step S8 in Figure 7). The insulating layer 8 contains silicon nitride. The insulating layer 8 may be formed by the CVD method.

[0129] Next, referring to Figure 8I, the unwanted portion of the insulating layer 8 is removed (step S9 in Figure 7). The unwanted portion of the insulating layer 8 may also be removed by an etching method (e.g., wet etching) through a mask 55 having a predetermined pattern. The mask 55 has an opening 56 that exposes the region in the insulating layer 8 where the first opening 27 is to be formed. This forms the first opening 27 in the insulating layer 8.

[0130] Next, referring to Figure 8J, the resin layer 9 is applied on top of the insulating layer 8 to cover the electrode 7 (step S12 in Figure 7). In this embodiment, the resin layer 9 contains polybenzoxazole as an example of a positive-type photosensitive resin.

[0131] Next, the resin layer 9 is selectively exposed and then developed (step S11 in Figure 7). This creates a second opening 28 communicating with the first opening 27 and a dicing opening 57 that exposes the dicing line 47 in the resin layer 9.

[0132] Next, referring to Figure 8K, the second wafer main surface 43 is ground (step S12 in Figure 7). In this step, the second wafer main surface 43 is ground using abrasive grains having a grit size of 500 or higher. Preferably, the grit size of the abrasive grains is between 1000 and 5000. As a result, multiple grinding marks 48 are formed on the second wafer main surface 43 (see also Figure 6B). At the same time that the second wafer main surface 43 is flattened, the SiC semiconductor wafer 41 is thinned.

[0133] Next, referring to Figure 8L, a metal layer 61 is formed on the second wafer main surface 43 (step S13 in Figure 7). In this embodiment, the metal layer 61 consists of a Ni layer. The Ni layer may be formed by sputtering. The thickness of the Ni layer may be between 100 Å and 1000 Å.

[0134] Next, referring to Figure 8M, an annealing process is performed on the main surface 43 of the second wafer (step S14 in Figure 7). In this step, a laser annealing process is performed as an example of an annealing process.

[0135] In the laser annealing process, pulsed laser light with a laser diameter φ of 50 μm to 200 μm (for example, around 100 μm) is used. The pulsed laser light is UV laser light with wavelengths in the ultraviolet region. The energy of the pulsed laser light is 1.0 J / cm². 2 More than 4.0J / cm 2 The following (for example, 3.0 J / cm²) 2 (To a certain extent) is also acceptable.

[0136] Pulsed laser light is injected into the main surface 43 of the second wafer through the metal layer 61. In parallel with the irradiation of the main surface 43 of the second wafer with pulsed laser light, the irradiation position of the pulsed laser light on the main surface 43 of the second wafer is moved along the orientation flat 45. One or more raised portions 11 are formed in the region of the main surface 43 of the second wafer where the pulsed laser light has been injected.

[0137] Furthermore, in the region of the second wafer main surface 43 where pulsed laser light is injected, a modified layer 4a is formed in which the SiC of the SiC semiconductor wafer 41 is modified to have other properties. More specifically, the SiC of the SiC semiconductor wafer 41 is modified to Si by the detachment and / or sublimation of C atoms from the SiC through heating.

[0138] This forms a modified layer 4a containing a Si modified layer. The modified layer 4a may also contain a silicon amorphous layer. The modified layer 4a may also contain C atoms. One or more raised portions 11 formed on the second wafer main surface 43 may be formed by this modified layer 4a. As a result, a group of raised portions 12, including multiple raised portions 11 and aligned with the orientation flat 45 ([11-20] direction), is formed on the second wafer main surface 43.

[0139] After one group of raised areas 12 (raised area region 13) is formed, the irradiation position of the pulsed laser light is moved in the [1-100] direction. Then, in parallel with the irradiation of the second wafer main surface 43 with the pulsed laser light, the irradiation position of the pulsed laser light on the second wafer main surface 43 is moved along the orientation flat 45.

[0140] As a result, another group of raised areas 12 extending substantially parallel to or parallel to one group of raised areas 12 is formed on the second wafer main surface 43. In the laser annealing process, this process is repeated until multiple groups of raised areas 12 are formed over substantially or entirely the second wafer main surface 43 (see also Figure 6B).

[0141] In this configuration, the metal layer 61 that has undergone laser annealing has a laminated structure including a carbon layer 62, a NiSi (nickel silicide) layer 63, and a Ni layer 64, which are stacked in this order from the second wafer main surface 43 side. In other words, the laser annealing method includes a step of reacting the metal layer 61 with the SiC semiconductor wafer 41 to silicide it. More specifically, the laser annealing method includes a step of forming the NiSi layer 63.

[0142] In the laser annealing process, in addition to the NiSi layer 63, a carbon layer 62 containing C atoms is formed as a byproduct within the metal layer 61. The carbon layer 62 is formed by the precipitation of C atoms that made up SiC.

[0143] In the metal layer 61, the carbon layer 62 and the NiSi layer 63 can act as delamination initiation points. In other words, the metal layer 61 can be used as the electrode 10 as is, but the metal layer 61 has problems with poor connection and increased resistance due to poor connection. Therefore, it is preferable to form a metal layer different from the metal layer 61 as the electrode 10.

[0144] The temperature applied to the metal layer 61 during the formation of the NiSi layer 63 is above the melting point of the electrode 7 (for example, above 1000°C). The laser annealing method allows for a localized increase in the temperature of the second wafer main surface 43, thereby suppressing the temperature rise of the electrode 7. Therefore, the melting of the electrode 7 can be appropriately suppressed.

[0145] Next, referring to Figure 8N, the metal layer 61 is removed. The metal layer 61 is removed until the main surface 43 of the second wafer is exposed.

[0146] In this process, first, the NiSi layer 63 and Ni layer 64 within the metal layer 61 are removed (step S15 in Figure 7). The NiSi layer 63 and Ni layer 64 may also be removed by wet etching.

[0147] Next, referring to Figure 8O, the carbon layer 62 within the metal layer 61 is removed (step S16 in Figure 7). The carbon layer 62 may also be removed by dry etching.

[0148] Next, referring to Figure 8P, the residues of the NiSi layer 63 and Ni layer 64 adhering to the second wafer main surface 43 are removed (step S17 in Figure 7). The NiSi layer 63 and Ni layer 64 may also be removed by wet etching.

[0149] Next, referring to Figure 8Q, the residue of the carbon layer 62 adhering to the second wafer main surface 43 is removed (step S18 in Figure 7). The carbon layer 62 may also be removed by dry etching. Next, the native oxide film is removed from the second wafer main surface 43 (step S19 in Figure 7). The native oxide film may also be removed by wet etching.

[0150] In this configuration, the process of removing the Ni-containing layers (NiSi layer 63 and Ni layer 64) and the carbon-containing layer (carbon layer 62) is repeated twice. This allows for proper removal of the metal layer 61. After the removal of the metal layer 61, the second wafer main surface 43, whose resistance has been reduced by laser annealing, is exposed.

[0151] Next, referring to Figure 8R, the electrode 10 is formed on the second wafer main surface 43 (step S20 in Figure 7). This step includes forming a Ti layer 31, a Ni layer 32, an Au layer 33, and an Ag layer 34 on the second wafer main surface 43 in that order. The Ti layer 31, Ni layer 32, Au layer 33, and Ag layer 34 may be formed by sputtering, respectively.

[0152] Of the electrodes 10, the Ti layer 31 is directly connected to the main surface 43 of the second wafer. The Ti layer 31 covers multiple groups of raised portions 12 collectively and forms ohmic contact between the Ti layer 31 and the multiple groups of raised portions 12 and between the Ti layer 31 and the multiple spaces 14.

[0153] Next, the SiC semiconductor wafer 41 is cut along the periphery (dicing line 47) of the multiple device formation regions 46 (step S21 in Figure 7). This cuts out multiple semiconductor devices 1 from the SiC semiconductor wafer 41. The semiconductor device 1 is manufactured through the process including the above.

[0154] Figure 9 is a graph showing the relationship between resistance and the thickness of the metal layer 61. In Figure 9, the vertical axis represents resistance (on-resistance) [Ω·cm]. 2 This represents [the thickness] of the metal layer 61. In Figure 9, the horizontal axis represents the thickness [Å] of the metal layer 61.

[0155] In Figure 9, "X" represents the overlap amount [μm] between adjacent laser irradiation positions with respect to the first direction X. In Figure 9, "Y" represents the distance [μm] between adjacent laser irradiation positions with respect to the second direction Y.

[0156] "+Y" means that adjacent laser irradiation positions are far apart with respect to the second direction Y. "-Y" means that adjacent laser irradiation positions overlap with respect to the second direction Y. The laser beam diameter φ is approximately 100 μm. The laser beam energy is measured while fixed at a predetermined value.

[0157] Figure 9 shows the first line A1, the second line B1, the third line C1, and the fourth line D1.

[0158] The first line A1 shows the relationship when (X, Y) = (90 μm, 50 μm). The second line B1 shows the relationship when (X, Y) = (65 μm, 50 μm). The third line C1 shows the relationship when (X, Y) = (85 μm, -10 μm). The fourth line D1 shows the relationship when (X, Y) = (80 μm, 15 μm).

[0159] Referring to the first to fourth broken lines A1 to D1, it was found that the resistance tends to increase as the thickness of the metal layer 61 decreases. This is thought to be because, when the thickness of the metal layer 61 is small, a portion of the metal layer 61 sublimes due to irradiation with pulsed laser light, and the annealing process is not properly carried out.

[0160] On the other hand, it was found that the resistance decreases when the thickness of the metal layer 61 increases to a certain extent. When the thickness of the metal layer 61 is 500 Å or more, the resistance is 2 Ω·cm, regardless of the amount of overlap at the irradiation position. 2 The result was as follows:

[0161] The results in Figure 9 show that the resistance value at the second main surface 4 depends on the thickness of the metal layer 61 formed during the manufacturing process. Furthermore, it was found that the resistance value can be optimized by adjusting the thickness of the metal layer 61 and the overlap amount of adjacent laser irradiation positions.

[0162] Figure 10 is a graph showing the relationship between resistance and the amount of overlap at the laser irradiation position. In Figure 10, the vertical axis represents resistance (on-resistance) [Ω·cm]. 2 This represents [the overlap amount [μm] of adjacent laser irradiation positions with respect to the first direction X.]. The thickness of the metal layer 61 is fixed to a predetermined value.

[0163] Figure 10 shows the first line A2, the second line B2, the third line C2, and the fourth line D2.

[0164] The first broken line A2 has a laser light energy of 1.5 J / cm². 2 This shows the relationship in the case where the laser light energy is 2.0 J / cm². The second broken line B2 represents the relationship when the laser light energy is 2.0 J / cm². 2 This shows the relationship in the case where the laser light energy is 2.5 J / cm². The third broken line C2 represents the relationship when the laser light energy is 2.5 J / cm². 2 This shows the relationship in the case where the laser light energy is 3.0 J / cm². The fourth piecewise curve D2 represents the relationship when the laser light energy is 3.0 J / cm². 2 This shows the relationship in that case.

[0165] Referring to the first to fourth broken lines A2 to D2, it was found that the resistance decreases as the energy of the laser light increases. Furthermore, even when the energy of the laser light is fixed, it was found that the resistance can be reduced by increasing the overlap amount of adjacent laser irradiation positions.

[0166] The results in Figure 10 show that the resistance value on the second main surface 4 depends on the energy of the laser light and the amount of overlap between adjacent laser irradiation positions. Furthermore, it was found that the resistance value can be optimized by adjusting these factors.

[0167] As described above, the semiconductor device 1 can increase the contact area of ​​the electrodes 10 with respect to the second main surface 4 by the raised portion group 12. This improves the electrical characteristics.

[0168] More specifically, the electrode 10 forms ohmic contact with the group of raised portions 12. This allows for good ohmic characteristics between the SiC semiconductor layer 2 and the electrode 10, thereby improving electrical properties.

[0169] Furthermore, in semiconductor device 1, the electrode 10 is directly connected to the second main surface 4. More specifically, the electrode 10 forms ohmic contact with the raised portion group 12 without the presence of a carbon layer. Also, the electrode 10 forms ohmic contact with the raised portion group 12 without the presence of a silicide layer.

[0170] Carbon layers and silicide layers are prone to delamination. Therefore, a structure in which the electrode 10 is directly connected to the second main surface 4 can effectively suppress connection problems and the increase in resistance caused by such connection problems.

[0171] Figure 11 is a bottom view corresponding to Figure 2, and shows a semiconductor device 71 according to a second embodiment of the present invention. In the following, structures corresponding to the structures described for semiconductor device 1 are given the same reference numerals and their descriptions are omitted.

[0172] Referring to Figure 11, the semiconductor device 71 has a plurality of raised portion groups 12, including a first raised portion group 12A and a second raised portion group 12B. The first raised portion group 12A includes a plurality of first raised portions 11A formed on the second main surface 4. The plurality of first raised portions 11A are portions that are raised on the second main surface 4 along the direction normal to the second main surface 4.

[0173] Multiple first raised portions 11A are formed spaced apart from each other along a first direction X and a second direction Y that intersects the first direction X. Some of the first raised portions 11A have a first portion 17A that overlaps with the first direction X in a first view as seen from the first direction X.

[0174] Furthermore, the first raised portion 11A is formed such that some of the first raised portions 11A are spaced apart from the first portion 17A, and it has a second portion 18A that overlaps with the first direction X when viewed in the first direction.

[0175] The multiple first raised portions 11A are formed continuously along the first direction X. More specifically, the multiple first raised portions 11A have a dotted pattern that is spaced apart along the first direction X and the second direction Y.

[0176] The multiple first raised portions 11A are formed continuously along the first direction X while maintaining this dotted pattern. In this embodiment, the dotted pattern of the multiple first raised portions 11A is formed from the periphery of one side surface 5A to the periphery of the other side surface 5C in a plan view.

[0177] The first group of raised areas 12A has a layout in which multiple raised areas 11 overlap in the first direction X when viewed from the first direction X. As a result, the first group of raised areas 12A forms a first group of raised areas region 13A that extends in a band shape along the first direction X, formed by a collection pattern of multiple raised areas 11 that are continuously scattered along the first direction X.

[0178] The second group of raised portions 12B includes a plurality of second raised portions 11B formed on the second main surface 4. The plurality of second raised portions 11B are portions that are raised on the second main surface 4 along the direction normal to the second main surface 4.

[0179] The multiple second raised portions 11B are formed at intervals from each other along the first direction X and the second direction Y which intersects the first direction X. The group of second raised portions 12B has a first portion 17B in which some of the multiple second raised portions 11B overlap with the second direction Y in a second-direction view as seen from the second direction Y.

[0180] Furthermore, the second raised portion group 12B is formed such that some of the second raised portions 11B are spaced apart from the first portion 17B, and has a second portion 18B that overlaps with the second direction Y when viewed in the second direction.

[0181] Multiple second raised portions 11B are formed continuously along the second direction Y. More specifically, the multiple second raised portions 11B have a dotted pattern that is spaced apart along the first direction X and the second direction Y.

[0182] The multiple second raised portions 11B are formed continuously along the second direction Y while maintaining this dotted pattern. In this embodiment, the dotted pattern of the multiple second raised portions 11B is formed from the periphery of one side surface 5B to the periphery of the other side surface 5D in a plan view.

[0183] The second raised portion group 12B has a layout in which multiple second raised portions 11B overlap in the second direction Y when viewed from the second direction Y. As a result, the second raised portion group 12B forms a second raised portion region 13B that extends in a band shape along the second direction Y, formed by a collection pattern of multiple second raised portions 11B that are continuously scattered along the second direction Y.

[0184] The second raised area group 12B (second raised area group region 13B) crosses the first raised area group 12A (first raised area group region 13A). As a result, an intersecting region 72 is formed on the second main surface 4. The intersecting region 72 includes the first raised area group 12A (first raised area group region 13A) and the second raised area group 12B (second raised area group region 13B), which intersect each other.

[0185] In this configuration, multiple first raised portions 12A are formed at intervals along the second direction Y on the second main surface 4. In other words, the scattered pattern of multiple first raised portions 11A is formed intermittently with respect to the second direction Y.

[0186] Furthermore, in this configuration, multiple second raised portions 12B are formed at intervals along the first direction X on the second main surface 4. In other words, the scattered pattern of multiple second raised portions 11B is formed intermittently with respect to the first direction X.

[0187] Therefore, in this configuration, the intersecting region 72 is formed in a matrix arrangement with spacing between them along the first direction X and the second direction Y. Furthermore, the space 14 is partitioned by the first group of raised parts 12A and the second group of raised parts 12B. The space 14 is formed in a matrix arrangement with spacing between them along the first direction X and the second direction Y.

[0188] In the intersection region 72, the multiple first raised portions 11A and the multiple second raised portions 11B may overlap each other. The thickness of the multiple first raised portions 11A and the multiple second raised portions 11B formed in the intersection region 72 may be greater than the thickness of the first raised portions 11A and the second raised portions 11B formed in the region outside the intersection region 72.

[0189] Furthermore, the number of first raised portions 11A and second raised portions 11B formed in the intersection region 72 may be greater than the number of first raised portions 11A and second raised portions 11B formed in the region outside the intersection region 72.

[0190] The first direction X may be set in the [11-20] direction, and the second direction Y may be set in the [1-100] direction. In other words, the first raised section group 12A (first raised section group region 13A) may be formed approximately parallel to or parallel to the [11-20] direction, and the second raised section group 12B (second raised section group region 13B) may be formed approximately parallel to or parallel to the [1-100] direction.

[0191] The first direction X may be set in the [1-100] direction, and the second direction Y may be set in the [11-20] direction. In other words, the first raised section group 12A (first raised section group region 13A) may be formed approximately parallel to or parallel to the [1-100] direction, and the second raised section group 12B (second raised section group region 13B) may be formed approximately parallel to or parallel to the [11-20] direction.

[0192] The first raised portion 11A and the first group of raised portions 12A correspond to the raised portion 11 and the group of raised portions 12 according to the first embodiment. The description of the raised portion 11 and the group of raised portions 12 according to the first embodiment shall apply mutatis mutandis to the description of the first raised portion 11A and the first group of raised portions 12A, and other specific descriptions of the first raised portion 11A and the first group of raised portions 12A shall be omitted.

[0193] The second raised portion 11B and the second group of raised portions 12B correspond to the raised portion 11 and the group of raised portions 12 according to the first embodiment. The description of the raised portion 11 and the group of raised portions 12 according to the first embodiment shall apply mutatis mutandis to the other description of the second raised portion 11B and the second group of raised portions 12B, and other specific descriptions of the second raised portion 11B and the second group of raised portions 12B shall be omitted.

[0194] In this embodiment, the electrode 10 covers the first group of raised parts 12A and the second group of raised parts 12B on the second main surface 4. In this embodiment, the electrode 10 covers multiple first group of raised parts 12A and multiple second group of raised parts 12B together.

[0195] The electrode 10 is formed in a film-like manner, following the outer surface of the first raised portion group 12A (outer surface of the first raised portion 11A), the outer surface of the second raised portion group 12B (outer surface of the second raised portion 11B), and the inner surface of the groove 16.

[0196] As a result, although not shown in the diagram, a raised portion 10a is formed on the outer surface of the electrode 10 in the portion that covers the outer surface of the first raised portion group 12A (the outer surface of the first raised portion 11A) and the outer surface of the second raised portion group 12B (the outer surface of the second raised portion 11B). In addition, a recessed portion 10b is formed on the outer surface of the electrode 10 in the portion that covers the groove 16.

[0197] Electrode 10 forms ohmic contact with the second main surface 4. More specifically, electrode 10 forms ohmic contact with the first raised portion group 12A and the second raised portion group 12B.

[0198] More specifically, the electrode 10 forms ohmic contact with a plurality of first raised portion groups 12A and a plurality of second raised portion groups 12B. In this embodiment, the electrode 10 also forms ohmic contact with the space 14.

[0199] The portion of the electrode 10 that covers the first group of raised parts 12A and the second group of raised parts 12B engages with the uneven portion demarcated by the multiple first group of raised parts 12A, the multiple second group of raised parts 12B, and the multiple grooves 16.

[0200] The contact area of ​​the electrode 10 with respect to the second main surface 4 is increased by the multiple first raised portion groups 12A and the multiple second raised portion groups 12B. The contact area of ​​the electrode 10 with respect to the second main surface 4 is also increased by the multiple grooves 16. As a result, the adhesion force of the electrode 10 with respect to the second main surface 4 is enhanced.

[0201] A semiconductor device 71 with such a structure is manufactured by performing the following steps in the process shown in Figure 8M (step S14 in Figure 7).

[0202] First, a plurality of first raised areas 12A are formed by a laser annealing process along a direction that is approximately parallel to or perpendicular to the orientation flat 45. Next, a plurality of second raised areas 12B are formed by a laser annealing process along a direction that intersects (orthogonal to) the orientation flat 45.

[0203] In this process, multiple first groups of raised portions 12A are formed in a direction intersecting (orthogonal to) the orientation flat 45, and multiple second groups of raised portions 12B may be formed approximately parallel to or parallel to the orientation flat 45. Subsequently, the semiconductor device 71 is manufactured through the processes shown in Figures 8N to 8R.

[0204] The first group of raised sections 12A and the second group of raised sections 12B may be formed in any order. Therefore, multiple first group of raised sections 12A may be formed after multiple second group of raised sections 12B have been formed. Furthermore, multiple first group of raised sections 12A and multiple second group of raised sections 12B may be formed alternately.

[0205] As described above, the semiconductor device 71 can also produce the same effects as those described for the semiconductor device 1.

[0206] Figure 12 is a cross-sectional view corresponding to Figure 5, and shows a semiconductor device 81 according to a third embodiment of the present invention. In the following, structures corresponding to the structures described for semiconductor device 1 are given the same reference numerals and their descriptions are omitted.

[0207] In the semiconductor device 81, the electrode 10 has a three-layer structure including a Ni layer 32, an Au layer 33, and an Ag layer 34 stacked in this order from the second main surface 4.

[0208] The Ni layer 32 is directly connected to the second main surface 4. The Ni layer 32 covers multiple groups of raised sections 12 collectively. The Ni layer 32 forms ohmic contact with the groups of raised sections 12 and with the space 14.

[0209] The Au layer 33 covers almost or entirely the Ni layer 32. The Ag layer 34 covers almost or entirely the Au layer 33. An electrode 10 with such a structure is formed by omitting the formation step of the Ti layer 31 in step S20 of Figure 7.

[0210] As described above, the semiconductor device 81 can achieve the same effects as those described for the semiconductor device 1. In the semiconductor device 81, the electrode 10 may have a single-layer structure consisting of a Ni layer 32.

[0211] Figure 13 is a cross-sectional view corresponding to Figure 5, and shows a semiconductor device 91 according to the fourth embodiment of the present invention. In the following, structures corresponding to the structures described for semiconductor device 1 are given the same reference numerals and their descriptions are omitted.

[0212] In the semiconductor device 91, the electrode 10 includes a metal layer 61, an Au layer 33, and an Ag layer 34. In this embodiment, the metal layer 61 has a laminated structure including a carbon layer 62, a NiSi layer 63, and a Ni layer 64 stacked in this order from the second main surface 4 side.

[0213] The metal layer 61 is connected to the second main surface 4. The metal layer 61 covers multiple groups of raised parts 12 collectively. The metal layer 61 forms ohmic contact with the groups of raised parts 12 and with the space 14. The Au layer 33 covers almost or entirely the entire area of ​​the metal layer 61. The Ag layer 34 covers almost or entirely the entire area of ​​the Au layer 33.

[0214] A semiconductor device 91 with this structure is formed by omitting the metal layer removal process (steps S15 to S19 in Figure 7) shown in Figures 8N to 8Q. In this semiconductor device 91, the Au layer 33 and Ag layer 34 are formed on the metal layer 61 in the process shown in Figure 8R.

[0215] As described above, although the connection strength of the electrode 10 cannot be increased to the same extent as that of the semiconductor device 1 because the electrode 10 includes a carbon layer 62 and a NiSi layer 63, it can achieve almost the same effects as those described for the semiconductor device 1. In the semiconductor device 91, the electrode 10 may have a laminated structure made of a metal layer 61.

[0216] Figure 14 is a top view showing a semiconductor device 92 according to a fifth embodiment of the present invention, with the structure above the first main surface 3 removed. Figure 15 is a cross-sectional view along the line XV-XV shown in Figure 14. Hereafter, structures corresponding to the structures described for semiconductor device 1 will be given the same reference numerals and their descriptions will be omitted.

[0217] Referring to Figures 14 and 15, the semiconductor device 92 has a JBS (Junction Barrier Schottky) structure 93 formed on the surface layer of the first main surface 3. More specifically, the JBS structure 93 includes an n-type diode region 23 and a p-type diode region 94. The diode region 94 forms a pn junction with the diode region 23.

[0218] In this embodiment, the multiple diode regions 94 are formed at intervals from each other on the surface of the diode region 23. Each of the multiple diode regions 94 is formed in a strip shape extending parallel to an arbitrary first direction X. The multiple diode regions 94 are formed at intervals along a second direction Y that intersects the first direction X.

[0219] As a result, the multiple diode regions 94 are arranged in a stripe pattern that sandwiches the diode region 23 in a plan view. Each of the multiple diode regions 94 forms a pn junction between itself and the corresponding diode region 23.

[0220] When the first direction X is set to the [11-20] direction, the multiple diode regions 94 may extend substantially parallel to or parallel to the [11-20] direction. When the first direction X is set to the [1-100] direction, the multiple diode regions 94 may extend substantially parallel to or parallel to the [1-100] direction.

[0221] In this configuration, the multiple diode regions 94 extend along the same direction as the multiple groups of raised parts 12. The multiple diode regions 94 may also extend along a direction that intersects (is perpendicular to) the multiple groups of raised parts 12.

[0222] Electrode 7 forms a Schottky junction with diode region 23 on the first main surface 3. This forms a Schottky barrier diode D with electrode 7 as the anode and diode region 23 as the cathode.

[0223] Electrode 7 forms ohmic contact with diode region 94 on the first main surface 3. As a result, a pn junction diode Dpn, with diode region 94 as the anode and diode region 23 as the cathode, is formed on the surface layer of the first main surface 3.

[0224] As described above, the semiconductor device 92 can achieve the same effects as those described for the semiconductor device 1. Furthermore, the semiconductor device 92 has a JBS structure 93 in the surface layer of the first main surface 3 that includes diode regions 23 and 94.

[0225] In the JBS structure 93, the depletion layer extends from the pn junction between the diode region 23 and the diode region 94. This relaxes the electric field of the Schottky junction formed between the electrode 7 and the diode region 23. As a result, leakage current can be reduced. The structures according to the first to fourth embodiments described above may be combined with the semiconductor device 92.

[0226] Figure 16 is a top view showing a semiconductor device 95 according to the sixth embodiment of the present invention, with the structure above the first main surface 3 removed. Figure 17 is a cross-sectional view along the line XVII-XVII shown in Figure 16. Hereafter, structures corresponding to the structures described for semiconductor device 1 will be given the same reference numerals and their descriptions will be omitted.

[0227] Referring to Figures 16 and 17, in the semiconductor device 95, the impurity region 24 includes a plurality (for example, 2 to 20) of impurity regions formed on the surface layer of the first main surface 3. In this embodiment, the impurity region 24 includes three impurity regions 24A, 24B, and 24C.

[0228] The impurity regions 24A to 24C are formed in this order, spaced apart, along the direction away from the diode region 23. The impurity regions 24A to 24C each extend in a band-like shape along the periphery of the diode region 23. The impurity regions 24A to 24C may each be formed in an endless (square ring) shape surrounding the diode region 23.

[0229] Of the impurity regions 24A to 24C, the innermost impurity region 24A may define the diode region 23. Impurity region 24B surrounds impurity region 24A. Impurity region 24C surrounds impurity region 24B.

[0230] As described above, the semiconductor device 95 can also achieve the same effects as those described for the semiconductor device 1. The structures according to the first to fifth embodiments described above may be combined with the semiconductor device 95.

[0231] Figure 18 is a top view showing a semiconductor device 101 according to the seventh embodiment of the present invention. Figure 19 is a bottom view of the semiconductor device 101 shown in Figure 18. Figure 20 is an enlarged view of region XX shown in Figure 18, with the structure above the first main surface 103 of the SiC semiconductor layer 102 removed. Figure 21 is a cross-sectional view along the line XXI-XXI in Figure 20. Figure 22 is a cross-sectional view along the line XXII-XXII in Figure 20. Figure 23 is an enlarged view of region XXIII in Figure 22.

[0232] Referring to Figures 18 to 23, the semiconductor device 101 has a SiC semiconductor layer 102 containing a SiC (silicon carbide) single crystal. The SiC semiconductor layer 102 may also contain a 4H-SiC single crystal.

[0233] A 4H-SiC single crystal has an off-angle that is tilted at an angle of no more than 10° from the

[0001] plane with respect to the [11-20] direction. The off-angle may be between 0° and 4°. The off-angle may be greater than 0° and less than 4°. Typically, the off-angle is set to 2° or 4°, more specifically in the range of 2°±10% or 4°±10%.

[0234] The SiC semiconductor layer 102 has a first main surface 103 on one side, a second main surface 104 on the other side, and side surfaces 105A, 105B, 105C, 105D connecting the first main surface 103 and the second main surface 104. The first main surface 103 and the second main surface 104 are formed in a square shape (rectangular shape in this embodiment) in a plan view viewed from their normal direction (hereinafter simply referred to as "plan view").

[0235] The side surface 105A faces the side surface 105C. The side surface 105B faces the side surface 105D. The four side surfaces 105A to 105D each extend planarly along the normal direction of the first main surface 103 and the second main surface 104. The length of each of the side surfaces 105A to 105D may be 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less).

[0236] The SiC semiconductor layer 102 includes an active region 106 and an outer region 107. The active region 106 is a region where a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed. The outer region 107 is a region outside the active region 106.

[0237] The active region 106 is formed in a central portion of the SiC semiconductor layer 102 with a space from the side surfaces 105A to 105D to an inner region in plan view. The active region 106 is formed in a square shape (rectangular shape in this embodiment) having four sides parallel to the four side surfaces 105A to 105D in plan view.

[0238] The outer region 107 is formed in a region between the side surfaces 105A to 105D and a peripheral edge of the active region 106. The outer region 107 is formed in an endless shape (square annular shape) surrounding the active region 106 in plan view.

[0239] A gate pad 108, gate fingers 109, and source pad 110 are formed on the first main surface 103. The gate pad 108, gate fingers 109, and source pad 110 may contain aluminum and / or copper.

[0240] The gate pad 108 is formed in a region along the side surface 105A in a plan view. The gate pad 108 is formed in a region along the central part of the side surface 105A in a plan view. The gate pad 108 may also be formed along a corner connecting any two of the four sides 105A to 105D in a plan view.

[0241] The gate pad 108 is formed in a rectangular shape in plan view. In plan view, the gate pad 108 is drawn out from the outer region 107 into the active region 106 and crosses the boundary between the outer region 107 and the active region 106.

[0242] The gate finger 109 includes an outer gate finger 109A and an inner gate finger 109B. The outer gate finger 109A extends from the gate pad 108 to the outer region 107. The outer gate finger 109A extends in a strip-like manner across the outer region 107.

[0243] In this embodiment, the outer gate finger 109A is formed along three sides 105A, 105B, and 105D of the SiC semiconductor layer 102, dividing the active region 106 from three directions.

[0244] The inner gate finger 109B is extended from the gate pad 108 into the active area 106. The inner gate finger 109B extends in a strip-like manner through the active area 106. The inner gate finger 109B extends from side 105B towards side 105D.

[0245] The source pad 110 is formed in the active region 106, spaced apart from the gate pads 108 and gate fingers 109. In a plan view, the source pad 110 covers the region demarcated by the gate pads 108 and gate fingers 109 and is formed in an inverted C shape.

[0246] A gate voltage is applied to the gate pad 108 and gate finger 109. The gate voltage may be between 10V and 50V (for example, around 30V). A source voltage is applied to the source pad 110. The source voltage may be a reference voltage (for example, GND voltage).

[0247] A resin layer 111 is formed on the first main surface 103. In Figure 18, the resin layer 111 is shown by hatching for clarity. The resin layer 111 covers the gate pad 108, gate finger 109, and source pad 110.

[0248] The resin layer 111 may contain a negative-type or positive-type photosensitive resin. In this embodiment, the resin layer 111 contains polybenzoxazole as an example of a positive-type photosensitive resin. The resin layer 111 may also contain polyimide as an example of a negative-type photosensitive resin.

[0249] The peripheral edge of the resin layer 111 is formed with a gap extending inward from the side surfaces 105A to 105D, exposing the first main surface 103. More specifically, the peripheral edge of the resin layer 111 exposes the interlayer insulating layer 161, which will be described later.

[0250] A gate pad opening 112 and a source pad opening 113 are formed in the inner part of the resin layer 111. The gate pad opening 112 exposes the gate pad 108. The source pad opening 113 exposes the source pad 110.

[0251] Referring to Figures 19 and 23, the second main surface 104 has a group of raised areas 115 including multiple raised areas 114, a space 116, and a groove 117. The group of raised areas 115 (multiple raised areas 114), the space 116, and the groove 117 each include areas facing the active area 106 and the outer area 107, respectively.

[0252] The raised portion group 115 (multiple raised portions 114), space 116, and groove 117 have a structure corresponding to the raised portion group 12 (multiple raised portions 11), space 14, and groove 16 according to the first embodiment (see also Figures 3 to 5, etc.).

[0253] The description of the raised portion group 12 (multiple raised portions 11), space 14, and groove 16 according to the first embodiment shall be applied mutatis mutandis to the description of the raised portion group 115, space 116, and groove 117 according to this embodiment, and other specific descriptions of the raised portion group 115 (multiple raised portions 114), space 116, and groove 117 shall be omitted.

[0254] The raised portion group 115, space 116, and groove 117 may have a structure corresponding to the raised portion group 12, space 14, and groove 16 of the semiconductor device 71 according to the second embodiment (see also Figure 11). In this case, the description of the raised portion group 12, space 14, and groove 16 according to the second embodiment shall apply mutatis mutandis to the description of the raised portion group 115, space 116, and groove 117 according to this embodiment.

[0255] Referring to Figures 20 to 22, the SiC semiconductor layer 102 in this configuration is n + The structure has a laminated form including an n-type SiC semiconductor substrate 121 and an n-type SiC epitaxial layer 122. The SiC semiconductor substrate 121 forms a second main surface 104. The SiC epitaxial layer 122 forms a first main surface 103.

[0256] The thickness of the SiC semiconductor substrate 121 may be not less than 5 µm and not more than 400 µm. The thickness of the SiC semiconductor substrate 121 may be not less than 5 µm and not more than 50 µm, not less than 50 µm and not more than 100 µm, not less than 100 µm and not more than 150 µm, not less than 150 µm and not more than 200 µm, not less than 200 µm and not more than 250 µm, not less than 250 µm and not more than 300 µm, not less than 300 µm and not more than 350 µm, or not less than 350 µm and not more than 400 µm.

[0257] The thickness of the SiC semiconductor substrate 121 is preferably not less than 80 µm and not more than 200 µm (for example, approximately 150 µm). Reducing the thickness of the SiC semiconductor substrate 121 makes it possible to reduce the resistance value by shortening the current path.

[0258] The thickness of the SiC epitaxial layer 122 may be not less than 1 µm and not more than 100 µm. The thickness of the SiC epitaxial layer 122 may be not less than 1 µm and not more than 25 µm, not less than 25 µm and not more than 50 µm, not less than 50 µm and not more than 75 µm, or not less than 75 µm and not more than 100 µm. The thickness of the SiC epitaxial layer 122 is preferably not less than 5 µm and not more than 15 µm (for example, approximately 10 µm).

[0259] The n-type impurity concentration of the SiC epitaxial layer 122 is not higher than the n-type impurity concentration of the SiC semiconductor substrate 121. The n-type impurity concentration of the SiC epitaxial layer 122 is lower than the n-type impurity concentration of the SiC semiconductor substrate 121.

[0260] The n-type impurity concentration of the SiC semiconductor substrate 121 is 1.0×10 18 cm -3 to 1.0×10 21 cm -3 , and may be equal to or less than that. The n-type impurity concentration of the SiC epitaxial layer 122 is 1.0×10 15 cm -3 to 1.0×10 18 cm -3 , and may be equal to or less than that.

[0261] In this embodiment, the SiC epitaxial layer 122 has multiple regions having different n-type impurity concentrations along the direction normal to the first main surface 103. More specifically, the SiC epitaxial layer 122 includes a high-concentration region 122a with a relatively high n-type impurity concentration, and a low-concentration region 122b with a lower n-type impurity concentration compared to the high-concentration region 122a.

[0262] The high-concentration region 122a is formed in the region on the side of the first main surface 103. The low-concentration region 122b is formed in the region on the side of the second main surface 104 relative to the high-concentration region 122a.

[0263] The n-type impurity concentration in the high-concentration region 122a is 1 × 10⁻⁶ 16 cm -3 The above 1 x 10 18 cm -3 The following may also apply: The n-type impurity concentration in the low-concentration region 122b is 1 × 10⁻⁶. 15 cm -3 The above 1 x 10 16 cm -3 The following is also acceptable.

[0264] The thickness of the high-concentration region 122a is less than or equal to the thickness of the low-concentration region 122b. More specifically, the thickness of the high-concentration region 122a is less than the thickness of the low-concentration region 122b. In other words, the thickness of the high-concentration region 122a is less than half the total thickness of the SiC epitaxial layer 122.

[0265] Referring to Figure 23, the group of raised portions 115 (multiple raised portions 114) and grooves 117 are formed in the SiC semiconductor substrate 121. A modified layer 104a is formed on the surface layer of the second main surface 104, in which a portion of the SiC in the SiC semiconductor layer 102 (SiC semiconductor substrate 121) has been modified to other properties. The modified layer 104a is formed by an annealing treatment method for the second main surface 104.

[0266] The modified layer 104a contains Si atoms and C atoms. More specifically, the modified layer 104a has a lower carbon density than the region outside the modified layer 104a in the SiC semiconductor layer 102 (SiC semiconductor substrate 121).

[0267] The modified layer 104a has a silicon density that exceeds the carbon density. In other words, the modified layer 104a includes a Si modified layer in which the SiC of the SiC semiconductor layer 102 (SiC semiconductor substrate 121) has been modified to Si. The Si modified layer may also be a Si amorphous layer.

[0268] The modified layer 104a may contain lattice defects resulting from the modification of SiC. In other words, the modified layer 104a may contain lattice defect regions having defect levels introduced as a result of the modification of SiC.

[0269] In this configuration, the modified layer 104a is formed in the region along the raised portion group 115 on the second main surface 104. As a result, multiple raised portions 114 in each raised portion group 115 are formed by the modified layer 104a.

[0270] In this configuration, the modified layer 104a is also formed in the space 116. The modified layer 104a extends from the raised portion group 115 to the space 116. In other words, the annealing treatment method for the second main surface 104 also extends to the space 116.

[0271] In the modified layer 104a, the thickness of the portion along the raised portion group 115 is greater than or equal to the thickness of the portion along the space 116 in the modified layer 104a, due to the presence of the raised portion 114. More specifically, the thickness of the portion along the raised portion group 115 in the modified layer 104a is greater than the thickness of the portion along the space 116 in the modified layer 104a.

[0272] The resistance value of the second main surface 104 when the raised portion group 115 is absent is greater than the resistance value of the second main surface 104 when the raised portion group 115 is present on the second main surface 104.

[0273] In other words, the multiple raised sections 115 have an electrical characteristic of having a resistance value less than or equal to the resistance value of a single SiC crystal. More specifically, the multiple raised sections 115 have a resistance value less than or equal to the resistance value of a single SiC crystal. Furthermore, the multiple raised sections 115 have a resistance value less than or equal to the resistance value of the space 116. More specifically, the multiple raised sections 115 have a resistance value less than the resistance value of the space 116.

[0274] The electrical resistance of the raised portion group 115 is reduced by the modified layer 104a. In other words, the resistance of the raised portion group 115 is less than or equal to the resistance of the SiC single crystal due to the modified layer 104a. The electrical resistance of the space 116 is also less than or equal to the resistance of the SiC single crystal due to the modified layer 104a.

[0275] A drain pad 123 is formed on the second main surface 104. The maximum voltage that can be applied between the source pad 110 and the drain pad 123 when the device is off may be between 1000V and 10000V.

[0276] Referring to Figure 23, the drain pad 123 is directly connected to the second main surface 104. The drain pad 123 covers the group of raised parts 115 on the second main surface 104. In this embodiment, the drain pad 123 covers multiple groups of raised parts 115 collectively.

[0277] The drain pad 123 is formed in a film-like manner, following the outer surface of the raised portion group 115 (the outer surfaces of the multiple raised portions 114) and the inner surface of the groove 117. As a result, the portion of the drain pad 123 that covers the outer surface of the raised portion group 115 (the outer surfaces of the multiple raised portions 114) has a raised portion 123a that is raised in a direction away from the second main surface 104. In addition, the portion of the drain pad 123 that covers the groove 117 has a recessed portion 123b that is recessed toward the second main surface 104.

[0278] The drain pad 123 forms ohmic contact with the second main surface 104. More specifically, the drain pad 123 forms ohmic contact with the group of raised portions 115.

[0279] More specifically, the drain pad 123 forms ohmic contact with the group of raised portions 115. In this embodiment, the drain pad 123 also forms ohmic contact with the space 116.

[0280] The drain pad 123 has a laminated structure including a plurality of electrode layers stacked on the second main surface 104. In this embodiment, the drain pad 123 has a four-layer structure including a Ti layer 124, a Ni layer 125, an Au layer 126, and an Ag layer 127, stacked in this order from the second main surface 104.

[0281] The Ti layer 124, Ni layer 125, Au layer 126, and Ag layer 127 are formed in a film-like manner, following the outer surface of the raised portion group 115 (the outer surface of the multiple raised portions 114) and the inner surface of the groove 117. The raised portion 123a and recess portion 123b of the drain pad 123 are formed on the outer surface of the Ag layer 127.

[0282] The Ti layer 124 is directly connected to the second main surface 104. The Ti layer 124 covers multiple groups of raised portions 115 collectively and forms ohmic contact with the second main surface 104. In this configuration, the Ti layer 124 also forms ohmic contact with the space 116.

[0283] The Ni layer 125 covers almost or entirely the Ti layer 124. The Au layer 126 covers almost or entirely the Ni layer 125. The Ag layer 127 covers almost or entirely the Au layer 126.

[0284] The thickness of the Ti layer 124 may be between 0.01 μm and 5 μm (for example, about 0.07 μm). The thickness of the Ni layer 125 may be between 0.1 μm and 40 μm (for example, about 1.2 μm).

[0285] The thickness of the Au layer 126 may be 0.1 μm or more and 40 μm or less (for example, about 0.07 μm). The thickness of the Ag layer 127 may be 0.1 μm or more and 40 μm or less (for example, about 0.3 μm). The drain pad 123 may have a single-layer structure consisting of a Ti layer 124, a Ni layer 125, an Au layer 126, or an Ag layer 127.

[0286] The drain pad 123 forms ohmic contact with the second main surface 104 without the need for a silicide layer, which is primarily composed of silicide. The drain pad 123 also forms ohmic contact with each group of raised sections 115 without the need for a silicide layer, which is primarily composed of silicide.

[0287] The drain pad 123 forms ohmic contact with the second main surface 104 without the need for a carbon layer, which is primarily composed of carbon. The drain pad 123 also forms ohmic contact with each group of raised portions 115 without the need for a carbon layer, which is primarily composed of carbon.

[0288] The drain pad 123 does not include any region in which a material mainly composed of silicide is formed in layers. Furthermore, the drain pad 123 does not include any region in which a material mainly composed of carbon is formed in layers.

[0289] The drain pad 123 may have a structure similar to that of the electrode 10 according to the third embodiment described above. The drain pad 123 may have a structure similar to that of the electrode 10 according to the fourth embodiment described above.

[0290] The SiC semiconductor substrate 121 is formed as the drain region 128 of the MISFET. The SiC epitaxial layer 122 is formed as the drift region 129 of the MISFET.

[0291] In the active region 106, a p-type body region 131 is formed on the surface of the first main surface 103. The p-type impurity concentration in the body region 131 is 1 × 10⁻⁶.17 cm -3 The above 1 x 10 20 cm -3 The following may also apply. This body region 131 defines the active region 106.

[0292] In the active region 106, a plurality of gate trenches 135 are formed in the surface layer of the first main surface 103. The plurality of gate trenches 135 are formed at intervals along the first direction X.

[0293] The multiple gate trenches 135 are formed in a strip-like shape extending substantially parallel to or parallel to the second direction Y. In a plan view, the multiple gate trenches 135 are formed in a stripe-like shape extending substantially parallel to or parallel to the second direction Y. In other words, in this configuration, the multiple gate trenches 135 intersect with the multiple groups of raised sections 115 in a plan view.

[0294] The multiple groups of raised sections 115 may be formed in a stripe shape extending substantially parallel to or parallel to the second direction Y. In this case, the multiple gate trenches 135 may extend substantially parallel to or parallel to the multiple groups of raised sections 115 in a plan view.

[0295] The multiple gate trenches 135 may be formed in a stripe shape extending parallel to the first direction X. In this case, the multiple gate trenches 135 may extend substantially parallel to or parallel to the multiple groups of raised parts 115 in a plan view.

[0296] In other words, each gate trench 135 may extend substantially parallel to or parallel to the [11-20] direction. Also, each gate trench 135 may extend substantially parallel to or parallel to the [1-100] direction which is perpendicular to the [11-20] direction.

[0297] In this configuration, each gate trench 135 extends in a band shape from one peripheral edge (side surface 105B) to the other peripheral edge (side surface 105D) on the first main surface 103 in a plan view.

[0298] Each gate trench 135 crosses the intermediate portion between one peripheral edge and the other peripheral edge of the first main surface 103. One end of each gate trench 135 is located on one peripheral edge of the first main surface 103. The other end of each gate trench 135 is located on the other peripheral edge of the first main surface 103.

[0299] Each gate trench 135 has a length on the order of millimeters (1 mm or more). In this embodiment, the length of each gate trench 135 is between 1 mm and 10 mm (for example, between 2 mm and 5 mm). The total length of one or more gate trenches 135 per unit area is 0.5 μm / μm 2 More than 0.75μm / μm 2 The following is also acceptable.

[0300] Each gate trench 135 includes an active trench portion 135a and a contact trench portion 135b. The active trench portion 135a is the portion formed in the active region 106 of the gate trench 135. The contact trench portion 135b is the portion drawn out from the active trench portion 135a to the outer region 107 of the gate trench 135.

[0301] Each gate trench 135 penetrates the body region 131 and reaches the SiC epitaxial layer 122. The bottom wall of each gate trench 135 is located within the SiC epitaxial layer 122. More specifically, the bottom wall of each gate trench 135 is located in the high-concentration region 122a of the SiC epitaxial layer 122.

[0302] With respect to the direction normal to the first main surface 103, the depth of the gate trench 135 may be 0.5 μm or more and 3 μm or less. The depth of the gate trench 135 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 4 μm or less. Preferably, the depth of the gate trench 135 is 0.5 μm or more and 1.0 μm or less.

[0303] The X-width of the gate trench 135 in the first direction may be 0.1 μm or more and 2 μm or less. The X-width of the gate trench 135 in the first direction may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less. Preferably, the X-width of the gate trench 135 in the first direction is 0.1 μm or more and 0.5 μm or less.

[0304] Each gate trench 135's opening edge 136 includes a curved portion 137 that curves inward from the gate trench 135. The opening edge 136 of the gate trench 135 is a corner connecting the first main surface 103 and the side wall of the gate trench 135. The electric field on the opening edge 136 of the gate trench 135 is mitigated by the curved portion 137.

[0305] In the surface layer of the body region 131, in the region along the side wall of the gate trench 135, n + A source region 138 of type n is formed. The n-type impurity concentration in the source region 138 is 1.0 × 10⁻⁶. 18 cm -3 The above 1.0 × 10 21 cm -3 The following is also possible: Multiple source regions 138 are formed along one side wall and the other side wall of the gate trench 135 with respect to the first direction X.

[0306] The multiple source regions 138 are each formed in a strip-like shape, extending approximately parallel or parallel to the second direction Y. The multiple source regions 138 are formed in a striped pattern in a plan view. The multiple source regions 138 intersect with the multiple groups of raised sections 115 in a plan view, similar to the gate trench 135.

[0307] A gate insulating layer 139 and a gate electrode layer 140 are formed within each gate trench 135. In Figure 20, the gate insulating layer 139 and the gate electrode layer 140 are indicated by hatching.

[0308] The gate insulating layer 139 contains silicon oxide. The gate insulating layer 139 may also contain other insulating films such as silicon nitride. The gate insulating layer 139 is formed in a film-like manner along the inner wall surface of the gate trench 135. The gate insulating layer 139 defines a recess space within the gate trench 135.

[0309] The gate insulating layer 139 includes a first region 139a, a second region 139b, and a third region 139c. The first region 139a is formed along the side wall of the gate trench 135. The second region 139b is formed along the bottom wall of the gate trench 135. The third region 139c is formed along the first main surface 103.

[0310] The thickness T1 of the first region 139a of the gate insulating layer 139 is smaller than the thickness T2 of the second region 139b of the gate insulating layer 139 and the thickness T3 of the third region 139c of the gate insulating layer 139.

[0311] The ratio T2 / T1 of the thickness T2 of the second region 139b to the thickness T1 of the first region 139a may be between 2 and 5. The ratio T3 / T1 of the thickness T3 of the third region 139c to the thickness T1 of the first region 139a may be between 2 and 5.

[0312] The thickness T1 of the first region 139a may be between 0.01 μm and 0.2 μm. The thickness T2 of the second region 139b may be between 0.05 μm and 0.5 μm. The thickness T3 of the third region 139c may be between 0.05 μm and 0.5 μm.

[0313] By forming the first region 139a thinly, the increase in carriers induced in the region near the side wall of the gate trench 135 in the body region 131 can be suppressed. This suppresses the increase in channel resistance. By forming the second region 139b thickly, the electric field concentration with respect to the bottom wall of the gate trench 135 can be mitigated.

[0314] By forming the third region 139c thicker, the breakdown voltage of the gate insulating layer 139 near the opening edge portion 136 of the gate trench 135 can be improved. By forming the third region 139c thicker, the disappearance of the third region 139c due to etching can be suppressed.

[0315] This prevents the first region 139a from being removed by etching due to the disappearance of the third region 139c. As a result, the gate electrode layer 140 can be properly positioned opposite the SiC semiconductor layer 102 with the gate insulating layer 139 in between.

[0316] The gate electrode layer 140 is embedded in the gate trench 135, sandwiched between the gate insulating layer 139. More specifically, the gate electrode layer 140 is embedded in a recess space within the gate trench 135 that is partitioned by the gate insulating layer 139. The gate electrode layer 140 is controlled by the gate voltage.

[0317] The gate electrode layer 140 is formed in a wall-like shape that extends along the normal direction of the first main surface 103 in a cross-sectional view. The gate electrode layer 140 has an upper end located on the opening side of the gate trench 135. The upper end of the gate electrode layer 140 is formed in a curved shape that is recessed toward the bottom wall of the gate trench 135.

[0318] The cross-sectional area of ​​the gate electrode layer 140 is 0.05 μm². 2 Above 0.5 μm 2 The following is also possible: The cross-sectional area of ​​the gate electrode layer 140 is the cross-sectional area obtained when the gate electrode layer 140 is cut in a direction perpendicular to the direction in which the gate trench 135 extends.

[0319] The cross-sectional area of ​​the gate electrode layer 140 is 0.05 μm². 2 More than 0.1μm 2 Below, 0.1μm 2 More than 0.2μm 2 Below, 0.2μm 2 More than 0.3μm 2 Below, 0.3μm 2 More than 0.4μm 2 The following, or 0.4 μm 2 Above 0.5 μm 2 The following is also possible: The cross-sectional area of ​​the gate electrode layer 140 is defined as the product of the depth of the gate electrode layer 140 and the width of the gate electrode layer 140.

[0320] The depth of the gate electrode layer 140 is the distance from the upper end to the lower end of the gate electrode layer 140. The width of the gate electrode layer 140 is the width of the gate electrode layer 140 at an intermediate position between the upper end and the lower end of the gate electrode layer 140.

[0321] If the upper end is curved (in this form, it is curved and concave downwards), the position of the upper end of the gate electrode layer 140 is set to an intermediate position on the upper surface of the gate electrode layer 140.

[0322] The gate electrode layer 140 contains p-type polysilicon doped with p-type impurities. The p-type impurities may include at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga).

[0323] The p-type impurity concentration in the gate electrode layer 140 is greater than or equal to the p-type impurity concentration in the body region 131. More specifically, the p-type impurity concentration in the gate electrode layer 140 is greater than the p-type impurity concentration in the body region 131.

[0324] The p-type impurity concentration in the gate electrode layer 140 is 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 22 cm -3 The following is also possible: The sheet resistance of the gate electrode layer 140 may be 10Ω / □ or more and 500Ω / □ or less (approximately 200Ω / □ in this configuration).

[0325] Referring to Figures 20 and 22, a gate wiring layer 141 is formed in the outer region 107. The gate wiring layer 141 is electrically connected to the gate pad 108 and the gate finger 109.

[0326] The gate wiring layer 141 is formed on the first main surface 103. More specifically, the gate wiring layer 141 is formed on the third region 139c of the gate insulating layer 139.

[0327] In this embodiment, the gate wiring layer 141 is formed along the gate finger 109. The gate wiring layer 141 is formed along three sides 105A, 105B, and 105D of the SiC semiconductor layer 102, and divides the active region 106 from three directions.

[0328] The gate wiring layer 141 is connected to the gate electrode layer 140, which is exposed from the contact trench portion 135b of each gate trench 135. In this embodiment, the gate wiring layer 141 is formed by a lead-out portion that extends from the gate electrode layer 140 onto the first main surface 103. The upper end of the gate wiring layer 141 is connected to the upper end of the gate electrode layer 140.

[0329] Referring to Figure 21, a low-resistance electrode layer 142 is formed on the gate electrode layer 140. The low-resistance electrode layer 142 covers the upper end of the gate electrode layer 140 within the gate trench 135.

[0330] The low-resistance electrode layer 142 includes a conductive material having a sheet resistance less than that of the gate electrode layer 140. The sheet resistance of the low-resistance electrode layer 142 may be between 0.01Ω / □ and 10Ω / □. The sheet resistance of the low-resistance electrode layer 142 may be between 0.01Ω / □ and 0.1Ω / □, between 0.1Ω / □ and 1Ω / □, between 1Ω / □ and 2Ω / □, between 2Ω / □ and 4Ω / □, between 4Ω / □ and 6Ω / □, between 6Ω / □ and 8Ω / □, or between 8Ω / □ and 10Ω / □.

[0331] The current supplied into the gate trench 135 flows through the low-resistance electrode layer 142, which has a relatively low sheet resistance, and is transmitted to the gate electrode layer 140. This allows the entire gate electrode layer 140 to quickly transition from the off state to the on state. Therefore, the delay in the switching response can be suppressed.

[0332] In particular, in the case of a gate trench 135 having a length on the order of millimeters (1 mm or more), current transmission takes time, but the low-resistance electrode layer 142 can appropriately suppress the delay in the switching response. In other words, the low-resistance electrode layer 142 is formed as a current-diffusing electrode layer that diffuses current within the gate trench 135.

[0333] The low-resistance electrode layer 142 is formed in a film-like manner. The low-resistance electrode layer 142 has a connecting portion 142a that is in contact with the upper end of the gate electrode layer 140 and a non-connecting portion 142b on the opposite side.

[0334] The connecting portion 142a and the disconnected portion 142b of the low-resistance electrode layer 142 may be formed in a curved shape following the upper end of the gate electrode layer 140. The connecting portion 142a and the disconnected portion 142b can take various forms.

[0335] The entire connecting portion 142a may be located above the first main surface 103. The entire connecting portion 142a may be located below the first main surface 103. The connecting portion 142a may include a portion located above the first main surface 103. The connecting portion 142a may include a portion located below the first main surface 103. The central portion of the connecting portion 142a may be located below the first main surface 103, and the peripheral portion of the connecting portion 142a may be located above the first main surface 103.

[0336] The entire unconnected portion 142b may be located above the first main surface 103. The entire unconnected portion 142b may be located below the first main surface 103. The unconnected portion 142b may include a portion located above the first main surface 103. The unconnected portion 142b may include a portion located below the first main surface 103. The central portion of the unconnected portion 142b may be located below the first main surface 103, and the peripheral portion of the unconnected portion 142b may be located above the first main surface 103.

[0337] The low-resistance electrode layer 142 has an edge portion 142c that is in contact with the gate insulating layer 139. The edge portion 142c is in contact with the corner of the gate insulating layer 139 that connects the first region 139a and the second region 139b.

[0338] The edge portion 142c is formed on the first main surface 103 side relative to the bottom of the source region 138. The edge portion 142c is formed on the first main surface 103 side of the boundary between the body region 131 and the source region 138. The edge portion 142c faces the source region 138 across the gate insulating layer 139. The edge portion 142c does not face the body region 131 across the gate insulating layer 139.

[0339] This prevents the formation of a current path in the region between the low-resistance electrode layer 142 and the body region 131 in the gate insulating layer 139. A current path can be formed by the undesirable diffusion of the electrode material of the low-resistance electrode layer 142 into the gate insulating layer 139.

[0340] In particular, a structure in which the edge 142c of the low-resistance electrode layer 142 is connected to the third region 139c (corner of the gate insulating layer 139) of the relatively thick gate insulating layer 139 is effective in reducing the risk of current path issues.

[0341] With respect to the normal direction of the first main surface 103, the thickness TR of the low-resistance electrode layer 142 is less than or equal to the thickness TG of the gate electrode layer 140 (TR ≤ TG). More specifically, the thickness TR of the low-resistance electrode layer 142 is less than or equal to half the thickness TG of the gate electrode layer 140 (TR ≤ TG / 2).

[0342] The ratio TR / TG of the thickness TR of the low-resistance electrode layer 142 to the thickness TG of the gate electrode layer 140 is 0.01 or more and 1 or less. The ratio TR / TG may also be 0.01 or more and 0.1 or less, 0.1 or more and 0.25 or less, 0.25 or more and 0.5 or less, 0.5 or more and 0.75 or less, or 0.75 or more and 1 or less.

[0343] The thickness TG of the gate electrode layer 140 may be 0.5 μm or more and 3 μm or less. The thickness TG may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less.

[0344] The thickness TR of the low-resistance electrode layer 142 may be 0.01 μm or more and 3 μm or less. The thickness TR may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less.

[0345] Referring to Figure 22, in this embodiment, the low-resistance electrode layer 142 also covers the upper end of the gate wiring layer 141. The portion of the low-resistance electrode layer 142 that covers the upper end of the gate wiring layer 141 is integrally formed with the portion of the low-resistance electrode layer 142 that covers the upper end of the gate electrode layer 140.

[0346] The low-resistance electrode layer 142 covers the entire area of ​​the gate electrode layer 140 and the entire area of ​​the gate wiring layer 141. The current supplied from the gate pad 108 and gate finger 109 to the gate wiring layer 141 flows through the low-resistance electrode layer 142, which has a relatively low sheet resistance, and is transmitted to the gate electrode layer 140 and the gate wiring layer 141.

[0347] This allows the entire gate electrode layer 140 to be quickly transitioned from the off state to the on state via the gate wiring layer 141. Therefore, the delay in the switching response can be suppressed. In particular, in the case of a gate trench 135 having a length on the order of millimeters (1 mm or more), the delay in the switching response can be appropriately suppressed by the low-resistance electrode layer 142 covering the upper end of the gate wiring layer 141.

[0348] The low-resistance electrode layer 142 includes a polyside layer. The polyside layer is formed by silicideizing the portion of the gate electrode layer 140 that forms the surface layer with a metallic material. More specifically, the polyside layer consists of a p-type polyside layer containing p-type impurities added to p-type polysilicon (gate electrode layer 140).

[0349] In this embodiment, the low-resistance electrode layer 142 has a resistivity of 10 μΩ·cm or more and 110 μΩ·cm or less. The resistivity of the low-resistance electrode layer 142 may be 10 μΩ·cm or more and 25 μΩ·cm or less, 25 μΩ·cm or more and 50 μΩ·cm or less, 50 μΩ·cm or more and 75 μΩ·cm or less, 75 μΩ·cm or more and 100 μΩ·cm or less, or 100 μΩ·cm or more and 110 μΩ·cm or less. The low-resistance electrode layer 142 contains at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, and WSi2.

[0350] In particular, NiSi, CoSi2, and TiSi2 among these species are suitable as polyside layers for forming the low-resistivity electrode layer 142 because their resistivity values ​​and temperature dependence are relatively small.

[0351] Furthermore, the inventors' verification revealed that when TiSi2 was used as the material for the low-resistance electrode layer 142, an increase in gate-source leakage current was observed when a low electric field was applied. In contrast, when CoSi2 was used, no increase in gate-source leakage current was observed when a low electric field was applied. Considering that NiSi has issues with heat resistance compared to CoSi2, CoSi2 is the most preferred material for the polyside layer forming the low-resistance electrode layer 142.

[0352] When the low-resistance electrode layer 142 is formed, the sheet resistance within the gate trench 135 is less than or equal to the sheet resistance of the gate electrode layer 140 alone. Preferably, the sheet resistance within the gate trench 135 is less than or equal to the sheet resistance of n-type polysilicon with added n-type impurities.

[0353] The sheet resistance within the gate trench 135 is approximated by the sheet resistance of the low-resistance electrode layer 142. That is, the sheet resistance within the gate trench 135 may be between 0.01Ω / □ and 10Ω / □. The sheet resistance within the gate trench 135 may be between 0.01Ω / □ and 0.1Ω / □, between 0.1Ω / □ and 1Ω / □, between 1Ω / □ and 2Ω / □, between 2Ω / □ and 4Ω / □, between 4Ω / □ and 6Ω / □, between 6Ω / □ and 8Ω / □, or between 8Ω / □ and 10Ω / □. Preferably, the sheet resistance within the gate trench 135 is less than 10Ω / □.

[0354] Referring again to Figures 20 and 21, in the active region 106, multiple source trenches 145 are formed in the first main surface 103. Each source trench 145 is formed in the region between two adjacent gate trenches 135.

[0355] Each source trench 145 is formed in a strip shape extending substantially parallel to or parallel to the second direction Y. Multiple source trenches 145 are formed in a stripe pattern in a plan view. Multiple source trenches 145 intersect multiple groups of raised sections 115 in a plan view, similar to the gate trench 135.

[0356] Each source trench 145 penetrates the body region 131 and reaches the SiC epitaxial layer 122. The bottom wall of each source trench 145 is located within the SiC epitaxial layer 122. More specifically, the bottom wall of each source trench 145 is located in the high-concentration region 122a of the SiC epitaxial layer 122.

[0357] The depth of the source trench 145 may be approximately equal to the depth of the gate trench 135. The depth of the source trench 145 may be greater than or equal to the depth of the gate trench 135.

[0358] With respect to the first direction X, the pitch between the centers of adjacent source trenches 145 may be 1.5 μm or more and 3 μm or less. The pitch between the centers of the source trenches 145 may be 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less.

[0359] With respect to the direction normal to the first main surface 103, the depth of the source trench 145 may be 0.5 μm or more and 10 μm or less. The depth of the source trench 145 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, or 7.5 μm or more and 10 μm or less.

[0360] The X-width in the first direction of the source trench 145 may be 0.1 μm or more and 2 μm or less. The X-width in the first direction of the source trench 145 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less.

[0361] The first-direction X-width of the source trench 145 may be approximately equal to the first-direction X-width of the gate trench 135. The first-direction X-width of the source trench 145 may be greater than or equal to the first-direction X-width of the gate trench 135.

[0362] Each source trench 145 has an opening edge 146 which includes a curved portion 147 that curves inward from the source trench 145. The opening edge 146 of the source trench 145 is a corner that connects the first main surface 103 and the side wall of the source trench 145.

[0363] The electric field on the opening edge 146 of the source trench 145 is dispersed along the curved portion 147. This reduces the concentration of the electric field on the opening edge 146 of the source trench 145.

[0364] In the SiC semiconductor layer 102, in the region along the side wall of the source trench 145, p + A type of contact region 148 is formed. Multiple contact regions 148 are formed on one side and the other side of a single source trench 145.

[0365] Multiple contact regions 148 are formed at intervals along the second direction Y. Multiple contact regions 148 are formed at intervals along the first direction X from the gate trench 135.

[0366] In the SiC semiconductor layer 102, a p-type deep well region 149 is formed in the region along the inner wall of the source trench 145. The deep well region 149 is formed in a band shape that extends along the source trench 145. The deep well region 149 extends along the inner wall of the source trench 145.

[0367] More specifically, the deep well region 149 extends along the side wall of the source trench 145 and covers the bottom wall of the source trench 145 through the edge. The deep well region 149 is connected to the body region 131 at the side wall of the source trench 145.

[0368] The deep well region 149 has a bottom located on the second main surface 104 side relative to the bottom wall of the gate trench 135. The deep well region 149 is formed in the high-concentration region 122a of the SiC epitaxial layer 122.

[0369] The p-type impurity concentration in the deep well region 149 may be approximately equal to the p-type impurity concentration in the body region 131. The p-type impurity concentration in the deep well region 149 may exceed the p-type impurity concentration in the body region 131. The p-type impurity concentration in the deep well region 149 may be less than the p-type impurity concentration in the body region 131.

[0370] The p-type impurity concentration in the deep well region 149 may be less than or equal to the p-type impurity concentration in the contact region 148. The p-type impurity concentration in the deep well region 149 may be less than the p-type impurity concentration in the contact region 148. The p-type impurity concentration in the deep well region 149 is 1.0 × 10⁻⁶ 17 cm -3 The above 1.0 × 10 19 cm -3 The following is also acceptable.

[0371] A source insulating layer 150 and a source electrode layer 151 are formed within each source trench 145. In Figure 2, the source insulating layer 150 and the source electrode layer 151 are indicated by hatching for clarity.

[0372] The source insulating layer 150 may contain silicon oxide. The source insulating layer 150 is formed in a film-like manner along the inner wall surface of the source trench 145, and defines a recess space within the source trench 145.

[0373] The source insulating layer 150 includes a first region 150a and a second region 150b. The first region 150a is formed along the side wall of the source trench 145. The second region 150b is formed along the bottom wall of the source trench 145.

[0374] The thickness T11 of the first region 150a of the source insulating layer 150 is smaller than the thickness T12 of the second region 150b of the source insulating layer 150. The ratio T12 / T11 of the thickness T11 of the second region 150b to the thickness T11 of the first region 150a may be between 2 and 5.

[0375] The thickness T11 of the first region 150a may be between 0.01 μm and 0.2 μm. The thickness T12 of the second region 150b may be between 0.05 μm and 0.5 μm.

[0376] The thickness T11 of the first region 150a may be approximately equal to the thickness T1 of the first region 139a of the gate insulating layer 139. The thickness T12 of the second region 150b may be approximately equal to the thickness T2 of the second region 139b of the gate insulating layer 139.

[0377] The source insulating layer 150 exposes the opening edge portion 146 of the source trench 145. More specifically, the source insulating layer 150 exposes the source region 138 and the contact region 148 from the opening edge portion 146 of the source trench 145.

[0378] The first region 150a of the source insulating layer 150 has, more specifically, an upper end located on the opening side of the source trench 145. The upper end of the first region 150a is formed below the first main surface 103.

[0379] The upper end of the first region 150a exposes the side wall of the source trench 145 on the opening side of the source trench 145. In this way, the first region 150a exposes the source region 138 and the contact region 148 from the opening edge portion 146 of the source trench 145.

[0380] The source electrode layer 151 is embedded in the source trench 145, sandwiched between the source insulating layer 150. More specifically, the source electrode layer 151 is embedded in a recess space within the source trench 145 that is partitioned by the source insulating layer 150. The source electrode layer 151 is controlled by the source voltage.

[0381] The source electrode layer 151 has an upper end located on the opening side of the source trench 145. The upper end of the source electrode layer 151 is formed below the first main surface 103.

[0382] The upper end of the source electrode layer 151 may be formed flush with the upper end of the source insulating layer 150. The upper end of the source electrode layer 151 may protrude above the upper end of the source insulating layer 150.

[0383] The upper end of the source electrode layer 151 may be located below the upper end of the source insulating layer 150. The thickness of the source electrode layer 151 may be 0.5 μm or more and 10 μm or less (for example, about 1 μm). The thickness of the source electrode layer 151 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less.

[0384] The source electrode layer 151 preferably contains polysilicon having properties similar to SiC in terms of material properties. This can reduce the stress generated within the SiC semiconductor layer 102. The source electrode layer 151 preferably contains p-type polysilicon with p-type impurities added.

[0385] In this case, the gate electrode layer 140 and the source electrode layer 151 can be formed simultaneously. The p-type impurity may include at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga).

[0386] The p-type impurity concentration in the source electrode layer 151 is greater than or equal to the p-type impurity concentration in the body region 131. More specifically, the p-type impurity concentration in the source electrode layer 151 is greater than the p-type impurity concentration in the body region 131.

[0387] The p-type impurity concentration in the source electrode layer 151 is 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 22 cm -3It may also be lower. The sheet resistance of the source electrode layer 151 may be 10Ω / □ or more and 500Ω / □ or less. The sheet resistance of the source electrode layer 151 may be 10Ω / □ or more and 50Ω / □ or less, 50Ω / □ or more and 100Ω / □ or less, 100Ω / □ or more and 200Ω / □ or less, 200Ω / □ or more and 300Ω / □ or less, 300Ω / □ or more and 400Ω / □ or less, or 400Ω / □ or more and 500Ω / □ or less.

[0388] The p-type impurity concentration in the source electrode layer 151 may be approximately equal to that of the gate electrode layer 140. The sheet resistance of the source electrode layer 151 may be approximately equal to that of the gate electrode layer 140.

[0389] The source electrode layer 151 may contain n-type polysilicon instead of p-type polysilicon. The source electrode layer 151 may contain at least one of tungsten, aluminum, copper, aluminum alloys, and copper alloys instead of p-type polysilicon.

[0390] Thus, the semiconductor device 101 has a trench gate electrode structure 152 and a trench source electrode structure 153. The trench gate electrode structure 152 includes a gate trench 135, a gate insulating layer 139, a gate electrode layer 140, and a low-resistance electrode layer 142. The trench source electrode structure 153 includes a source trench 145, a source insulating layer 150, and a source electrode layer 151.

[0391] Referring to Figures 21 and 22, an interlayer insulating layer 161 is formed on the first main surface 103. The interlayer insulating layer 161 selectively covers the active region 106 and the outer region 107. The interlayer insulating layer 161 covers the trench gate electrode structure 152 in the active region 106 and the gate wiring layer 141 in the outer region 107.

[0392] The interlayer insulating layer 161 may contain silicon oxide or silicon nitride. Gate contact holes 162 and source contact holes 163 are formed in the interlayer insulating layer 161.

[0393] The gate contact hole 162 exposes the gate wiring layer 141 (low-resistance electrode layer 142) in the outer region 107. The source contact hole 163 exposes the source region 138, contact region 148, and trench source electrode structure 153 in the active region 106. A gate pad 108, gate finger 109, and source pad 110 are formed on the interlayer insulating layer 161.

[0394] The gate finger 109 enters the gate contact hole 162 from above the interlayer insulating layer 161. Within the gate contact hole 162, the gate finger 109 is electrically connected to the low-resistance electrode layer 142. As a result, electrical signals from the gate pad 108 are transmitted to the gate electrode layer 140 via the low-resistance electrode layer 142, which has a relatively low resistance value.

[0395] The source pad 110 extends from above the interlayer insulating layer 161 into the source contact hole 163. Within the source contact hole 163, the source pad 110 is electrically connected to the source region 138, the contact region 148, and the source electrode layer 151. The source electrode layer 151 may be formed using a portion of the source pad 110.

[0396] Figure 24 is a graph illustrating sheet resistance. In Figure 24, the vertical axis represents sheet resistance [Ω / □], and the horizontal axis represents the item. Figure 24 shows the first bar graph L1, the second bar graph L2, and the third bar graph L3.

[0397] The first bar graph L1 represents the sheet resistance of n-type polysilicon. The second bar graph L2 represents the sheet resistance of p-type polysilicon. The third bar graph L3 represents the sheet resistance in the gate trench 135 when a low-resistance electrode layer 142 is formed on the p-type polysilicon. The low-resistance electrode layer 142 here contains TiSi2 (p-type titanium silicide).

[0398] Referring to the first bar graph L1, the sheet resistance of n-type polysilicon was 10Ω / □. Referring to the second bar graph L2, the sheet resistance of p-type polysilicon was 200Ω / □. Referring to the third bar graph L3, the sheet resistance when a low-resistance electrode layer 142 was formed on p-type polysilicon was 2Ω / □.

[0399] p-type polysilicon has a different work function than n-type polysilicon, and by embedding p-type polysilicon in the gate trench 135, the gate threshold voltage Vth can be increased by about 1V.

[0400] However, p-type polysilicon has a sheet resistance that is several tens of times (about 20 times) higher than that of n-type polysilicon. Therefore, when p-type polysilicon is used as the material for the gate electrode layer 140, energy loss increases significantly as the parasitic resistance in the gate trench 135 (hereinafter simply referred to as "gate resistance") increases.

[0401] In contrast, in a structure having a low-resistance electrode layer 142 on p-type polysilicon, the sheet resistance can be reduced to less than 1 / 100th compared to a structure without the low-resistance electrode layer 142. Furthermore, in a structure with the low-resistance electrode layer 142, the sheet resistance can be reduced to less than 1 / 5th compared to a gate electrode layer 140 containing n-type polysilicon.

[0402] As described above, the semiconductor device 101 allows the raised portion group 115 to increase the contact area of ​​the drain pad 123 with respect to the second main surface 104. This improves the electrical characteristics.

[0403] More specifically, the drain pad 123 forms ohmic contact with the raised portion group 115. This allows for good ohmic characteristics between the SiC semiconductor layer 102 and the drain pad 123, thereby improving electrical characteristics.

[0404] Furthermore, in the semiconductor device 101, a trench gate electrode structure 152 is formed in which a gate electrode layer 140 is embedded in a gate trench 135 with a gate insulating layer 139 in between. In this trench gate electrode structure 152, the gate electrode layer 140 is covered by a low-resistance electrode layer 142 within the limited space of the gate trench 135.

[0405] The gate electrode layer 140 contains p-type polysilicon, which allows for an increase in the gate threshold voltage Vth. The low-resistance electrode layer 142 contains a conductive material having a sheet resistance less than that of p-type polysilicon.

[0406] This allows for a reduction in gate resistance. As a result, the current can be efficiently diffused along the trench gate electrode structure 152, thereby shortening the switching delay.

[0407] In particular, the structure in which the gate electrode layer 140 is covered with a low-resistance electrode layer 142 eliminates the need to increase the p-type impurity concentration in the body region 131. Therefore, the gate threshold voltage Vth can be increased while preventing an increase in channel resistance.

[0408] Furthermore, in the semiconductor device 101, the gate wiring layer 141 in the outer region 107 is covered with a low-resistance electrode layer 142. This also helps to reduce the gate resistance in the gate wiring layer 141.

[0409] In particular, in a structure in which the gate electrode layer 140 and the gate wiring layer 141 are covered by a low-resistance electrode layer 142, current can be efficiently diffused along the trench gate electrode structure 152. Therefore, the switching delay can be appropriately reduced.

[0410] Figure 25 is an enlarged view of the region corresponding to Figure 20, and is an enlarged view for illustrating the structure of the semiconductor device 171 according to the eighth embodiment of the present invention. Figure 26 is a cross-sectional view along the line XXVI-XXVI shown in Figure 25. Hereinafter, structures corresponding to the structure of the semiconductor device 101 will be given the same reference numerals and their description will be omitted.

[0411] Referring to Figures 25 and 26, in the semiconductor device 171, an outer gate trench 172 is formed on the first main surface 103 in the outer region 107. The outer gate trench 172 extends in a strip shape across the outer region 107.

[0412] The outer gate trench 172 extends along the gate finger 109 in the region below the gate finger 109. More specifically, the outer gate trench 172 is formed along three sides 105A, 105B, and 105D of the SiC semiconductor layer 102, partitioning the active region 106 from three directions. The outer gate trench 172 may be formed in an endless manner (e.g., a quadrangular ring) surrounding the active region 106.

[0413] The outer gate trench 172 communicates with the contact trench portion 135b of each gate trench 135. As a result, the outer gate trench 172 and the gate trenches 135 are formed by a single trench.

[0414] A gate wiring layer 141 is embedded in the outer gate trench 172. The gate wiring layer 141 is connected to the gate electrode layer 140 at the communication point between the outer gate trench 172 and the contact trench portion 135b.

[0415] In this configuration, the low-resistance electrode layer 142 covers the upper surface of the gate wiring layer 141 within the outer gate trench 172. Therefore, both the low-resistance electrode layer 142 covering the gate electrode layer 140 and the low-resistance electrode layer 142 covering the gate wiring layer 141 are located within a single trench.

[0416] As described above, the semiconductor device 171 can achieve the same effects as those described for the semiconductor device 101. Furthermore, with the semiconductor device 171, it is not necessary to bring out the gate wiring layer 141 onto the first main surface 103.

[0417] This prevents the gate wiring layer 141 from facing the SiC semiconductor layer 102 across the gate insulating layer 139 at the opening edge of the gate trench 135 and the outer gate trench 172. As a result, the concentration of the electric field at the opening edge of the gate trench 135 can be suppressed.

[0418] Figure 27 is a cross-sectional view of the region corresponding to Figure 21, and is a cross-sectional view illustrating the structure of the semiconductor device 181 according to the ninth embodiment of the present invention. In the following description, structures corresponding to the structure of the semiconductor device 101 are given the same reference numerals and their explanation is omitted.

[0419] Referring to Figure 27, in the semiconductor device 181, each source trench 145 is formed deeper than the gate trench 135. The bottom wall of each source trench 145 is located on the second main surface 104 side relative to the bottom wall of the gate trench 135. More specifically, the bottom wall of each source trench 145 is located in the high-density region 122a of the SiC epitaxial layer 122.

[0420] The ratio of the depth of the source trench 145 to the depth of the gate trench 135 may be 1.5 or more, provided that the bottom wall of the source trench 145 is located within the high-concentration region 122a. Preferably, the ratio of the depth of the source trench 145 to the depth of the gate trench 135 is 2 or more.

[0421] The depth of the gate trench 135 may be between 0.5 μm and 3 μm (for example, about 1 μm). The depth of the source trench 145 may be between 0.75 μm and 10 μm (for example, about 2 μm).

[0422] The contact region 148 extends along the inner wall of the source trench 145, similar to the semiconductor device 101, and has a bottom portion located on the second main surface 104 side relative to the bottom wall of the gate trench 135. The contact region 148 is formed in the high-concentration region 122a of the SiC epitaxial layer 122.

[0423] As described above, the semiconductor device 181 can achieve the same effects as those described for the semiconductor device 101.

[0424] Figure 28 is a plan view of the region corresponding to Figure 20, and is a plan view for illustrating the structure of the semiconductor device 191 according to the 10th embodiment of the present invention. In the following description, structures corresponding to the structure of the semiconductor device 101 are given the same reference numerals and their explanation is omitted.

[0425] Referring to Figure 28, in this embodiment, the gate trench 135 is formed in a grid shape in plan view. The gate trench 135 integrally includes a plurality of gate trenches 135 extending parallel to a first direction X, and a plurality of gate trenches 135 extending substantially parallel or parallel to a second direction Y.

[0426] The first main surface 103 is divided into multiple cell regions 192 in a matrix by gate trenches 135. Each cell region 192 is formed in a rectangular shape in plan view. Source trenches 145 are formed in each of the multiple cell regions 192. The source trenches 145 may also be formed in a rectangular shape in plan view.

[0427] The cross-sectional view along the line XXI-XXI in Figure 28 is approximately the same as the cross-sectional view shown in Figure 21. The cross-sectional view along the line XXII-XXII in Figure 28 is approximately the same as the cross-sectional view shown in Figure 22.

[0428] As described above, the semiconductor device 191 can achieve the same effects as those described for the semiconductor device 101. The gate trench 135, which has a lattice-shaped structure instead of a stripe-shaped structure, can also be applied to other forms.

[0429] Figure 29 is a cross-sectional view of the region corresponding to Figure 21 and is a plan view for illustrating the structure of semiconductor device 201 according to the 11th embodiment of the present invention. In the following description, structures corresponding to the structure of semiconductor device 101 are denoted by the same reference numerals and their explanation is omitted.

[0430] Referring to Figure 29, in semiconductor device 201, the SiC semiconductor layer 102 is n + Instead of the type SiC semiconductor substrate 121, p + Includes a SiC semiconductor substrate 202 of type p + The SiC semiconductor substrate 202 is formed as the collector region of an IGBT (Insulated Gate Bipolar Transistor).

[0431] The description of semiconductor device 101 is applied mutatis mutandis to the description of semiconductor device 201, by substituting the "source" of MISFET with the "emitter" of IGBT, and the "drain" of MISFET with the "collector" of IGBT.

[0432] In other words, the source pad 110 and source region 138 can be interpreted as the emitter pad (110) and emitter region (138), respectively. Similarly, the drain pad 123 and drain region 128 can be interpreted as the collector electrode layer (123) and collector region (128), respectively.

[0433] As described above, the semiconductor device 201 can achieve the same effects as those described for the semiconductor device 101.

[0434] Although embodiments of the present invention have been described, the present invention can be implemented in other forms.

[0435] In each of the embodiments described above, a structure in which the conductivity type of each semiconductor portion is reversed may be adopted. That is, the p-type portion may be made n-type, and the n-type portion may be made p-type.

[0436] In the embodiments described above, examples were given in which the SiC semiconductor layers 2 and 102 have a stacked structure including SiC semiconductor substrates 21 and 121 and SiC epitaxial layers 22 and 122. However, the SiC semiconductor layers 2 and 102 may have a single-layer structure consisting of the SiC semiconductor substrates 21 and 121. Alternatively, the SiC semiconductor layers 2 and 102 may have a single-layer structure consisting of the SiC epitaxial layers 22 and 122.

[0437] In the first to sixth embodiments described above, an example was described in which the electrode 10 includes a Ti layer 31, a Ni layer 32, an Au layer 33, and / or an Ag layer 34. However, the electrode 10 may include an Al layer instead of, or in addition to, the Ti layer 31, Ni layer 32, Au layer 33, and / or Ag layer 34.

[0438] The electrode 10 may have a laminated structure in which at least two of the Ti layer 31, Ni layer 32, Au layer 33, Ag layer 34, and Al layer are stacked in any manner. Alternatively, the electrode 10 may have a single-layer structure including an Al layer.

[0439] In the seventh to eleventh embodiments described above, an example was given in which a SiC epitaxial layer 122 having a high-concentration region 122a and a low-concentration region 122b is formed by an epitaxial growth method. However, the SiC epitaxial layer 122 can also be formed by the following process.

[0440] First, a SiC epitaxial layer 122 with a relatively low n-type impurity concentration is formed by epitaxial growth. Next, n-type impurities are introduced into the surface layer of the SiC epitaxial layer 122 by ion implantation. This forms a SiC epitaxial layer 122 having a high-concentration region 122a and a low-concentration region 122b.

[0441] In the seventh to eleventh embodiments described above, examples were given in which a gate electrode layer 140 and a gate wiring layer 141 containing p-type polysilicon doped with p-type impurities were formed. However, if the increase in gate threshold voltage Vth is not a concern, the gate electrode layer 140 and the gate wiring layer 141 may contain n-type polysilicon doped with n-type impurities instead of p-type polysilicon.

[0442] In other words, the low-resistance electrode layer 142 may contain n-type polysilicon. In this case, the low-resistance electrode layer 142 may be formed by silicideizing the portion that forms the surface layer of n-type polysilicon with a metallic material. With such a structure, the gate resistance can be reduced.

[0443] In the seventh to eleventh embodiments described above, an example was described in which the drain pad 123 includes a Ti layer 124, a Ni layer 125, an Au layer 126, and / or an Ag layer 127. The drain pad 123 may include an Al layer instead of, or in addition to, the Ti layer 124, Ni layer 125, Au layer 126, and / or Ag layer 127.

[0444] In the seventh to eleventh embodiments described above, the drain pad 123 may have a laminated structure in which at least two of the Ti layer 124, Ni layer 125, Au layer 126, Ag layer 127, and Al layer are laminated in any manner. The drain pad 123 may also have a single-layer structure including an Al layer.

[0445] In the seventh to tenth embodiments described above, the structure of the semiconductor device 201 according to the eleventh embodiment may be adopted. That is, in the seventh to tenth embodiments described above, n + Instead of the type SiC semiconductor substrates 21 and 121, p + A SiC semiconductor substrate 202 of type 1 may be used. In this case, in the description of each embodiment above, "source" shall be read as "emitter" and "drain" as "collector".

[0446] Examples of features extracted from this specification and drawings are shown below.

[0447] [A1] A semiconductor device comprising: a SiC semiconductor layer having a first main surface on one side and a second main surface on the other side; a semiconductor element formed on the first main surface; a group of raised portions including a plurality of raised portions formed at intervals from each other on the second main surface; and an electrode directly connected to the group of raised portions on the second main surface.

[0448] This semiconductor device allows for an increase in the contact area of ​​the electrodes with respect to the second main surface through the raised portion group. This improves the electrical characteristics. Furthermore, because the electrodes are directly connected to the raised portion group, the increase in resistance due to poor connections can be suppressed.

[0449] [A2] The semiconductor device according to A1, wherein the electrode is connected to the group of raised portions without a silicide layer.

[0450] [A3] The semiconductor device according to A1 or A2, wherein the electrode is connected to the group of raised portions without a carbon layer.

[0451] [A4] The semiconductor device according to any one of A1 to A3, wherein the electrode contains at least one of Ti, Ni, Au, and Ag.

[0452] [A5] The semiconductor device according to any one of A1 to A4, wherein the electrode includes a Ti layer in contact with the raised portion group.

[0453] [A6] The semiconductor device according to any one of A1 to A4, wherein the electrode includes a Ni layer in contact with the group of raised portions.

[0454] [A7] The semiconductor device according to any one of A1 to A6, wherein the group of raised portions has a first portion in which some of the raised portions overlap each other when viewed from a first direction which is one of the plane directions of the second main surface.

[0455] [A8] The semiconductor device according to A7, wherein the group of raised portions has a second portion which overlaps with the first portion in the first view, some of the raised portions are formed spaced apart from the first portion in the first view.

[0456] [A9] The semiconductor device according to A7 or A8, wherein the group of raised portions is one of the planar directions of the first main surface and is formed in multiples at intervals along a second direction intersecting the first direction.

[0457] [A10] The semiconductor device according to A9, wherein the distance between a plurality of adjacent groups of the raised portions is 100 μm or less.

[0458] [A11] The semiconductor device according to A10, wherein the distance is 50 μm or less.

[0459] [A12] The semiconductor device according to A10 or A11, wherein the distance is 20 μm or less.

[0460] [A13] The semiconductor device according to any one of A7 to A12, wherein the SiC semiconductor layer comprises 4H-SiC, and the first direction is the [11-20] direction of 4H-SiC.

[0461] [A14] The semiconductor device according to any one of A7 to A12, wherein the SiC semiconductor layer comprises 4H-SiC, and the first direction is the [1-100] direction of 4H-SiC.

[0462] [A15] The semiconductor device according to A13 or A14, wherein the SiC semiconductor layer has an off-angle tilted at an angle of 10° or less with respect to the [11-20] direction from the (0001) plane of 4H-SiC.

[0463] [A16] The semiconductor device according to A15, wherein the off-angle is 0° or more and 4° or less.

[0464] [A17] The semiconductor device according to A15 or A16, wherein the off-angle is greater than 0° and less than 4°.

[0465] [A18] The semiconductor device according to any one of A7 to A17, wherein the group of raised portions is formed on the second main surface in a range of 10 μm to 200 μm with respect to a direction perpendicular to the first direction.

[0466] [A19] The semiconductor device according to A18, wherein the range is 50 μm or more and 150 μm or less.

[0467] [A20] The semiconductor device according to A18 or A14, wherein the range is 80 μm or more and 120 μm or less.

[0468] [A21] The semiconductor device according to any one of A1 to A20, further comprising a groove formed on the second main surface.

[0469] [A22] The semiconductor device according to A21, wherein the groove includes a portion that intersects with the group of raised portions.

[0470] [A23] The semiconductor device according to A21 or A22, wherein the group of raised portions includes portions in which some of the multiple raised portions are formed at intervals along the groove in a plan view taken from the direction normal to the second main surface.

[0471] [A24] The semiconductor device is the semiconductor device according to any one of A1 to A23, wherein the semiconductor element includes a Schottky barrier diode.

[0472] [A25] The semiconductor device is the semiconductor device according to any one of A1 to A23, wherein the semiconductor element includes a field-effect transistor.

[0473] [B1] A semiconductor device comprising: a SiC semiconductor layer having a first main surface on one side and a second main surface on the other side; a semiconductor element formed on the first main surface; a group of raised portions including a plurality of raised portions formed on the second main surface at intervals from each other, wherein some of the plurality of raised portions have a first portion that overlaps with each other when viewed from a first direction which is one of the surface directions of the second main surface; and an electrode formed on the second main surface and connected to the group of raised portions.

[0474] This semiconductor device allows for an increase in the contact area of ​​the electrodes with respect to the second main surface through the use of raised sections. This improves the electrical characteristics.

[0475] [B2] The semiconductor device according to B1, wherein the group of raised portions has a second portion which overlaps with the first portion in the first view, and some of the raised portions are formed spaced apart from the first portion in the first view.

[0476] [B3] The semiconductor device according to B1 or B2, wherein the group of raised portions is one of the planar directions of the first main surface and is formed in multiples at intervals along a second direction intersecting the first direction.

[0477] [B4] The semiconductor device according to B3, wherein the distance between a plurality of adjacent groups of the aforementioned raised portions is 100 μm or less.

[0478] [B5] The semiconductor device described in B4, wherein the distance is 50 μm or less.

[0479] [B6] The semiconductor device according to B4 or B5, wherein the distance is 20 μm or less.

[0480] [B7] The semiconductor device according to any one of B1 to B6, wherein the group of raised portions is formed on the second main surface in a range of 10 μm to 200 μm with respect to a direction perpendicular to the first direction.

[0481] [B8] The semiconductor device according to B7, wherein the range is 50 μm or more and 150 μm or less.

[0482] [B9] The semiconductor device according to B7 or B8, wherein the range is 80 μm or more and 120 μm or less.

[0483] [B10] The semiconductor device according to any one of B1 to B9, wherein the SiC semiconductor layer comprises 4H-SiC, and the first direction is the [11-20] direction of the 4H-SiC.

[0484] [B11] The semiconductor device according to any one of B1 to B9, wherein the SiC semiconductor layer includes 4H-SiC, and the first direction is the [1-100] direction of the 4H-SiC.

[0485] [B12] The semiconductor device according to B10 or B11, wherein the SiC semiconductor layer has an off-angle tilted at an angle of 10° or less with respect to the [11-20] direction from the (0001) plane of the 4H-SiC.

[0486] [B13] The semiconductor device according to B12, wherein the off-angle is 0° or more and 4° or less.

[0487] [B14] The semiconductor device according to B12 or B13, wherein the off-angle is greater than 0° and less than 4°.

[0488] [B15] The semiconductor device according to any one of B1 to B14, wherein the electrode comprises at least one of Ti, Ni, Au, and Ag.

[0489] [B16] The semiconductor device according to any one of B1 to B15, wherein the electrode includes a Ti layer in contact with the group of raised portions.

[0490] [B17] The semiconductor device according to any one of B1 to B15, wherein the electrode includes a Ni layer in contact with the group of raised portions.

[0491] [B18] The semiconductor device according to any one of B1 to B17, further comprising a groove formed on the second main surface of the SiC semiconductor layer.

[0492] [B19] The semiconductor device according to B18, wherein the groove includes a portion that intersects with the group of raised portions.

[0493] [B20] The semiconductor device according to B18 or B19, wherein the group of raised portions includes portions in which some of the multiple raised portions are formed at intervals along the groove in a plan view taken from the direction normal to the second main surface.

[0494] [B21] The semiconductor device is the semiconductor device according to any one of B1 to B20, wherein the semiconductor element includes a Schottky barrier diode.

[0495] [B22] The semiconductor device is the semiconductor device according to any one of B1 to B20, wherein the semiconductor element includes a field-effect transistor.

[0496] [C1] A semiconductor device comprising: a semiconductor layer having a main surface on which a gate trench is formed; a gate insulating layer formed along the inner wall of the gate trench; a gate electrode layer containing p-type polysilicon doped with p-type impurities, embedded in the gate trench with the gate insulating layer in between; and a low-resistance electrode layer covering the gate electrode layer, containing a conductive material having a sheet resistance less than the sheet resistance of the gate electrode layer.

[0497] This semiconductor device forms a trench gate electrode structure in which a gate electrode layer is embedded in a gate trench with a gate insulating layer in between. In this trench gate electrode structure, the gate electrode layer is covered by a low-resistance electrode layer.

[0498] The gate electrode layer contains p-type polysilicon. This allows for an increase in the gate threshold voltage. Furthermore, the low-resistance electrode layer contains a conductive material having a sheet resistance less than that of p-type polysilicon. This allows for a reduction in gate resistance.

[0499] [C2] The semiconductor device according to C1, wherein the low-resistance electrode layer includes a polyside layer in which the p-type polysilicon is silicided with a metallic material.

[0500] [C3] The semiconductor device according to C2, wherein the polyside layer includes at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, and WSi2.

[0501] [C4] The semiconductor device according to any one of C1 to C3, wherein the low-resistance electrode layer is formed in the form of a film.

[0502] [C5] The semiconductor device according to any one of C1 to C4, wherein the thickness of the low-resistance electrode layer is less than or equal to the thickness of the gate electrode layer.

[0503] [C6] The semiconductor device according to any one of C1 to C5, wherein the gate insulating layer includes a first region formed along the side wall of the gate trench and a second region formed along the bottom wall of the gate trench, and the thickness of the second region of the gate insulating layer is equal to or greater than the thickness of the first region of the gate insulating layer.

[0504] [C7] The semiconductor device according to C6, wherein the gate insulating layer has a third region that covers the main surface of the semiconductor layer, and the thickness of the third region of the gate insulating layer is equal to or greater than the thickness of the first region of the gate insulating layer.

[0505] [C8] The semiconductor device according to any one of C1 to C7, wherein the gate trench has a curved portion that curves inward toward the gate trench at the opening edge portion connecting the main surface of the semiconductor layer and the side wall of the gate trench.

[0506] [C9] The semiconductor device according to any one of C1 to C7, wherein the gate trench has an inclined portion that slopes downward from the main surface of the semiconductor layer toward the side wall of the gate trench at the opening edge portion connecting the main surface of the semiconductor layer and the side wall of the gate trench.

[0507] [C10] The semiconductor device according to any one of C1 to C9, wherein the gate insulating layer includes a bulge that bulges inward at the opening edge of the gate trench, and the low-resistance electrode layer is in contact with the bulge of the gate insulating layer.

[0508] [C11] The semiconductor device according to C10, wherein the bulging portion of the gate insulating layer protrudes in a curved manner toward the inside of the gate trench.

[0509] [C12] A semiconductor device according to any one of C1 to C11, further comprising a source region, a body region, and a drain region formed in this order from the main surface of the semiconductor layer toward the thickness direction along the side wall of the gate trench, wherein the low-resistance electrode layer faces the source region across the gate insulating layer.

[0510] [C13] A semiconductor device according to any one of C1 to C12, further comprising an emitter region, a body region, and a collector region formed in this order from the main surface of the semiconductor layer toward the thickness direction along the side wall of the gate trench, wherein the low-resistance electrode layer faces the emitter region across the gate insulating layer.

[0511] [C14] The semiconductor device according to any one of C1 to C13, wherein the semiconductor layer includes SiC.

[0512] [C15] A method for manufacturing a semiconductor device, comprising the steps of: forming a gate trench on the main surface of a semiconductor layer; forming a gate insulating layer along the inner wall of the gate trench; forming a gate electrode layer by embedding p-type polysilicon with p-type impurities in the gate trench, sandwiching the gate insulating layer; and forming a low-resistance electrode layer by covering the gate electrode layer with a conductive material having a sheet resistance lower than that of the gate electrode layer.

[0513] [C16] The method for manufacturing a semiconductor device according to C15, wherein the step of forming the low-resistance electrode layer includes the step of forming a polyside layer that covers the gate electrode layer by silicideizing the surface layer of the gate electrode layer with a metallic material.

[0514] [C17] The method for manufacturing a semiconductor device according to C16, wherein the metallic material includes at least one of Ti, Ni, Co, Mo, and W.

[0515] [C18] A method for manufacturing a semiconductor device according to any one of C15 to C17, wherein the step of forming the low-resistance electrode layer includes the step of forming the low-resistance electrode layer having a thickness less than or equal to the thickness of the gate electrode layer.

[0516] [D1] A semiconductor device comprising: a SiC semiconductor layer having a first main surface on one side and a second main surface on the other side; a semiconductor element formed on the first main surface; a group of raised portions including a plurality of raised portions formed on the second main surface at intervals from each other, wherein some of the raised portions have a first portion that overlaps with each other when viewed from a first direction which is one of the surface directions of the second main surface; a groove formed on the second main surface of the SiC semiconductor layer; and an electrode formed on the second main surface and connected to the group of raised portions.

[0517] [D2] The semiconductor device according to D1, wherein the groove includes a portion that intersects the group of raised portions.

[0518] [D3] The semiconductor device according to D1 or D2, wherein the group of raised portions includes a portion in which some of the multiple raised portions are formed at intervals along the groove in a plan view taken from the direction normal to the second main surface.

[0519] [D4] A semiconductor device comprising: a SiC semiconductor layer having a first main surface on one side and a second main surface on the other side; a semiconductor element formed on the first main surface; a group of raised portions including a plurality of raised portions formed on the second main surface at intervals from each other, wherein some of the plurality of raised portions have a first portion that overlaps with each other when viewed from a first direction which is one of the plane directions of the second main surface; and an electrode formed on the second main surface and connected to the group of raised portions, wherein the group of raised portions is formed in a plurality at intervals along a second direction which is one of the plane directions of the first main surface and intersects the first direction.

[0520] [D5] The semiconductor device according to D4, wherein the distance between a plurality of adjacent groups of the raised portions is 100 μm or less.

[0521] [D6] The semiconductor device according to D5, wherein the distance is 50 μm or less.

[0522] [D7] The semiconductor device according to D5 or D6, wherein the distance is 20 μm or less.

[0523] [D8] A semiconductor device comprising: a SiC semiconductor layer having a first main surface on one side and a second main surface on the other side; a semiconductor element formed on the first main surface; a group of raised portions including a plurality of raised portions formed on the second main surface at intervals from each other, wherein some of the plurality of raised portions have a first portion that overlaps with each other when viewed from a first direction which is one of the surface directions of the second main surface; and an electrode formed on the second main surface and connected to the group of raised portions, wherein the group of raised portions is formed on the second main surface in a range of 10 μm to 200 μm with respect to a direction orthogonal to the first direction.

[0524] [D9] The semiconductor device according to D8, wherein the range is 50 μm or more and 150 μm or less.

[0525] [D10] The semiconductor device according to D8 or D9, wherein the range is 80 μm or more and 120 μm or less.

[0526] [D11] The semiconductor device according to any one of D1 to D10, wherein the group of raised portions has a second portion which overlaps with the first portion in the first view, some of the raised portions are formed spaced apart from the first portion in the first view.

[0527] [D12] The semiconductor device according to any one of D1 to D11, wherein the SiC semiconductor layer comprises 4H-SiC, and the first direction is the [11-20] direction of the 4H-SiC.

[0528] [D13] The semiconductor device according to any one of D1 to D11, wherein the SiC semiconductor layer includes 4H-SiC, and the first direction is the [1-100] direction of the 4H-SiC.

[0529] [D14] The semiconductor device according to D12 or D13, wherein the SiC semiconductor layer has an off-angle tilted at an angle of 10° or less with respect to the [11-20] direction from the (0001) plane of the 4H-SiC.

[0530] [D15] The semiconductor device according to D14, wherein the off-angle is 0° or more and 4° or less.

[0531] [D16] The semiconductor device according to D14 or D15, wherein the off-angle is greater than 0° and less than 4°.

[0532] [D17] The semiconductor device according to any one of D1 to D16, wherein the electrode includes at least one of Ti, Ni, Au, and Ag.

[0533] [D18] The semiconductor device according to any one of D1 to D17, wherein the electrode includes a Ti layer in contact with the group of raised portions.

[0534] [D19] The semiconductor device according to any one of D1 to D17, wherein the electrode includes a Ni layer in contact with the group of raised portions.

[0535] [D20] The semiconductor device is a semiconductor device according to any one of D1 to D19, which includes a Schottky barrier diode.

[0536] [D21] The semiconductor device is a semiconductor device according to any one of D1 to D19, wherein the semiconductor element includes a field-effect transistor.

[0537] [E1] A semiconductor device comprising: a SiC semiconductor layer having a first main surface on one side and a second main surface on the other side; a semiconductor element formed on the first main surface; a group of raised portions including a plurality of raised portions formed on the second main surface at intervals from each other in a first direction and a second direction intersecting the first direction; an electrode directly connected to the group of raised portions on the second main surface; and a SiC layer formed on the surface of the second main surface, the SiC layer having a higher silicon density than the SiC semiconductor layer, wherein the group of raised portions is formed on the SiC layer.

[0538] [E2] The semiconductor device according to E1, wherein the electrode is connected to the group of raised portions without a silicide layer.

[0539] [E3] The semiconductor device according to E1 or E2, wherein a space is defined adjacent to the group of raised portions on the second main surface in which no raised portions are formed, and the SiC layer includes a portion along the group of raised portions and a portion along the space.

[0540] [E4] The semiconductor device according to any one of E1 to E3, wherein the electrode contains at least one of Ti, Ni, Au, and Ag.

[0541] [E5] The semiconductor device according to any one of E1 to E4, wherein the electrode includes a Ti layer in contact with the group of raised portions.

[0542] [E6] The semiconductor device according to any one of E1 to E4, wherein the electrode includes a Ni layer in contact with the group of raised portions.

[0543] [E7] The semiconductor device according to any one of E1 to E6, wherein the group of raised portions has a layout in which the multiple raised portions overlap in the first direction when viewed from the first direction.

[0544] [E8] The semiconductor device according to any one of E1 to E7, wherein the group of raised portions has a layout in which a plurality of the raised portions are continuously formed in the first direction.

[0545] [E9] A semiconductor device according to any one of E1 to E8, wherein a plurality of the aforementioned raised portions are formed at intervals in the second direction.

[0546] [E10] The semiconductor device according to E9, wherein the distance between a plurality of adjacent groups of the raised portions is 100 μm or less.

[0547] [E11] The semiconductor device according to any one of E1 to E10, wherein the group of raised portions is formed in a range of 10 μm to 200 μm with respect to the second direction.

[0548] [E12] The semiconductor device according to any one of E1 to E11, further comprising a groove formed on the second main surface.

[0549] [E13] The semiconductor device according to E12, wherein the groove intersects the group of raised portions.

[0550] [E14] The semiconductor device according to E12 or E13, wherein the group of raised portions includes a plurality of raised portions formed along the groove.

[0551] [E15] The semiconductor device according to any one of E1 to E14, wherein the SiC semiconductor layer comprises 4H-SiC and the first direction is the [11-20] direction.

[0552] [E16] The semiconductor device according to any one of E1 to E14, wherein the SiC semiconductor layer comprises 4H-SiC, and the first direction is the [1-100] direction.

[0553] [E17] The semiconductor device according to E15 or E16, wherein the SiC semiconductor layer has an off-angle tilted to within 10° with respect to the (0001) plane toward the [11-20] direction.

[0554] [E18] The semiconductor device according to E17, wherein the off-angle is 0° or more and 4° or less.

[0555] [E19] The semiconductor device is a semiconductor device according to any one of E1 to E18, wherein the semiconductor element includes a Schottky barrier diode.

[0556] [E20] The semiconductor device is a semiconductor device according to any one of E1 to E18, wherein the semiconductor element includes a field-effect transistor.

[0557] [A1]~[A25], [B1]~[B22], [C1]~[C18], [D1]~[D21], and [E1]~[E20] can be combined in any manner among them.

[0558] This specification does not limit any combination of the features shown in the first to eleventh embodiments. The first to eleventh embodiments can be combined with each other in any manner and in any form. In other words, a configuration in which the features shown in the first to eleventh embodiments are combined in any manner and in any form may be adopted.

[0559] This application corresponds to Japanese Patent Application No. 2018-068567 and Japanese Patent Application No. 2018-068568, both filed with the Japan Patent Office on March 30, 2018, and the full disclosures of these applications are incorporated herein by reference.

[0560] Although embodiments of the present invention have been described in detail, these are merely specific examples used to clarify the technical content of the present invention, and the present invention should not be construed as being limited to these specific examples. The scope of the present invention is limited only by the appended claims. [Explanation of symbols]

[0561] 1 Semiconductor device 2 SiC semiconductor layer 3. First Main Surface 4. Second main surface 10 electrodes 11 Ridges 11A 1st ridge group 11B 2nd ridge group 15 Ridge 16 groove 21 SiC semiconductor substrates 31 Ti layer 32 Ni layer 62 Carbon Layer 63 NiSi layer 71 Semiconductor Equipment 81 Semiconductor Equipment 91 Semiconductor Equipment 101 Semiconductor Equipment 102 SiC semiconductor layer 103 First Main Surface 104 Second Main Surface 114 Ridges 116 Groove 121 SiC semiconductor substrate 124 Ti layer 125 Ni layer 171 Semiconductor Equipment 181 Semiconductor Equipment 191 Semiconductor Equipment 201 Semiconductor Equipment 202 SiC semiconductor substrate D Schottky barrier diode X 1st direction Y Second direction

Claims

1. A SiC semiconductor layer having a first main surface on one side and a second main surface on the other side, A semiconductor element formed on the first main surface, The second main surface includes a plurality of raised portions formed at intervals from each other, and a group of raised portions having a first portion in which some of the plurality of raised portions overlap each other when viewed from a first direction which is one of the surface directions of the second main surface, Includes an electrode formed on the second main surface and connected to the group of raised portions, The electrode has a laminated structure including a carbon layer, a NiSi layer, and a Ni layer stacked in this order from the second main surface, wherein the electrode is a semiconductor device.

2. The semiconductor device according to claim 1, wherein the group of raised portions has a second portion in which some of the raised portions are spaced apart from the first portion in a first view and overlap each other in a first view.

3. The semiconductor device according to claim 1 or 2, wherein the group of raised portions is one of the planar directions of the first main surface and is formed in a plurality at intervals along a second direction intersecting the first direction.

4. The semiconductor device according to claim 3, wherein the distance between a plurality of adjacent groups of raised portions is 100 μm or less.

5. The semiconductor device according to claim 4, wherein the distance is 50 μm or less.

6. The semiconductor device according to claim 4 or 5, wherein the distance is 20 μm or less.

7. The semiconductor device according to any one of claims 1 to 6, wherein the group of raised portions is formed on the second main surface in a range of 10 μm to 200 μm with respect to a direction perpendicular to the first direction.

8. The semiconductor device according to claim 7, wherein the range is 50 μm or more and 150 μm or less.

9. The semiconductor device according to claim 7 or 8, wherein the range is 80 μm or more and 120 μm or less.

10. The SiC semiconductor layer comprises 4H-SiC, The semiconductor device according to any one of claims 1 to 9, wherein the first direction is the [11-20] direction of the 4H-SiC.

11. The SiC semiconductor layer comprises 4H-SiC, The semiconductor device according to any one of claims 1 to 9, wherein the first direction is the [1-100] direction of the 4H-SiC.

12. The semiconductor device according to claim 10 or 11, wherein the SiC semiconductor layer has an off-angle that is tilted at an angle of 10° or less with respect to the [11-20] direction from the (0001) plane of the 4H-SiC.

13. The semiconductor device according to claim 12, wherein the aforementioned off-angle is 0° or more and 4° or less.

14. The semiconductor device according to claim 12 or 13, wherein the off-angle is greater than 0° and less than 4°.

15. The semiconductor device according to any one of claims 1 to 14, further comprising grooves formed on the second main surface of the SiC semiconductor layer.

16. The semiconductor device according to claim 15, wherein the groove includes a portion that intersects the group of raised portions.

17. The semiconductor device according to claim 15 or 16, wherein the group of raised portions includes a portion in a plan view taken from the direction normal to the second main surface in which some of the multiple raised portions are formed at intervals along the groove.

18. The semiconductor device according to any one of claims 1 to 17, wherein the semiconductor element includes a Schottky barrier diode.

19. The semiconductor device according to any one of claims 1 to 17, wherein the semiconductor element includes a field-effect transistor.

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