Cryogenic interface system, quantum information processing system, and method for driving the same

Abstract

In large-scale quantum computers, heat inflow due to wiring and the negative impact on qubits due to heat generation from optical interfaces are significant challenges. Conventional fixed connections have been unable to resolve the trade-off between heat and information. [Solution] In the interface system of the present invention, a signal processing circuit (120) driven by power extracted from light as the main power source in a first cooling stage (100) synthesizes analog operation signals from logic information in place and supplies them to a second cooling stage (200) via low-loss wiring (140). Furthermore, the quantum information processing system includes a shuttle path (220) for physically transporting qubits (Q) from the computation area (210a) to the communication area (210b), and minimizes thermal noise by performing power gating of the interface in synchronization with this transport.

Description

Technical Field

[0001] The present invention relates to interface technology for controlling electronic equipment such as quantum computers that operate in cryogenic environments, and in particular to a cryogenic interface system, a quantum information processing system, and a driving method thereof for performing high-speed, low-latency qubit control and error correction processing while blocking heat inflow from room temperature environments.

Background Art

[0002] Quantum devices such as superconducting qubits, ion traps, and neutral atoms need to operate in cryogenic environments of about 10 mK (millikelvin) to 100 mK to suppress thermal noise. Currently, with the scaling up of quantum computers, the number of coaxial cables connecting room-temperature control devices and cryogenic quantum processors has increased, and the "Wiring Bottleneck", in which heat inflow through these metal wires strains the cooling capacity of refrigerators, has become a serious issue .

[0003] Furthermore, in quantum information processing using neutral atom arrays or ion trap schemes, shuttling technology that physically transports qubits within a potential (Quantum Charge-Coupled Device: QCCD architecture, etc.) is known. However, conventional shuttling is mainly aimed at implementing logic gates, and the configuration as a thermal management architecture that physically separates the "computation area" and the "communication area" for quantum communication with the room-temperature side and interfacing with optical transducers, and transports qubits to the communication area only when communication is required has not been sufficiently studied.

[0004] Prior art has disclosed a configuration (Power over Fiber) in which a photodiode placed in an intermediate cooling stage converts an optical signal into an electrical signal and relays it directly to the next stage. However, this is merely a transparent relay of the signal and does not consider active signal generation in the intermediate stage or spatial isolation between the arrangement of qubits and the heat source. Furthermore, the output voltage of the photoelectric conversion element is low and insufficient to generate the high-voltage RF signals required for ion traps, etc. [Overview of the project] [Problems that the invention aims to solve]

[0005] In particular, in conventional configurations where quantum devices and optical transducers are fixedly integrated on a chip, the powerful optical pumps and electric drive circuits required to drive the transducers become sources of heat and noise, resulting in an essential trade-off between reduced qubit coherence and improved optical conversion efficiency. In other words, the physical superposition of "heat and information" pathways, in addition to wiring bottlenecks, is a fundamental obstacle to the practical application of large-scale quantum processors. This invention has been made in view of the above problems, and aims to provide a system that minimizes heat inflow to the coldest point while achieving high-precision quantum control and error correction by defining the intermediate cooling stage as an active processing layer that separates and converts heat and information, and by utilizing the physical movement (shuttle) of qubits. [Means for solving the problem]

[0006] The present invention provides an interface system that performs "energy medium conversion" and "information quality conversion" in an intermediate cooling stage (first cooling stage) located between room temperature and a quantum device (coldest point). Specifically, "light energy" and "logical control information" are transmitted from room temperature, and the first cooling system The signal processing circuit positioned on the stage uses the received power as its primary power source and synthesizes analog operation signals on the spot based on logical information. This prevents heat inflow associated with conductive wiring and analog signal relay.

[0007] Furthermore, the quantum information processing system of the present invention eliminates the aforementioned trade-off by separating the energy and information transmission path (interface section) from room temperature to cryogenic temperatures from the arrangement of the qubits themselves, and by adopting a configuration that physically transfers the qubits from the computation area to the communication area. In other words, the transducers and signal processing circuits are kept in standby (sleep) mode when no qubits are present, and the qubits are shuttled to the communication domain only when communication or reading is required, synchronously activating the optical power supply system through "dynamic thermal management (Power Gating)." This dramatically reduces the average heat generation over time. [Effects of the Invention]

[0008] According to the present invention, by eliminating physical conductive wiring connecting room temperature and the cryogenic section, and synthesizing the control waveform in close proximity to the quantum device, high-precision quantum control becomes possible, which is less susceptible to the bandwidth limitations and thermal noise of the wiring. Furthermore, by integrating with shuttle technology, the interface section, which is a heat source, and the computing core section can be physically separated. This makes it possible to maintain the qubit coherence time even when scaling up, which will greatly contribute to the practical application of fault-tolerant quantum computers. [Brief explanation of the drawing]

[0009] [Figure 1] This is a configuration diagram of an interface system according to the first embodiment of the present invention. [Figure 2] This is a detailed circuit block diagram including the light receiving and conversion section, the hybrid drive circuit, and the filter structure. [Figure 3] This is a conceptual diagram of a shuttle-type quantum information processing system according to a third embodiment of the present invention. [Modes for carrying out the invention]

[0010] [First Embodiment: Interface System] Figure 1 shows the configuration of a cryogenic interface system 10 according to one embodiment of the present invention. Light from an external light source 30 is transmitted to a first cooling stage 100 (e.g., 4K) via an optical medium 31. In this specification, "optical medium" refers to a form of non-conductive interface that has electrical insulation properties and is capable of transmitting energy and information. This is a broad concept that includes not only optical fiber cables but also spatial optical transmission lines and insulated waveguide structures.

[0011] The power extracted by the light receiving and conversion unit 110 drives the signal processing circuit 120. The light receiving and conversion unit 110 uses an InGaAs or GaAs-based photovoltaic cell (PV) optimized for operation in cryogenic environments, and a high-density energy buffer such as a deep trench capacitor is connected to the subsequent stage. This enables shuttle transition By accumulating light energy during idle periods such as when the system is in operation, it becomes possible to compensate for the instantaneous peak power during gate operations. While the present invention primarily aims to eliminate heat inflow from the room temperature environment through conductive wiring, it does not preclude the use of auxiliary conductive wiring that is so fine or highly resistive that heat inflow is negligible, for system initialization or bias adjustment. However, steady-state drive power is mainly supplied by the light receiving and conversion unit 110.

[0012] In this embodiment, the signal processing circuit 120 does not consume high power continuously at all times, but rather consumes high power intermittently (in bursts) in synchronization with the operation timing of the quantum device, and The system may be configured to reduce power consumption during the operating period (idle period). This allows the high-density energy buffer to cover peak power consumption even when the average power supplied from the light receiving conversion unit 110 is relatively small.

[0013] For example, the length of the idle period is T_idle, and the signal is sent from the light receiving conversion unit 110 to the signal processing circuit 120. If the average power supplied is P_avg and the charge / discharge efficiency of the energy buffer is η_buf (0 < η_buf ≤ 1), then the energy E_store that can be stored in the buffer during the idle period is approximately E_store ≒ η_buf·P_avg·T_idle It is expressed as follows. On the other hand, in a single operation of a quantum device (e.g., gate operation or readout operation), if the load capacitance is C_load and the drive voltage amplitude is V_drive, then the idealized charge and discharge The energy E_req required is approximately E_req ≈ C_load·V_drive^2 It can be estimated as follows (in reality, E_req can be estimated to be a larger value because it includes wiring losses, switching losses, etc.).

[0014] Therefore, in the design, circuit parameters such as P_avg, T_idle, C_load, V_drive, buffer capacitance, and equivalent series resistance (ESR) should be selected so that E_store is greater than or equal to E_req (or required energy including losses) for the desired operating sequence. Within the range where such energy budget conditions are met, it becomes possible to operate the quantum device using optical power supply and an energy buffer without the need for steady-state power supply from conductive wiring at room temperature.

[0015] The signal processing circuit 120 generates an RF signal to drive a quantum device (e.g., an ion trap electrode) based on logic control information. In this context, using single-flux quantum (SFQ) circuits, which consume extremely low power, is thermally advantageous for digital processing such as logical operations and error detection. SFQ circuits have extremely low switching energy, approximately 10⁻¹⁹ joules, and can synthesize highly accurate voltage waveforms using architectures such as the Josephson arbitrary waveform synthesizer (JAWS). On the other hand, driving an ion trap may require high-voltage, wide-band analog signals. Since the output voltage of a single SFQ circuit is low, cryogenic CMOS (Cryo-CMOS) is provided in the subsequent stage It is also possible to adopt a hybrid configuration in which an amplifier circuit using the above or a high electron mobility transistor (HEMT) is arranged to voltage-amplify and output minute pulses from the SFQ. This enables wide-band high-speed shuttling control. Furthermore, when a narrow bandwidth is sufficient (such as for maintaining a static trap), power consumption can be further reduced by using a resonant step-up circuit with a superconducting coil. In this way, the configuration is such that an optimal driving method is selected or switched according to the application (shuttle movement or static holding).

[0016] Here, when driving a quantum device (e.g., an ion trap electrode) requires a voltage amplitude of several volts or more, and it is required that the output voltage amplitude of the signal processing circuit 120 is sufficiently large relative to the DC voltage obtained from the light receiving conversion unit 110, a configuration using a resonant step-up circuit is particularly effective, and in some cases, it may be employed as a substantially essential configuration to satisfy the high voltage requirement.

[0017] The resonant step-up circuit forms a resonant system consisting of a superconducting inductance component and a capacitance component, and enables generation of a high-frequency signal with a larger voltage amplitude relative to the input through energy storage and circulation near the resonant frequency. In a cryogenic environment, wiring resistance can be reduced, so the quality factor (Q) of the resonant system can be increased, making it easier to obtain a desired voltage amplitude more efficiently even under the same input conditions.

[0018] Note that when wide bandwidth is required, an amplifier circuit (Cryo-CMOS, HEMT, etc.) is used Prioritizing broadband amplification, and prioritizing a resonant boost circuit when narrowband is acceptable (e.g., static trap maintenance, driving at a specific frequency), or combining both to obtain a stepped voltage amplitude, is also possible. This ensures design flexibility that can be implemented according to the desired voltage amplitude, bandwidth, and power consumption requirements.

[0019] The generated signal is output to a second cooling stage 200 (e.g., 10 mK) via a thermal anchor 150 and a passive filter 160, and then through low-loss wiring 140 such as superconducting wiring. Here, the photoreception and conversion unit 110 may include, in addition to the photoelectric conversion function (reception), an optical modulation function (transmission unit) for transmitting information supplied from the signal processing circuit 120 to the room temperature side.

[0020] [Second Embodiment: Loss Error Detection Function] The signal processing circuit 120 also has the function of processing the readout signals from the qubits. In particular, for dual-rail encoded qubits, it has the function of detecting the state in which the signals from both rails are "0" (no photons) as a physical "erasure" using an SFQ compass. Includes a rectifier circuit. This comparator immediately generates flag information upon detecting a loss error. Since this process is completed within the first cooling stage, latency is significantly reduced compared to cases where the signal is sent back and forth to room temperature, enabling high-speed feedback control.

[0021] [Third Embodiment: Shuttle-Type Quantum Information Processing System] As shown in Figure 3, the quantum device array 210 on the second cooling stage 200 is divided into a computation area 210a and a communication area 210b (a holding area 210c may be provided if necessary). The qubits Q (ions or atoms) are normally located in the computation area 210a and are not affected by thermal influence from the interface system 10. When external communication or readout is required, the qubit Q is physically transported to the communication area 210b via the shuttle path 220. At this time, the system transitions the interface system 10 from sleep state to active state (power gating) in accordance with the timing of the qubit's movement. After signal exchange in the communication area 210b, the qubit Q returns to the computation area 210a, and the interface system 10 returns to the low-power state.

[0022] In this embodiment, the interface system 10 is activated only for the time necessary for signal transmission in the communication domain 210b, and remains in a low-power state (sleep state) at all other times, thereby suppressing thermal disturbances to the second cooling stage 200 (e.g., 10mK). That is, for heat generated on the first cooling stage 100 side (e.g., 4K) to propagate to the second cooling stage 200 side, a finite heat conduction process is required via low-loss wiring 140, thermal anchors 150, passive filters 160, etc., and this heat propagation involves a time delay (thermal time constant). Therefore, by transferring the qubit Q to the communication domain 210b to activate the interface system 10 for a short time, and then returning the qubit Q to the computation domain 210a and returning the interface system 10 to the low-power state after signal transmission, the time window in which the qubit Q is susceptible to thermal influences can be reduced. [Industrial applicability]

[0023] This invention can be used as a control platform for superconducting quantum computers, ion trap type quantum computers, neutral atom type quantum computers, and the like, and is an indispensable technology in realizing large-scale distributed quantum systems of several thousand qubits or more. [Explanation of Symbols]

[0024] 10 Interface Systems 100 First cooling stage (4K) 110 Light receiving and conversion section (including PV and deep groove capacitor) 120 Signal processing circuits (including SFQ, CMOS amplifier, and resonant boost circuit) 130 Monitoring Department 140 Low-loss wiring (superconducting wiring) 150 Thermal anchor structure 160 Passive filter circuit 200 Second cooling stage (10mK) 210 Quantum Device Arrays 210a calculation area 210b Communication area 210c holding area 220 Shuttle Routes Q qubit

Claims

1. An interface system for operating a quantum device on a second cooling stage in an extremely low-temperature environment having a first cooling stage maintained at a first temperature and a second cooling stage maintained at a second temperature lower than the first temperature, A light receiving and conversion unit that receives light transmitted via an optical medium from a light source placed in a room temperature environment and extracts at least a portion of power and logical control information from said light, A signal processing circuit is arranged in the first cooling stage, uses the power extracted by the light receiving conversion unit as its main drive source, operates without receiving a steady power supply from the room temperature side via conductive wiring, and takes the logic control information as input. Equipped with, The signal processing circuit generates analog operation signals within the first cooling stage for physically driving or controlling the quantum device based on the input logic control information. The analog operation signal is output to the second cooling stage via low-loss wiring, at least a portion of which is made of superconducting material. An interface system characterized by the following:

2. The signal processing circuit includes a cryogenic drive circuit that takes the DC voltage supplied from the light receiving conversion unit as input and generates a high-frequency signal or pulse signal having a voltage amplitude higher than the DC voltage necessary for driving the quantum device. The cryogenic drive circuit is A resonant boost circuit that utilizes the resonance phenomenon of superconducting inductance and capacitance components. Amplifier circuit using semiconductor transistors that operate in extremely low temperature environments, Or an optical drive circuit that sequentially drives multiple photoelectric conversion elements connected in series, The interface system according to claim 1, characterized in that it is composed of at least one of the following.

3. The signal processing circuit receives a signal related to the state of the quantum device as input from the second cooling stage via the low-loss wiring, and performs an analysis process to determine the type of error contained in the signal, or flag information indicating an Erasure Error, from the first Generated within the cooling stage, The flag information or determination result is supplied to the light receiving conversion unit as logical control information for transmitting to the room temperature environment. The interface system according to claim 1.

4. The light receiving conversion unit has a plurality of conversion elements or light receiving regions, The first cooling stage further includes a monitoring unit that monitors the local heat generation state or power supply state in the light receiving conversion unit. The monitoring unit controls the light receiving conversion unit or the signal processing circuit to dynamically change the light energy receiving position or the power extraction path based on the monitoring results. The interface system according to claim 1.

5. The light receiving conversion unit and the signal processing circuit are thermally connected to the heat sink of the first cooling stage, The output terminal of the analog control signal is connected to the low-loss wiring via a thermal anchor structure that is thermally separated from the heat sink of the first cooling stage. The first cooling stage has a thermal structure that prevents the thermal load generated by signal generation in the light receiving conversion unit and the signal processing circuit from propagating to the second cooling stage. The interface system according to claim 1.

6. A quantum information processing system having a quantum device array placed in an extremely low-temperature environment, wherein the quantum device array includes an operation domain for performing quantum logic operations and a communication domain used for quantum communication or measurement with the outside, A shuttle path is provided for physically transporting individual qubits between the respective regions. In the aforementioned communication domain, the interface system described in any one of claims 1 to 5 is used to perform conversion or reading of quantum information between the qubit and the optical medium, The system includes dynamic thermal management control means that activates the supply of optical energy to the interface system or the signal generation operation in synchronization with the period during which the qubit resides in the communication domain or during the period during which an operation in the communication domain is required, and transitions to a low-power state during other periods. A quantum information processing system characterized by the following features.

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