Manufacturing method for semiconductor devices

Abstract

To inspect a dopant concentration distribution inside a semiconductor device without destroying the semiconductor device.SOLUTION: A manufacturing method for a semiconductor device has the steps for forming a first diffusion region (26) by ion-implantation of a dopant into an element region (20) of a semiconductor wafer, forming a second diffusion region (56) by ion-implantation of a dopant into a dicing region of the semiconductor wafer under the same conditions as those for ion-implantation into the first diffusion region, dicing the semiconductor wafer so that the second diffusion region is exposed on a cut surface, and measuring a dopant concentration distribution in the second diffusion region by contacting a probe (80) to the cut surface.SELECTED DRAWING: Figure 11

Description

Technical Field

[0001] The technology disclosed in the present specification relates to a method for manufacturing a semiconductor device.

[0002] Patent Document 1 discloses a technique for measuring a dopant concentration distribution inside a semiconductor device using a scanning probe microscope. As scanning probe microscopes, for example, scanning capacitance microscopes (i.e., SCM: Scanning Capacitance Microscope) and scanning spreading resistance microscopes (i.e., SSRM: Scanning Spreading Resistance Microscope) are known. In the measurement method of Patent Document 1, a semiconductor device is cut, a probe of a scanning probe microscope is brought into contact with the cut surface, and the dopant concentration distribution on the cut surface is measured. This enables measurement of the dopant concentration distribution inside the semiconductor device.

Prior Art Literature

Patent Literature

[0003]

Patent Document 1

Summary of the Invention

Problem to be Solved by the Invention

[0004] In the technique of Patent Document 1, a semiconductor device is cut to measure the dopant concentration distribution inside the semiconductor device. For this reason, non-destructive inspection of the semiconductor device cannot be performed. The present specification proposes a technique for inspecting the dopant concentration distribution inside a semiconductor device without destroying the semiconductor device.

Means for Solving the Problem

[0005] A method for manufacturing a semiconductor device disclosed herein includes the steps of: forming a first diffusion region by ion implanting a dopant into an element region of a semiconductor wafer; forming a second diffusion region by ion implanting a dopant into a dicing region of the semiconductor wafer under the same conditions as ion implantation for the first diffusion region; dicing the semiconductor wafer such that the second diffusion region is exposed on the cut surface; and measuring the dopant concentration distribution in the second diffusion region by contacting a probe with the cut surface.

[0006] The above "conditions" include at least one of the following: ion implantation acceleration voltage, ion species to be implanted, dose amount during ion implantation, ion implantation tilt angle, and ion implantation twist angle.

[0007] In this manufacturing method, a second diffusion region is formed by ion implanting a dopant into the dicing region of a semiconductor wafer under the same conditions as ion implantation for the first diffusion region. Therefore, the dopant is distributed in the second diffusion region in a manner corresponding to that of the first diffusion region. Subsequently, the semiconductor wafer is diced so that the second diffusion region is exposed on the cut surface, and the dopant concentration distribution within the second diffusion region is measured by contacting a probe with the cut surface. Since the dopant is distributed in the second diffusion region in a manner corresponding to that of the first diffusion region, the dopant concentration distribution in the first diffusion region (i.e., inside the semiconductor device) can be inspected by measuring the dopant concentration distribution in the second diffusion region. Thus, this manufacturing method makes it possible to inspect the dopant concentration distribution inside a semiconductor device without damaging the semiconductor device. [Brief explanation of the drawing]

[0008] [Figure 1] Magnified view of the top surface of a semiconductor wafer. [Figure 2] Diagram illustrating the element formation process. [Figure 3] Diagram illustrating the element formation process. [Figure 4] Diagram illustrating the element formation process. [Figure 5] Diagram illustrating the element formation process. [Figure 6] Diagram illustrating the element formation process. [Figure 7] Diagram illustrating the element formation process. [Figure 8] Diagram illustrating the element formation process. [Figure 9] Diagram illustrating the dicing process. [Figure 10] Diagram illustrating the dicing process. [Figure 11] Diagram illustrating the inspection process. [Modes for carrying out the invention]

[0009] In one example of a manufacturing method disclosed herein, ion implantation into the first diffusion region and ion implantation into the second diffusion region may be performed simultaneously.

[0010] This configuration allows ion implantation into the first diffusion region and ion implantation into the second diffusion region to be performed under the same conditions.

[0011] In one example of a manufacturing method disclosed herein, the dopant may be ion-implanted into the element region through a mask having a first opening during ion implantation of the first diffusion region, and the dopant may be ion-implanted into the dicing region through a mask having a second opening during ion implantation of the second diffusion region. In this case, the width of the first opening may be substantially equal to the width of the second opening.

[0012] Furthermore, the statement that the width of the first opening is substantially equal to the width of the second opening means that the width of the first opening is within the error range during opening formation relative to the width of the second opening.

[0013] With this configuration, the dopant concentration distribution in the second diffusion region becomes closer to the dopant concentration distribution in the first diffusion region, allowing for a more accurate examination of the dopant concentration distribution in the first diffusion region.

[0014] In an example manufacturing method disclosed in the present specification, in the step of dicing the semiconductor wafer, dicing may be performed by cleavage.

[0015] According to this configuration, crystals are less likely to be destroyed on the cut surface, so the dopant concentration distribution in the second diffusion region can be suitably measured.

[0016] The example manufacturing method disclosed in the present specification may further comprise a step of forming an electrode (46) electrically connected to the second diffusion region without intermediation of a pn junction. In the step of measuring the dopant concentration distribution in the second diffusion region, a current may be passed between the probe and the electrode.

[0017] According to this configuration, the dopant concentration distribution in the second diffusion region can be suitably measured.

[0018] Figure 1 is an enlarged view of an upper surface of a semiconductor wafer used in the manufacturing method according to an embodiment. The semiconductor wafer is made of a semiconductor such as Si, SiC, or GaN. The entire semiconductor wafer before processing is constituted by an n-type drain region 22 shown in Figure 2 and the like. As shown in Figure 1, a plurality of element regions 20, a dicing region 50, and a TEG region 52 are defined on the upper surface of the semiconductor wafer. Note that the element regions 20, the dicing region 50, and the TEG region 52 are virtually defined regions, and are regions that cannot be visually recognized in the stage before processing. The element regions 20 are regions where semiconductor elements are formed in an element formation step described later. On the upper surface of the semiconductor wafer, the plurality of element regions 20 are defined in a matrix. The dicing region 50 is a space provided between each of the element regions 20. The dicing region 50 is a region to be cut in a dicing step described later. The TEG region 52 is defined within the dicing region 50. The TEG region 52 is a region where a TEG (Test Element Group) is formed in an element formation step described later.

[0019] Figures 2 to 8 are cross-sectional views of a semiconductor wafer during a manufacturing process. In each of Figures 2 to 8, the left diagram (a) is a cross-section of the element region 20 at the position of line A-A in Figure 1, and the right diagram (b) is a cross-section of the TEG region 52 at the position of line B-B in Figure 1. In the manufacturing method of the embodiment, an element forming step, a dicing step and an inspection step are performed in this order.

[0020] (Element forming step) First, as shown in Figure 2, an n-type first drift region 24 is formed on a drain region 22 by epitaxial growth. The first drift region 24 is an n-type region having a lower n-type impurity concentration than the drain region 22. The first drift region 24 is formed over the entire area of the element region 20 and the dicing region 50.

[0021] Next, as shown in Figure 3, a mask layer 70 is formed on the first drift region 24. The mask layer 70 is formed over the entire area of the element region 20 and the dicing region 50. Next, openings 70a and 70b are formed in the mask layer 70. Here, a plurality of openings 70a are formed in the element region 20, and a plurality of openings 70b are formed in the TEG region 52. Although not shown in the drawings, a large number of openings 70a are formed in a wide range in the element region 20. The number of openings 70b formed in the TEG region 52 is smaller than the number of openings 70a formed in the element region 20. The openings 70a and 70b extend long in a direction perpendicular to the plane of Figure 3. The longitudinal dimension of the opening 70a is larger than the longitudinal dimension of the opening 70b. The width W70a of the opening 70a is equal to the width W70b of the opening 70b.

[0022] Next, as shown in Figure 4, p-type impurities are implanted into the first drift region 24 from above via the mask layer 70. This forms multiple p-type regions 26 in the device region 20 and multiple p-type regions 56 in the TEG region 52. Since p-type impurities are implanted into the device region 20 and the TEG region 52 simultaneously in a single ion implantation, p-type impurities are implanted into the device region 20 (i.e., p-type region 26) and the TEG region 52 (i.e., p-type region 56) under the same conditions. That is, the acceleration voltage is equal, the implanted ion species are equal, the dose is equal, the tilt angle is equal, and the twist angle is equal for ion implantation into the p-type region 26 and ion implantation into the p-type region 56. Also, as mentioned above, the width W70a of the opening 70a and the width W70b of the opening 70b are equal. Therefore, in the cross-section shown in Figure 4, the shape of the p-type region 26 and the shape of the p-type region 56 are approximately equal. Furthermore, in the cross-section shown in Figure 4, the p-type impurity concentration distribution in the p-type region 26 and the p-type impurity concentration distribution in the p-type region 56 are approximately equal. After the formation of the p-type regions 26 and 56, the mask layer 70 is removed.

[0023] Next, as shown in Figure 5, a second n-type drift region 30 is formed on the semiconductor wafer by epitaxial growth. The second drift region 30 is an n-type region having approximately the same n-type impurity concentration as the first drift region 24. The second drift region 30 is formed over the entire area of ​​the device region 20 and the dicing region 50.

[0024] Next, as shown in Figure 6, a mask layer 72 is formed on the second drift region 30. The mask layer 72 is formed over the entire area of ​​the element region 20 and the dicing region 50. Next, openings 72a and 72b are formed in the mask layer 72. Here, multiple openings 72a are formed in the element region 20, and multiple openings 72b are formed in the TEG region 52. Here, an opening 72a is formed above each p-type region 26, and an opening 72b is formed above each p-type region 56. The width W72a of the opening 72a is equal to the width W72b of the opening 72b. The widths W72a and W72b are narrower than the widths W70a and W70b.

[0025] Next, as shown in Figure 7, p-type impurities are implanted into the second drift region 30 from above via the mask layer 72. This forms multiple p-type regions 27 in the device region 20 and multiple p-type regions 57 in the TEG region 52. A p-type region 27 is formed above each p-type region 26, connected to the p-type region 26. Hereafter, p-type regions 26 and 27 will be collectively referred to as p-type region 28. A p-type region 57 is formed above each p-type region 56, connected to the p-type region 56. Hereafter, p-type regions 56 and 57 will be collectively referred to as p-type region 58. Since p-type impurities are implanted into the device region 20 and the TEG region 52 simultaneously in a single ion implantation, p-type impurities are implanted into the device region 20 (i.e., p-type region 27) and the TEG region 52 (i.e., p-type region 57) under the same conditions. In other words, the acceleration voltage is the same for ion implantation into p-type region 27 and ion implantation into p-type region 57, the implanted ion species are the same, the dose is the same, the tilt angle is the same, and the twist angle is the same. Also, as described above, the width W72a of opening 72a and the width W72b of opening 72b are the same. Therefore, in the cross-section shown in Figure 7, the shape of p-type region 27 and the shape of p-type region 57 are approximately the same. Also, in the cross-section shown in Figure 7, the p-type impurity concentration distribution in p-type region 27 and the p-type impurity concentration distribution in p-type region 57 are approximately the same. After the formation of p-type regions 27 and 57, the mask layer 72 is removed.

[0026] Next, as shown in Figure 8, within the device region 20, a semiconductor layer is further stacked on the semiconductor wafer (i.e., above the second drift region 30 and the p-type region 27), and a p-type body region 32, a p-type contact region 34, and an n-type source region 36 are formed within the stacked semiconductor layers. Also, within the device region 20, a gate insulating film 38, a gate electrode 40, an interlayer insulating film 42, and a source electrode 44 are formed on the semiconductor wafer. As shown in Figure 8, the body region 32, contact region 34, source region 36, gate insulating film 38, gate electrode 40, interlayer insulating film 42, and source electrode 44 are not formed within the dicing region 50, which includes the TEG region 52. Next, as shown in Figure 8, an inspection electrode 46 is formed within the TEG region 52, in contact with the upper surface of the second drift region 30 and the upper surface of the p-type region 57. The inspection electrode 46 may be connected to the source electrode 44 or separated from the source electrode 44. Note that the inspection electrode 46 may be formed at the same time as the source electrode 44. Next, a drain electrode 48 is formed on the lower surface of the semiconductor wafer, in contact with the drain region 22. The drain electrode 48 is formed over the entire lower surface of the semiconductor wafer.

[0027] As shown in Figure 8, a MOSFET (metal-oxide-semiconductor field effect transistor) is formed within the element region 20 by the processing. Within the drift regions 24 and 30, a superjunction structure is provided by multiple p-type regions 28 arranged at intervals. Therefore, the MOSFET has a high breakdown voltage. In addition, within the TEG region 52, a p-type region 58 is formed which has almost the same cross-sectional shape and p-type impurity concentration distribution as the p-type region 28. Since no current flows through the TEG region 52 when the semiconductor device is in use, the TEG region 52 has almost no effect on the characteristics of the MOSFET.

[0028] (Dicing process) Next, the semiconductor wafer is divided into multiple chips (i.e., semiconductor devices) by dicing. Here, the semiconductor wafer is divided along the center line 50c of each dicing region 50 shown in Figure 1. Figures 9 and 10 show the details of the dicing process. In the dicing process, first, as shown in Figure 9, with the upper surface of the semiconductor wafer supported by a suction table 94, a roller blade 90 is pressed against the lower surface of the semiconductor wafer. This forms a crack 92 along the thickness direction of the semiconductor wafer at the location on the lower surface of the semiconductor wafer that is pressed by the roller blade 90. Here, the roller blade 90 is moved along the center line 50c of the dicing region 50 to form the crack 92 along the center line 50c. Next, as shown in Figure 10, the area of ​​the lower surface of the semiconductor wafer that does not overlap with the center of the dicing region 50 is supported by a support plate 96. Next, with the semiconductor wafer supported by the support plate 96, the tip of a separation plate 98 is pressed against the upper surface of the semiconductor wafer along the center line 50c. When the separator plate 98 is pressed against the upper surface of the semiconductor wafer, the semiconductor wafer cleaves along the crack 92 (i.e., along the center line 50c in Figure 1). This divides the semiconductor wafer into multiple semiconductor devices. When the semiconductor wafer is divided, the cross-section of the p-type region 58 of the TEG region 52 shown in Figure 8(b) is exposed on the cut surface.

[0029] (Inspection process) Next, the inspection process of the semiconductor device is performed. In the inspection process, the p-type impurity concentration distribution within the p-type region 58 is measured by SCM or SRRM. As described above, the p-type region 58 is exposed on the side surface of each semiconductor device (i.e., the cut surface in the dicing process). In the inspection process, as shown in Figure 11, the probe 80 of the inspection device is brought into contact with the p-type region 58 exposed on the side surface of the semiconductor device. The conductive stage 82 of the inspection device is also brought into contact with the inspection electrode 46. Then, a current is passed between the probe 80 and the inspection electrode 46. By scanning the surface of the p-type region 58 with the probe 80 while passing this current, the p-type impurity concentration distribution within the p-type region 58 is measured. Since the p-type region 58 is electrically connected to the inspection electrode 46 without a pn junction, the p-type impurity concentration distribution within the p-type region 58 can be accurately measured in the inspection process without being affected by the pn junction. The p-type impurity concentration distribution within the p-type region 58 is approximately equal to the p-type impurity concentration distribution within the p-type region 28. Therefore, the inspection process allows for the determination of the p-type impurity concentration distribution within the p-type region 28. Thus, this method allows for the inspection of the p-type impurity concentration distribution within the p-type region 28 without damaging the semiconductor device.

[0030] As described above, this manufacturing method allows for inspection of the p-type impurity concentration distribution within the p-type region 28 without damaging the semiconductor device. This enables the manufacture of highly reliable semiconductor devices that have undergone inspection.

[0031] In the embodiment described above, ion implantation into the p-type region 26 and ion implantation into the p-type region 56 were performed simultaneously. However, ion implantation into the p-type region 26 and ion implantation into the p-type region 56 may be performed in separate steps. Even when these are performed in separate steps, if ion implantation into the p-type region 26 and ion implantation into the p-type region 56 are performed under the same conditions, a p-type impurity concentration distribution almost identical to that in the p-type region 26 can be formed in the p-type region 56. Similarly, ion implantation into the p-type region 27 and ion implantation into the p-type region 57 may be performed in separate steps.

[0032] Furthermore, in the embodiments described above, the p-type region 28 formed by ion implantation was inspected, but the n-type region formed by ion implantation may also be inspected by the techniques disclosed herein. In this case, the n-type region within the device region can be inspected by forming the n-type region in the device region and the TEG region by ion implantation and measuring the n-type impurity concentration distribution within the n-type region within the TEG region. In this case, the n-type impurity concentration in the n-type region within the TEG region can be accurately detected by electrically connecting the n-type region within the TEG region to the inspection electrode without a pn junction.

[0033] Furthermore, in the embodiments described above, the semiconductor wafer was cleaved using a roller blade 90, but the semiconductor wafer may be cleaved by other methods. Alternatively, the semiconductor wafer may be diced by cutting using a dicing saw or the like. However, in this case, a damaged layer with destroyed crystallinity is formed on the cut surface after cutting. Therefore, it may be necessary to remove the damaged layer by etching or the like. In contrast, when dicing is performed by cleavage, a cut surface with high crystallinity can be formed.

[0034] The components of the technology disclosed herein are listed below. (Composition 1) A method for manufacturing a semiconductor device, A process of forming a first diffusion region by ion implanting a dopant into the device region of a semiconductor wafer, A step of forming a second diffusion region by ion implanting a dopant into the dicing region of the semiconductor wafer under the same conditions as ion implantation for the first diffusion region, A step of dicing the semiconductor wafer such that the second diffusion region is exposed on the cut surface, A step of measuring the dopant concentration distribution in the second diffusion region by bringing a probe into contact with the cut surface, A manufacturing method having the following characteristics. (Configuration 2) The manufacturing method according to configuration 1, wherein ion implantation into the first diffusion region and ion implantation into the second diffusion region are performed simultaneously. (Composition 3) In the ion implantation of the first diffusion region, a dopant is implanted into the element region through a mask having a first opening. In the ion implantation of the second diffusion region, the dopant is injected into the dicing region through a mask provided with a second opening. The width of the first opening is substantially equal to the width of the second opening. The manufacturing method described in configuration 1 or 2. (Composition 4) The manufacturing method according to any one of configurations 1 to 3, wherein the step of dicing the semiconductor wafer is performed by cleavage. (Composition 5) The process further comprises the step of forming electrodes on the surface of the semiconductor wafer, The second diffusion region is electrically connected to the electrode without a pn junction. In the step of measuring the dopant concentration distribution within the second diffusion region, a current is passed between the probe and the electrode. A manufacturing method described in any one of items 1 to 4 of the composition.

[0035] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of Symbols]

[0036] 20: Element region, 24: First drift region, 28: p-type region, 30: Second drift region, 46: Test electrode, 50: Dicing region, 52: TEG region, 58: p-type region, 80: Probe

Claims

1. A method for manufacturing a semiconductor device, A step of forming a first diffusion region (26) by ion implanting a dopant into the element region (20) of a semiconductor wafer, A step of forming a second diffusion region (56) by ion implanting a dopant into the dicing region of the semiconductor wafer under the same conditions as ion implantation for the first diffusion region, A step of dicing the semiconductor wafer such that the second diffusion region is exposed on the cut surface, A step of measuring the dopant concentration distribution in the second diffusion region by bringing a probe (80) into contact with the cut surface, A manufacturing method having the following characteristics.

2. The manufacturing method according to claim 1, wherein ion implantation into the first diffusion region and ion implantation into the second diffusion region are performed simultaneously.

3. In the ion implantation of the first diffusion region, a dopant is ion-implanted into the element region through a mask provided with a first opening (70a). In the ion implantation of the second diffusion region, the dopant is ion-implanted into the dicing region through a mask provided with a second opening (70b). The width of the first opening is substantially equal to the width of the second opening. The manufacturing method according to claim 1 or 2.

4. The manufacturing method according to claim 1 or 2, wherein the step of dicing the semiconductor wafer is performed by cleavage.

5. The process further includes forming an electrode (46) on the surface of the semiconductor wafer that is electrically connected to the second diffusion region without a pn junction, In the step of measuring the dopant concentration distribution within the second diffusion region, a current is passed between the probe and the electrode. The manufacturing method according to claim 1 or 2.

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