Semiconductor substrate, method for manufacturing the same, and image sensor

Abstract

This application discloses a semiconductor substrate, a method for manufacturing the same, and an image sensor. The semiconductor substrate of this application includes a substrate having a first surface; a capture layer located on the side of the substrate away from the first surface and used to capture metal ions from the substrate or metal ions that have passed through the substrate; and a backside sealing layer located on the side of the capture layer away from the substrate. In this application, the capture layer is provided on one side of the base of the semiconductor substrate, thereby improving the external impurity adsorption ability of the semiconductor substrate. Using the semiconductor substrate of this application as the base of an image sensor reduces the dark current and the number of white pixels in the image sensor.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a substrate, an image sensor and a manufacturing method thereof.

[0002] The present application claims priority to the Chinese Patent Application filed with the China National Intellectual Property Administration on August 30, 2023, with the application number 202311114955.5 and the title of the invention "Semiconductor substrate, manufacturing method thereof and image sensor", the entire content of which is incorporated herein by reference. Background Art

[0003] A semiconductor substrate is a base material used in the manufacture of semiconductor devices. Silicon substrates are commonly used as semiconductor substrate materials because they have excellent electrical properties, thermal stability and processability, and the quality of silicon substrates is extremely important for the performance and manufacturing of semiconductor devices. Summary of Invention Problem to be Solved by Invention

[0004] The external impurity adsorption capacity of semiconductor substrates is relatively low, and they are susceptible to contamination by metal ions, resulting in relatively low product yield. When a semiconductor substrate is applied to a device, the dark current and the number of white pixels of the device are relatively large, which affects the quality of the chip device. Means for Solving Problem

[0005] An embodiment of the present application provides a semiconductor substrate, wherein the semiconductor substrate comprises: a substrate having a first surface; a capture layer located on a side of the substrate away from the first surface; and a back surface sealing layer located on a side of the capture layer away from the substrate.

[0006] In some embodiments, the capture layer is used to capture metal ions, the metal ions comprising metal ions in the substrate and metal ions that have passed through the first surface and entered the substrate.

[0007] In some embodiments, the thickness of the capture layer is 1000 Å to 8000 Å.

[0008] In some embodiments, the resistivity of the substrate is 0.010 ohm-cm to 0.020 ohm-cm.

[0009] Accordingly, the embodiments of the present application provide a manufacturing method relating to a semiconductor substrate, and the manufacturing method relating to the semiconductor substrate is To provide a substrate having a first surface, To form a capture layer located on the side away from the first surface of the substrate, This includes forming a back-side sealing layer located on the side of the capture layer away from the substrate.

[0010] In some embodiments, the thickness of the trapping layer in the thickness direction of the substrate is 1000 Å to 8000 Å.

[0011] In some embodiments, the step of forming the capture layer is, Forming a second polysilicon layer located on the first surface, A first polysilicon layer is formed, and the substrate has a second surface opposite to the first surface, 1 The polysilicon layer is located on the second surface, The method includes removing the second polysilicon layer, leaving the first polysilicon layer, and using the first polysilicon layer as the capture layer.

[0012] In some embodiments, the first polysilicon layer is manufactured by the following method: A polysilicon layer is deposited on the surface of the substrate using a silicon-containing gas, with the amount of silicon-containing gas used being 2 L / 1000 Å to 4 L / 1000 Å.

[0013] In some embodiments, the second polysilicon layer is manufactured by the following method: A polysilicon layer is deposited on the surface of the substrate using a silicon-containing gas, with the amount of silicon-containing gas used being 2 L / 1000 Å to 4 L / 1000 Å.

[0014] In some embodiments, during the step of forming the first polysilicon layer, the substrate is placed in an environment with a temperature range of 600°C to 660°C.

[0015] In some embodiments, during the step of forming the second polysilicon layer, the substrate is placed in an environment with a temperature range of 600°C to 660°C.

[0016] In some embodiments, the second polysilicon layer is removed by a chemical mechanical polishing method, the chemical mechanical polishing method comprising grinding the second polysilicon layer and removing the second polysilicon layer.

[0017] In some embodiments, the first substrate is adsorbed onto a polishing head, the polishing head has a cavity, and in the thickness direction of the semiconductor substrate, the cavity has a first thickness H1 μm, and the first substrate has a second thickness H2 μm, 0

[0018] Embodiments of the present application provide an image sensor comprising the semiconductor substrate described above, or comprising a semiconductor substrate manufactured by the manufacturing method relating to the semiconductor substrate described above. The semiconductor substrate serves as the base for the image sensor.

[0019] In some embodiments, the semiconductor substrate includes a P-type substrate. [Effects of the Invention]

[0020] ​The present application provides a semiconductor substrate, a method for manufacturing the same, and an image sensor. The semiconductor substrate of the present application comprises a substrate having a first surface, a capture layer located on a side away from the first surface of the substrate and used for capturing metal ions from the substrate or metal ions that have passed through the substrate, and a back surface sealing layer located on a side of the capture layer away from the substrate. According to the present application, by providing the capture layer on one side of the base body of the semiconductor substrate, the external impurity adsorption capacity of the semiconductor substrate is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Hereinafter, in order to more clearly describe the technical solutions in the embodiments of the present application, the accompanying drawings used in the description of the embodiments are briefly described. The accompanying drawings in the following description are only some of the embodiments of the present application, and it is obvious that those skilled in the art can obtain other accompanying drawings based on these drawings without creative efforts.

[0022] [Figure 1] It is a flow diagram relating to the manufacturing process of the semiconductor substrate according to an embodiment of the present application. [Figure 2] It is a flow diagram relating to the manufacturing process of the semiconductor substrate according to an embodiment of the present application. [Figure 3] It is a flow diagram relating to the manufacturing process of the semiconductor substrate according to an embodiment of the present application. [Figure 4] It is a schematic diagram showing the structure of the semiconductor substrate according to an embodiment of the present application. [Figure 5] It is a schematic diagram showing the structure of the image sensor according to an embodiment of the present application. [Figure 6] It is a schematic diagram showing the structure of a grinding disc and a semiconductor substrate according to an embodiment of the present application. [Figure 7] These are test results of geometric flatness for the manufactured semiconductor substrate according to an embodiment of the present application. Here, Figure A is the test result of the maximum local flatness SFQR, Figure B is the test result of the maximum edge flatness ESFQR, Figure C is the average value result of the maximum local flatness, Figure D is the average value result of the maximum edge flatness, and Figure E is the test result of the maximum local flatness of the 95% distribution count. [Figure 8]This is a schematic diagram showing the structure of the manufactured image sensor according to the embodiment of the present invention. [Figure 9] This is a schematic diagram showing the structure of a front-illuminated image sensor according to an embodiment of the present invention. [Figure 10] This is a test result showing that the semiconductor substrate of the embodiment of this application is used for dark current in an image sensor. [Figure 11] This is a test result showing that the semiconductor substrate of the embodiment of this application is used as a white pixel in an image sensor. [Modes for carrying out the invention]

[0023] The following describes the technical concepts in the embodiments of this application clearly and completely, but it is clear that the embodiments described are only a subset of the embodiments of this application, not all of them. All other embodiments that a person skilled in the art could obtain without inventive effort based on the embodiments of this application are within the scope of protection of this application. Furthermore, in the description of this application, the term "including" means "including, but not limited to." Terms such as "first," "second," and "third" are used merely as markers and do not enforce any numerical requirement or ordering. Each embodiment of this application may exist in a certain scope. It should be understood that descriptions in a certain scope are for convenience and brevity only and should not be interpreted as a rigid limitation on the scope of this application. Accordingly, the listed scope descriptions are considered to specifically disclose all possible partial scopes and single numerical values ​​within those scopes. For example, the description of a range from 1 to 6 specifically discloses a partial range, e.g., 1 to 3, 1 to 4, 1 to 5, 2 to 4, 2 to 6, 3 to 6, etc., and a single digit within the numerical range, e.g., 1, 2, 3, 4, 5, and 6, which applies regardless of the range. Furthermore, whenever a numerical range is indicated herein, it means that it includes any enumerated digit (fraction or integer) within the range mentioned. In this application, the X direction is the thickness direction, and the Y direction is the extension direction of the semiconductor substrate.

[0024] As shown in Figure 4, an embodiment of the present invention provides a semiconductor substrate, which includes a substrate 100 having a first surface 101, a capture layer 200 located on the side of the substrate 100 away from the first surface 101 and used to capture metal ions from the substrate 100 or metal ions that have passed through the substrate 100, and a back-side sealing layer 300 located on the side of the capture layer 200 away from the substrate 100. By providing the capture layer 200 on one side of the substrate of the semiconductor substrate 100, the present invention improves the external impurity adsorption capacity of the semiconductor substrate, effectively reduces contamination by metal ions, and increases the product yield.

[0025] In some embodiments, the thickness of the capture layer 200 is 1000 Å to 8000 Å. For example, the numerical value of the thickness (Å) of the capture layer 200 is one of the values ​​among 1000, 2000, 3000, 4000, 5000, 6000, 7000, and 8000, or a range consisting of any two of these numbers. For example, the thickness of the capture layer 200 is 1000 Å to 5000 Å, or 1000 Å to 3000 Å. In this application, since the geometric flatness of the substrate deteriorates when the capture layer 200 is provided, the thickness of the capture layer 200 in this application is within the range of 1000 Å to 8000 Å, which satisfies the external impurity adsorption capacity of the semiconductor substrate in this application and improves the degree of deterioration of the flatness of the device due to the installation of the capture layer 200.

[0026] In some embodiments, the substrate 100 uses a silicon substrate, and the resistivity of the substrate 100 is 0.010 ohm-cm to 0.020 ohm-cm. For example, the resistivity (ohm-cm) of the substrate 100 is one of the values ​​among 0.01, 0.011, 0.012, 0.013, 0.014, 0.015, 0.016, 0.017, 0.018, 0.019, and 0.020, or any two of these values.

[0027] In some embodiments, the resistivity of the substrate 100 is changed by the following methods. For example, the silicon substrate is ion-doped, and the doping method may be ion implantation. Alternatively, the resistivity of the substrate 100 is changed by adding doping elements of different concentrations to the silicon material during the manufacturing process of the silicon substrate.

[0028] In some embodiments, the capture layer 200 contains polysilicon, which is used as an impurity adsorption material to capture metal ions from the outer layer. When the semiconductor substrate of the present invention is applied to a device, it is possible to capture metal ions in the device layer and reduce the dark current and the number of white pixels of the device.

[0029] In some embodiments, the back sealing layer 300 is a silicon oxide layer, and the thickness of the back sealing layer 300 is 3000 Å to 4000 Å. For example, the thickness (Å) of the back sealing layer 300 is one of the values ​​among 3000, 3100, 3200, 3300, 3400, 3500, 3600, 3700, 3800, 3900, and 4000, or a range consisting of any two of these numbers.

[0030] In some embodiments, the back sealing layer 300 contains low-temperature silicon dioxide (LTO).

[0031] In some embodiments, the deposition temperature of the low-temperature silicon oxide is 400°C to 800°C, for example, the deposition temperature (°C) is a value from among 400, 450, 500, 550, 600, 650, 700, 750, and 800, or any two of these values. In some embodiments, the manufacturing temperature of the back sealing layer 300 is 600 to 650°C.

[0032] In some embodiments, the back-side sealing layer 300 is manufactured by the following method: Chemical vapor deposition is performed on the substrate 100 having the trapping layer 200 to manufacture the back-side sealing layer 300. In some embodiments, the range of the oxygen introduction flow rate (Standard Cubic Centimeters per Minute, sccm) is 495 to 616. In some embodiments, the range of the SiH4 introduction flow rate (Standard Cubic Centimeters per Minute, sccm) is 45 to 56.

[0033] In some embodiments, embodiments of the present application provide a method for manufacturing a semiconductor substrate, which includes the following:

[0034] As shown in Figure 1, a substrate 100 is provided, which has a first surface 101.

[0035] A capture layer 200 is formed, and the capture layer 200 is located on the side of the substrate 100 away from the first surface 101. A back sealing layer 300 is formed, and the back sealing layer 300 is located on the side of the capture layer 200 away from the substrate 100.

[0036] In some examples, the thickness of the trapping layer 200 in the substrate thickness direction X is 1000 Å to 8000 Å.

[0037] As shown in Figure 2, the step of forming the capture layer 200 includes the following:

[0038] A second polysilicon layer 220 is formed, and the second polysilicon layer 220 is located on the first surface 101.

[0039] A first polysilicon layer 210 is formed, and the substrate 100 has a second surface 102 opposite to the first surface 101. First polysilicon layer 210 It is located on the second surface 102.

[0040] As shown in Figure 3, the second polysilicon layer 220 is removed, leaving the first polysilicon layer 210. The first polysilicon layer 210 is designated as the capture layer 200.

[0041] In some embodiments, the first polysilicon layer 210 is manufactured by the following method: The first polysilicon layer 210 is deposited on the surface of the substrate 100 using a silicon-containing gas. The amount of silicon-containing gas used is 2 L / 1000 Å to 4 L / 1000 Å. For example, the value of the amount of silicon-containing gas used (L / 1000 Å) is within the range of any of 2.0, 2.5, 3.0, 3.5, or 4.0, or any two of these values. By controlling the amount of silicon-containing gas used, the thickness of the first polysilicon layer 210 can be controlled, and the deposition rate of the first polysilicon layer 210 on the surface of the substrate 100 can be further controlled, thereby reducing the influence of the manufacturing of the polysilicon layer on the flatness of the semiconductor substrate 1.

[0042] In some embodiments, the second polysilicon layer 220 is manufactured by the following method: The second polysilicon layer 220 is deposited on the surface of the substrate 100 using a silicon-containing gas. The amount of silicon-containing gas used is 2 L / 1000 Å to 4 L / 1000 Å. For example, the value of the amount of silicon-containing gas used (L / 1000 Å) is within the range of any of 2.0, 2.5, 3.0, 3.5, or 4.0, or any two of these values. By controlling the amount of silicon-containing gas used, the thickness of the second polysilicon layer 220 can be controlled, and the deposition rate of the second polysilicon layer 220 on the surface of the substrate 100 can be further controlled, thereby improving the quality of the manufactured semiconductor substrate.

[0043] In some embodiments, during the step of forming the first polysilicon layer 210, the substrate 100 is placed in an environment with a temperature range of 600°C to 660°C.

[0044] In some embodiments, during the step of forming the second polysilicon layer 220, the substrate 100 is placed in an environment with a temperature range of 600°C to 660°C.

[0045] In some embodiments, the temperature (°C) for forming the first polysilicon layer 210 is a value within the range of 600, 610, 620, 630, 6405, 650, 660, or any two of these values.

[0046] In some embodiments, the temperature (°C) for forming the second polysilicon layer 220 is a value within the range of 600, 610, 620, 630, 6405, 650, 660, or any two of these values.

[0047] In some embodiments, polysilicon layers are formed simultaneously on both sides of the substrate 100, that is, a first polysilicon layer 210 and a second polysilicon layer 220 are formed simultaneously on both sides of the substrate 100 to obtain a first substrate 110. The temperature range for forming the first polysilicon layer 210 and the second polysilicon layer 220 is 600°C to 620°C, or 640°C to 660°C.

[0048] If the thickness of the polysilicon layer to be manufactured is 4000 Å or less, it may be manufactured by the following method.

[0049] In some embodiments, the first polysilicon layer 210 and the second polysilicon layer 220 are manufactured by the following method: The polysilicon layers are manufactured when the first temperature range is 600°C to 620°C and the first flow rate of the silicon-containing gas is 3 L / 1000 Å to 4 L / 1000 Å.

[0050] In some embodiments, the polysilicon layer is manufactured when the second temperature range is 640°C to 660°C and the second flow rate of the silicon-containing gas is 2 L / 1000 Å to 3 L / 1000 Å.

[0051] If the thickness of the polysilicon layer to be manufactured is greater than 4000 Å, it may be manufactured by the following method.

[0052] In some embodiments, the first polysilicon layer 210 and the second polysilicon layer 220 are manufactured by the following method: The polysilicon layers are manufactured when the first temperature range is 600°C to 620°C and the third flow rate of the silicon-containing gas is 2.8 L / 1000 Å to 3.4 L / 1000 Å.

[0053] In some embodiments, the polysilicon layer is manufactured when the second temperature range is 640°C to 660°C and the fourth flow rate of the silicon-containing gas is 2.25 L / 1000 Å to 2.75 L / 1000 Å.

[0054] In some embodiments, the silicon-containing gas includes SiH4.

[0055] In some embodiments, the second polysilicon layer 220 is removed by chemical mechanical polishing.

[0056] As shown in Figure 6, the apparatus for performing chemical mechanical polishing includes a grinding disc 2 and a polishing head 3, the polishing head 3 having a cavity 300. When performing chemical mechanical polishing, the surface of the semiconductor substrate is adsorbed by a pressurized airbag in the intermediate gas pipe, that is, the first substrate 110 adheres closely to the polishing head 3 above by vacuum adsorption, the transport pipe delivers a grinding fluid containing etching solution and abrasive particles, and the second polysilicon layer 220 is removed by the high-speed rotation of the polishing head 3.

[0057] In some embodiments, in the thickness direction (X direction) of the semiconductor substrate 1, the cavity 300 has a first thickness H1 μm, and the substrate has a second thickness H2 μm, 0

[0058] ​In some embodiments, the difference between H1 and H2 is a distance S μm from the bottom surface 301 of the polishing head 3 to the top surface of the first substrate 110. In the present application, the bottom surface and the top surface are descriptions of orientation, and do not limit the specific structure of the present application.

[0059] In some embodiments, the distance S from the bottom surface 301 of the polishing head 3 to the top surface of the first substrate 110 satisfies 0 < S ≤ 20 μm. For example, the value of S is any one of 5, 10, 15, and 20, or a range consisting of any two of these values.

[0060] In some embodiments, the value of the first thickness H1 of the cavity 300 is 780 μm to 790 μm. For example, the value of the first thickness H1 is any one of 780, 785, and 790, or a range consisting of any two of these values.

[0061] In some embodiments, the value of the second thickness H2 of the first substrate 110 is 765 μm to 785 μm. For example, the value of the second thickness H2 is any one of 765, 770, 775, 780, and 785, or a range consisting of any two of these values.

[0062] When H1-H2 in the present application is greater than 20 μm, for example, when the height of the selected cavity 300 is 800 μm, the thickness of the first substrate 110 is 775 μm, and the thickness of the manufactured polysilicon layer is within the range of 1000 Å to 8000 Å, when a geometric flatness test is performed on the obtained substrate, the geometric flatness of the substrate decreases. On the other hand, it has been found that reducing the distance between the lower surface of the cavity 300 and the first substrate 110 can alleviate the influence of the polysilicon layer manufactured according to the present application on the deterioration of the geometric flatness of the substrate.

[0063] In some embodiments, the geometric flatness of the semiconductor substrate 1 in the present application can be represented by the maximum local flatness and the maximum edge flatness.

[0064] In some embodiments, the present invention uses an optical microscope, a scanning electron microscope (SEM), or an atomic force microscope (AFM) as the device for flatness testing.

[0065] As shown in Figures 5 and 7, an embodiment of the present invention provides an image sensor (CIS, CMOS Image Sensor), the image sensor includes the semiconductor substrate 1 described above, the semiconductor substrate 1 is the base of the image sensor, and an element layer 400 is provided on the outer layer of the semiconductor substrate 1.

[0066] As shown in Figure 7, in some embodiments, the semiconductor substrate of the present application is a P-type substrate, and the image sensor includes an NMOS transistor structure and a PMOS transistor structure. The image sensor shown in Figure 7 of the present application is intended only as the enumerated structure. The semiconductor substrate 1 of the present application may also be an N-type substrate. The image sensor may be a front-illuminated image sensor or a back-illuminated image sensor.

[0067] In some embodiments, Figure 8 is a schematic diagram showing the structure of a front-illuminated sensor provided in the present invention. The image sensor includes a sensor body, a color filter 500, and a lens 600. The sensor body includes a substrate and a CMOS element structure, i.e., an element layer 400, provided on the substrate.

[0068] In some examples, the color filter 500 is used to capture light of different colors. A variety of color filters, such as a Bayer filter or an X-Trans filter, may be selected.

[0069] In some embodiments, the lens 600 is used to collect light and guide it to the sensor. A type of lens such as a plano-convex lens or a biconvex lens may be selected.

[0070] In some embodiments, when the semiconductor substrate manufactured according to the above embodiments of the present invention is applied to an image sensor, it is possible to improve the effect of leakage due to excess metal ions in the element on the dark current and the number of white pixels under different operating temperature conditions.

[0071] In some embodiments, the average dark current of an image sensor using the semiconductor substrate 1 of the present invention ranges from 16.3 to 16.6 pixels.

[0072] In some embodiments, the range of white pixels in an image sensor to which the semiconductor substrate 1 of the present invention is applied is 200 to 250.

[0073] Example 1 is as follows:

[0074] For the semiconductor substrate, a P-type single-crystal silicon polished wafer with a diameter of 300 mm is defined as substrate 100, with a resistivity of 0.010 to 0.020 ohm-cm and an outer layer thickness H2 of 775 μm.

[0075] A substrate 100 is processed using an LPCVD furnace, the purity of the silicon-containing gas SiH4 is set to 99.9999% or higher, the purity of N2 is set to 99.9999999% or higher, polysilicon is deposited using the LPCVD furnace, and the same single-crystal silicon raw material is processed to produce a polysilicon layer. The manufacturing process is shown in Table 1.

[0076] The second polysilicon layer 220 is removed. Specifically, in the thickness direction X of the substrate, the polishing head 3 has a grinding cavity 300, and the cavity 300 has a first thickness H1 of 780 μm.

[0077] A back-side sealing layer 300 is manufactured. Specifically, an APCVD furnace is selected to process the substrate 100, the purity of the silicon-containing gas SiH4 is set to 99.9999 or higher, the purity of O2 is set to 99.9999999 or higher, and the purity of N2 is set to 99.9999999 or higher. A low-temperature oxide layer is deposited using an APCVD furnace, with a deposition temperature range of 640-650°C. The same single-crystal silicon raw material is selected and processed to manufacture the oxide layer, resulting in a back-side sealing film thickness of 3000 Å, and obtaining the semiconductor substrate shown in Figure 4.

[0078] Examples 2 to 12 are as follows.

[0079] The manufacturing method is the same as in Example 1, but the difference lies in the adjustment of the manufacturing parameters for the polysilicon layer. These are specifically shown in Table 1.

[0080] Comparative Example 1 is as follows:

[0081] We will not manufacture the 200-unit trap layer.

[0082] Manufacturing process parameters related to semiconductor substrates [Table 1]

[0083] The geometric flatness of Examples 5 (5k), 7 (4k), 8 (3k), 10 (2k), 11 (1K), and Comparative Example 1 (BSL) was tested, and the test results are shown in Table 2 and Figure 7.

[0084] Test results of geometric flatness for semiconductor substrates [Table 2]

[0085] As can be seen from the results in Table 2 and Figure 2, when the thickness of the capture layer 200 manufactured in this application is within the range of 1000 Å to 3000 Å, the deterioration of the geometric flatness of the semiconductor substrate 1 is improved compared to Comparative Example 1 in which the capture layer 200 is not deposited. Furthermore, in this application, when the thickness of the capture layer 200 manufactured after improving the CMP method is within the range of 3000 Å to 8000 Å, the degree of deterioration of geometric flatness is suppressed. In this application, the thickness range of the capture layer 200 manufactured is 5000 Å to 8000 Å, and the range of maximum local flatness (nm) is 130 nm to 250 nm. In this application, the thickness range of the capture layer 200 manufactured is 4000 Å to 8000 Å, and the range of maximum edge flatness (μm) is 130 nm to 250 nm.

[0086] Figure 2 shows the average values ​​of the maximum local flatness (SFQR Mean / nm) and maximum edge flatness (ESFQR Mean / nm) of the trapping layer 200 of the present invention. The results, which are consistent with the trends of the maximum local flatness and maximum edge flatness, indicate that the degree of deterioration of the flatness of the semiconductor substrate 1 was improved by the manufacturing of the trapping layer 200 of the present invention.

[0087] Examples of applications are as follows:

[0088] The semiconductor substrate 1 manufactured in Example 2 (Poly+LTO 8k+3k), Example 5 (Poly+LTO 5k+3k), Example 8 (Poly+LTO 3k+3k), and Comparative Example 1 (POR) will be applied to an image sensor (CMOS).

[0089] Image sensors are manufactured by the following methods:

[0090] Using an ion implantation method, a circuit structure including NMOS and PMOS as shown in Figure 8 is formed on a semiconductor substrate 1.

[0091] Specifically, the manufacturing of the gate electrode involves forming a gate electrode on a semiconductor substrate 1 using polysilicon to control the transmission of electric current.

[0092] Specifically, the formation of the oxide layer involves forming silicon dioxide on the semiconductor substrate 1 as an oxide layer to isolate and protect the circuit.

[0093] Metal deposition specifically involves depositing metallic copper onto the oxide layer to form electrodes and connecting wires.

[0094] Specifically, exposure and etching involve limiting the shape and structure of the circuit to the oxide layer through the exposure process, and then removing excess material through etching to form the desired circuit structure.

[0095] Specifically, the formation of a dielectric layer involves creating a dielectric layer between the metal electrode and the connecting wire to isolate and protect the circuit.

[0096] Specifically, metal filling involves filling the dielectric layer with metal to form the tops of the electrodes and connecting wires.

[0097] Packaging and testing are specifically performed after the manufacturing of the image sensor is complete. The sensor body is packaged in packaging material, and electrical characteristics testing and image quality testing are then conducted.

[0098] The test method specifically involves testing the dark current using a dark current imaging sensor.

[0099] If the object being tested is a white pixel, the dark-field testing method is used.

[0100] Test results of applying the semiconductor substrate manufactured in this invention to a front-illuminated image sensor. [Table 3]

[0101] As can be seen from the data in Figure 10 (where D-Mean in Figure 10 represents the test data related to dark current), Figure 11 (where Peak02 in Figure 11 represents the test data related to white pixels), and Table 3, the verification results for the elements of the semiconductor substrate 1 manufactured in this application indicate that an image sensor having a back polysilicon layer ( That is, the semiconductor substrates 1 manufactured in Example 2 (Poly+LTO 8k+3k), Example 5 (Poly+LTO 5k+3k), and Example 8 (Poly+LTO 3k+3k) correspond to lines consisting of normal quantiles obtained by applying them to an image sensor. ) but semiconductor substrates that do not use a back polysilicon layer ( That is, the semiconductor substrate 1 manufactured in Comparative Example 1 (POR) corresponds to the line consisting of normal quantiles obtained by applying it to an image sensor. Compared to the previous method, both showed a significant improvement trend, with both dark current and white pixels showing a substantial decrease and a tendency towards tighter pixels. The above demonstrates that by using a semiconductor substrate having a back polysilicon layer manufactured according to the present invention, the leakage phenomenon caused by metal ion contamination generated during processing can be more favorably suppressed. Therefore, according to the present invention, the dark current and white pixels of CIS products can be effectively improved, and consequently, the quality of CIS chip elements can be improved.

[0102] In the embodiments described above, each embodiment has its own focus, and for parts not explained in detail in one embodiment, one can refer to the descriptions in other embodiments.

[0103] Although the semiconductor substrate, its manufacturing method, and image sensor provided in the embodiments of this application have been described in detail above, this specification describes the principles and embodiments of this application by applying specific examples, and the descriptions of the embodiments above are intended to aid in understanding the technical proposal and its core concept. Furthermore, those skilled in the art can modify the specific embodiments and scope of application according to the technical concept of this application, and therefore, the contents of this specification should not be interpreted as limiting this application. [Explanation of Symbols]

[0104] 1: Semiconductor substrate 100: Circuit board 101: 1st surface 102:Second surface 110: 1st base material 200: Capture layer 210: First polysilicon layer 220: Second polysilicon layer 300: Backside sealing layer 2: Grinding disc 3: Polishing head 300: Cavity 301: Bottom

Claims

1. A substrate (100) having a first surface (101), A capture layer (200) is used to capture metal ions from the substrate (100) or metal ions that have passed through the substrate (100), and contains polysilicon, is located on the side of the substrate (100) away from the first surface (101), and has a thickness of 1000 Å to 3000 Å in the thickness direction (X) of the substrate (100), The device includes a back-side sealing layer (300) located on the side of the trapping layer (200) away from the substrate (100), and having a thickness of 3000 Å to 4000 Å. Semiconductor substrate.

2. The resistivity of the substrate (100) is The range is 0.010 ohm-cm to 0.020 ohm-cm. The semiconductor substrate according to claim 1.

3. To provide a substrate (100) having a first surface (101), Used to capture metal ions from the substrate (100) or metal ions that have passed through the substrate (100), and containing polysilicon, and located on the side of the substrate (100) away from the first surface (101), forming a capture layer (200) with a thickness of 1000 Å to 3000 Å in the thickness direction of the substrate (100), The method includes placing the substrate (100) having the capture layer (200) in an environment with a temperature range of 600°C to 650°C to form a back surface sealing layer (300) located on the side of the capture layer (200) away from the substrate (100) and having a thickness of 3000 Å to 4000 Å. Manufacturing methods for semiconductor substrates.

4. The step of forming the aforementioned capture layer (200) is, To form a second polysilicon layer (220) located on the first surface (101), A first polysilicon layer (210) is formed, the substrate (100) has a second surface (102) opposite to the first surface (101), the first polysilicon layer (210) is located on the second surface (102), and a first substrate (110) is obtained. This includes removing the second polysilicon layer (220), leaving the first polysilicon layer (210), and making the first polysilicon layer (210) the capture layer (200), A method for manufacturing a semiconductor substrate according to claim 3.

5. The first polysilicon layer (210) is manufactured by depositing polysilicon onto the surface of the substrate (100) using a silicon-containing gas. A method for manufacturing a semiconductor substrate according to claim 4.

6. The amount of silicon-containing gas used is 2 L / 1000 Å to 4 L / 1000 Å. A method for manufacturing a semiconductor substrate according to claim 5.

7. The second polysilicon layer (220) is manufactured by depositing polysilicon onto the surface of the substrate (100) using a silicon-containing gas. A method for manufacturing a semiconductor substrate according to claim 4.

8. The amount of silicon-containing gas used is 2 L / 1000 Å to 4 L / 1000 Å. A method for manufacturing a semiconductor substrate according to claim 7.

9. In the step of forming the first polysilicon layer (210), the substrate (100) is placed in an environment with a temperature range of 600°C to 660°C. A method for manufacturing a semiconductor substrate according to claim 4.

10. In the step of forming the second polysilicon layer (220), the substrate (100) is placed in an environment with a temperature range of 600°C to 660°C. A method for manufacturing a semiconductor substrate according to claim 4.

11. The second polysilicon layer (220) is removed by a chemical mechanical polishing method. A method for manufacturing a semiconductor substrate according to claim 4.

12. The chemical mechanical polishing method includes grinding the second polysilicon layer (220) and removing the second polysilicon layer (220). A method for manufacturing a semiconductor substrate according to claim 11.

13. The first substrate (110) is adsorbed onto a polishing head (3), the polishing head (3) has a cavity (300), and in the thickness direction (X) of the semiconductor substrate (1), the cavity (300) has a first thickness H １ The first substrate (110) has a thickness of μm, and the second thickness H ２ Having μm, 0 < H １ -H ２ Satisfying ≤20 μm, A method for manufacturing a semiconductor substrate according to claim 12.

14. An image sensor, The semiconductor substrate (1) is included in claim 1 or 2, The semiconductor substrate (1) is used as the base for the image sensor. Image sensor.

15. The semiconductor substrate (1) includes a P-type substrate, The image sensor according to claim 14.

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