Tape-out of whole and partial dies from a common design.

Abstract

To provide a chip design method and a set of integrated circuits that are taped out from a common design database.SOLUTION: The chip design method comprises: defining the area of a full instance of the integrated circuit; defining one or more cut lines to identify portions to be removed for one or more partial instances. A variety of techniques and mechanisms are defined to permit the tape outs to occur from a common design database, so that the effort to tape out partial instances may be minimized compared to the effort to tape out the full instance.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments described herein relate to integrated circuits, and more specifically to integrated circuits designed for full and partial tape-out. Background Art

[0002] An integrated circuit includes various digital logic circuits and / or analog circuits integrated on a single semiconductor substrate or "chip". A wide variety of integrated circuits exist, ranging from fixed-function hardware to system-on-chip (SOC) that includes microprocessors, processors, integrated memory controllers, and various other components forming a highly integrated chip that can be the core of a system.

[0003] A given integrated circuit can be designed for use in a variety of systems (e.g., "general-purpose" components). While a given integrated circuit can include a set of components that enables its use in various systems, a particular system may not require all components, or all functions and / or performance of all components. Extra components / functions are effectively wasted, resulting in unrecoverable costs and power consumption (at least leakage power) in the system. For portable systems that operate at least sometimes on a limited power source (e.g., a battery), inefficient use of power, in contrast to the essentially unlimited supply from a wall outlet, leads to inefficient use of the limited supply and even unacceptably short time between required charges for the limited supply.

[0004] Therefore, matching integrated circuit functionality to the requirements of a given system is important for manufacturing high quality products. However, custom integrated circuit design for many different systems also incurs costs in terms of design and verification effort for each integrated circuit. Brief Description of the Drawings

[0005] The following detailed description references the accompanying drawings briefly described below.

[0006] [Figure 1] This is a block diagram of one embodiment of an integrated circuit design that supports whole and partial instances.

[0007] [Figure 2] This figure shows various embodiments of the whole and partial instances of the integrated circuit shown in Figure 1. [Figure 3] This figure shows various embodiments of the whole and partial instances of the integrated circuit shown in Figure 1. [Figure 4] This figure shows various embodiments of the whole and partial instances of the integrated circuit shown in Figure 1.

[0008] [Figure 5] This is a block diagram of one embodiment of an integrated circuit shown in Figure 1, in which each sub-region of the integrated circuit has a local clock source.

[0009] [Figure 6] This is a block diagram of one embodiment of an integrated circuit shown in Figure 1, which has local analog pads in each sub-region of the integrated circuit.

[0010] [Figure 7] This is a block diagram of one embodiment of the integrated circuit shown in Figure 1, which has exclusion regions at the corners of each sub-region and regions for interconnect "bumps" that exclude regions near the edges of each sub-region.

[0011] [Figure 8] This is a block diagram showing one embodiment of a stub and a corresponding circuit component.

[0012] [Figure 9] A block diagram showing one embodiment of a pair of integrated circuits and specific additional details of a pair of integrated circuits.

[0013] [Figure 10] This is a block diagram of one embodiment of an integrated circuit design method.

[0014] [Figure 11] It is a block diagram showing a test bench configuration for testing whole and partial instances.

[0015] [Figure 12] It is a block diagram showing a test bench configuration for component-level testing.

[0016] [Figure 13] It is a flowchart showing one embodiment of a method for designing and manufacturing an integrated circuit.

[0017] [Figure 14] It is a flowchart showing one embodiment of a method for manufacturing an integrated circuit.

[0018] [Figure 15] It is a block diagram of one embodiment of a computer-accessible storage medium.

[0019] [Figure 16] It is a block diagram of various systems that can use an integrated circuit.

[0020] While the embodiments described in this disclosure may allow for various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the drawings and the detailed description relating to the drawings are not intended to limit the embodiments to the particular forms disclosed, but rather the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the appended claims. The headings used herein are for organizational purposes only and are not intended to be used to limit the scope of the description. MODE FOR CARRYING OUT THE INVENTION

[0021] In one embodiment, the integrated circuit method and design support two or more tape-outs of different implementation forms of the integrated circuit and their final manufacturing, based on a common design database. The design may support a whole instance in which all circuit components included in the design are contained in a manufactured chip, and one or more sub-instances containing a subset of the circuit components within the manufactured chip. Sub-instances can be manufactured on smaller dies, but the circuit components, as well as their physical placement and routing to the sub-instance, may be the same as the corresponding areas in the whole instance. That is, a sub-instance can be created by removing a portion of the area of ​​the whole instance and the components on it from the design database. Design, verification, synthesis, timing analysis, design rule checks, electrical analysis, etc., may be shared across the whole instance and sub-instances. Furthermore, in one embodiment, integrated circuit chips suitable for various products with different computational requirements, form factors, cost structures, power supply limitations, etc., may be supported from the same design process. In one embodiment, a whole instance of a SOC may be linked with other whole instances or even different SOCs to build a larger system. In one embodiment, a partial instance may be linked with a whole instance, other partial instances, and / or other SOCs to construct a larger system. In one embodiment, a partial instance of a given SOC may include partial instances of a given circuit component.

[0022] For example, a whole instance may include a certain number of computing units (e.g., a central processing unit (CPU) processor, a graphics processing unit (GPU), a coprocessor attached to a CPU processor, a digital signal processor, an image signal processor, and other specialized processors). A partial instance may include fewer computing units. A whole instance may include a certain amount of memory capacity via multiple memory controllers, while a partial instance may include fewer memory controllers supporting smaller memory capacities. In one embodiment, the number of memory channels may be reduced, thereby reducing bandwidth. That is, a reduction in memory controllers / memory channels may support smaller memory and / or smaller memory bandwidth. A whole instance may include a certain number of input / output (I / O) devices and / or interfaces (also called peripheral devices / interfaces or simply peripherals). A partial instance may have fewer I / O devices / interfaces.

[0023] In one embodiment, a partial instance may further include a stub region. The stub region can provide termination for input signals to circuit components included in the partial instance, the source of those input signals in the whole instance being the circuit components in the removed region, and therefore the input signals are unconnected in the absence of the stub. Output signals from the circuit components to the circuit components in the removed region may reach at least the edge of the stub and may be unconnected. In one embodiment, the stub region may include metallization, as necessary, to connect the input signals to a power (digital 1) or ground (digital 0) wire (e.g., power and ground grid) in order to provide proper functionality for the circuit components in the partial instance. For example, a power manager block in a partial instance may receive input from a removed circuit component, the input may be connected to a power or ground grid to indicate that the removed circuit component is powered off or idle, so that the power manager block does not wait for a response from the removed circuit component when changing the power state. In one embodiment, the stub region may include only metallization (wiring). In other words, the stub region can exclude active circuit configurations (e.g., transistors formed on the semiconductor substrate). The metallization layer (or metal layer) is formed above the surface region of the semiconductor substrate to provide wire interconnects between active circuit elements (or provide digital 1 / 0 values ​​within the stub region). By managing the partial instance design in this way, the amount of verification required for a partial instance can be minimized compared to the effort required for the whole instance. For example, additional timing verification may not be necessary, and additional physical design verification may be minimal.

[0024] Figure 1 is a block diagram showing one embodiment of an integrated circuit, including a whole instance and several partial instances. The whole instance of the integrated circuit is indicated by curly braces 12 ("Chip 1"), and partial instances of the integrated circuit are indicated by curly braces 14 and 16 ("Chip 2" and "Chip 3"). The whole instance, Chip 1, includes several circuit components 10A to 10D. The physical locations of the circuit components 10A to 10D on the surface of the semiconductor substrate chip or die (reference no. 18) of the whole instance are indicated by the arrangement of the circuit components 10A to 10D. Figure 1 is a simplified representation, and there may be more circuit components, and the physical arrangement may differ from the arrangement shown in Figure 1. Various interconnects between the circuit components 10A to 10D are used for communication between components and are not shown in Figure 1. The interconnects, as well as the interconnects within the circuit components 10A to 10D themselves, may be mounted in the metallization layer above the semiconductor substrate surface.

[0025] Each sub-instance corresponds to the “shear lines” 20A to 20B in Figure 1. The shear lines divide the circuit components 10A to 10D included in the whole instance into circuit components 10A to 10D included in various sub-instances. For example, chip 2 is defined by shear line 20A and includes circuit components 10A to 10C but does not include circuit component 10D. Similarly, chip 3 is defined by shear line 20B and includes circuit components 10A to 10B but does not include circuit components 10C to 10D. Shear lines may be defined in the design database or may be part of the design process, but do not necessarily have to be explicitly shown in the design database.

[0026] Generally, a design database may include multiple computer files that store descriptions of circuit components 10A-10D and their interconnects. The design database may include register transfer level (RTL) descriptions of circuits expressed in hardware description languages ​​(HDL) such as Verilog or VHDL. For circuits implemented directly rather than synthesized from RTL descriptions using a library of standard cells, the design database may include circuit descriptions from circuit editor tools. The design database may include netlists resulting from synthesis that describe standard cell instances and their interconnects. The design database may include physical layout descriptions of circuit components and their interconnects, and may include tape-out description files that describe the integrated circuit in terms of geometric shapes and layers that can be used to create masks for the integrated circuit manufacturing process. Tape-out description files may be expressed in formats such as Graphical Design System (GDSII) format or Open Artwork System Interchange Standard (OASIS) format. Any combination of the above may be included in the design database.

[0027] Shear lines 20A to 20B divide the area of ​​chip 18 into sub-regions, within which subsets of circuit components 10A to 10D are instantiated. For example, shear line 20B divides the area of ​​chip 18 into a first sub-region (above line 20B as oriented in Figure 1) and a second sub-region (below line 20B). Shear line 20A further divides the second sub-region into third and fourth sub-regions, with the third sub-region being adjacent to or touching the first sub-region. The combination of the first and second sub-regions represents the whole instance. The first sub-region alone (along with the stub region) represents the smallest partial instance (chip 3). The first and third sub-regions represent other partial instances (chip 2) in this embodiment.

[0028] The physical location of circuit components within a given sub-region, as well as the interconnects within and between circuit components, may not change between the whole instance and the partial instance. Therefore, if the circuit components within the whole instance satisfy the timing, physical design, and electrical requirements for the normal manufacturing and use of the whole instance, the same requirements should generally be satisfied by the partial instance. The physical design and electrical requirements within the stub region may need to be verified, and specific physical design requirements, such as corner exclusion zones and controlled collapse chip connect (C4) bump exclusion zones, may be applied to the sub-region, as discussed below. However, in one embodiment, once the whole instance has been verified and is ready for tape-out, the tape-out of the partial instance can be carried out with minimal effort.

[0029] Figures 2-4 show partial and whole instances of the embodiment shown in Figure 1. Figure 4 is the whole instance and therefore includes circuit components 10A-10D. Figures 2 and 3 correspond to chip 3 and chip 2, respectively. Thus, the partial instance of Figure 2 includes circuit components 10A-10B from the first sub-region and stub region 22 (stub 1). The partial instance of Figure 3 includes circuit components 10A-10B from the first sub-region, circuit component 10C from the second sub-region, and stub region 24 (stub 2). In another embodiment, a partial instance may be formed by removing a portion between shear lines 20A-20B, for example, component circuit 10C, and joining the remaining sub-regions, for example, component circuits 10A-10B and component circuit 10D. If three or more shear lines are defined, even more deformations may be supported by removing one or more sub-regions between each shear line. Such embodiments may be implemented by implementing stub regions (which may be smaller than the removed sub-regions) between the shear lines, or by ensuring that the wires on both sides of the removed sub-region coincide and connect correctly when the sub-region is removed and the remaining sub-region is moved together. In yet another embodiment in which multiple shear lines are used, one or more shear lines may be perpendicular to the other shear lines, allowing the sub-region to be removed in two or more directions. In various embodiments, any combination of perpendicular shear lines and removal / joining of intermediate portions may be implemented.

[0030] A circuit component can be any set of circuits arranged to implement a specific component of an IC (e.g., a CPU or GPU, a processor or GPU cluster, a memory controller, a communication structure or part thereof, a peripheral device or peripheral interface circuit, etc.). A given circuit component can have a hierarchical structure. For example, a processor cluster circuit component can have multiple instances of a processor, which may be copies of the same processor design placed multiple times within the area occupied by the cluster.

[0031] According to this description, the method may include defining, in a design database corresponding to the integrated circuit design, the area occupied by the integrated circuit design when manufactured on a semiconductor substrate. For example, the area may be the area of ​​the whole instance as shown in Figures 1 and 4. The method may further include defining shear lines (which may be one of several shear lines). The shear lines can divide the area into a first sub-region and a second sub-region, and the combination of the first and second sub-regions represents the whole instance. The first sub-region and the stub region represent a partial instance of the integrated circuit containing fewer circuit components than the whole instance. In the design database, the physical locations of multiple circuit components included in both the whole instance and the partial instance of the integrated circuit are defined within the first sub-region. The relative positions of multiple circuit components within the first sub-region and the interconnects of multiple circuit components within the first sub-region may not change in the whole instance and the partial instance. The physical locations of other multiple circuit components included in the whole instance but excluded from the partial instance are defined within the second sub-region. The stub region is also defined in the design database. A stub region may include the end of a wire that would otherwise traverse a shear line between the first and second subregions. The stub region can ensure the correct operation of several circuit components within the first subregion in the absence of the second subregion in a partial instance. A first dataset relating to the whole instance may be created using the first and second subregions, and the first dataset defines the whole instance for the purpose of manufacturing the whole instance. A second dataset relating to a partial instance may also be created using the first subregion and the stub region. The second dataset defines a partial instance for the purpose of manufacturing a partial instance. In one embodiment, the method may further include defining a second shear line within the second subregion to divide the second subregion into a third and a fourth subregion. The third subregion may be adjacent to the first subregion, and the third and first subregions may represent a second partial instance of the integrated circuit.The method may further include creating a third dataset relating to the second subinstance using the first subregion, the third subregion, and the second stub region. The third dataset defines the second subinstance for the production of the second subinstance.

[0032] As described above, stub regions can exclude circuit configurations. For example, stub regions can exclude active circuit configurations such as transistors or other circuits formed on the semiconductor substrate. Stub regions can exclude circuits that may similarly be formed on the metallization layer (e.g., explicit resistors, inductors, or capacitors). The metallization layer has parasitic properties (e.g., resistance, inductance, and capacitance), but explicitly defined circuits are not permitted. Stub regions may contain only wiring in one or more metallization layers above the surface area of ​​the semiconductor substrate.

[0033] Another method may include, for example, receiving a first data set and a second data set at a semiconductor manufacturing facility or “foundry”. This method may further include manufacturing a first number of whole instances of an integrated circuit based on the first data set and manufacturing a second number of partial instances of an integrated circuit based on the second data set.

[0034] An integrated circuit implementing a partial instance of the present disclosure may include a plurality of circuit components physically arranged on the surface of a semiconductor substrate forming the integrated circuit, and a plurality of wire terminations along a single edge of the surface (e.g., a stub region). The plurality of wire terminations can be electrically connected to a plurality of supply wires of the integrated circuit to provide fixed digital logic levels on wires that are inputs to one or more of the plurality of circuit components. Power supply wires may be part of a power supply grid (e.g., a power and / or ground grid) within the metallization layer of the integrated circuit. The power and ground grid may also be referred to as a power and ground grid. Input wires terminated by wire terminations are oriented to intersect the single edge and lack circuits configured to drive wires within the integrated circuit (e.g., wires are driven in the whole instance by circuit components in a second sub-region that are not present in the partial instance). Regions along a single edge containing the plurality of wire terminations also exclude active circuit elements. For example, a region along a single edge may include only wiring in one or more metallization layers above the surface region of the semiconductor substrate.

[0035] The methods described herein may affect various areas of the overall design process for integrated circuits. For example, floor planning is an element of the design process in which various circuit components are assigned to areas on a semiconductor substrate. During floor planning, the presence of partial instances and the location of shear lines can be taken into consideration to ensure that all circuit components included in an instance are contained within a first sub-region, and other circuit components are contained within a second sub-region (or third and fourth sub-regions, etc.). Furthermore, the shape of the sub-regions may be carefully designed to provide efficient use of the area in both the whole instance and partial instances. A main bus or other interconnect that can provide communication between circuit components throughout the whole instance may be designed to properly manage communication in various instances (for example, in a partial instance, the bus may terminate in a stub region or be unconnected in a stub region, and thus communication should not be transmitted in the direction of the stub region). Floor planning may also take into consideration tape-out requirements for both the whole instance and partial instances (for example, various exclusion zones, as will be discussed in more detail below). Furthermore, floor planning can attempt to minimize the number of wires crossing shear lines in order to simplify the verification that partial instances are working correctly.

[0036] In one embodiment, considerations during the floor planning phase may include specifying certain essential connections that may be affected by shear in partial instances. Clock interconnects and analog interconnects may be examples. Often, a clock interconnect (or “clock tree”) is designed such that the distance and electrical load from the clock generator or clock source to the clock termination are approximately the same or “balanced” across various state elements within the circuit configuration. State elements may include, for example, flip-flops (“flops”), registers, latches, memory arrays, and other clock storage devices.

[0037] To maintain balance between various instances of an integrated circuit design, individual clock trees may be defined between local clock sources within each sub-region and state elements within that sub-region. For example, Figure 5 is a block diagram showing one embodiment of shear lines 20A to 20B that divide the overall instance into sub-regions for shearing the integrated circuit (chip 18) into an overall instance and partial instances. Each of the local clock sources 30A to 30C, indicated by the lines within each sub-region, is shown, driving an individual clock tree. The clock trees do not have to traverse the shear lines 20A to 20B; that is, a clock tree within a given sub-region can remain within that sub-region.

[0038] The clock source can be any circuit configured to generate a clock signal for a circuit configuration linked in a clock tree. For example, the clock source may be a phase-locked loop (PLL), a delay-locked loop (DLL), a clock splitter, etc. The clock source can be coupled to the clock input of an integrated circuit to which an external clock signal is provided, and the clock source can multiply or divide the frequency while locking the phase or clock edge to the external signal.

[0039] Therefore, the method may further include defining one or more first clock trees in a first sub-region to distribute clocks within the first sub-region, and defining one or more second clock trees in a second sub-region to distribute clocks within the second sub-region. One or more first clock trees may be electrically isolated from one or more second clock trees in the overall instance. The clock trees may be physically independent (e.g., connected to different local clock sources) as shown in Figure 5. The clock trees do not need to have shear lines traversing other sub-regions. In the manufacturing method, the first dataset may further include one or more first clock trees for distributing clocks within a first sub-region, and one or more second clock trees for distributing clocks within a second sub-region, and in the overall instance, one or more first clock trees may be electrically isolated from one or more second clock trees.

[0040] In one embodiment, the integrated circuit may include one or more clock trees for distributing a clock within a first sub-region of a first region, and one or more second clock trees for distributing a clock within a second sub-region. The one or more first clock trees may be electrically isolated from the one or more second clock trees.

[0041] Figure 6 is a block diagram illustrating one embodiment of the entire die 18 divided by shear lines 20A to 20B, and the provision of local analog pads 32A to 32C within each sub-region defined by the shear lines 20A to 20B. The analog pads 32A to 32C may provide connection points for analog inputs to the chip. Analog signals often have special requirements, such as shielding from digital noise that can affect the accuracy and functionality of the analog signals. These signals are continuous value signals, in contrast to digital signals, which only represent digital values ​​and not transitions between them. Ensuring that analog requirements are met within each sub-region can simplify the design of the entire integrated circuit. In one embodiment, if there is no use of analog signals within a given sub-region, that sub-region may be excluded from analog pads and signal routing.

[0042] Therefore, the method may further include defining one or more first analog inputs in a first sub-region and defining one or more second analog inputs in a second sub-region. The one or more first analog inputs may remain in the first sub-region, and the one or more second analog inputs may remain in the second sub-region. That is, analog signals on or derived from the inputs may be transmitted on wires that do not cross the shear lines 20A to 20B. In the manufacturing method, the first data set may further include one or more first analog inputs in a first sub-region, and the one or more first analog inputs may remain in the first sub-region, and the first data set may further include one or more second analog inputs in a second sub-region, and the one or more second analog inputs may remain in the second sub-region.

[0043] According to this disclosure, an integrated circuit may comprise a first plurality of circuit components physically arranged within a first region on the surface of a semiconductor substrate forming the integrated circuit, and a second plurality of circuit components physically arranged within a second region on the surface of the semiconductor substrate forming the integrated circuit. One or more first analog inputs may be provided within the first region, and one or more first analog inputs may be isolated to the first plurality of circuit components. One or more second analog inputs may be provided within the second region, and one or more second analog inputs may be isolated to the second plurality of circuit components.

[0044] Another feature of an integrated circuit that may be considered is a design-feedback (DFT) strategy. A DFT generally includes one or more ports, on which a DFT interface is defined, such as an interface compatible with the Joint Test Access Group (JTAG) specification. The DFT may include defining a scan chain of state elements to scan in and scan out states in the design, and the scan chain may be defined to remain, for example, within a given sub-region. To minimize shear line crossing communications as much as possible, separate DFT ports may be provided within each sub-region. If shear line crossing communications are necessary, such signals, like other signals, can be terminated (input to the sub-region) and left unconnected in a stub region (output to the sub-region). In one embodiment, the scan network and other DFT networks may be designed as a hierarchical ring, so that parts within removed circuit components can be disconnected from the DFT network without further affecting the remaining network.

[0045] In one embodiment, several circuit components may be instantiated multiple times within the overall instance. One or more instances may be in a sub-region not included in one or more of the partial instances. These circuit components are designed to satisfy all requirements (timing, physical, electrical) at each location of the instance and may therefore be over-engineered for some other locations (e.g., a circuit component may be designed to accommodate worst-case clock skew across those locations). Furthermore, partial instances may have different packaging solutions that require additional design to handle differences within the package (e.g., different IR voltage drops).

[0046] In one embodiment, a foundry may need to manufacture certain "non-logical" cells on a semiconductor substrate. These cells are not part of the integrated circuit itself, but may be used by the foundry to coordinate the manufacturing process. The cells required by the foundry may have strict rules and may depend on the die size, and therefore, the placement of these cells in the floor plan of the overall instance may need to be planned so that they are also properly positioned in the partial instance(s).

[0047] Figure 7 illustrates embodiments of various types of exclusion areas (or exclusion zones), another consideration in integrated circuit design. On the left side of Figure 7, the entire instance of the entire die 18 (chip 1) is shown together with a partial instance on the right, with chip 3 at the top (located above the shear line 20B indicated by the dotted line 34 within the entire instance) and chip 2 at the bottom (located above the shear line 20A indicated by the dashed line 36 within the entire instance). For each instance, the corners of the chip have exclusion zones where circuit configuration is not permitted (or must adhere to much stricter design rules than other parts of the semiconductor substrate surface). Corner exclusion zones can be defined because the mechanical stress on the corners of the semiconductor die can be greater than the mechanical stress at other locations on the chip. Corner exclusion zones are indicated by shaded areas shown by reference numeral 38 in Figure 7.

[0048] Therefore, the overall instance has a “corner” exclusion zone along the side of the chip, not only at each of the four corners but also at the corners of the sub-regions adjacent to the shear lines 20A-20B, and these shear lines terminate at the corners of the chip of the partial instance. The additional corner exclusion zones may be the same size as the corner exclusion zones of the overall instance, or they may be different in size, depending on whether the size of the corner exclusion zones increases or decreases in accordance with the overall size of the die.

[0049] Therefore, the method may further include defining a plurality of exclusion zones at each corner of a semiconductor substrate, and circuit components are excluded from the plurality of exclusion zones in accordance with the mechanical requirements of the manufacturing process used to manufacture the integrated circuit. The method may further include defining an additional exclusion zone at the corner of a first sub-region adjacent to a shear line, thereby so that a partial instance includes an exclusion zone at each corner of the semiconductor substrate on which the partial instance is formed. A first dataset in the manufacturing method may include a plurality of exclusion zones at each corner of a semiconductor substrate, and circuit components are excluded from the plurality of exclusion zones in accordance with the mechanical requirements of the manufacturing process used to manufacture the integrated circuit, and the first dataset may include an additional exclusion zone at the corner of a first sub-region adjacent to a second sub-region, thereby so that a partial instance includes an exclusion zone at each corner of the semiconductor substrate on which the partial instance is formed.

[0050] Furthermore, an integrated circuit (including, for example, the entire instance) may comprise: a first plurality of circuit components physically arranged within a first region of the surface of a semiconductor substrate forming the integrated circuit; a plurality of exclusion zones at each corner of the semiconductor substrate, from which circuit components are excluded in accordance with the mechanical requirements of a manufacturing process used to manufacture the integrated circuit; and another plurality of exclusion zones separated from each corner along a pair of nominally parallel edges of the semiconductor substrate, from which circuit components are excluded, and which have substantially the same dimensions as the other plurality of exclusion zones.

[0051] Figure 7 also shows the permissible locations of C4 bumps in the whole and partial instances of the integrated circuit, which are indicated as double-shaded areas of reference no. 40 in Figure 7. Areas outside the area indicated by the double-shaded area 40 do not have to be permissible locations for C4 bumps (e.g., C4 bump exclusion zones), or stricter rules may be established for placing C4 bumps in those areas. Thus, permissible / exclusion zones exist at each edge of each instance. That is, C4 exclusion zones may exist around the whole die 18 and on both sides of the shear lines 20A-20B. Thus, the method may further include defining a second exclusion zone along the edge of a first sub-region adjacent to a second sub-region, where controlled collapse chip connection (C4) connections are excluded from the second exclusion zone. In the manufacturing method, the first data set may further include a second exclusion zone along the edge of the first sub-region adjacent to the second sub-region, and control collapse chip connection (C4) connections are excluded from the second exclusion zone. In one embodiment, the integrated circuit may include a second exclusion zone along the lines between a plurality of exclusion zones, and control collapse chip connection (C4) connections are excluded from the second exclusion zone.

[0052] Figure 8 is a block diagram showing in more detail one embodiment of the circuit component 10B and stub region 22 of the embodiment of chip 3 shown in Figure 2. A similar connection to circuit component 10A may also be provided, and the stub region 24 in Figure 3 may be similar to circuit components 10A-10C. The stub region 22 is provided for inputs provided by the removed circuit component, which is part of the whole instance but not part of the partial instance, as indicated by the dotted line from the end to the edge of the stub region 22 in Figure 8, for the V for circuit component 10B. DD Termination 50 (input is coupled upward or binary 1), and V SS Alternatively, it may include terminations such as ground termination 52 (input coupled downwards or coupled to binary 0). The choice of binary 1 or binary 0 for a given termination may depend on the logical effect of the input within the circuit component 10B. Generally, terminations can be selected as either values ​​that allow the receiving circuit to proceed without further input from the removed circuit component that supplies the input (e.g., as the output of the removed circuit component) in the whole instance. Terminations provide a known value when the driving circuit is absent for a signal. The output of circuit component 10B connected to the removed circuit component may reach the stub region 22 (e.g., reference numerals 54 and 56), but may be unconnected (e.g., not connected to the receiving circuit). In the whole instance or a relatively large sub-instance, output wires 54 and 56 may extend to circuit components that are not present in the sub-instance (shown by dotted lines in Figure 8).

[0053] Therefore, an input terminated in a stub region may be a wire that extends into the stub region and is oriented to intersect the edge of the integrated circuit where the stub region is located. The input lacks a circuit configured to drive the wire within the integrated circuit (for example, the wire is driven in the whole instance by a circuit component that is not present in the partial instance).

[0054] In other cases, it may be desirable to replace the local input for input from the removed circuit component. For example, a loopback circuit or ring interconnect structure used for testing may locally complete the loopback / ring in a partial instance. To support such instances, a receiving circuit component (e.g., circuit component 10B) may include a logic circuit for selecting between the local signal and the input from the removed component. For example, in Figure 8, circuit component 10B may include multiple multiplexers (mux) 58 and 60. Each mux 58 or 60 may be connected to an input wire normally supplied from a circuit component that is not present in the partial instance. The input wire may reach the stub region 22 but may be unconnected. Alternatively, the input wire may be terminated with binary 1 or zero as needed. Termination of such inputs may prevent the input from floating and the floating input from causing a waste current between the power supply and ground for a significant period. The mux selection wire is also supplied from the stub region 22 and binary 0 (V SS ) or binary 1 (V DD ) can be terminated, allowing the mux to select a local wire. If a source circuit component exists for the input wire (for example, in the whole instance or a relatively large partial instance), the mux selection wire can be supplied from the source circuit component (dotted line in Figure 8). In such cases, the mux selection wire can be a dynamic signal that can select between a local input and an input from the source circuit component if desired during operation, or it can be coupled to an opposite binary value compared to the mux selection wire in the stub region 22.

[0055] Accordingly, in one embodiment of the method, the overall instance may include a plurality of other circuit components in a second sub-region, which may include a plurality of outputs that are a plurality of inputs to a plurality of circuit components in the first sub-region. The plurality of circuit components may include a plurality of multiplexer circuits having corresponding inputs of a plurality of inputs as inputs. The method may include representing a plurality of selection signals for the plurality of multiplexer circuits in a stub region. The plurality of selection signals may be terminated in the stub region with binary values ​​that select inputs to the plurality of multiplexer circuits different from the mux inputs to which the plurality of inputs are connected. In one embodiment, the plurality of selection signals may be terminated in the second sub-region with different binary values.

[0056] In one embodiment, the integrated circuit may include a plurality of circuit components physically arranged on the surface of a semiconductor substrate forming the integrated circuit. The plurality of circuit components include a plurality of multiplexer circuits, each having a first input wire, a second input wire, and a selection control wire. The integrated circuit may further include a region along a single edge of the surface, which is the power source for the selection control wire, the second input wire reaches the single edge of the surface and is unconnected, and the selection control wire is electrically connected to the supply wire of the integrated circuit. The voltage on the supply wire in use corresponds to a digital logic level that causes the plurality of multiplexer circuits to select the first input wire as the output of the plurality of multiplexer circuits.

[0057] Next, we refer to Figure 9, a block diagram of one embodiment of a pair of integrated circuits 76 and 78, which may be an overall instance of chip 18. In one embodiment, shear lines 20A-20B are shown with respect to the integrated circuit 76, and specific additional details of the integrated circuit 76 are shown. In particular, the integrated circuit 76 may include a number of network switches 70A-70H, which may be part of a communication network within the integrated circuit 76. The communication network may be an example of a circuit component and may be configured to provide communication between other circuit components (e.g., a processor, memory controller, peripherals, etc.).

[0058] Network switches 70A-70H can be connected to each other using any configuration, such as a ring, mesh, or star. When a given communication message or packet is received by network switches 70A-70H, the network switches 70A-70H can determine which output to send the packet to in order to move it toward its destination. The direction may depend on which instance of the integrated circuit the network switch is manufactured from. For example, if the entire instance is manufactured, a given network switch such as network switch 70E may transmit the packet either upward or downward, as shown in Figure 9 (or, if another circuit component not shown and connected to network switch 70E is the target of the packet, network switch 70E may transmit the packet to that circuit component). However, if a partial instance is formed based on shear line 20A, network switch 70E cannot transmit the packet downward because there is no receiving circuit. Similarly, in that scenario, network switch 70F cannot transmit the packet downward. If a partial instance is formed based on shear line 20B, network switches 70C and 70D cannot transmit the packet downward.

[0059] Therefore, at least some of the operations of the network switches 70A-70H may be instance-dependent. Multiple methods may exist for managing these differences. For example, inputs to the switches may specify an instance (output by a stub area, or, in the case of a whole instance, by circuit components in the area below the shear line 20B). In the illustrated embodiment, a routing table or other programmable resource 74 may be included in each network switch 70A-70H. The routing table 74 may be programmed at initialization (e.g., by boot code or other firmware) based on the instance in place.

[0060] Similarly, different instances may have different numbers of memory controllers (for example, circuit components in a removed subregion may contain memory controllers, and additional memory controllers may exist in the remaining subregion). The memory address space may be mapped onto memory controllers, and therefore the mapping may vary based on the number of memory controllers actually present in a given whole or partial instance. Network switches 70A-70H that carry memory operation packets may also be programmable with data describing address mappings, using programmable resources. Other circuit components that may need to communicate properly functioning address mappings may similarly have programmable resources.

[0061] In the illustrated embodiment, a pair of integrated circuits 76 and 78 may be configured to communicate with each other and function as if they were a single integrated circuit die. For example, network switches 70A-70H on each integrated circuit 76 and 78 may be configured to communicate via a die-to-die (D2D) interface circuit 72 to form a single communication interconnect across the integrated circuits 76 and 78. Thus, a packet originating on either integrated circuit die may have a destination on the other integrated circuit die and can be transmitted seamlessly via the D2D interface circuit 72 to a target that is therefore virtually invisible to the software running in the system.

[0062] Since a partial instance of an integrated circuit contains less than one instance of the entire circuit configuration, one of the component circuits that can be removed from each partial instance is the D2D interface circuit 72. That is, the D2D interface circuit 72 can be instantiated within a sub-region that is removed from each partial instance (for example, below the shear line 20A in the illustrated embodiment).

[0063] Figure 10 is a flowchart illustrating various parts of the design and demonstration / verification method for one embodiment of an integrated circuit supporting whole and partial instances. The design database for the whole instance is shown in the upper center of Figure 10 (reference number 80). The design databases for the partial instances are shown to the left and right of the whole instance (reference numbers 82 and 84). Design databases 82 and 84 retrieve the contents of the sub-regions forming the integrated circuit and the corresponding stub regions 22 and 24, as shown in Figure 10, from design database 80, as indicated by arrows 86 and 88.

[0064] Databases 80, 82, and 84 may be analyzed using static timing analysis (block 90) to verify that the design meets timing requirements, physical verification (block 92) to verify that the design meets various physical design rules, and electrical verification (block 94) to verify that the design meets electrical requirements such as power grid stability and impedance (along with the packages used per design, which may vary between whole and partial instances). Physical design rules may include features such as minimum spacing between traces in devices and / or trace layers and device size. Physical design rules may also include corner exclusion, C4 bump exclusion, etc., as described above. Furthermore, in one embodiment, there may be additional “antenna” rules to address for outputs from circuit components that are not connected in partial instances.

[0065] The results of various verification steps may be considered and triaged for design changes (design change orders or ECOs) that are expected to improve the results of subsequent executions of various verifications (triage ECO blocks 96, 98, and 100). ECOs may be performed in the design database 80 regardless of which instance gives rise to the ECO (arrows 102, 104, and 106). Thus, the design database 80 may be somewhat over-designed if the worst-case correction required for the design arises from one of the partial instances. If changes are made in a sub-region included in a partial instance, design databases 82 and 84 may be extracted from the design database 80 after the changes have been made to update the partial instance.

[0066] Once various validations are complete (clean blocks 108, 110, and 112), tape-out is performed on the whole instance and partial instances (blocks 114, 116, and 118), and datasets for each instance are obtained (blocks 120, 122, and 124).

[0067] In various embodiments, there may be additional analysis and design flows, but similarly, any ECO identified by various design efforts may be implemented in the overall instance design database 80 and then extracted into the partial design databases 82 and 84.

[0068] Another area of ​​integrated circuit design methodology that may be affected by support for whole and partial instances of integrated circuit designs is design proof (DV). DV generally involves testing the design of an integrated circuit, or parts thereof such as a given circuit component, to ensure that the design operates as expected and meets the functional and / or performance requirements of the design. For example, DV may involve defining a test bench to stimulate design and measurement behavior for expected results. The test bench may include, for example, additional HDL code describing the stimuli. To avoid significant rework and additional resources required to perform DV on all instances of the design, a configurable test bench environment covering each instance may be defined. At the component level, components may be tested using the reproduction of chip-level differences between instances.

[0069] Figure 11 is a block diagram showing one embodiment of a testbench configuration for chip-level DV. In this embodiment, the testbench may include a test top level 170 which may include a definition description ($DEFINE) which can be selected to be chip 1 (whole instance), chip 2 (partial instance), or chip 3 (partial instance). That is, for a given simulation, the $DEFINE description may be set to the instance being tested (labeled one of chip 1, chip 2, or chip 3). The test top level 170 may further include a device under test (DUT) 172 (e.g., integrated circuits in partial and whole instances) and a testbench (TB) 174.

[0070] DUT172 may include the integrated circuit components included in each instance (for example, in this embodiment, circuit components 10A to 10B common to each instance). The common part 176 may be unconditionally included in DUT172 for a given simulation. Depending on the instance being tested in a given simulation, one of three additional parts may be conditionally included. For example, if chip 1 is being tested (and therefore the $DEFINE description lists chip 1), the other circuit components 10C to 10D may be included (reference number 178). If chip 2 is being tested (and therefore the $DEFINE description lists chip 2), circuit component 10C and stub 24 may be included (reference number 180). If chip 3 is being tested (and therefore the $DEFINE description lists chip 3), stub 22 may be included in the worst case (reference number 182).

[0071] Testbench 174 may similarly be configurable based on the $DEFINE description. Testbench 174 may include a common part 184 corresponding to a common part 176 (e.g., the stimuli of common part 176). Other parts 184, 186, or 188 may be selectively included based on the $DEFINE description describing chip 1, chip 2, and chip 3, respectively. The stimuli of the corresponding parts 178, 180, and 182 may be included, respectively. That is, the stimuli of the combination of circuit components 10C to 10D may be included in part 186. The stimuli of the combination of circuit component 10C and stub 24 may be included in part 188, and the stimuli of stub 22 may be included in part 190. In one embodiment, part 190 may be omitted because stub 22 does not have to include any active circuit configuration. Alternatively, differences in operation in common part 176 can be captured within part 190.

[0072] Therefore, the same overall setup for test top level 170 allows for the simulation of any instance of the design, with only changes to the $DEFINE description for selecting the design.

[0073] Figure 12 shows an example of circuit component level testing by replication. In this example, chip 1 is shown with specific inputs / outputs (e.g., interfaces) between circuit component 10C and circuit component 10B. Interfaces between other inputs and outputs of circuit components 10A and 10D are received by circuit component 10B but are not shown in Figure 12 for simplification.

[0074] Therefore, the test configuration for circuit component 10B may include the circuit component 10B of the DUT (reference number 192). The interface between circuit component 10B and circuit component 10C may be modeled via a model of circuit component 10C in testbench 194. The model may be a behavioral model of circuit component 10C. Alternatively, the model may be a bus function model of circuit component 10C that faithfully reproduces the operation of circuit component 10C on the interface but omits many internal operations. Any model may be used. The test configuration may be replicated to test the placement of chip 3, for example, including stub 22 to couple various input signals from circuit component 10C to circuit component 10B on the interface upward and downward. The replicated placement includes DUT 192 and testbench 196 that instantiates the upward and downward coupling of stub 22.

[0075] In one embodiment, design integration (DI) can be similarly modified. Design integration includes the process of connecting various circuit components 10A-10D and may provide any necessary “glue logic” that can enable correct communication between circuit components 10A-10D. Various configurations may change when various instances of the integrated circuit are tapeped out. For example, the routing of packets through network switches 70A-70H (or a subset of switches included in a given instance) may be instance-dependent. Therefore, the programming of the routing table 74 may change based on the instance. Other behaviors of the design, such as power management, may also change. If the behavior is not adequately controlled by pull-ups and pull-downs in stubs 22 or 24, fuses may be used to identify the instance and, therefore, the programming of various configuration registers in the routing table 74 or other circuit components 10A-10D. The fuses may be part of the stubs or included in the circuit components 10A-10D and may be selectively blown for a given instance.

[0076] Figure 13 is a flowchart illustrating one embodiment of a method for designing and manufacturing an integrated circuit. For ease of understanding, the blocks are shown in a specific order, but other orders may be used. Individual blocks may be executed in parallel.

[0077] The method may include defining, in a design database corresponding to an integrated circuit design, the area occupied by the integrated circuit design when manufactured on a semiconductor substrate (block 130). The method may further include, optionally, defining a shear line, or two or more shear lines. The shear line can divide the area into a first sub-region and a second sub-region, where the combination of the first and second sub-regions represents an overall instance of the integrated circuit, and the first sub-region and stub region represent a partial instance of the integrated circuit containing fewer circuit components than the overall instance (block 132). The method may further include representing, in the design database, the physical locations of multiple circuit components included in both the overall instance and the partial instance of the integrated circuit within the first sub-region (block 134). In one embodiment, the relative positions of the multiple circuit components within the first sub-region and the interconnects of the multiple circuit components within the first sub-region do not change in the overall instance and the partial instance. The method may further include representing the physical locations of several other circuit components that are included in the overall instance but excluded from the partial instance of the second sub-region in the design database (block 136). The method may further include defining wire terminations in stub regions within the design database that would otherwise traverse shear lines between the first and second sub-regions to ensure the correct operation of several circuit components in the first sub-region in the absence of the second sub-region in the partial instance (block 138). The method may further include creating a first dataset for the overall instance using the first and second sub-regions (block 140). The first dataset may define the overall instance for manufacturing the overall instance. The method may further include creating a second dataset for the partial instance using the first sub-region and stub regions, the second dataset defining the partial instance for manufacturing the partial instance (block 142). The method may further include manufacturing whole and partial instances based on the first and second datasets, respectively (block 144).

[0078] In one embodiment, the stub region may exclude circuit configurations. For example, the stub region may include only wiring in one or more metallization layers above the surface region of the semiconductor substrate. In one embodiment, the other multiple circuit components in the second sub-region may include multiple outputs which are multiple inputs to the multiple circuit components in the first sub-region. The multiple circuit components may include multiple multiplexer circuits having corresponding inputs among the multiple inputs as inputs. The method may further include representing multiple selection signals for the multiple multiplexer circuits in the stub region. The multiple selection signals may be terminated in the stub region with binary values ​​that select inputs of multiple multiplexer circuits different from the inputs to which the multiple inputs are connected. The multiple selection signals may be terminated in the second sub-region with different binary values.

[0079] In one embodiment, the method may further include defining a plurality of exclusion zones at each corner of a semiconductor substrate. Circuit components may be excluded from the plurality of exclusion zones according to the mechanical requirements of the manufacturing process used to manufacture the integrated circuit. The method may further include defining additional exclusion zones at the corners of a first sub-region adjacent to a shear line, thereby allowing a partial instance to include exclusion zones at each corner of the semiconductor substrate on which the partial instance is formed.

[0080] In one embodiment, the method may further include defining a second exclusion zone along the edge of the first sub-region adjacent to the second sub-region. A control collapse chip connection (C4) connection may be excluded from the second exclusion zone. In one embodiment, the method may further include defining one or more first analog inputs within the first sub-region and defining one or more second analog inputs within the second sub-region. One or more first analog inputs may initially remain within the first sub-region, and one or more second analog inputs may remain within the second sub-region. In one embodiment, the method may further include defining one or more first clock trees within the first sub-region to distribute the clock within the first sub-region, and defining one or more second clock trees within the second sub-region to distribute the clock within the second sub-region. One or more first clock trees may be electrically isolated from one or more second clock trees in the overall instance. In one embodiment, the method may further include defining a second shear line in a second sub-region in a design database. The second shear line can divide the second sub-region into a third sub-region and a fourth sub-region, the third sub-region being adjacent to the first sub-region. The third sub-region and the first sub-region may represent a second partial instance of an integrated circuit. The method may further include creating a third dataset relating to the second partial instance using the first sub-region, the third sub-region and the second stub region. The third dataset may define the second partial instance for manufacturing.

[0081] Figure 14 is a flowchart illustrating one embodiment of a method for manufacturing an integrated circuit. For ease of understanding, the blocks are shown in a specific order, but other orders may be used. Individual blocks may be executed in parallel.

[0082] In one embodiment, the method may include receiving a first dataset relating to an entire instance of an integrated circuit design (block 150). The first dataset may define an entire instance for manufacturing the entire instance. The entire instance may include a first plurality of circuit components physically located in a first sub-region of the area occupied on the semiconductor substrate by the entire instance, and a second plurality of circuit components physically located in a second sub-region of the area occupied on the semiconductor substrate by the entire instance. The method may further include receiving a second dataset relating to a partial instance of an integrated circuit design (block 152). The second dataset may define a partial instance for manufacturing the partial instance. The partial instance may include a first plurality of circuit components in the first sub-region, and the relative positions of the first plurality of circuit components in the first sub-region and the interconnects of the first plurality of circuit components in the first sub-region do not change in the entire instance and the partial instance. A partial instance may further include a stub region adjacent to the first subregion, the stub region terminating wires that would otherwise interconnect components in the first and second subregions, thereby ensuring the correct operation of the first set of circuit components in the first subregion in the absence of the second subregion in the partial instance. The method may further include manufacturing a first set of whole instances of an integrated circuit based on a first data set (block 154), and manufacturing a second set of partial instances of an integrated circuit based on a second data set (block 156).

[0083] In one embodiment, the stub region excludes circuit configurations. For example, the stub region may include only wiring in one or more metallization layers above the surface region of the semiconductor substrate. In one embodiment, the other multiple circuit components in the second sub-region include multiple outputs which are multiple inputs to the first multiple circuit components in the first sub-region, and the first multiple circuit components include multiple multiplexer circuits, each having one of the multiple inputs as an input. The stub region may further include multiple selection signals for the multiple multiplexer circuits. In one embodiment, the multiple selection signals are terminated in the stub region with binary values ​​that select inputs of the multiple multiplexer circuits that are different from the inputs to which the multiple inputs are connected. The multiple selection signals may be terminated in the second sub-region with different binary values ​​in the overall instance.

[0084] In one embodiment, the first dataset may include a plurality of exclusion zones at each corner of the semiconductor substrate. Circuit components may be excluded from the plurality of exclusion zones according to the mechanical requirements of the manufacturing process used to manufacture the integrated circuit. The first dataset may further include additional exclusion zones at the corners of the first sub-region adjacent to the second sub-region, thereby allowing a partial instance to include exclusion zones at each corner of the semiconductor substrate on which the partial instance is formed. In one embodiment, the first dataset may further include a second exclusion zone along the edge of the first sub-region adjacent to the second sub-region, with controlled collapse chip connections (C4) connections excluded from the second exclusion zone. In one embodiment, the first dataset may further include one or more first analog inputs in the first sub-region and one or more second analog inputs in the second sub-region. One or more first analog inputs remain within the first sub-region, and one or more second analog inputs remain within the second sub-region. In one embodiment, the first dataset may further include one or more first clock trees for distributing clocks within a first subregion and one or more second clock trees for distributing clocks within a second subregion, wherein in the overall instance, one or more first clock trees are electrically isolated from one or more second clock trees. Computer-readable storage media

[0085] Referring now to Figure 15, a block diagram of one embodiment of a computer-readable storage medium 800 is shown. Generally, a computer-accessible storage medium may include any storage medium that is accessible by a computer when in use to provide instructions and / or data to the computer. For example, a computer-accessible storage medium may include magnetic or optical media, such as (fixed or removable) disks, tapes, CD-ROMs, DVD-ROMs, CD-Rs, CD-RWs, DVD-Rs, DVD-RWs, or Blu-rays. The storage medium may further include volatile or non-volatile memory media, such as RAM (e.g., synchronous DRAM (SDRAM), Rambus DRAM (RDRAM), static RAM (SRAM), etc.), ROMs, or flash memory. The storage medium may be physically mounted in the computer from which it provides instructions / data. Alternatively, the storage medium may be connected to the computer. For example, the storage medium may be connected to the computer via a network or wireless link, such as network-attached storage. The storage medium may be connected via a peripheral device interface such as a Universal Serial Bus (USB). Generally, computer-accessible storage media 800 can store data in a non-temporary manner, where non-temporary in this context may mean that instructions / data are not transmitted over signals. For example, non-temporary storage may be volatile (stored instructions / data may be lost upon power outage) or non-volatile.

[0086] The computer-accessible storage medium 800 in Figure 15 may store databases 802, 804, and 806 representing whole instances and partial instances of integrated circuits. Generally, databases 802, 804, and 806 may be databases that are read by a program and used directly or indirectly to manufacture hardware containing instances. For example, the databases may be operation-level descriptions or register-transfer-level (RTL) descriptions of hardware functions in a high-level design language (HDL) such as Verilog or VHDL. The descriptions can be read by a synthesis tool that can synthesize the descriptions to generate a netlist containing a list of gates from a synthesis library. The netlist contains a set of gates that also represent the functions of the hardware containing the instances. The netlist can then be arranged and routed to generate a dataset that describes the geometric shapes applied to the mask. The mask can then be used in various semiconductor fabrication steps to generate one or more semiconductor circuits corresponding to the instances. Alternatively, databases 802, 804, and 806 on the computer-accessible storage medium 800 may, as desired, be netlists or datasets (with or without synthetic libraries).

[0087] The computer-accessible storage medium 800 stores a representation of the instance, but other embodiments may, if necessary, hold representations of any part of the instance. Computer system

[0088] Next, moving to Figure 16, a block diagram of one embodiment of system 700 is shown. In the illustrated embodiment, system 700 includes at least one instance of a system on a chip (SOC) 706 coupled to one or more peripheral devices 704 and an external memory 702. A power supply unit (PMU) 708 is presented which supplies supply voltage to the SOC 10 and one or more supply voltages to the memory 702 and / or peripheral devices 704. In some embodiments, two or more instances of SOC 706 may be included (and two or more memories 702 may also be included). More specifically, SOC 706 may be any (e.g., whole or in part) instance of the integrated circuit described herein.

[0089] The peripheral device 704 may include any desired circuit configuration depending on the type of system 700. For example, in one embodiment, the system 700 The system 700 may be a mobile device (e.g., a personal digital assistant (PDA), a smartphone, etc.), and the peripheral device 704 may include devices for various types of wireless communication, such as Wi-Fi, Bluetooth, cellular, and global positioning systems. The peripheral device 704 may also include additional storage devices, such as RAM storage, solid-state storage, or disk storage. The peripheral device 704 may include user interface devices such as a display screen, including a touch display screen or a multi-touch display screen, a keyboard or other input devices, a microphone, and a speaker. In other embodiments, the system 700 may be any type of computing system (e.g., a desktop personal computer, a laptop computer, a workstation, a nettop, etc.).

[0090] External memory 702 may include any type of memory. For example, external memory 702 may be dynamic RAM (DRAM) such as SRAM, synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, RAMBUS DRAM, or low-power versions of DDR DRAM (e.g., LPDDR, mDDR, etc.). External memory 702 may include one or more memory modules on which memory devices such as single inline memory modules (SIMMs) or dual inline memory modules (DIMMs) are mounted. Alternatively, external memory 702 may include one or more memory devices mounted on the SOC 706 in a chip-on-chip or package-on-package configuration.

[0091] As illustrated, System 700 is shown to be applicable to a wide range of areas. For example, System 700 may be used as part of the chips, circuits, components, etc., of a desktop computer 710, a laptop computer 720, a tablet computer 730, a cellular or mobile phone 740, or a television 750 (or a set-top box connected to a television). A smartwatch and a health monitoring device 760 are also illustrated. In some embodiments, the smartwatch may include a variety of general-purpose computing-related functions. For example, the smartwatch may provide access to email, mobile phone services, a user calendar, etc. In various embodiments, the health monitoring device may be a dedicated medical device or may otherwise include dedicated health-related functions. For example, the health monitoring device may monitor the user's vital signs, track the user's proximity to other users for epidemiological social distancing, perform contact tracing, and provide communication to emergency services in the event of a health crisis. In various embodiments, the smartwatch described above may or may not include some or any of the health monitoring-related functions. Other wearable devices, such as devices worn around the neck, implantable devices in the human body, and glasses designed to provide augmented and / or virtual reality experiences, are also intended.

[0092] System 700 may be further used as part of a cloud-based service(s) 770. For example, the aforementioned devices and / or other devices may access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Furthermore, System 700 may be used in one or more other devices in a home. For example, household appliances may monitor and detect conditions of note. For example, various household devices (e.g., refrigerators, cooling systems, etc.) may monitor their status and alert the homeowner (or repair facility) if a specific event is detected. Alternatively, a thermostat may monitor the temperature in the home and automate the adjustment of the heating / cooling system based on the homeowner's response history to various conditions. Also, Figure 16 illustrates the application of System 700 to various modes of transport. For example, System 700 may be used in control and / or entertainment systems for aircraft, trains, buses, rental vehicles, private cars, ships ranging from privately owned boats to cruise ships, and scooters (rented or owned). In various cases, System 700 can be used to provide automatic guidance (e.g., autonomous vehicles), general system control, and other methods. Many other embodiments of these are possible and contemplated. Note that the devices and applications shown in Figure 16 are illustrative and not intended to be limiting. Other devices are possible and contemplated. ***

[0093] This disclosure includes references to “one embodiment” or a group of “embodiments” (e.g., “several embodiments” or “various embodiments”). Embodiments are different implementations or examples of the disclosed concepts. References to “embodiments,” “one embodiment,” “a particular embodiment,” etc., do not necessarily refer to the same embodiment. Numerous possible embodiments, including those specifically disclosed, and modifications or substitutions within the spirit or scope of this disclosure are intended.

[0094] This disclosure can discuss the potential benefits that may arise from the disclosed embodiments. All implementations of these embodiments will inevitably exhibit some or all of the potential benefits. Whether a benefit is realized for a particular implementation depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why an implementation within the claims may not exhibit some or all of any disclosed benefits. For example, a particular implementation may include other circuits outside the scope of this disclosure that, together with one of the disclosed embodiments, negate or reduce one or more of the disclosed benefits. Furthermore, suboptimal design execution of a particular implementation (e.g., implementation technique or tool) may also negate or reduce the disclosed benefits. Even assuming skilled execution, the realization of benefits may still depend on other factors, such as the environmental conditions in which the implementation is deployed. For example, the inputs supplied to a particular implementation may prevent one or more of the problems addressed in this disclosure from occurring on certain occasions, and as a result, the benefits of the solution may not be realized. Given the existence of possible external factors of this disclosure, it is expressly intended that any potential benefits described herein should not be construed as limitations on claims that must be satisfied to demonstrate infringement. Rather, the identification of such potential benefits is intended to illustrate the types of improvements available to designers who have an interest in this disclosure. The acceptable description of such benefits (e.g., the statement that a particular benefit "may occur") is not intended to convey any doubt as to whether such benefits can actually be realized, but rather to acknowledge the technical reality that the realization of such benefits often depends on additional factors.

[0095] Unless otherwise specified, the embodiments are non-limiting. That is, even if only a single embodiment describes a particular feature, the disclosed embodiments are not intended to limit the scope of claims made based on this disclosure. The disclosed embodiments are intended to be illustrative, not limiting, unless there is a statement to the contrary in this disclosure. The foregoing is intended to enable claims that cover not only the disclosed embodiments but also alternatives, modifications, and equivalents that would be obvious to a person skilled in the art who would benefit from this disclosure.

[0096] For example, the features of this application can be combined in any preferred manner. Therefore, new claims can be formulated for any such combination of features during the examination of this application (or an application claiming priority to this application). In particular, referring to the attached claims, features from dependent claims can be combined with features from other dependent claims, including claims dependent on other independent claims, as appropriate. Similarly, features from each independent claim can be combined as appropriate.

[0097] Accordingly, each of the attached dependent claims may be constructed to depend on a single other claim, but additional dependencies are also contemplated. Any combination of features in the dependent claims that are consistent with this disclosure is contemplated and may be claimed in this application or another application. In summary, the combinations are not limited to those specifically enumerated in the attached claims.

[0098] Where appropriate, claims prepared in one format or legal type (e.g., apparatus) are intended to also support corresponding claims in another format or legal type (e.g., method). ***

[0099] As this disclosure is a legal document, various terms and phrases may be subject to administrative and judicial interpretation. The following paragraphs, and the provisions provided through this disclosure, are hereby publicly noted as being used in interpreting the claims made pursuant to this disclosure.

[0100] References to singular items (i.e., nouns or noun phrases preceded by "a," "an," or "the") are intended to mean "one or more" unless otherwise explicitly stated in the context. Therefore, references to "items" in the claims do not, without context, exclude additional instances of an item. "Multiple" items refer to a set of two or more items.

[0101] In this specification, the word "may" is used in an allowable sense (i.e., possible, feasible) and not in an obligatory sense (i.e., not required).

[0102] The terms and forms "comprising" and "including" are open-ended and mean "to include, but not to limit."

[0103] Where the term “or” is used in this disclosure in relation to a list of options, it will generally be understood to be used in an inclusive sense unless otherwise explicitly stated in the context. Thus, the enumeration of “x or y” is equivalent to “x or y, or both,” and therefore includes 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, the phrase “either x or y, but not both” clarifies that “or” is used in an exclusive sense.

[0104] The enumerations "w, x, y, z, or any combination thereof" or "...at least one of w, x, y, and z" are intended to cover all possibilities, including single elements up to the total number of elements in the set. For example, in the set [w, x, y, z], these expressions cover any single element in the set (e.g., w, but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. Thus, the phrase "...at least one of w, x, y, and z" refers to at least one element in the set [w, x, y, z], thereby covering all possible combinations in this list of elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0105] In this disclosure, various “labels” may precede nouns or noun phrases. Unless otherwise explicitly stated in the context, the various labels used for features (e.g., “first circuit,” “second circuit,” “specific circuit,” “given circuit,” etc.) refer to different examples of the feature. Furthermore, when applied to features, the labels “first,” “second,” and “third” do not imply any type of order (e.g., spatial, temporal, logical, etc.) unless otherwise specified.

[0106] As used herein, the phrase "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the determination; that is, the determination may be based on the specified factor alone, or on the specified factor and other unspecified factors. Consider the phrase "determine A based on B." This phrase identifies B as a factor used to determine A or that influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on some other factor, such as C. This phrase is intended to cover embodiments in which A is determined based solely on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0107] The phrases “in response to” and “in response to” describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may affect or otherwise trigger the effect, either in conjunction with a specific factor or independently of the specified factor. That is, the effect may depend on these factors alone, or on the specified factor and other unspecified factors. Consider the phrase “perform A in response to B.” This phrase means that B is a factor that triggers the performance of A, or a specific outcome with respect to A. This phrase does not exclude the fact that the performance of A may also depend on other factors, such as C. This phrase also does not exclude the fact that performing A may depend on both B and C. This phrase is intended to include embodiments in which A is performed only in response to B. As used herein, the phrase “in response to” is synonymous with the phrase “in response to at least partially.” Similarly, the phrase “in response to” is synonymous with the phrase “in at least partially.” ***

[0108] Within this disclosure, various entities (which may be referred to as "units," "circuits," or other components, etc.) may be described or claimed to be “configured” to perform one or more tasks or operations. The expression “configured to perform one or more tasks” is used herein to refer to structures (i.e., physical things). More specifically, the expression is used to indicate that the structure is arranged to perform one or more tasks while in operation. A structure may be said to be “configured” to perform some task even when it is not currently in operation. Thus, entities described or explained as “configured” to perform some task refer to physical things such as devices, circuits, systems having a processor unit and memory storing program instructions executable to perform the task. This phrase is not used herein to refer to intangible things.

[0109] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. Even if not specifically stated, it is understood that those entities are "configured" to perform those tasks / operations.

[0110] The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA is not considered "configured" to perform a particular function. However, this unprogrammed FPGA may be "configurable" to perform that function. After proper programming, the FPGA can then be said to be "configured" to perform a particular function.

[0111] For the purposes of a U.S. patent application based on this disclosure, any claim that states a structure is “configured” to perform one or more tasks is not expressly intended to invoke Section 112(f) of the U.S. Patent Act with respect to that claim element. If an applicant wishes to invoke Section 112(f) during the examination process of a U.S. patent application based on this disclosure, it would use “means for” performing the function to describe the claim element.

[0112] This disclosure may describe various “circuits.” These circuits or “circuit configurations” constitute hardware that includes various types of circuit elements, such as combinational logic, clock memory devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), and programmable logic arrays. Circuits may be custom designed or obtained from standard libraries. In various implementations, circuit configurations may include digital components, analog components, or a combination of both, as needed. Certain types of circuits may be generally referred to as “units” (e.g., decoding units, arithmetic logic units (ALUs), function units, memory management units (MMUs), etc.). Such units also refer to circuits or circuit configurations.

[0113] The disclosed circuits / units / components and other elements shown in the drawings and described herein include hardware elements such as those described in the preceding paragraphs. Often, the internal arrangement of hardware elements within a particular circuit can be specified by describing the function of that circuit. For example, a particular “decoder unit” may be described as performing the function of “processing the opcode of an instruction and routing the instruction to one or more of several functional units,” meaning that the decoder unit is “configured” to perform this function. The detail of this function is sufficient to imply to a person skilled in the art of computer technology a set of possible structures of the circuit.

[0114] In various embodiments, as discussed in the preceding paragraph, circuits, units, and other elements are defined by the function or operation they are configured to perform. The arrangement of such circuits / units / components relative to each other and the way they interact generates a microarchitectural specification of hardware that is ultimately manufactured in an integrated circuit or programmed into an FPGA, forming a physical implementation of the microarchitectural specification. Thus, a microarchitectural specification is recognized by those skilled in the art as a structure from which many physical implementations can be derived, and all of its implementations belong to the broader structure described by the microarchitectural specification. That is, a person skilled in the art, presented with the microarchitectural specification provided pursuant to this disclosure, will implement the structure by coding the circuit / unit / component description in a hardware description language (HDL), such as Verilog or VHDL, using ordinary art without excessive experimentation. The HDL description is often expressed in a form that appears functional. However, to those skilled in the art, this HDL description is a method used to translate the structure of a circuit, unit, or component into the next level of implementation detail. Such HDL descriptions can take the form of behavioral code (typically not synthesizable), register transfer language (RTL) code (typically synthesizable, in contrast to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connections). The HDL description may be synthesized against a library of cells designed for a given integrated circuit manufacturing technique, modified for timing, power, and other reasons, resulting in a final design database that can be sent to a foundry to generate a mask and ultimately manufacture the integrated circuit. Some hardware circuits or parts thereof can also be custom designed in a schematic editor and incorporated into the integrated circuit design along with the synthesized circuits. The integrated circuit may further include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, and inductors), as well as interconnects between transistors and circuit elements.In some embodiments, multiple integrated circuits connected integrally can be implemented to realize the hardware circuit, and / or, in some embodiments, separate elements can be used. Alternatively, the HDL design may be integrated into a programmable logic array such as a field programmable gate array (FPGA), or implemented on an FPGA. This decoupling between the design of this set of circuits and the subsequent low-level implementation of these circuits generally leads to scenarios where the circuit or logic designer does not specify any particular set of structures for the low-level implementation form, other than a description of how the circuit is configured, because this process is performed at different stages of the circuit implementation process.

[0115] The fact that the same specifications of a circuit can be implemented using many different low-level combinations of circuit elements results in a multitude of equivalent structures for that circuit. As mentioned above, these low-level circuit implementation forms can vary depending on changes in manufacturing technology, the foundry chosen to manufacture the integrated circuit, the library of cells provided for a particular project, and so on. Often, the choice made by different design tools or methods to generate these different implementation forms can be arbitrary.

[0116] Furthermore, in a given embodiment, a single implementation of a specific functional specification of a circuit typically involves a large number of devices (e.g., millions of transistors). Therefore, given this sheer volume of information, it is impractical to fully enumerate the low-level structures used to implement a single embodiment, let alone a vast number of equivalent possible implementations. For this reason, this disclosure describes the circuit structure using functional omissions commonly used in the industry.

[0117] The description of the subject matter of this application includes, but is not limited to, the following embodiments: Examples of the method: 1. A method, Receiving a first dataset relating to an overall instance of an integrated circuit design, wherein the first dataset defines the overall instance for manufacturing the overall instance, and the overall instance includes a first plurality of circuit components physically located in a first sub-region of the region occupied on the semiconductor substrate by the overall instance, and a second plurality of circuit components physically located in a second sub-region of the region occupied on the semiconductor substrate by the overall instance. Receiving a second dataset relating to a partial instance of an integrated circuit design, wherein the second dataset defines the partial instance for manufacturing the partial instance, the partial instance comprising a first plurality of circuit components within a first sub-region, the relative positions of the first plurality of circuit components within the first sub-region and the interconnects of the first plurality of circuit components within the first sub-region being unchanged in the whole instance and the partial instance, the partial instance further comprising a stub region adjacent to the first sub-region, the stub region comprising the ends of wires that would otherwise interconnect the components within the first and second sub-regions, and ensuring the correct operation of the first plurality of circuit components within the first sub-region in the absence of the second sub-region in the partial instance, Based on the first dataset, the first multiple overall instances of the integrated circuit are manufactured, A method comprising manufacturing a second set of partial instances of an integrated circuit based on a second dataset. 2. The method according to Example 1, wherein the stub region excludes the circuit configuration. 3. The method according to Example 2, wherein the stub region includes only wiring in one or more metallization layers above the surface region of the semiconductor substrate. 4. The method according to Embodiment 1, wherein a plurality of other circuit components in the second sub-region include a plurality of outputs which are a plurality of inputs to a plurality of first circuit components in the first sub-region, the first plurality of circuit components include a plurality of multiplexer circuits each having one of the plurality of inputs as an input, and the stub region further includes a plurality of selection signals to the plurality of multiplexer circuits. 5. The method according to Embodiment 4, wherein multiple selection signals are terminated in a stub region with binary values ​​that select the inputs of multiple multiplexer circuits, which are different from the inputs to which the multiple inputs are connected. 6. The method according to Embodiment 5, wherein multiple selection signals are terminated in a second sub-region with different binary values ​​in the overall instance. 7. The method according to Example 1, wherein the first dataset includes a plurality of exclusion zones at each corner of the semiconductor substrate, the circuit components are excluded from the plurality of exclusion zones according to the mechanical requirements of the manufacturing process used to manufacture the integrated circuit, and the first dataset includes additional exclusion zones at the corners of the first sub-region adjacent to the second sub-region, thereby the partial instance includes exclusion zones at each corner of the semiconductor substrate on which the partial instance is formed. 8. The method according to Example 1, wherein the first dataset further includes a second exclusion zone along the edge of the first subregion adjacent to the second subregion, and control collapse chip connection (C4) connections are excluded from the second exclusion zone. 9. The method according to Embodiment 1, wherein the first dataset further includes one or more first analog inputs in a first sub-region, with one or more first analog inputs remaining within the first sub-region, and the first dataset further includes one or more second analog inputs in a second sub-region, with one or more second analog inputs remaining within the second sub-region. 10. The method according to Embodiment 1, wherein the first dataset further includes one or more first clock trees for distributing clocks within a first subregion and one or more second clock trees for distributing clocks within a second subregion, and in the overall instance, one or more first clock trees are electrically isolated from one or more second clock trees. Examples of integrated circuits: 11. Integrated circuits, A plurality of circuit components physically arranged on the surface of a semiconductor substrate forming an integrated circuit, comprising a plurality of multiplexer circuits, wherein a given multiplexer circuit of the plurality of multiplexer circuits has a first input wire, a second input wire, and a selection control wire, A region along a single edge of the surface, The region is the power source for the selection control wire. The second input wire reaches a single edge of the surface and is unconnected. A selection control wire is electrically connected to the supply wire of an integrated circuit, and the voltage on the supply wire in use corresponds to a digital logic level that causes multiple multiplexer circuits to select a first input wire as the output of the multiple multiplexer circuits, in a region. An integrated circuit comprising: 12. Integrated circuits, A first plurality of circuit components physically arranged within a first region on the surface of a semiconductor substrate forming an integrated circuit, Multiple exclusion zones at each corner of a semiconductor substrate, wherein circuit components are excluded from the multiple exclusion zones according to the mechanical requirements of the manufacturing process used to manufacture the integrated circuit, Separated from each corner and along a pair of nominally parallel edges of the semiconductor substrate, there are other exclusion zones from which circuit components are excluded, and the other exclusion zones are substantially the same size as the other exclusion zones. An integrated circuit comprising: 13. The integrated circuit according to Example 12, further comprising a second exclusion zone along a line between multiple exclusion zones, wherein the control collapse chip connection (C4) connection is excluded from the second exclusion zone. 14. One or more first analog inputs within a first sub-domain of a first domain, which remain within the first sub-domain, The integrated circuit according to Embodiment 12, further comprising one or more second analog inputs in a second sub-region of the first region adjacent to the first sub-region, the second analog inputs remaining within the second sub-region. 15. One or more clock trees for distributing clocks within a first sub-domain of a first domain, It further comprises one or more second clock trees for distributing clocks within a second sub-region, The integrated circuit according to Example 12, wherein one or more first clock trees are electrically isolated from one or more second clock trees. 16. Integrated circuits, A first plurality of circuit components physically arranged within a first region on the surface of a semiconductor substrate forming an integrated circuit, A second set of circuit components physically arranged within a second region on the surface of a semiconductor substrate forming an integrated circuit, One or more first analog inputs within a first region, separated into a first plurality of circuit components, One or more second analog inputs in a second region, separated into a second plurality of circuit components, An integrated circuit comprising:

[0118] If the above disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art. The following claims are intended to be interpreted as encompassing all such variations and modifications.

Claims

1. A method for manufacturing an integrated circuit, wherein the method is Receiving a dataset for manufacturing an instance of an integrated circuit, the instance is A plurality of circuit components physically arranged on the surface of a semiconductor substrate including the aforementioned integrated circuit, A plurality of termination connections formed in a stub region of the integrated circuit along a single edge of the surface, wherein the plurality of termination connections are wires, which are inputs to one or more of the plurality of circuit components, are oriented to intersect the single edge, and are electrically connected to a plurality of supply wires of the integrated circuit for providing a fixed digital logic level on the wires, which lack circuits configured to drive the wires, and the stub region includes a plurality of termination connections that exclude active circuit elements. A method comprising manufacturing a plurality of instances of the integrated circuit based on the dataset.

2. The method according to claim 1, The plurality of circuit components include a multiplexer circuit having a first input wire, a second input wire, and a selection control wire. The second input wire reaches the single edge of the surface and is not connected. The selection control wire is electrically connected to the supply wire of the integrated circuit in order to cause the multiplexer circuit to select the first input wire as the output of the multiplexer circuit.

3. A method according to claim 1, wherein the stub region comprises only wiring in one or more metallization layers on the surface of the semiconductor substrate.

4. The method according to claim 1, The first subset of the plurality of circuit components is physically arranged within a first sub-region of the surface of the semiconductor substrate. The aforementioned instance is A plurality of exclusion zones located at each corner of the semiconductor substrate, wherein circuit components are excluded from the plurality of exclusion zones in accordance with the mechanical requirements of the manufacturing process used to manufacture the integrated circuit, A method further comprising: an additional plurality of exclusion zones separated from each of the aforementioned corners and along a pair of parallel edges of the semiconductor substrate, located at the corners of the first sub-region, wherein circuit components are excluded from the additional plurality of exclusion zones, and the additional plurality of exclusion zones are the same dimensions as the plurality of exclusion zones.

5. A method according to claim 4, wherein an instance of the method further includes a second exclusion zone along a line between the plurality of exclusion zones, wherein a control collapse chip connection (C4) connection is excluded from the second exclusion zone.

6. The method according to claim 4, wherein the instance is One or more first analog inputs in the first sub-region, wherein the one or more first analog inputs remain within the first sub-region, A method further comprising: one or more second analog inputs in a second sub-region adjacent to the first sub-region, wherein the one or more second analog inputs remain within the second sub-region.

7. The method according to claim 4, wherein the instance is One or more first clock trees for distributing clocks within the first sub-region, A method further comprising: one or more second clock trees for distributing a clock within a second sub-region adjacent to the first sub-region, wherein the one or more first clock trees are electrically isolated from the one or more second clock trees.

8. The method according to Claim 1, The first subset of the plurality of circuit components is physically arranged within a first sub-region of the surface of the semiconductor substrate. The instance further includes one or more first analog inputs in the first sub-region, wherein a wire for transmitting signals derived from the one or more first analog inputs is included within the first sub-region. The instance further includes one or more second analog inputs in a second sub-region adjacent to the first sub-region, wherein the wires for transmitting signals derived from the one or more second analog inputs are located within the second sub-region. method.

9. The method according to Claim 1, The first subset of the plurality of circuit components is physically arranged within a first sub-region of the surface of the semiconductor substrate. The instance further includes one or more first clock trees for distributing clocks within the first subregion, The instance further includes one or more second clock trees for distributing clocks within a second sub-region adjacent to the first sub-region, The one or more first clock trees are electrically isolated from the one or more second clock trees. method.

10. The method according to Claim 1, The first subset of the plurality of circuit components is physically arranged within a first sub-region of the surface of the semiconductor substrate. The aforementioned instance is A plurality of exclusion zones located at each corner of the semiconductor substrate, wherein circuit components are excluded from the plurality of exclusion zones in accordance with the mechanical requirements of the manufacturing process used to manufacture the integrated circuit, A plurality of additional exclusion zones located at the corners of the first sub-region, separated from each of the aforementioned corners and along a pair of parallel edges of the semiconductor substrate, wherein circuit components are excluded from the plurality of additional exclusion zones, Methods that further include this.

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