Imaging device

Abstract

This imaging device comprises: a semiconductor substrate; a plurality of pixels arrayed on the semiconductor substrate in a first direction; and a first signal line positioned above the semiconductor substrate. Each of the pixels includes a photoelectric conversion unit that converts light into a signal charge, a transistor that has a gate electrically connected to the first signal line, and a capacitive element. In a first pixel of the pixels, at least a portion of the transistor overlaps the capacitive element in the plan view. The first signal line does not overlap the capacitive element on the entire line width in the plan view.

Description

[Technical Field]

[0001] The present disclosure relates to an image pickup apparatus. [Background Art]

[0002] An image sensor is used in digital cameras and the like. Examples of the image sensor include a CCD (Charge Coupled Device) image sensor, a CMOS (Complementary Metal Oxide Semiconductor) image sensor, and the like. An image pickup apparatus can be configured using an image sensor. In an image pickup apparatus according to one example, a photodiode is provided on a semiconductor substrate. In an image pickup apparatus according to another example, a photoelectric conversion film is laminated above a semiconductor substrate.

[0003] Patent Document 1 discloses an image pickup apparatus having a photodiode. Patent Document 2 discloses an image pickup apparatus having a photoelectric conversion film. In the image pickup apparatuses disclosed in Patent Document 1 and Patent Document 2, a pixel includes a capacitive element. The entire disclosure of Patent Document 2 is incorporated herein by reference. [Prior Art Documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Unexamined Patent Publication No. 2016-105468 [Patent Document 2] Japanese Unexamined Patent Publication No. 2018-195803 [Summary of the Invention] [Problem to be Solved by the Invention]

[0005] There is a demand for an image pickup apparatus capable of high-speed imaging. [Means for Solving the Problem]

[0006] An image pickup apparatus according to an aspect of the present disclosure includes: a semiconductor substrate, and A plurality of pixels arranged in a first direction on the semiconductor substrate, A first signal line located above the semiconductor substrate, Equipped with, Each of the aforementioned plurality of pixels is A photoelectric conversion unit that converts light into signal charge, A transistor having a gate electrically connected to the first signal line, Capacitive elements, Includes, In the first pixel among the plurality of pixels, At least a portion of the transistor overlaps with the capacitive element in a plan view, In a plan view, the first signal line does not overlap with the capacitive element in terms of overall line width.

[0007] An imaging device relating to one aspect of this disclosure is: Semiconductor substrate and A plurality of pixels arranged in a first direction on the semiconductor substrate, A first signal line located above the semiconductor substrate, Equipped with, Each of the aforementioned plurality of pixels is A photoelectric conversion unit that converts light into signal charge, A transistor having a gate electrically connected to the first signal line, Capacitive elements, Includes, In the first pixel among the plurality of pixels, At least a portion of the transistor overlaps with the capacitive element in a plan view, In a plan view, the first signal line does not overlap with the capacitive element for a distance longer than half the maximum length of the capacitive element in the first direction. [Effects of the Invention]

[0008] The above-described aspects of this disclosure are suitable for providing an imaging device capable of high-speed imaging. [Brief explanation of the drawing]

[0009] [Figure 1] FIG. 1 is a diagram schematically illustrating an exemplary circuit configuration of an image capturing apparatus according to the first embodiment. [Figure 2] FIG. 2 is a diagram illustrating an exemplary circuit configuration of a pixel according to the first embodiment. [Figure 3] FIG. 3 is a plan view schematically illustrating an example of a layout of some elements in the pixel according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view schematically illustrating a cross-section along the line A-A' shown in FIG. 3. [Figure 5] FIG. 5 is a diagram illustrating an exemplary circuit configuration of a pixel using a photodiode. [Figure 6] FIG. 6 is a schematic diagram for explaining a plurality of pixels according to the first embodiment. [Figure 7] FIG. 7 is a schematic diagram for explaining a plurality of pixels according to a modification. [Figure 8] FIG. 8 is a plan view for explaining a direction in which a signal line extends. [Figure 9] FIG. 9 is a plan view for explaining a direction in which a signal line extends. [Figure 10] FIG. 10 is a plan view for explaining a direction in which a signal line extends. [Figure 11] FIG. 11 is a plan view for explaining dimensions of a capacitive element. [Figure 12] FIG. 12 is a plan view for explaining a maximum length of a capacitive element. [Figure 13] FIG. 13 is a plan view for explaining a maximum length of a capacitive element. [Figure 14] FIG. 14 is a plan view schematically illustrating an example of a layout of some wirings and some elements in a pixel according to the first embodiment. [Figure 15] FIG. 15 is a cross-sectional view schematically illustrating a cross-section of an image capturing apparatus according to a first reference example. [Figure 16] FIG. 16 is a cross-sectional view schematically illustrating a cross-section of an image capturing apparatus according to a second reference example. [Figure 17]Figure 17 is a schematic cross-sectional view showing a cross-section of the imaging device according to Embodiment 1. [Figure 18] Figure 18 is a cross-sectional view showing a capacitive element having a trench structure. [Figure 19] Figure 19 is a schematic plan view showing an example of the layout of some wiring and some elements in a pixel according to Embodiment 2. [Figure 20] Figure 20 is a schematic plan view showing an example of the layout of some wiring and some elements in a pixel according to Embodiment 3. [Figure 21] Figure 21 is a schematic plan view showing an example of the layout of some wiring and some elements in a pixel according to Embodiment 4. [Figure 22] Figure 22 is a schematic plan view showing an example of the layout of some wiring and some elements in a pixel according to Embodiment 5. [Figure 23] Figure 23 is a schematic plan view showing an example of the layout of some elements in some wiring and pixels according to other embodiments. [Figure 24] Figure 24 is a schematic plan view showing an example of the layout of some elements in some wiring and pixels according to other embodiments. [Modes for carrying out the invention]

[0010] (Knowledge that forms the basis of this disclosure) An example imaging device includes a plurality of pixels arranged in a predetermined direction. Each pixel includes a plurality of transistors. A signal line is connected to each transistor. Each signal line extends from a peripheral circuit along a predetermined direction so as to traverse the plurality of pixels, is connected to the corresponding transistor of each pixel, and transmits a control signal to the corresponding transistor. Each pixel also includes a capacitive element. The capacitive element is used for purposes such as expanding the dynamic range and noise cancellation.

[0011] Capacitive elements may have high capacitance values. In this case, the proportion of the area occupied by the capacitive element in a pixel tends to be large in a planar view. Therefore, the signal line and the capacitive element tend to overlap in a planar view. According to the inventors' research, this overlap increases the parasitic capacitance between the signal line and the capacitive element, delaying the control signal flowing through the signal line and potentially slowing down the imaging speed.

[0012] Therefore, the inventors considered a configuration that enables high-speed imaging by devising an arrangement of capacitive elements and signal lines.

[0013] (Summary of one aspect of this disclosure) The imaging device relating to the first aspect of this disclosure is Semiconductor substrate and A plurality of pixels arranged in a first direction on the semiconductor substrate, A first signal line located above the semiconductor substrate, Equipped with, Each of the aforementioned plurality of pixels is A photoelectric conversion unit that converts light into signal charge, A transistor having a gate electrically connected to the first signal line, Capacitive elements, Includes, In the first pixel among the plurality of pixels, At least a portion of the transistor overlaps with the capacitive element in a plan view, In a plan view, the first signal line does not overlap with the capacitive element in terms of overall line width.

[0014] The technology relating to the first embodiment is suitable for providing an imaging device capable of high-speed imaging.

[0015] In a second aspect of this disclosure, for example, in the imaging device according to the first aspect, The gate of the transistor of the first pixel may include a first portion that does not overlap with the capacitive element in a plan view. The first portion of the transistor in the first pixel may be electrically connected to the first signal line.

[0016] The configuration of the second embodiment is an example of a configuration that connects a signal line to the gate of a transistor corresponding to the signal line.

[0017] In a third aspect of this disclosure, for example, the imaging device according to the second aspect may further include vias in contact with the first portion, The first portion of the transistor may be electrically connected to the first signal line via the via.

[0018] The third aspect is an example of a configuration that connects a signal line to the gate of a transistor corresponding to the signal line.

[0019] In a fourth aspect of this disclosure, for example, an imaging device according to any one of the first to third aspects may further include branched signal lines. The aforementioned branch signal line may extend from the first signal line. In a plan view, the direction in which the branch signal line extends may differ from the direction in which the first signal line extends. The first signal line may be electrically connected to the transistor of the first pixel via the branch signal line.

[0020] The configuration of the fourth aspect is an example of a configuration that connects a signal line to the gate of a transistor corresponding to the signal line.

[0021] In a fifth aspect of this disclosure, for example, in an imaging device according to any one of the first to fourth aspects, In a plan view, the first signal line does not need to overlap with the capacitive element of the first pixel by a width of more than half the line width.

[0022] The technology relating to the fifth embodiment is suitable for providing an imaging device capable of high-speed imaging.

[0023] In the sixth aspect of this disclosure, for example, in an imaging device according to any one of the first to fifth aspects, The first signal line does not necessarily have to overlap with the capacitive element of the first pixel in a plan view.

[0024] The technology relating to the sixth embodiment is suitable for providing an imaging device capable of high-speed imaging.

[0025] In a seventh aspect of this disclosure, for example, an imaging device according to any one of the first to sixth aspects may further include a plurality of wiring layers located above the semiconductor substrate. The plurality of wiring layers may include a first wiring layer and a second wiring layer that are adjacent to each other. The capacitive element may be configured using the first wiring layer. The first signal line may be included in the second wiring layer.

[0026] As in the seventh embodiment, when a capacitive element is constructed using one of two adjacent wiring layers, and the other wiring layer contains a signal line, the parasitic capacitance between the signal line and the capacitive element can become large. Large parasitic capacitance means that the effect of suppressing parasitic capacitance is easily achieved based on the planar layout of the signal line and capacitive element according to the first embodiment. In other words, this means that this planar layout is likely to contribute to faster imaging.

[0027] In the eighth aspect of this disclosure, for example, in an imaging device according to any one of the first to seventh aspects, In a plan view, the maximum length of the capacitive element of the first pixel along the first direction may be greater than one-third of the length of the first pixel along the first direction.

[0028] The signal lines are electrically connected to each of the pixels arranged in the first direction. When the maximum length of the capacitive elements along the first direction is as large as in the eighth embodiment, the parasitic capacitance between the signal lines and the capacitive elements can become large. Large parasitic capacitance means that the effect of suppressing parasitic capacitance is easily achieved based on the planar layout of the signal lines and capacitive elements according to the first embodiment. In other words, this means that this planar layout is likely to contribute to faster imaging.

[0029] In the ninth aspect of this disclosure, for example, in an imaging device according to any one of the first to eighth aspects, When the direction perpendicular to the thickness direction of the semiconductor substrate and the first direction is defined as the second direction, In a plan view, the maximum length of the first capacitive element of the first pixel in the first direction may be greater than the maximum length of the first capacitive element of the first pixel in the second direction.

[0030] The signal lines are electrically connected to each of the pixels arranged in the first direction. In the configuration of the tenth embodiment, the maximum length of the capacitive elements in the direction along the first direction tends to be large. As a result, the parasitic capacitance between the signal lines and the capacitive elements may be large. Large parasitic capacitance means that the effect of suppressing parasitic capacitance is easily achieved based on the planar layout of the signal lines and capacitive elements according to the first embodiment. In other words, this means that this planar layout is likely to contribute to faster imaging.

[0031] In the tenth aspect of this disclosure, for example, in an imaging device according to any one of the first to ninth aspects, The capacitive element of the first pixel may include a first electrode, a second electrode, and an insulating layer between the first electrode and the second electrode.

[0032] The capacitive element of the tenth embodiment is an example of the configuration of a capacitive element.

[0033] In the eleventh aspect of this disclosure, for example, in the imaging device according to the tenth aspect, The first electrode and the second electrode may contain metal.

[0034] The capacitive element of the 11th embodiment is an example of the configuration of a capacitive element.

[0035] In a twelfth aspect of this disclosure, for example, in an imaging device according to any one of the first to eleventh aspects, The capacitive element of the first pixel may have the largest area in a plan view among the capacitive elements included in the first pixel.

[0036] Parasitic capacitance between large-area capacitive elements and signal lines, as defined in the 12th embodiment, can be large. Large parasitic capacitance means that the effect of suppressing parasitic capacitance is easily achieved based on the planar layout of signal lines and capacitive elements according to the first embodiment. In other words, this means that this planar layout is likely to contribute to faster imaging.

[0037] The imaging device relating to the 13th aspect of this disclosure is Semiconductor substrate and A plurality of pixels arranged in a first direction on the semiconductor substrate, A first signal line located above the semiconductor substrate, Equipped with, Each of the aforementioned plurality of pixels is A photoelectric conversion unit that converts light into signal charge, A transistor having a gate electrically connected to the first signal line, Capacitive elements, Includes, In the first pixel among the plurality of pixels, At least a portion of the transistor overlaps with the capacitive element in a plan view, In a plan view, the first signal line does not overlap with the capacitive element for a distance longer than half the maximum length of the capacitive element in the first direction.

[0038] The technology relating to the 13th embodiment is suitable for providing an imaging device capable of high-speed imaging.

[0039] The imaging device relating to the 14th aspect of this disclosure is Vertical scanning circuit and Semiconductor substrate and A pixel provided on the semiconductor substrate, At least one signal line positioned above the semiconductor substrate, Equipped with, The aforementioned pixel is A photoelectric conversion unit that converts light into signal charge, A charge storage region for accumulating the aforementioned signal charge, An amplifying transistor that generates an electrical signal corresponding to the voltage in the charge storage region, A reset transistor for resetting the voltage in the charge storage region, MIM capacitance element, Includes, The at least one signal line includes a reset signal line that electrically connects the vertical scanning circuit and the gate of the reset transistor. In a plan view, the reset signal line is spaced apart from the MIM capacitive element.

[0040] The technology relating to the 14th embodiment is suitable for providing an imaging device capable of high-speed imaging. Note that "the signal lines are spaced apart from the MIM capacitive elements in a plan view" means that the signal lines do not overlap with the MIM capacitive elements in a plan view. "At least one signal line" in the 17th embodiment may be multiple signal lines.

[0041] In the 15th aspect of this disclosure, for example, in the imaging device according to the 14th aspect, The pixel may include a feedback transistor provided on a feedback path that negatively feeds back the electrical signal generated by the amplification transistor to the charge storage region. The at least one signal line may include a feedback control line that electrically connects the vertical scanning circuit and the gate of the feedback transistor. In a plan view, the feedback control line may be spaced apart from the MIM capacitive element.

[0042] The technology relating to the 15th embodiment is suitable for providing an imaging device capable of high-speed imaging.

[0043] In the sixteenth aspect of this disclosure, for example, in the imaging device according to the fourteenth or fifteenth aspect, The pixel may include an address transistor that determines the timing for outputting the electrical signal from the amplification transistor. The at least one signal line may include an address signal line that electrically connects the vertical scanning circuit and the gate of the address transistor. In a plan view, the address signal line may be spaced apart from the MIM capacitive element.

[0044] The technology relating to the 16th embodiment is suitable for providing an imaging device capable of high-speed imaging.

[0045] In a 17th aspect of this disclosure, for example, in an imaging device according to any one of the 14th to 16th aspects, The pixel may include a transfer transistor provided between the photoelectric conversion unit and the charge storage region. The at least one signal line may include a transfer control line that electrically connects the vertical scanning circuit and the gate of each of the transfer transistors of the plurality of pixels. In a plan view, the transfer control line may be spaced apart from the MIM capacitive element.

[0046] The technology relating to the 17th embodiment is suitable for providing an imaging device capable of high-speed imaging.

[0047] Unless otherwise inconsistent, the technologies relating to the first to seventeenth embodiments can be combined in any way.

[0048] In the embodiments, terms such as "upper," "lower," "top surface," and "bottom surface" are used solely to specify the relative positions of the components and are not intended to limit the orientation of the imaging device when in use.

[0049] In this embodiment, "plan view" refers to the view from the thickness direction of the semiconductor substrate.

[0050] In the embodiments, the term "via" may be used. In the embodiments, the via hole and the conductor inside it are collectively referred to as a "via".

[0051] In the embodiments, the term "transistor control signal" may be used. In the embodiments, a transistor control signal is a signal transmitted to a transistor for controlling the transistor. In a typical example, the transistor control signal is transmitted to the gate, drain, or source of the transistor.

[0052] In the embodiment, the expression "element A is connected to element B" may be used. This expression includes cases where part or all of element A is included in B.

[0053] In this embodiment, the transistor polarity and the conductivity type of the impurity region are examples only. The transistor polarity and the conductivity type of the impurity region may be reversed, as long as there is no contradiction. Adjustments to each element accompanying the reversal of the transistor polarity and the conductivity type of the impurity region can be made as appropriate.

[0054] In the embodiments, "connection" and "electrically connected" are interchangeable unless otherwise specified. In the embodiments, "gate" and "gate electrode" are interchangeable unless otherwise specified.

[0055] In the embodiments, the configuration of the pixels may be described. Unless otherwise inconsistent, the described configuration may appear in each pixel. Furthermore, the relationship between the pixel elements and signal lines may be described. Unless otherwise inconsistent, the described relationship may appear in each pixel.

[0056] The embodiments will be described in detail below with reference to the drawings.

[0057] (Embodiment 1) Figure 1 is a schematic diagram showing an exemplary circuit configuration of an imaging device according to Embodiment 1. The imaging device 100 shown in the figure includes a plurality of pixels 99 and peripheral circuits. The plurality of pixels 99 constitute a pixel region. The plurality of pixels 99 are constructed using a semiconductor substrate. The semiconductor substrate is not limited to a substrate in which the entire surface is semiconductor. The semiconductor substrate may have a semiconductor layer and an insulating layer, and the surface of the semiconductor substrate on the side in which the pixel region is formed may be composed of a semiconductor layer. In Figure 1 and other figures, each individual pixel included in the plurality of pixels 99 is denoted as pixel 10.

[0058] In the illustrated example, the multiple pixels 99 are arranged in both row and column directions. The vertical direction is the column direction, and the horizontal direction is the row direction. In the illustrated example, the multiple pixels 99 are arranged in two dimensions. However, the multiple pixels 99 may also be arranged in one dimension. In other words, the imaging device 100 can be a line sensor. The imaging device 100 may have only one pixel 10.

[0059] Pixel 10 is connected to power supply wiring 22. A voltage of 1 or more is supplied to pixel 10 via power supply wiring 22. This "voltage of 1 or more" may be "voltage of 2 or more" or "two different voltages". Pixel 10 includes a photoelectric conversion unit. The photoelectric conversion unit has a photoelectric conversion film. The photoelectric conversion film is laminated on a semiconductor substrate. The photoelectric conversion unit is provided on the semiconductor substrate via a wiring layer. As shown in the figure, the imaging device 100 also has a storage control line 17 for applying the same constant voltage to all photoelectric conversion units.

[0060] The peripheral circuitry includes a vertical scanning circuit 16, a load circuit 19, a column signal processing circuit 20, and a horizontal signal readout circuit 21. In the illustrated configuration, the column signal processing circuit 20 and the load circuit 19 are arranged for each column of multiple pixels 99 arranged in two dimensions. In other words, in this example, the peripheral circuitry includes multiple column signal processing circuits 20 and multiple load circuits 19.

[0061] The vertical scanning circuit 16 is also called a row scanning circuit. The vertical scanning circuit 16 is connected to the address signal line 30 and the reset signal line 26. The vertical scanning circuit 16 can apply a predetermined voltage to the address signal line 30 or the reset signal line 26. Multiple pixels 99 constitute multiple rows. A row is selected by applying the predetermined voltage, and the signal voltage of the pixel 10 belonging to the selected row is read out, or the pixel is reset. In the illustrated example, the vertical scanning circuit 16 is also connected to the feedback control line 28 and the sensitivity adjustment line 32.

[0062] The vertical scanning circuit 16 can supply a predetermined voltage to multiple pixels 99 via the sensitivity adjustment line 32. In this embodiment, each pixel 10 has one or more capacitive elements within the pixel.

[0063] Multiple pixels 99 constitute multiple columns. Pixels 10 belonging to each column are electrically connected to a column signal processing circuit 20 via a vertical signal line 18 corresponding to each column. A load circuit 19 is electrically connected to the vertical signal line 18. The column signal processing circuit 20 is also called a row signal storage circuit. The column signal processing circuit 20 performs noise suppression signal processing and analog-to-digital conversion (AD conversion), etc. Noise suppression signal processing is, for example, correlated double sampling. A horizontal signal readout circuit 21 is electrically connected to the multiple column signal processing circuits 20, which are provided corresponding to the columns. The horizontal signal readout circuit 21 is also called a column scanning circuit. The horizontal signal readout circuit 21 sequentially reads signals from the multiple column signal processing circuits 20 to a horizontal common signal line 23.

[0064] Figure 2 shows an exemplary circuit configuration of a pixel 10 according to Embodiment 1. The pixel 10 includes a photoelectric conversion unit 15. The photoelectric conversion unit 15 converts incident light into photoelectric energy. In the illustrated example, the photoelectric conversion unit 15 has a counter electrode 15a, a photoelectric conversion film 15b, and a pixel electrode 15c. The photoelectric conversion film 15b is positioned between the counter electrode 15a and the pixel electrode 15c. The photoelectric conversion film 15b is laminated on a semiconductor substrate. The photoelectric conversion film 15b is made of an organic or inorganic material. An inorganic material is, for example, amorphous silicon. A voltage of 1 or more is supplied to the pixel 10 via a power supply wiring 22. As described above, this "voltage of 1 or more" may be "voltage of 2 or more" or "two different voltages".

[0065] A counter electrode 15a is provided on the light-receiving side of the photoelectric conversion film 15b. The counter electrode 15a is made of a transparent conductive material. An example of a transparent conductive material is ITO (Indium Tin Oxide). A pixel electrode 15c is provided on the opposite side of the counter electrode 15a via the photoelectric conversion film 15b. The pixel electrode 15c collects the charge generated by photoelectric conversion in the photoelectric conversion film 15b. The pixel electrode 15c is made of a metal such as aluminum or copper, or polysilicon that has been doped with impurities to provide conductivity.

[0066] As shown in the figure, the counter electrode 15a is connected to the storage control line 17. The pixel electrode 15c is connected to the charge storage region 44. By controlling the potential of the counter electrode 15a via the storage control line 17, either the hole or the electron from the hole-electron pair generated by photoelectric conversion can be collected by the pixel electrode 15c. When using holes as the signal charge, the potential of the counter electrode 15a should be higher than that of the pixel electrode 15c. The following example illustrates the case where holes are used as the signal charge. For example, a voltage of about 10V is applied to the counter electrode 15a via the storage control line 17. As a result, the signal charge is stored in the charge storage region 44. Of course, electrons can also be used as the signal charge. The charge storage region 44 is also called a floating diffusion node.

[0067] Pixel 10 includes an amplification transistor 34, a reset transistor 36, a capacitance section 41, and a capacitance element 42. In the illustrated configuration, the capacitance element 42 has a larger capacitance value than the capacitance section 41. In the configuration illustrated in Figure 2, one of the source and drain of the reset transistor 36 and one electrode of the capacitance section 41 are connected to a charge storage region 44. These are electrically connected to the pixel electrode 15c. The other of the source and drain of the reset transistor 36 and the other electrode of the capacitance section 41 are connected to one electrode of the capacitance element 42. The capacitance section 41 is connected between the source and drain of the reset transistor 36. Hereinafter, the node including the connection point between the capacitance section 41 and the capacitance element 42 may be referred to as the reset-drain node 46.

[0068] Of the electrodes of the capacitive element 42, the electrode not connected to the reset drain node 46 is connected to the sensitivity adjustment line 32. The potential of the sensitivity adjustment line 32 is set to, for example, 0V. The potential of the sensitivity adjustment line 32 does not need to be fixed during the operation of the imaging device 100. For example, a pulse voltage may be supplied from the vertical scanning circuit 16 shown in Figure 1.

[0069] As shown in the figure, the gate of the amplification transistor 34 is connected to the charge storage region 44. The gate of the amplification transistor 34 is electrically connected to the pixel electrode 15c. One of the source and drain of the amplification transistor 34 is connected to the power supply wiring 22. If the amplification transistor 34 is an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), one of the above-mentioned source and drain of the amplification transistor 34 is the drain. The power supply wiring 22 functions as a source follower power supply. The other of the source and drain of the amplification transistor 34 is connected to the vertical signal line 18 via the address transistor 40, which will be described later. The vertical signal line 18 is a signal line that transmits the electrical signal output from the amplification transistor 34. The amplification transistor 34 and the load circuit 19 shown in Figure 1 constitute a source follower circuit. The amplification transistor 34 amplifies the signal generated by the photoelectric conversion unit 15.

[0070] As shown in the figure, pixel 10 includes an address transistor 40. The address transistor 40 is also called a row selection transistor. As described above, one of the sources and drains of the amplification transistor 34 is connected to the power supply wiring 22. The other of the sources and drains of the amplification transistor 34 is connected to the source or drain of the address transistor 40. The gate of the address transistor 40 is connected to the address signal line 30.

[0071] As shown in the figure, pixel 10 includes a feedback transistor 38. As described above, the source and the other drain of the amplification transistor 34 are connected to the address transistor 40. The other source and drain of the amplification transistor 34 are connected to one of the source and drain of the feedback transistor 38. During noise cancellation operation, a feedback path is formed from the charge storage region 44 to the charge storage region 44, via the amplification transistor 34, the feedback transistor 38, and the capacitance unit 41 or reset transistor 36 in that order. The output of the amplification transistor 34 is negatively fed back to the charge storage region 44 via this feedback path.

[0072] A voltage corresponding to the amount of signal charge stored in the charge storage region 44 is applied to the gate of the amplification transistor 34. The amplification transistor 34 amplifies this voltage. During readout operation, the voltage amplified by the amplification transistor 34 is selectively read out as an electrical signal by the address transistor 40.

[0073] In this embodiment, the charge storage region 44 includes an impurity region provided on the semiconductor substrate 2. Specifically, this impurity region is the source or drain of the reset transistor 36. In the examples shown in Figures 3 and 4 described later, this impurity region is the third diffusion layer 36s.

[0074] In this embodiment, the photoelectric conversion unit 15 converts light into signal charge. The signal charge is stored in the charge storage region 44. The amplification transistor 34 generates an electrical signal corresponding to the voltage in the charge storage region 44. The address transistor 40 determines the timing for outputting the electrical signal from the amplification transistor 34. The reset transistor 36 resets the voltage in the charge storage region 44. Furthermore, a feedback transistor 38 is provided on the feedback path that negatively feeds back the electrical signal generated by the amplification transistor 34 to the charge storage region 44.

[0075] In each row, the reset signal line 26 connects the vertical scanning circuit 16 to the gate of the reset transistor 36. The address signal line 30 connects the vertical scanning circuit 16 to the gate of the address transistor 40. The feedback control line 28 connects the vertical scanning circuit 16 to the gate of the feedback transistor 38.

[0076] Each of the amplification transistors 34, reset transistor 36, feedback transistor 38, and address transistor 40 may be an N-channel MOSFET or a P-channel MOSFET. It is not necessary for all of them to be either N-channel or P-channel MOSFETs. The following examples illustrate the case where the amplification transistor 34, reset transistor 36, feedback transistor 38, and address transistor 40 are N-channel or P-channel MOSFETs.

[0077] (Plan view of pixels and device structure) Next, the device structure of pixel 10 will be described with reference to Figures 3 and 4.

[0078] Figure 3 is a schematic plan view showing an example of the layout of some elements in a pixel according to Embodiment 1. Figure 4 is a schematic cross-sectional view showing a cross-section along the line A-A' shown in Figure 3.

[0079] Pixel 10 is constructed using a semiconductor substrate 2. Here, we will describe an example in which a p-type silicon (Si) substrate is used as the semiconductor substrate 2.

[0080] In this embodiment, four transistors, namely an amplification transistor 34, a reset transistor 36, a feedback transistor 38, and an address transistor 40, are arranged within the pixel 10. The amplification transistor 34, reset transistor 36, feedback transistor 38, and address transistor 40 are provided on the semiconductor substrate 2. Each element of the pixel 10 is isolated by an element isolation region 2s provided on the semiconductor substrate 2. In this example, the set of reset transistor 36 and feedback transistor 38, and the amplification transistor 34 and address transistor 40 are isolated by the element isolation region 2s.

[0081] A reset drain node 46 is provided between the reset transistor 36 and the feedback transistor 38. The reset drain node 46 includes a fourth diffusion layer 36d provided in the semiconductor substrate 2. In the illustrated example, the fourth diffusion layer 36d is one of the source and drain of the feedback transistor 38. The fourth diffusion layer 36d is one of the source and drain of the reset transistor 36. In other words, the fourth diffusion layer 36d is shared by the feedback transistor 38 and the reset transistor 36.

[0082] Pixel 10 has a photoelectric conversion unit 15. The photoelectric conversion unit 15 is provided above the semiconductor substrate 2. An interlayer insulating layer 4 is provided on the semiconductor substrate 2. In the interlayer insulating layer 4, a first insulating layer 4a, a second insulating layer 4b, a third insulating layer 4c, a fourth insulating layer 4d, and a fifth insulating layer 4e are stacked in this order. The first insulating layer 4a to the fifth insulating layer 4e are made of, for example, silicon dioxide (SiO2). A plurality of wiring layers WLs are arranged between the semiconductor substrate 2 and the photoelectric conversion unit 15. Specifically, the plurality of wiring layers WLs include a first wiring layer 61, a second wiring layer 62, and a third wiring layer 63. The second wiring layer 62 is located closer to the photoelectric conversion unit 15 than the first wiring layer 61. The third wiring layer 63 is located closer to the photoelectric conversion unit 15 than the second wiring layer 62. The first wiring layer 61 is provided within the second insulating layer 4b. The second wiring layer 62 is located within the third insulating layer 4c. The third wiring layer 63 is located within the fourth insulating layer 4d. The capacitive element 42 is included in the first wiring layer 61. The reset signal line 26, the feedback control line 28, and the address signal line 30 are included in the second wiring layer 62. The number of wiring layers and insulating layers can be set arbitrarily and is not limited to the example shown.

[0083] A photoelectric conversion film 15b is laminated on the fifth insulating layer 4e. The photoelectric conversion film 15b has a light-receiving surface 15h. Light from an object is incident on the light-receiving surface 15h. A counter electrode 15a is placed on the light-receiving surface 15h. A pixel electrode 15c is placed on the surface of the photoelectric conversion film 15b opposite to the light-receiving surface 15h. The pixel electrode 15c is electrically isolated between multiple pixels 99.

[0084] In the configuration illustrated in Figure 4, the semiconductor substrate 2 comprises a support substrate 2a, a well 2w, and an impurity layer 2gw. The well 2w has a relatively high acceptor concentration. Here, the well 2w is a P-type region. The impurity layer 2gw is a region with the opposite conductivity to the well 2w. Here, the impurity layer 2gw is an N-type region. The support substrate 2a and the well 2w are electrically connected by a connection region (not shown) provided in the impurity layer 2gw. The connection region is an impurity region with the same conductivity as the well 2w.

[0085] The first diffusion layer 34s, the second diffusion layer 34d, the third diffusion layer 36s, the fourth diffusion layer 36d, the fifth diffusion layer 38d, the sixth diffusion layer 40s, and the seventh diffusion layer 40d are regions with the opposite conductivity to well 2w. Here, the first diffusion layer 34s, the second diffusion layer 34d, the third diffusion layer 36s, the fourth diffusion layer 36d, the fifth diffusion layer 38d, the sixth diffusion layer 40s, and the seventh diffusion layer 40d are N-type regions.

[0086] An insulating film 39 is provided on the semiconductor substrate 2. The insulating film 39 is, for example, a silicon dioxide film. Gates 34e, 36e, 38e, and 40e are provided on the insulating film 39. Gates 34e, 36e, 38e, and 40e are electrodes made of, for example, polysilicon.

[0087] As shown in Figure 3, the amplification transistor 34 includes a first diffusion layer 34s, a second diffusion layer 34d, and a gate 34e. The amplification transistor 34 also includes a portion of the insulating film 39. One of the first diffusion layer 34s and the second diffusion layer 34d constitutes the source of the amplification transistor 34, and the other constitutes the drain of the amplification transistor 34. The aforementioned portion of the insulating film 39 constitutes the gate insulating film of the amplification transistor 34. The gate 34e is provided on this gate insulating film.

[0088] The reset transistor 36 includes a third diffusion layer 36s, a fourth diffusion layer 36d, and a gate 36e. The reset transistor 36 also includes a portion of the insulating film 39. One of the third diffusion layer 36s and the fourth diffusion layer 36d constitutes the source of the reset transistor 36, and the other constitutes the drain of the reset transistor 36. The portion of the insulating film 39 described above constitutes the gate insulating film of the reset transistor 36. The gate 36e is provided on this gate insulating film.

[0089] The feedback transistor 38 includes a fourth diffusion layer 36d, a fifth diffusion layer 38d, and a gate 38e. The feedback transistor 38 also includes a portion of the insulating film 39. One of the fourth diffusion layer 36d and the fifth diffusion layer 38d constitutes the source of the feedback transistor 38, and the other constitutes the drain of the feedback transistor 38. The aforementioned portion of the insulating film 39 constitutes the gate insulating film of the feedback transistor 38. The gate 38e is provided on this gate insulating film.

[0090] The address transistor 40 includes a sixth diffusion layer 40s, a seventh diffusion layer 40d, and a gate 40e. The address transistor 40 also includes a portion of the insulating film 39. One of the sixth diffusion layer 40sd and the seventh diffusion layer 40d constitutes the source of the address transistor 40, and the other constitutes the drain of the address transistor 40. The aforementioned portion of the insulating film 39 constitutes the gate insulating film of the address transistor 40. The gate 40e is provided on this gate insulating film.

[0091] As shown in Figure 4, the capacitive element 42 includes a first electrode 42d, a second electrode 42e, and an insulating layer 42g. The insulating layer 42g is positioned between the first electrode 42d and the second electrode 42e. In the illustrated example, the first electrode 42d is located relatively below, and the second electrode 42e is located relatively above. The insulating layer 42g has a film shape.

[0092] In this embodiment, the first electrode 42d and the second electrode 42e contain a metal. However, the first electrode 42d and the second electrode 42e may also contain a metal compound, polysilicon, etc. The metal compound is, for example, a metal oxide. The insulating layer 42g contains, for example, a high dielectric material such as HfO2, a nitride, etc.

[0093] In this embodiment, the capacitive element 42 is a MIM (Metal Insulator Metal) capacitive element. An MIM capacitive element is a capacitive element having an MIM structure. The "M" in MIM refers to at least one of a metal and a metal compound. The "I" in MIM is an insulator, such as an oxide. In other words, the MIM capacitive element is a concept that encompasses the MOM (Metal Oxide Metal) capacitive element. An MOM capacitive element is a capacitive element having an MOM structure. With an MIM capacitive element, a capacitive element 42 with high capacitance density can be realized. In particular, using an insulator with a high dielectric constant as the insulator makes it easier to realize a capacitive element 42 with high capacitance density.

[0094] The capacitance section 41 may have characteristics similar to those described for the capacitance element 42. The capacitance section 41 may also be a capacitance element. The capacitance section 41 may also be a parasitic capacitance between wires. The configuration of the capacitance section 41 and the configuration of the capacitance element 42 may be the same or different.

[0095] In this embodiment, the capacitive element 42 is the one with the largest area in a plan view among the capacitive elements included in the pixel 10. In this embodiment, the concept of a capacitive element does not include parasitic capacitance. Parasitic capacitance includes, for example, parasitic capacitance in the diffusion region and parasitic capacitance between wirings.

[0096] Let me explain the above statement, "Capacitive element 42 has the largest area in a planar view among the capacitive elements included in the pixel 10." This statement is intended to encompass the configuration in which the pixel 10 contains only capacitive element 42. Furthermore, this statement is intended to encompass the configuration in which the pixel 10 contains multiple capacitive elements, and among these multiple capacitive elements, capacitive element 42 has the largest area in a planar view.

[0097] The first electrode 42d is electrically connected to the fourth diffusion layer 36d. The second electrode 42e is electrically connected to the sensitivity adjustment line 32 shown in Figure 2. A predetermined voltage is applied to the second electrode 42e from a voltage source via the sensitivity adjustment line 32. Here, the voltage source is the vertical scanning circuit 16. By controlling the potential of the second electrode 42e, the potential of the charge storage region 44 can be controlled. In other words, by adjusting the voltage supplied to the second electrode 42e via the sensitivity adjustment line 32, the sensitivity of the imaging device 100 can be adjusted. Furthermore, by supplying a constant voltage to the second electrode 42e, the potential of the second electrode 42e can be maintained at a constant potential. This makes it possible to make the second electrode 42e of the capacitive element 42, which has a relatively large capacitance value, function as a shield electrode.

[0098] As described above, multiple pixels 99 constitute rows and columns. In the circuit configuration illustrated in Figure 2, rows are selected to perform the noise cancellation operation. In other words, noise cancellation is typically performed by sequentially selecting pixels 10 along the column direction.

[0099] The photoelectric conversion unit 15 may be a photodiode. The photodiode may be an embedded photodiode provided in the semiconductor substrate 2. Alternatively, a transfer transistor may be provided between the photoelectric conversion unit 15 and the charge storage region 44. Figure 5 shows an exemplary circuit configuration of a pixel using a photodiode. In the example in Figure 5, a photodiode 11 is used as the photoelectric conversion unit 15. The charge storage region 44 is connected to the photoelectric conversion unit 15 via the transfer transistor 37. That is, the charge storage region 44 is connected to the photoelectric conversion unit 15. In Figure 5, the transfer control line 27 is a control line that transmits a control signal to the transfer transistor 37 for controlling the transfer transistor 37.

[0100] Hereinafter, the terms "multiple pixels PXs," "first direction D1," and "second direction D2" may be used. Multiple pixels PXs are arranged in the first direction D1. Multiple pixels PXs are contained within multiple pixels 99. The second direction D2 is a direction perpendicular to the thickness direction of the semiconductor substrate 2 and the first direction D1. The first direction D1 can be either the row direction or the column direction. The second direction D2 can be the other of the row direction or the column direction.

[0101] Figure 6 is a schematic diagram illustrating a plurality of pixels PXs according to Embodiment 1. As shown in Figure 6, in Embodiment 1, the first direction D1 is the row direction. The second direction D2 is the column direction. The plurality of pixels PXs constitute one row by being arranged along the row direction.

[0102] Figure 7 is a schematic diagram illustrating multiple pixels PXs in the modified example. As shown in Figure 7, in the modified example, the first direction D1 is the column direction, and the second direction D2 is the row direction. Multiple pixels PXs form a single column by being arranged along the column direction.

[0103] In this embodiment, the imaging device 100 includes a semiconductor substrate 2, a plurality of pixels PXs, and a plurality of signal lines SLs. The plurality of pixels PXs are arranged in a first direction D1 on the semiconductor substrate 2. The plurality of signal lines SLs are located above the semiconductor substrate 2. Each of the plurality of pixels PXs includes a photoelectric conversion unit 15, an amplifying transistor 34, a plurality of transistors TRs, and a capacitive element 42. The photoelectric conversion unit 15 converts light into signal charge. The signal charge from the photoelectric conversion unit 15 is input to the gate 34e of the amplifying transistor 34. Each of the plurality of transistors TRs is electrically connected to the corresponding signal line among the plurality of signal lines SLs.

[0104] As can be seen from Figures 1, 6, and 7, there may be multiple combinations of pixels PXs and signal lines SLs in the imaging device 100. Specifically, however, the number of such combinations present in the imaging device 100 may be just one.

[0105] Let's explain the above expression, "Each of the multiple pixels PXs includes a photoelectric conversion unit 15, an amplifying transistor 34, multiple transistors TRs, and a capacitive element 42." This expression is not intended to require that all pixels arranged in the first direction D1 include these elements. A configuration may also be adopted in which the pixels arranged in the first direction D1 include pixels other than the multiple pixels PXs, and these other pixels do not include a photoelectric conversion unit, an amplifying transistor, multiple transistors, and a capacitive element.

[0106] The gate 34e of the amplification transistor 34 is connected to the photoelectric conversion unit 15. The expression "The gate 34e of the amplification transistor 34 is connected to the photoelectric conversion unit 15" will be explained. This expression is intended to include configurations in which the gate 34e and the photoelectric conversion unit 15 are electrically connected without the need for other transistors. Furthermore, this expression is intended to include configurations in which other transistors are interposed between the gate 34e and the photoelectric conversion unit 15, and the gate 34e and the photoelectric conversion unit 15 are electrically connected when the other transistor is in the ON state. For example, this expression includes configurations in which a transfer transistor 37 is interposed between the gate 34e and the photoelectric conversion unit 15.

[0107] A control signal is transmitted to each of the multiple transistors TRs from the corresponding signal line among the multiple signal lines SLs. Each of the multiple transistors TRs is controlled by the control signal transmitted to it. The term "control signal" in "A control signal is transmitted to each of the multiple transistors TRs from the corresponding signal line among the multiple signal lines SLs" will be explained below. As mentioned above, the transistor to which the control signal is transmitted is controlled by the control signal. In this context, "a transistor is controlled" typically means that the gate-source voltage of the transistor is controlled. By controlling the gate-source voltage, it is possible to control the on / off state of the transistor or the operating range of the transistor.

[0108] In this embodiment, the plurality of transistors TRs include a reset transistor 36. The plurality of transistors TRs include a feedback transistor 38. The plurality of transistors TRs include an address transistor 40. The plurality of transistors TRs may also include a transfer transistor 37. On the other hand, the plurality of transistors TRs do not include an amplification transistor 34.

[0109] In this embodiment, the multiple signal lines SLs extend along the first direction D1.

[0110] In this embodiment, the plurality of signal lines SLs include a reset signal line 26. The plurality of signal lines SLs include a feedback control line 28. The plurality of signal lines SLs include an address signal line 30. In a configuration in which a transfer transistor 37 is provided, the plurality of signal lines SLs may include a transfer control line 27.

[0111] In this embodiment, the multiple signal lines SLs are M signal lines, where M is a natural number greater than or equal to 1. M may also be a natural number greater than or equal to 2, 3, 4, 5, 6, 7, or 8. M may also be the total number of signal lines that transmit transistor control signals to the multiple pixels PXs. In other words, the multiple signal lines SLs may be all the signal lines that constitute the signal lines that transmit transistor control signals.

[0112] Multiple signal lines SLs may include all signal lines that extend along a first direction D1 and are electrically connected to multiple pixels PXs. In other words, multiple signal lines SLs may include all signal lines that satisfy both the first and second requirements. The first requirement is that they extend along a first direction D1. The second requirement is that they are electrically connected to multiple pixels PXs.

[0113] In this embodiment, the imaging device 100 includes a vertical scanning circuit 16. The vertical scanning circuit 16 supplies control signals to a plurality of signal lines SLs.

[0114] The following describes the direction in which the signal lines extend. Figures 8 to 10 are plan views illustrating the direction in which signal line X extends. In the following explanation, the horizontal direction Dh and the vertical direction Dv are mutually orthogonal directions.

[0115] In the example in Figure 8, the signal line X extends entirely along the lateral direction Dh. In the example in Figure 8, the direction in which the signal line X extends is the lateral direction Dh. That is, the signal line X extends along the lateral direction Dh.

[0116] In the example in Figure 9, signal line X extends entirely along the horizontal direction Dh. On the other hand, branch signal line Y is connected to signal line X. Branch signal line Y extends entirely along the vertical direction Dv. In the example in Figure 9, the direction in which signal line X extends is based on the direction in which signal line X extends, and not on the direction in which branch signal line Y extends. In other words, the direction in which signal line X extends is the horizontal direction Dh. That is, signal line X extends along the horizontal direction Dh.

[0117] In the example in Figure 10, the signal line X has a portion of length Lh extending in the lateral direction Dh and a portion of length Lv extending in the vertical direction Dv. In the example in Figure 10, length Lh is longer than length Lv. In the example in Figure 10, the direction in which the signal line X extends is the direction of the longer of length Lh and length Lv. Since Lh > Lv, the direction in which the signal line X extends is the lateral direction Dh. In other words, the signal line X extends along the lateral direction Dh.

[0118] Figure 11 is a plan view illustrating the dimensions of the capacitive element 42. In this embodiment, in a plan view, the maximum length ML1 of the capacitive element 42 along the first direction D1 is greater than one-third of the length PL of the pixel 10 along the first direction D1. The maximum length ML1 of the capacitive element 42 along the first direction D1 may also be greater than half the length PL of the pixel 10 along the first direction D1. The boundary of the pixel 10 may be a virtual median line defined from the region in which the components of each pixel 10 are arranged. For example, the boundary of the pixel 10 may be the median line between the pixel electrodes 15c of adjacent pixels 10.

[0119] In this embodiment, in a plan view, the maximum length ML1 of the capacitive element 42 in the first direction D1 is greater than the maximum length ML2 of the capacitive element 42 in the second direction D2.

[0120] The maximum lengths ML1 and ML2 will be explained with reference to Figures 12 and 13. Figures 12 and 13 are plan views illustrating the maximum lengths ML1 and ML2 of the capacitive element 42.

[0121] In the example shown in Figure 12, the capacitive element 42 is rectangular in plan view. Here, the concept of a rectangle includes a square. In the example shown in Figure 12, the length of one of the two sides of this rectangle is the maximum length ML1, and the length of the other side is the maximum length ML2.

[0122] In the example shown in Figure 13, the capacitive element 42 has a shape obtained by removing a portion of a rectangle in a plan view. The smallest rectangle that accommodates this shape and has sides extending along a first direction D1 and sides extending along a second direction D2 is defined as rectangle LEC. Here, the concept of a rectangle includes a square. In the example shown in Figure 13, the length of one of the two sides of rectangle LEC is the maximum length ML1, and the length of the other side is the maximum length ML2. The maximum lengths ML1 and ML2 can be defined in this way even if the capacitive element 42 has a different shape in a plan view.

[0123] Figure 14 is a schematic plan view showing an example of the layout of some wirings and some elements in pixels according to Embodiment 1. In Figure 14, parts (a), (b), and (c) are arranged from left to right. Part (a) shows the arrangement of each transistor on the surface 60 of the semiconductor substrate 2. Part (b) shows the arrangement of the capacitive elements 42 and wiring in the first wiring layer 61. Part (c) shows the arrangement of wiring in the second wiring layer 62. These points are also the same for Figures 19 to 24, which will be described later.

[0124] As can be seen from Figure 14, in this embodiment, none of the multiple signal lines SLs overlap with the capacitive element 42 in terms of overall line width in a plan view. This configuration reduces parasitic capacitance between the multiple signal lines SLs and the capacitive element 42, and suppresses the delay of signals flowing through the multiple signal lines SLs. For this reason, this configuration is suitable for providing an imaging device 100 capable of high-speed imaging.

[0125] Here, we will explain the expression, "None of the multiple signal lines SLs overlap with the capacitive element 42 in terms of overall line width in a plan view." This expression is intended to encompass configurations in which there is no overlap between the multiple signal lines SLs and the capacitive element 42 in a plan view. This expression is intended to encompass configurations in which there is overlap between the multiple signal lines SLs and the capacitive element 42 in a plan view, but the overlap width of the signal line with the capacitive element 42 is less than the line width of the signal line.

[0126] The advantages of the above configuration will be further explained with reference to Figures 15 to 17. Note that Figures 15 to 17 only show one of the multiple signal lines SLs, specifically signal line SLx. Signal line SLx may correspond to the reset signal line 26. Signal line SLx may correspond to the feedback control line 28. Signal line SLx may correspond to the address signal line 30. Signal line SLx may correspond to the transfer control line 27.

[0127] Figure 15 is a schematic cross-sectional view showing a cross-section of an imaging device according to the first reference example. Specifically, this cross-section is parallel to the thickness direction of the semiconductor substrate 2. In the first reference example, in a plan view, the signal line SLx overlaps with the capacitive element 42 across its entire line width. In this case, it is difficult to reduce the parasitic capacitance between the signal line SLx and the capacitive element 42, and it is difficult to suppress the delay of the signal flowing through the signal line SLx. For this reason, this configuration is disadvantageous from the viewpoint of providing an imaging device capable of high-speed imaging.

[0128] Figure 16 is a schematic cross-sectional view showing a cross-section of the imaging device according to the second reference example. Specifically, this cross-section is parallel to the thickness direction of the semiconductor substrate 2. In the second reference example, in a plan view, the signal line SLx overlaps with the capacitive element 42 across its entire line width. However, in the second reference example, the distance between the signal line SLx and the capacitive element 42 in the thickness direction of the semiconductor substrate 2 is larger than in the first reference example. This makes it possible to reduce the parasitic capacitance between the signal line SLx and the capacitive element 42. However, if the above distance is large, the electrical path FDL that electrically connects the pixel electrode 15c and the third diffusion layer 36s tends to become longer. Since the charge storage region 44 includes the third diffusion layer 36s and the electrical path FDL, a longer electrical path FDL increases the capacitance of the charge storage region 44. This means that the sensitivity of the imaging device 100 deteriorates. This also means that the fringe capacitance FC between the signal line SLx and the electrical path FDL tends to become larger. Furthermore, the electrical FDL (Functional Distribution Line) can be constructed using vias, wiring, etc.

[0129] Figure 17 is a schematic cross-sectional view showing a cross-section of the imaging device 100 according to Embodiment 1. Specifically, this cross-section is parallel to the thickness direction of the semiconductor substrate 2. In this embodiment, in a plan view, the signal line SLx does not overlap with the capacitive element 42 in terms of overall line width. This configuration reduces parasitic capacitance between the signal line SLx and the capacitive element 42, and suppresses the delay of the signal flowing through the signal line SLx. Therefore, this configuration is suitable for providing an imaging device capable of high-speed imaging. Furthermore, as can be understood from the comparison with the second reference example shown in Figure 16, this configuration reduces parasitic capacitance between the signal line SLx and the capacitive element 42 without increasing the length of the electrical path FDL. Therefore, this configuration is suitable for ensuring the sensitivity of the imaging device 100 and reducing fringe capacitance FC. This is especially true for the configuration in which "none of the multiple signal lines SLs overlap with the capacitive element 42 in terms of overall line width in a plan view."

[0130] As can be understood from the explanation using Figures 15 to 17, the electrical path FDL can be shortened appropriately by appropriately reducing the distance between the pixel electrode 15c and the semiconductor substrate 2. This avoids a situation where the capacitance of the charge storage region 44 becomes large, making it difficult to obtain sensitivity. The distance between the pixel electrode 15c and the semiconductor substrate 2 is, for example, 1 μm or more and 5 μm or less. Specifically, this distance may be 2 μm or more and 4 μm or less.

[0131] Specifically, as can be seen from Figure 14, in this embodiment, none of the multiple signal lines SLs overlap with the capacitive element 42 in a plan view by more than half the width of the line width. This configuration is suitable for providing an imaging device 100 capable of high-speed imaging.

[0132] More specifically, in this embodiment, none of the multiple signal lines SLs overlap with the capacitive element 42 in a plan view. In other words, none of the multiple signal lines SLs have any portion that overlaps with the capacitive element 42 in a plan view. Furthermore, none of the multiple signal lines SLs may be spaced apart from the capacitive element 42 in a plan view. This configuration is suitable for providing an imaging device 100 capable of high-speed imaging.

[0133] In this embodiment, voltages different from the voltage applied to the second electrode 42e of the capacitive element 42 are applied to multiple signal lines SLs. In situations where different voltages are applied in this way, parasitic capacitance is likely to adversely affect the signals flowing through the multiple signal lines SLs. However, as described above, in this embodiment, the parasitic capacitance between the multiple signal lines SLs and the capacitive element 42 can be reduced by the layout of the multiple signal lines SLs and the capacitive element 42. Therefore, the adverse effects can be suppressed.

[0134] The capacitive element 42 may have a trench structure. Figure 18 is a cross-sectional view showing a capacitive element 42 having a trench structure. The trench structure makes it easier to secure the capacitance value of the capacitive element 42. Here, a trench structure refers to a structure that includes a bent portion. Specifically, in a capacitive element 42 having a trench structure, its first electrode 42d, second electrode 42e, and insulating layer 42g include a bent portion.

[0135] When there are large capacitive elements 42 or the like, conductive foreign matter generated during the semiconductor manufacturing process is likely to form a leakage path between the capacitive elements 42 and the multiple signal lines SLs. However, as described above, in this embodiment, none of the multiple signal lines SLs overlap with the capacitive elements 42 in terms of overall line width when viewed from above. With this configuration, it is less likely that leakage will occur due to residual conductive foreign matter, leading to a decrease in yield.

[0136] In this embodiment, the imaging device 100 includes a plurality of wiring layers WLs. The plurality of wiring layers WLs have a first wiring layer 61 and a second wiring layer 62. In the plurality of wiring layers WLs, the first wiring layer 61 and the second wiring layer 62 are adjacent to each other. The capacitive element 42 is constructed using the first wiring layer 61. The plurality of signal lines SLs are included in the second wiring layer 62. In one specific example, as shown in Figure 4, both the first electrode 42d and the second electrode 42e belong to the first wiring layer 61. In another specific example, the plurality of wiring layers WLs include a zero wiring layer adjacent to the first wiring layer 61, which is located on the opposite side from the second wiring layer 62 when viewed from the first wiring layer 61. That is, the zero wiring layer, the first wiring layer 61, and the second wiring layer 62 are arranged in this order. The first electrode 42d belongs to the zero wiring layer, and the second electrode 42e belongs to the first wiring layer 61.

[0137] In this embodiment, the plurality of transistors TRs include a second transistor. One of the sources and drains of the second transistor is connected to the photoelectric conversion unit 15. The plurality of signal lines SLs include a second signal line. The second signal line is electrically connected to the gate of the second transistor. In this embodiment, the second signal line extends along the first direction D1.

[0138] The combination of the second transistor and the second signal line may be the combination of the reset transistor 36 and the reset signal line 26. The combination of the second transistor and the second signal line may be the combination of the transfer transistor 37 and the transfer control line 27.

[0139] Let's explain the above expression, "One of the sources and drains of the second transistor is connected to the photoelectric conversion unit 15." This expression is intended to include configurations in which one of the sources and drains of the second transistor is electrically connected to the photoelectric conversion unit 15 without the need for other transistors. Furthermore, this expression is intended to include configurations in which another transistor is interposed between one of the sources and drains of the second transistor and the photoelectric conversion unit 15, and the two are electrically connected when the other transistor is in the ON state. For this reason, the combination of the second transistor and the second signal line can be the combination of the feedback transistor 38 and the feedback control line 28. The combination of the second transistor and the second signal line can also be the combination of the address transistor 40 and the address signal line 30.

[0140] In this embodiment, the plurality of transistors TRs include a third transistor. The plurality of signal lines SLs include a third signal line. The gate of the third transistor may be electrically connected to the third signal line. Specifically, the gate of each of the plurality of transistors TRs may be electrically connected to the corresponding signal line among the plurality of signal lines SLs. In this embodiment, the third signal line extends along the first direction D1.

[0141] The combination of the third transistor and the third signal line may be the combination of the reset transistor 36 and the reset signal line 26. The combination of the third transistor and the third signal line may be the combination of the feedback transistor 38 and the feedback control line 28. The combination of the third transistor and the third signal line may be the combination of the address transistor 40 and the address signal line 30. The combination of the third transistor and the third signal line may be the combination of the transfer transistor 37 and the transfer control line 27.

[0142] Returning to Figure 14, in this embodiment, each of the gates of the multiple transistors TRs includes a first portion p1 that does not overlap with the capacitive element 42 in a plan view. Each of the first portions p1 of the multiple transistors TRs is electrically connected to the corresponding signal line among the multiple signal lines SLs. In this configuration, since the capacitive element 42 and the first portion p1 do not overlap in a plan view, the capacitive element 42 is less likely to get in the way when providing an electrical path connecting the signal line and the first portion p1.

[0143] Note that each of the multiple transistors TRs may overlap with the capacitive element 42. For example, in Figure 14, parts of the reset transistor 36 and the feedback transistor 38 overlap with the capacitive element 42. That is, the gate 36e, the third diffusion layer 36s, and the fourth diffusion layer 36d of the reset transistor 36 overlap with the capacitive element 42. Also, the gate 38e and the fourth diffusion layer 36d of the feedback transistor 38 overlap with the capacitive element 42.

[0144] In this embodiment, in a plan view, each of the first portion p1 of the plurality of transistors TRs has a portion that overlaps with the corresponding signal line among the plurality of signal lines SLs. With this configuration, a layout can be adopted in which an electrical path connecting the signal line and the first portion p1 is provided in the overlapping portion in the plan view.

[0145] In this embodiment, the imaging device 100 includes a plurality of vias vi. Each of the first portion p1 of the plurality of transistors TRs is electrically connected to a corresponding signal line among the plurality of signal lines SLs via a corresponding via among the plurality of vias vi.

[0146] In this embodiment, in each of the multiple transistors TRs, the voltage from the corresponding signal line among the multiple signal lines SLs is applied to the first part p1, i.e., the gate electrode of the corresponding transistor TRs.

[0147] In this embodiment, the imaging device 100 includes a branch signal line BL. The plurality of signal lines SLs include the first signal line. The branch signal line BL extends from the first signal line. In a plan view, the direction in which the branch signal line BL extends is different from the direction in which the first signal line extends. The plurality of transistors TRs include the first transistor. The first signal line, the branch signal line BL, and the gate of the first transistor are electrically connected in this order. In this embodiment, the first signal line extends along the first direction D1.

[0148] In this embodiment, in a plan view, the branch signal line BL does not overlap with the capacitive element 42. In this configuration, since the branch signal line BL and the capacitive element 42 do not overlap in a plan view, the capacitive element 42 is less likely to get in the way when providing an electrical path connecting the branch signal line BL and the gate of the first transistor.

[0149] In this embodiment, in a plan view, the branch signal line BL has a portion that overlaps with the gate of the first transistor. With this configuration, a layout can be adopted in which an electrical path connecting the branch signal line BL and the gate of the first transistor is provided in the overlapping portion in the plan view.

[0150] In this embodiment, the first signal line is electrically connected to the gate of the first transistor via the branch signal line BL and via vi in ​​that order.

[0151] In this embodiment, the direction in which the branch signal line BL extends is different from the direction in which the first signal line extends, and they are electrically connected by via vi. This configuration allows for increased flexibility in the wiring layout for electrically connecting the gate of the first transistor and the first signal line, while suppressing parasitic capacitance between the path through which the control signal flows and the capacitive element 42.

[0152] In this embodiment, multiple vias vi extend along the thickness direction of the semiconductor substrate 2. The first signal line extends along the first direction D1. The branch signal line BL extends along the second direction D2.

[0153] In the example shown in Figure 14, the combination of the first transistor and the first signal line is the combination of the reset transistor 36 and the reset signal line 26. However, the combination of the first transistor and the first signal line may also be the combination of the feedback transistor 38 and the feedback control line 28. The combination of the first transistor and the first signal line may also be the combination of the address transistor 40 and the address signal line 30. The combination of the first transistor and the first signal line may also be the combination of the transfer transistor 37 and the transfer control line 27. These points are also true in the embodiments described later.

[0154] The first transistor, second transistor, and third transistor may be the same single transistor. Alternatively, two transistors selected from the group consisting of the first, second, and third transistors may be the same single transistor, with the remaining one being a different transistor. The first, second, and third transistors may also be three different transistors.

[0155] The first signal line, the second signal line, and the third signal line may be the same single signal line. Alternatively, two of the group consisting of the first signal line, the second signal line, and the third signal line may be the same single signal line, and the remaining one may be a different signal line. The first signal line, the second signal line, and the third signal line may be three different signal lines.

[0156] The following describes several other embodiments. Elements common to earlier and later embodiments are given the same reference numerals, and their descriptions may be omitted. Also, descriptions of functions and effects common to earlier and later embodiments may be omitted. The descriptions of each embodiment are mutually applicable, as long as they do not conflict technically. As long as they do not conflict technically, each embodiment may be combined with another.

[0157] (Embodiment 2) Figure 19 is a schematic plan view showing an example of the layout of some wiring and some elements in a pixel according to Embodiment 2.

[0158] In Embodiment 2, unlike Embodiment 1, the imaging device does not have a branch signal line BL. Instead, the imaging device includes a connection wiring CL. In Embodiment 2, the connection wiring CL is provided in the first wiring layer 61 at a different location from the capacitive element 42. Specifically, the connection wiring CL is physically and electrically isolated from the capacitive element 42.

[0159] The direction in which the connecting wire CL extends is different from the direction in which the first signal line extends. The first signal line is electrically connected to the gate of the first transistor via a via vi, the connecting wire CL, and another via vi in ​​that order. Typically, these two vias vi extend along the thickness direction of the semiconductor substrate 2. In this embodiment, the first signal line extends along the first direction D1. The connecting wire CL extends along the second direction D2.

[0160] Thus, in Embodiment 2, the direction in which the connecting wiring CL extends is different from the direction in which the first signal line extends, and they are electrically connected by via vi. With this configuration, it is possible to increase the degree of freedom in the wiring layout for electrically connecting the gate of the first transistor and the first signal line while suppressing parasitic capacitance between the path through which the control signal flows and the capacitive element 42.

[0161] In the example shown in Figure 19, the combination of the first transistor and the first signal line is the combination of the reset transistor 36 and the reset signal line 26. The reset signal line 26 is electrically connected to the gate 36e of the reset transistor 36 via a via vi, a connecting wire CL, and another via vi in ​​that order.

[0162] However, the combination of the first transistor and the first signal line may also be a combination of the feedback transistor 38 and the feedback control line 28. In this case, the feedback control line 28 may be electrically connected to the gate 38e of the feedback transistor 38 via a via vi, a connecting wire CL, and another via vi in ​​that order.

[0163] The combination of the first transistor and the first signal line may also be the combination of the address transistor 40 and the address signal line 30. In this case, the address signal line 30 may be electrically connected to the gate 40e of the address transistor 40 via a via vi, a connecting wire CL, and another via vi in ​​that order.

[0164] The combination of the first transistor and the first signal line may also be a combination of the transfer transistor 37 and the transfer control line 27. In this case, the transfer control line 27 may be electrically connected to the gate of the transfer transistor 37 via a via vi, a connecting wire CL, and another via vi in ​​that order.

[0165] (Embodiment 3) Figure 20 is a schematic plan view showing an example of the layout of some wiring and some elements in a pixel according to Embodiment 3.

[0166] Unlike Embodiment 1, Embodiment 3 does not have a branch signal line BL. Instead, in a plan view, the gate shape of the first transistor in Embodiment 3 is different from the gate shape of the first transistor in Embodiment 1.

[0167] Specifically, the gate of the first transistor in Embodiment 3 has a base portion and an extension portion. The shape of the base portion is the same as the shape of the gate of the first transistor in Embodiment 1. The extension portion extends from the base portion in a direction different from the direction in which the first signal line extends. Here, the direction in which the extension portion extends refers, for example, to the longitudinal direction of the extension portion in a plan view. The first signal line is electrically connected to the extension portion via via vi. In this embodiment, the first signal line extends along a first direction D1. The extension portion extends from the base portion along a second direction D2. In this example, with respect to the first direction D1, the dimensions of the extension portion are smaller than the dimensions of the base portion. With respect to the second direction D2, the dimensions of the extension portion are larger than the dimensions of the base portion.

[0168] Thus, in Embodiment 3, the direction in which the extension portion extends and the direction in which the first signal line extends are different, and they are electrically connected by via vi. With this configuration, parasitic capacitance between the path through which the control signal flows and the capacitive element 42 can be suppressed, while increasing the degree of freedom in the wiring layout for electrically connecting the gate of the first transistor and the first signal line.

[0169] In the example shown in Figure 20, the combination of the first transistor and the first signal line is the combination of the reset transistor 36 and the reset signal line 26. The gate 36e of the reset transistor 36 has a base portion 36e1 and an extended portion 36e2.

[0170] However, the combination of the first transistor and the first signal line may also be a combination of the feedback transistor 38 and the feedback control line 28. In this case, the gate 38e of the feedback transistor 38 may have a base portion and an extended portion.

[0171] The combination of the first transistor and the first signal line may also be the combination of the address transistor 40 and the address signal line 30. In this case, the gate 40e of the address transistor 40 may have a base portion and an extension portion.

[0172] The combination of the first transistor and the first signal line may be a combination of the transfer transistor 37 and the transfer control line 27. In this case, the gate of the transfer transistor 37 may have a base portion and an extended portion.

[0173] (Embodiment 4) FIG. 21 is a plan view schematically showing an example of a layout of a plurality of wirings and a plurality of elements in a pixel according to Embodiment 4.

[0174] In Embodiment 4, unlike Embodiment 1, among the plurality of signal lines SLs, the signal line JL overlaps with the capacitive element 42 with a width equal to half of the line width in a plan view. Even with this configuration, the parasitic capacitance between the signal line JL and the capacitive element 42 can be reduced compared to a case where the entire line width of the signal line JL overlaps with the capacitive element 42 in a plan view.

[0175] More generally, in a plan view, J% of the line width of the signal line JL overlaps with the capacitive element 42, where J may be greater than 0 and equal to or less than 50. In Embodiment 4, J is 50.

[0176] In the example of FIG. 21, the signal line JL is the reset signal line 26. However, the signal line JL may be the feedback control line 28, the address signal line 30, or the transfer control line 27.

[0177] In the example of FIG. 21, the number of signal lines overlapping with the capacitive element 42 by J% of the line width (where 0<J≦50) in a plan view is one. However, this number may be plural.

[0178] (Embodiment 5) FIG. 22 is a plan view schematically showing an example of a layout of a plurality of wirings and a plurality of elements in a pixel according to Embodiment 5.

[0179] In Embodiment 5, unlike Embodiment 1, the signal line KL among the plurality of signal lines SLs has a bent shape in a plan view. The signal line KL overlaps the capacitive element 42 over a distance equal to half the maximum length ML1 of the capacitive element 42 in the first direction D1 in a plan view. Even with this configuration, the parasitic capacitance between the signal line KL and the capacitive element 42 can be reduced compared to a case where the signal line KL overlaps the capacitive element 42 over the same distance as the maximum length ML1 in a plan view.

[0180] More generally, the signal line KL overlaps the capacitive element 42 over a distance of K% of the maximum length ML1 in a plan view, and K may be greater than 0 and 50 or less. In Embodiment 5, K is 50.

[0181] In the example of FIG. 22, the signal line KL is the reset signal line 26. However, the one signal line may be the feedback control line 28, may be the address signal line 30, or may be the transfer control line 27.

[0182] In the example of FIG. 22, the number of signal lines overlapping the capacitive element 42 over a distance of K% (where 0<K≦50) of the maximum length ML1 in a plan view is one. However, this number may be plural.

[0183] In the example of FIG. 22, the reset signal line 26 has a bent shape in a plan view. The feedback control line 28 may have a bent shape in a plan view, the address signal line 30 may have a bent shape in a plan view, and the transfer control line 27 may have a bent shape in a plan view.

[0184] From the previously described embodiments together with Embodiment 5 described with reference to FIG. 22, the following technology is derived; None of the plurality of signal lines SLs overlap the capacitive element 42 over a distance longer than half the maximum length ML1 of the capacitive element 42 in the first direction D1 in a plan view.

[0185] This configuration reduces parasitic capacitance between the multiple signal lines SLs and the capacitive element 42, thereby suppressing the delay of signals flowing through the multiple signal lines SLs. For this reason, this configuration is suitable for providing an imaging device 100 capable of high-speed imaging.

[0186] (Other embodiments) Other embodiments will be described below. Figures 23 and 24 are schematic plan views showing examples of wiring and the layout of some elements in pixels according to other embodiments.

[0187] For example, as shown in Figure 23, Embodiment 1 may be combined with the feature that at least one of the multiple signal lines SLs does not extend in a straight line but has a bent shape.

[0188] Furthermore, as shown in Figure 23, for example, the shape of the capacitive element 42 does not have to be rectangular in a plan view.

[0189] As described above, each of the multiple signal lines SLs transmits transistor control signals to each of the multiple transistors TRs. In one example, the wiring other than the signal lines that transmit transistor control signals is arranged so that it overlaps with the capacitive element 42 in a plan view. In the example in Figure 24, the sensitivity adjustment line 32 overlaps with the capacitive element 42 in a plan view. The sensitivity adjustment line 32 is connected to the first electrode 42d of the capacitive element 42. That is, the sensitivity adjustment line 32 is at the same potential as the first electrode 42, so parasitic capacitance between them is not a problem. Note that there do not need to be any signal lines that overlap with the capacitive element 42 in a plan view.

[0190] In the embodiment described above, each of the multiple signal lines SLs is connected to the gate of each of the multiple transistors TRs. However, the multiple signal lines SLs may include wiring connected to the source or drain of the transistors. In one example, the transistors are controlled by signals flowing through the wiring connected to the source or drain of the transistors. Typically, these signals control the gate-source voltage of the transistors. All of the multiple signal lines SLs may be connected to the source or drain of the corresponding transistors.

[0191] Furthermore, a configuration having multiple photoelectric conversion units within a single pixel may be adopted. A configuration having a photodiode as the photoelectric conversion unit may also be adopted. A configuration having a photoelectric conversion unit in which a photoelectric conversion film is arranged between a pair of electrodes, and a photoelectric conversion unit that is a photodiode, within a single pixel may also be adopted. [Industrial applicability]

[0192] The technology described herein can reduce parasitic capacitance in signal lines and enable high-speed imaging. This technology is useful for digital cameras and the like. [Explanation of Symbols]

[0193] 2 Semiconductor substrates 2a Support board 2s element isolation area 2gw impurity layer 2w well 4 interlayer insulating layer 4a First insulating layer 4b Second insulating layer 4c Third insulating layer 4d Fourth insulating layer 4e Fifth insulating layer 10 pixels 11 Photodiode 15 Photoelectric conversion unit 15a Counter electrode 15b Photoelectric conversion film 15c pixel electrode 15h Photosensitive area 16 Vertical scanning circuit 17. Accumulation control line 18 Vertical signal lines 19 Load circuit 20-column signal processing circuit 21 Horizontal signal readout circuit 22 Power wiring 23 Horizontal common signal line 26 Reset signal line 27 Transfer control line 28 Feedback control lines 30 Address signal lines 32 Sensitivity adjustment line 34 Amplifying transistors Gate 34e 34s First diffusion layer 34d Second Diffusion Layer 36 Reset Transistor 36e Gate 36e1 Basic part 36e2 Extension part 36s Third diffusion layer 36d Fourth Diffusion Layer 37 Transfer transistors 38 Feedback Transistors Gate 38e 38d Fifth Diffusion Layer 39 Insulating film 40 Address Transistors 40e gate 40s Sixth diffusion layer 40d 7th diffusion layer 41 Capacity part 42 Capacitive elements 42d 1st electrode 42e 2nd electrode 42g insulating layer 44 Charge accumulation region 46 Reset Drain Node 60 surface 61 1st wiring layer 62 2nd wiring layer 63 3rd wiring layer 99 Multiple pixels 100 Imaging device p1 1st part vi BL branch signal line CL connection wiring D1 1st direction D2 2nd direction Dh (horizontal direction) Dv vertical direction FC Fringe Capacity FDL Electrical Path LEC rectangle PXs Multiple pixels SLs (Multiple signal lines) TRs (Multiple Transistors) WLs (Multiple Wiring Layers) SLx signal line JL signal line KL signal line X signal line Y branch signal line

Claims

1. Semiconductor substrate and A plurality of pixels arranged in a first direction on the semiconductor substrate, A first signal line located above the semiconductor substrate, Equipped with, Each of the aforementioned plurality of pixels is A photoelectric conversion unit that converts light into signal charge, A transistor having a gate electrically connected to the first signal line, Capacitive elements, Includes, In the first pixel among the plurality of pixels, At least a portion of the gate, source, or drain of the transistor overlaps with the capacitive element in a plan view. The first signal line, in a plan view, does not overlap with the capacitive element in terms of overall line width. Imaging device.

2. The gate of the transistor of the first pixel includes a first portion that does not overlap with the capacitive element in a plan view. The first portion of the transistor of the first pixel is electrically connected to the first signal line. The imaging apparatus according to claim 1.

3. Further comprising vias adjacent to the first portion, The first portion of the transistor is electrically connected to the first signal line via the via. The imaging apparatus according to claim 2.

4. It also has branch signal lines, The aforementioned branch signal line extends from the first signal line, In a plan view, the direction in which the branch signal line extends is different from the direction in which the first signal line extends. The first signal line is electrically connected to the transistor of the first pixel via the branch signal line. The imaging apparatus according to claim 1 or 2.

5. The first signal line is electrically connected to the gate of the transistor of the first pixel via the branch signal line. The imaging apparatus according to claim 4.

6. In a plan view, the first signal line does not overlap with the capacitive element of the first pixel by a width of more than half the line width. The imaging apparatus according to claim 1 or 2.

7. The first signal line does not overlap with the capacitive element of the first pixel in a plan view. The imaging apparatus according to claim 1 or 2.

8. The semiconductor substrate further comprises a plurality of wiring layers located above it, The plurality of wiring layers have a first wiring layer and a second wiring layer that are adjacent to each other. The capacitive element is constructed using the first wiring layer, The first signal line is included in the second wiring layer. The imaging apparatus according to claim 1 or 2.

9. In a plan view, the maximum length of the capacitive element of the first pixel along the first direction is greater than one-third of the length of the first pixel along the first direction. The imaging apparatus according to claim 1 or 2.

10. When the direction perpendicular to the thickness direction and the first direction of the semiconductor substrate is defined as the second direction, In a plan view, the maximum length of the first capacitive element of the first pixel in the first direction is greater than the maximum length of the first capacitive element of the first pixel in the second direction. The imaging apparatus according to claim 1 or 2.

11. The capacitive element of the first pixel includes a first electrode, a second electrode, and an insulating layer between the first electrode and the second electrode. The imaging apparatus according to claim 1 or 2.

12. The first electrode and the second electrode contain a metal. The imaging apparatus according to claim 11.

13. The capacitive element of the first pixel is the one with the largest area in a plan view among the capacitive elements included in the first pixel. The imaging apparatus according to claim 1 or 2.

14. Semiconductor substrate and A plurality of pixels arranged in a first direction on the semiconductor substrate, A first signal line located above the semiconductor substrate, Equipped with, Each of the aforementioned plurality of pixels is A photoelectric conversion unit that converts light into signal charge, A transistor having a gate electrically connected to the first signal line, Capacitive elements, Includes, In the first pixel among the plurality of pixels, At least a portion of the gate, source, or drain of the transistor overlaps with the capacitive element in a plan view. The first signal line, in a plan view, does not overlap with the capacitive element over a distance longer than half the maximum length of the capacitive element in the first direction. Imaging device.

Images