Delta-sigma modulator

Abstract

To provide a delta-sigma modulator with high resolution.SOLUTION: A delta-sigma modulator 10 includes: a first integration unit that integrates an input analog signal; a second integration unit that integrates a signal output by the first integration unit; a quantizer that quantizes a signal output by the second integration unit; a DA converter that DA-converts an output of the quantizer and outputs a feedback signal to be fed back to the first integration unit; and a control unit that has a control circuit 180 and a reset circuit 190 and that controls the first integration unit and the second integration unit to perform different integration operations in a first period and a second period. The second integration unit receives and integrates a feedback signal output from the DA converter via the first integration unit in the first period and the second period.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to a delta-sigma modulator. [Background technology]

[0002] Conventionally, an incremental delta-sigma modulator has been known as a method for achieving high resolution with low power consumption. This modulator operates as an integrator with a first-order feedback coefficient of 1 until a predetermined period has elapsed, and then operates as an amplifier with a first-order feedback coefficient greater than 1 after the predetermined period has elapsed (see, for example, Patent Document 1). [Prior art document] [Patent] Patent Document 1: Japanese Unexamined Patent Publication No. 2019-118100 [Overview of the project]

[0003] In a first embodiment of the present invention, a delta-sigma modulator is provided. The delta-sigma modulator may include a first integrator that integrates an input analog signal. The delta-sigma modulator may include a second integrator that integrates the signal output by the first integrator. The delta-sigma modulator may include a quantizer that quantizes the signal output by the second integrator. The delta-sigma modulator may include a DA converter that outputs a feedback signal which is used to feed back the output of the quantizer to the first integrator. The delta-sigma modulator may include a control unit that controls the first and second integrators to perform different integration operations in a first period and a second period. The second integrator may receive the feedback signal output by the DA converter via the first integrator during the first and second periods and integrate it.

[0004] The control unit may control the first integrator to operate as an integrator with a smaller feedback coefficient in the second period than in the first period. The control unit may also control the second integrator to operate as an integrator with a larger feedback coefficient in the second period than in the first period.

[0005] The control unit may control the first integrator to operate as an integrator with a feedback coefficient of 1 during the first period and as an integrator with a feedback coefficient of 0 during the second period. The control unit may control the second integrator to operate as an integrator with a feedback coefficient of 1 during the first period and as an integrator with a feedback coefficient greater than 1 during the second period.

[0006] The first integrator may, during the second period, output the feedback signal output by the DA converter to the second integrator with the same gain as when it was input to the first integrator.

[0007] The first integrator may have an adder to which a feedback signal is input. The first integrator may have a first switching unit that outputs the signal output by the adder with a gain of 1 during the first period and alternately outputs it with gains of 1 and 0 during the second period. The first integrator may have a feedback path that returns the output of the first switching unit to the input of the adder. The first integrator may output the signal through the feedback path in both the first and second periods.

[0008] The first switching unit may include a first delay element that delays the signal output by the summing unit, and an amplifier that outputs the signal output by the summing unit with a gain of 0. The first switching unit may also include a multiplexer to which the output of the first delay element and the output of the amplifier are input.

[0009] The delta-sigma modulator may be an incremental AD converter that resets after each cycle of the AD conversion that converts the input analog signal into a digital signal. The multiplexer may output a signal with an amplifier gain of 0 during the reset period.

[0010] The second integrator may have a second switching unit that outputs the signal from the first integrator with a delay during the first period, and outputs the signal from the first integrator without delay during the second period.

[0011] The second switching unit may have a first switched-capacitor circuit connected to the output of the first integrator. The second switching unit may have a first changeover switch connected to the first switched-capacitor circuit. The second switching unit may have a second switched-capacitor circuit connected in parallel with the first switched-capacitor circuit. The second switching unit may have a second changeover switch connected to the second switched-capacitor circuit. The control unit may turn on the first changeover switch during the first period to discharge from the first switched-capacitor circuit, thereby delaying the output of the signal from the first integrator, and turn on the second changeover switch during the second period to discharge from the second switched-capacitor circuit, thereby outputting the signal from the first integrator without delay during the second period.

[0012] It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. Furthermore, subcombinations of these features may also constitute an invention. [Brief explanation of the drawing]

[0013] [Figure 1] This example shows the configuration of a delta-sigma modulator according to this embodiment. [Figure 2] A more detailed configuration example of the delta-sigma modulator according to this embodiment is shown. [Figure 3] An example of the actual circuit of the first integrating section of the delta-sigma modulator according to this embodiment is shown. [Figure 4] An example of the operating characteristics of the first integrating unit is shown. [Figure 5] An example of the actual circuit of the second integrating section of the delta-sigma modulator according to this embodiment is shown. [Figure 6] This embodiment shows a delta-sigma modulator. [Modes for carrying out the invention]

[0014] Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0015] FIG. 1 shows a configuration example of a delta-sigma modulator 10 according to the present embodiment. As an example, the delta-sigma modulator 10 receives an input analog signal A sig to a digital signal D out is an incremental AD converter that resets after each cycle of AD conversion for converting. The delta-sigma modulator 10 can achieve higher resolution by repeating one cycle of AD conversion consisting of a first period and a second period and a reset period after AD conversion. The delta-sigma modulator 10 includes an addition / subtraction unit 110, a first integration unit 120, a second integration unit 130, a selection unit 140, a quantizer 150, a DA converter 170, a control circuit 180, and a reset circuit 190. Note that the control unit of the present application may include the control circuit 180 and the reset circuit 190 of the present embodiment.

[0016] The addition / subtraction unit 110 is connected to an input terminal 100, the first integration unit 120, and the DA converter 170. The addition / subtraction unit 110 receives an analog signal A input to the input terminal 100 sig from which a feedback signal A output from the DA converter 170 FB is subtracted to obtain an analog signal A IN1 is output to the first integration unit 120.

[0017] The first integration unit 120 is connected to the second integration unit 130 and the selection unit 140, and integrates the analog signal A sig input to the input terminal 100. The first integration unit 120 may be an analog integrator. The first integration unit 120 integrates the analog signal A sig which is a difference between the analog signal A FB and the feedback signal A IN1 , and outputs an analog signal A OUT1 to the second integration unit 130 and the selection unit 140.

[0018] The second integrator 130 is connected to the selection unit 140 and receives the analog signal A output by the first integrator 120. OUT1 The second integrator 130 may be an analog integrator. The second integrator 130 integrates the feedback signal A output by the DA converter 170 during the first and second periods. FB The signal is received via the first integrator 120, integrated, and the resulting analog signal A is obtained. OUT2 This is output to the selection unit 140.

[0019] The selection unit 140 is connected to the input terminal 100 and the quantizer 150, and receives the analog signal A input to the input terminal 100. sig , the analog signal A output by the first integrator 120 OUT1 , and the analog signal A output by the second integrator 130 OUT2 Select at least one of the following to obtain analog signal A corresponding to the selected signal. SUM2 The output is provided. The selection unit 140 may be configured to perform feedforward control of the delta-sigma modulator 10.

[0020] The quantizer 150 is connected to the output terminal 160 and the DA converter 170, and quantizes the signal output by the second integrator 130. The quantizer 150 quantizes the analog signal A output by the selection unit 140. SUM2 Quantized digital signal D out The quantizer 150 outputs analog signal A in response to an externally supplied clock signal. SUM2 The signal may be quantized. The quantizer 150 functions as a 1-bit quantizer to convert the binary digital signal D out It may be quantized to this. Alternatively, the quantizer 150 functions as a multibit quantizer, and the multi-level digital signal D out It may also be quantized.

[0021] The DA converter 170 receives the output D of the quantizer 150. OUT Feedback signal A is fed back to the first integrator 120 after being converted using DA (digital-to-analog) conversion. FBThe DA converter 170 outputs a digital signal D in synchronization with the clock signal, etc. OUT The feedback signal A is an analog signal. FB You may convert it to this.

[0022] The control circuit 180 is connected to the second integration unit 130 and the selection unit 140, and outputs control signals to switch the operation of the second integration unit 130 and the selection unit 140. The control circuit 180 may switch the operation of the second integration unit 130 and the selection unit 140 at predetermined timings. The control circuit 180 may output different control signals to the second integration unit 130 and the selection unit 140. The control circuit 180 may also notify the reset circuit 190 of the timing when a reset signal should be supplied.

[0023] The reset circuit 190 is connected to the first integrator 120 and the second integrator 130, and at predetermined intervals, the output A of the first integrator 120 and the second integrator 130 is reset. OUT It outputs a reset signal to reset it. The first integrator 120 and the second integrator 130 are controlled by a control signal from the control circuit 180 and a reset signal from the reset circuit 190 to perform different integrating operations in the first and second periods.

[0024] Figure 2 shows a more detailed configuration example of the delta-sigma modulator 10 according to this embodiment. Figure 2 shows in more detail the first integration unit 120, the second integration unit 130, and the selection unit 140 in the delta-sigma modulator 10 of Figure 1. These will be described in more detail below.

[0025] The first integration unit 120 includes a first addition unit 200 and a first switching unit 201, and has a feedback path that returns the output of the first switching unit 201 to the input of the first addition unit 200. The first addition unit 200 is connected to an addition / subtraction unit 110, a feedback path, and the input of the first switching unit 201, and receives a feedback signal A via the addition / subtraction unit 110. FB A signal corresponding to this is input. The first adder 200 receives the analog signal A from the addition / subtraction unit 110. IN1 And, analog signal A from the first switching unit 201OUT1 The two are added together, and the first switching unit 201 receives the analog signal A SUM1 Outputs.

[0026] The first switching unit 201 receives the analog signal A output by the first adding unit 200. SUM1 The signal is output with a gain of 1 during the first period, and alternately output with gains of 1 and 0 during the second period. The first switching unit 201 includes a first delay element 205, a first amplifier 210, a first multiplexer 215, a second delay element 220, and a second multiplexer 225.

[0027] The first delay element 205 is connected between the first adder 200 and one input of the first multiplexer 215, and receives signal A from the first adder 200. SUM1 The signal A is output with a delay. The first amplifier 210 is connected between the first adder 200 and the other input of the first multiplexer 215, and the signal A output by the first adder 200 is delayed. SUM1 The first multiplexer 215 outputs a signal with a gain of 0 (i.e., 0V). The output of the first multiplexer 215 is connected to the input of the second delay element 220 and the second multiplexer 225, and the output of the first delay element 205 and the output of the first amplifier 210 are input to it, and in response to the reset signal it outputs either the output of the first delay element 205 or the output of the first amplifier 210. During the reset period, the first multiplexer 215 may output a signal that the first amplifier 210 outputs with a gain of 0 in response to the reset signal.

[0028] The second delay element 220 is connected between the output of the first multiplexer 215 and the other input of the second multiplexer 225, and delays the signal from the first multiplexer 215 before outputting it. The output of the second multiplexer 225 is connected to the inputs of the second integrator 130 and the first adder 200. The second multiplexer 225 receives the output of the second delay element 220 and the output of the first multiplexer 215 as inputs, and outputs either the output of the second delay element 220 or the output of the first multiplexer 215 in response to a reset signal.

[0029] With this structure, the first integrator 120 receives signal A through the same feedback path in both the first and second periods. OUT1 This outputs a signal A corresponding to the feedback signal output from the first integrator 120. OUT1 This signal is input to the second integrator 130 under the same conditions (noise, phase, etc.) for both the first and second periods. As a result, the first integrator 120 and the second integrator 130 receive the feedback signal A from a single DA converter 170. FB This can be used in the first and second periods without any additional adjustments to the conditions.

[0030] The second integrator 130 includes a second switching unit 203, a second adder 240, a second amplifier 245, a fourth multiplexer 250, and a fourth delay element 255. The second integrator 130 has a feedback path that returns the output of the second adder 240 to the input of the second adder 240 via the second amplifier 245, the fourth multiplexer 250, and the fourth delay element 255.

[0031] The second switching unit 203 receives signal A from the first integrating unit 120 during the first period. OUT1 The signal A from the first integrator 120 is output with a delay, and in the second period, the signal A from the first integrator 120 is output. OUT1 The signal A is output without delay. The second switching unit 203 includes a third delay element 230 and a third multiplexer 235. The third delay element 230 is connected between the first integrator 120 and one input of the third multiplexer 235, and the signal A output by the first integrator 120 is output. OUT1 The signal is delayed and output. The third multiplexer 235 has its other input connected to the first integrator 120 and its output connected to the input of the second adder 240. The third multiplexer 235 outputs either the output of the third delay element 230 or the output of the first integrator 120 in response to the control signal. In the first period, the third multiplexer 235 outputs the signal from the third delay element 230, and in the second period, it outputs the signal A from the first integrator 120. OUT1 You may output this.

[0032] The second adder 240 receives the analog signal A from the third multiplexer 235. IN2 The analog signal from the feedback path is added to this, and the resulting analog signal A is obtained by adding the two signals together. OUT2 The second amplifier 245 is connected between the output of the second adder 240 and one input of the fourth multiplexer 250, and outputs the analog signal A from the second adder 240 at a magnification of x (x>1). OUT2 The signal is amplified and output. The other input of the fourth multiplexer 250 is connected to the output of the second adder 240, and the output of the fourth delay element 255 is connected to the fourth delay element 255. The fourth multiplexer 250 outputs either the output of the second adder 240 or the output of the second amplifier 245 according to the control signal. The fourth delay element 255 is connected to the second adder 240 and delays the signal from the fourth multiplexer 250 before outputting it to the second adder 240.

[0033] The fourth multiplexer 250 receives signal A from the second adder 240 during the first period. OUT2 The output is provided, and in the second period, the signal from the second amplifier 245 may be output.

[0034] The selection unit 140 includes a third amplifier 260, a first switch 265, and a third adder 270. The third amplifier 260 is connected between the output of the first integrator 120 and the first switch 265, and receives the analog signal A from the first integrator 120. OUT1 The signal is amplified by a factor greater than 1 (for example, a factor of 2 in this embodiment) and output. One end of the first switch 265 is connected to the third adder 270 and is turned on / off according to the control signal to connect / disconnect the third amplifier 260 and the third adder 270. The third adder 270 is connected to the quantizer 150 and receives the analog signal A from the input terminal 100. sig , analog signal A from the first integrator 120 OUT1 , analog signal A from the second integrator 130 OUT2 The input is added and the analog signal A SUM2 The output is given by the selection unit 140, which outputs analog signal A during the first period. sig , 2A OUT1 , and AOUT2 The two values ​​are added together and output, and in the second period, analog signal A sig and A OUT2 You may add it and output the result.

[0035] Next, the operation of the delta-sigma modulator 10 according to this embodiment will be described. The control circuit 180 and the reset circuit 190 may control the first integrator 120 to operate as an integrator with a smaller feedback coefficient in the second period than in the first period, and the second integrator 130 to operate as an integrator with a larger feedback coefficient in the second period than in the first period. For example, the control circuit 180 and the reset circuit 190 may control the first integrator 120 to operate as an integrator with a feedback coefficient of 1 in the first period and as an integrator with a feedback coefficient of 0 in the second period, and the second integrator 130 to operate as an integrator with a feedback coefficient of 1 in the first period and as an integrator with a feedback coefficient greater than 1 in the second period.

[0036] Here, the feedback coefficient represents the magnification of the amplifier placed in the feedback path of each of the first integrator 120 and the second integrator 130. For example, in the path from the output to the input of the adder of the first integrator 120 and the second integrator 130, the feedback coefficient is 1 when the signal input to the path passes through the path without going through an amplifier, and the feedback coefficient is x when the signal input to the path passes through an amplifier with magnification x.

[0037] During the first period, in the first integrator 120, the first multiplexer 215 may output a signal from the first delay element 205 in response to a reset signal, and the second multiplexer 225 may output a signal from the second delay element 220 in response to a reset signal. During the second period, in the first integrator 120, the first multiplexer 215 may output a signal from the first amplifier 210 with a multiplier of 0 in response to a reset signal, and the second multiplexer 225 may output a signal that has been input without going through the second delay element 220 in response to a reset signal. As a result, during the first period, the analog signal A output by the first integrator 120 is OUT1 This is expressed by the following equation.

[0038]

number

[0039] Furthermore, during the second period, the analog signal A output by the first integrator 120 OUT1 This is expressed by the following equation. In the second period, the first integrator 120 operates as a delay element without a feedback coefficient and has a gain of 1, so the first integrator 120 processes the feedback signal A output by the DA converter 170 during the second period. FB This is output to the second integral unit 130 with the same gain as when it is input to the first integral unit 120.

[0040]

number

[0041] During the first period, in the second integrator 130, the third multiplexer 235 outputs a delayed signal from the third delay element 230 in accordance with the control signal, and during the second period, the third multiplexer 235 outputs a delayed signal A that is input without going through the third delay element 230 in accordance with the control signal. OUT1The output may be... Also, in the first period, in the second integrator 130, the fourth multiplexer 250 may output the input signal without going through the second amplifier 245 in accordance with the control signal, and in the second period, the fourth multiplexer 250 may output the signal from the second amplifier 245 amplified by x times in accordance with the control signal. In the first and second periods, the fourth delay element 255 delays and outputs the signal from the fourth multiplexer 250.

[0042] The second adder 240 adds the analog signal A, which is the result of adding the input signals. OUT2 This outputs the analog signal A output by the second integrator 130 during the first period. OUT2 This is expressed by the following equation.

[0043]

number

[0044] Furthermore, during the second period, the analog signal A output by the second integrator 130 is OUT2 This is shown by the following equation. As shown by the following equation, in the second period A IN2 Because the numerator of the coefficient is 1, the second integrator 130 receives the feedback signal A from the DA converter 170 under the same conditions as the first integrator 120. FB A signal corresponding to the signal can be used.

[0045]

number

[0046] In the selection unit 140, the first switch 265 is turned on by the control signal during the first period and turned off by the control signal during the second period. Therefore, in the first period, the selection unit 140 receives the following analog signal A SUM2 Outputs.

[0047]

number

[0048] Furthermore, the selection unit 140, in the second period, uses the following analog signal A SUM2 Outputs.

[0049]

number

[0050] In this embodiment, the delta-sigma modulator 10 can obtain two types of output by switching the circuit operation between the first period and the second period using the control circuit 180 and the reset circuit 190. When the quantization noise generated in the quantizer 150 is E1, the output D of the delta-sigma modulator 10 is OUT In the first period, it is expressed as follows:

[0051]

number

[0052] Here, the output signals A of the first integrator 120 and the second integrator 130 are OUT The initial value is 0, and the analog signal A is input to the delta-sigma modulator 10. sig If is approximately a constant value, the output of the i-th (i>1) quantizer 150 is D OUT (i) If so, analog signal A sig This is expressed as follows:

[0053]

number

[0054] Analog signal A input to delta-sigma modulator 10 sig This is the output D of quantizer 150. OUT It is expressed using and analog signal A sig The digital signal D obtained by digital conversion SIG This can be calculated. Furthermore, the quantization noise E1 of the quantizer 150 is given by the following equation.

[0055]

number

[0056] Furthermore, the output A of the second integrator 130 OUT2 In the second period, this is expressed by the following equation.

[0057]

number

[0058] Here, let m be the number of input clocks. An integrator with a feedback coefficient greater than 1 is given by the following equation.

[0059]

number

[0060] Furthermore, the initial value of the second integral unit 130 is A. OUT2 (n) Therefore, A SIG This is shown by the following equation.

[0061]

number

[0062] Therefore, analog signal A input to the delta-sigma modulator 10 SIG The output D of quantizer 150 OUT It can be expressed using analog signal A SIG The digital signal D obtained by digital conversion SIG It is possible to calculate this.

[0063] Figure 3 shows an example of the actual circuit of the first integrator 120 of the delta-sigma modulator 10 according to this embodiment. The first integrator 120 includes a second switch 300, a third switch 310, a first capacitor 305, a fourth switch 320, a fifth switch 315, a fourth amplifier 325, a first feedback capacitor 330, and a first reset switch 335.

[0064] The second switch 300 is connected between the input of the first integrator 120 and the first capacitor 305. The third switch 310 is connected between the node between the second switch 300 and the first capacitor 305 and the reference potential. The first capacitor 305 is connected between the second switch 300 and the fourth switch 320. The fourth switch 320 is connected to one terminal of the fourth amplifier 325. The fifth switch 315 is connected between the node between the fourth switch 320 and the first capacitor 305 and the reference potential. The second switch 300, the third switch 310, the first capacitor 305, the fourth switch 320, and the fifth switch 315 constitute a switched-capacitor circuit. The second switch 300 and the fifth switch 315 may be turned on when the first timing signal is high and turned off when it is low. The third switch 310 and the fourth switch 320 may be turned on when the second timing signal is high and turned off when it is low.

[0065] The first and second timing signals may alternately go high and are synchronized with a roughly constant clock period, and the same applies hereafter. The reference potential may be a predetermined potential, for example 0V (ground potential), and the same applies hereafter.

[0066] For example, during the period φ1 when the first timing signal is high, one end of the first capacitor 305 is connected to the input terminal of the first integrator 120, and the other end is connected to a reference potential, and the analog signal A from the input terminal is connected. IN1The capacitor is charged. In this case, during the period φ2 when the second timing signal is high, one end of the first capacitor 305 is connected to a reference potential and the other end is connected to one input terminal of the fourth amplifier 325 to discharge the charged charge. The first capacitor 305 repeats charging and discharging by repeating periods φ1 and φ2.

[0067] The fourth amplifier 325 has one end of the fourth switch 320 connected to one input terminal (negative terminal), a reference potential connected to the other input terminal (positive terminal), and the output terminal of the first integrator 120 connected to the output terminal. The first feedback capacitor 330 is connected between one input terminal (negative terminal) and the output terminal of the fourth amplifier 325. The first feedback capacitor 330 stores the signal input to one input terminal of the fourth amplifier 325. The first reset switch 335 is connected between one input terminal (negative terminal) and the output terminal of the fourth amplifier 325 and is connected in parallel with the first feedback capacitor 330. The first reset switch 335 is turned on and off in response to the reset signal, and when turned on, it discharges the charge stored in the first feedback capacitor 330, making it possible to set the output of the first integrator 120 (fourth amplifier 325) to 0V.

[0068] Figure 4 shows an example of the operating characteristics of the first integrator 120. In Figure 4, the incremental period represents the first period, the exponential period represents the second period, and the rst period represents the reset period. In Figure 4, the horizontal axis represents time, and the vertical axis represents voltage. Figure 4 shows examples of the first timing signal for period φ1 and the second timing signal for period φ2, an example of the reset signal (RST), and the output signal A from the output terminal of the first integrator 120. OUT1 This shows that, in other words, periods φ1 and φ2 switch on and off at predetermined intervals, and the reset signal is high during the reset period. Also, Figure 4 shows the analog signal A input to the first integrator 120. IN1 However, this example shows that the voltage is 0V until time 0, and then remains approximately constant from time 0 onward.

[0069] Output signal A of the first integrator 120OUT1 changes in accordance with an n-cycle timing signal (that is, n times of charging and discharging) in a first period. That is, the first integrating unit 120 receives the input analog signal A IN and operates to amplify the input analog signal A by n times (A OUT1 =nA IN1 ), wherein n corresponds to the number of input clocks.

[0070] In a second period, the reset signal RST rises and falls in synchronization with a first timing signal. Accordingly, the output signal A of the first integrating unit 120 in the second period OUT1 becomes 0V in a period φ1 when the first timing signal is high. In addition, the output signal A of the first integrating unit 120 OUT1 in a period φ2 when the second timing signal is high: since the first integrating unit 120 amplifies the input analog signal A sig again, A OUT1 =A IN1 is obtained. As described above, in the second period, the first integrating unit 120 outputs the feedback signal output by the DA converter 170 to the second integrating unit 130 with the same gain as when the feedback signal is input to the first integrating unit 120.

[0071] In a reset period during which the reset signal remains high, the output signal A of the first integrating unit 120 OUT1 satisfies A OUT1 =0V regardless of the period φ1 and the period φ2.

[0072] Figure 5 shows an example of the actual circuit of the second integrator 130 of the delta-sigma modulator 10 according to this embodiment. The second integrator 130 includes a first switched-capacitor circuit 510, a second switched-capacitor circuit 520, a first changeover switch 531, a second changeover switch 532, a fifth amplifier 540, a second feedback capacitor 550, a second reset switch 560, a third changeover switch 571, a fourth changeover switch 572, and a third switched-capacitor circuit 580. The first switched-capacitor circuit 510, the second switched-capacitor circuit 520, the first changeover switch 531, and the second changeover switch 532 constitute the second switching section 203 in Figure 2.

[0073] The first switched-capacitor circuit 510 is connected between the output of the first integrator 120 and the first changeover switch 531. The first switched-capacitor circuit 510 includes a sixth switch 511, a seventh switch 513, a third capacitor 512, an eighth switch 514, and a ninth switch 515. The sixth switch 511 is connected between the input terminal of the second integrator 130 and the third capacitor 512. The seventh switch 513 is connected between the node between the sixth switch 511 and the third capacitor 512 and the reference potential. The third capacitor 512 is connected between the sixth switch 511 and the eighth switch 514. The eighth switch 514 is connected between the first changeover switch 531 and the third capacitor 512. The ninth switch 515 is connected between the node between the eighth switch 514 and the third capacitor 512 and the reference potential.

[0074] The sixth switch 511 and the ninth switch 515 may be turned on when the first timing signal is high and turned off when it is low. The seventh switch 513 and the eighth switch 514 may be turned on when the second timing signal is high and turned off when it is low.

[0075] For example, during a period φ1 in which the first timing signal is high, one terminal of the third capacitor 512 is connected to the input terminal of the second integrating unit 130, and the other terminal is connected to a reference potential, whereby the analog signal A from the input terminal IN2 is charged. Further, during a period φ2 in which the second timing signal is high, one terminal of the third capacitor 512 is connected to the reference potential, and the other terminal is connected to the first changeover switch 531, so that when the first changeover switch 531 is on, the charged electric charge is discharged to the fifth amplifier 540. The third capacitor 512 repeats charging and discharging by repeating the period φ1 and the period φ2.

[0076] The second switched capacitor circuit 520 is connected between the output of the first integrating unit 120 and the second changeover switch 532, and is connected in parallel with the first switched capacitor circuit 510. The second switched capacitor circuit 520 includes a tenth switch 521, an eleventh switch 523, a fourth capacitor 522, a twelfth switch 524, and a thirteenth switch 525. The tenth switch 521 is connected between the input terminal of the second integrating unit 130 and the fourth capacitor 522. The eleventh switch 523 is connected between a node between the tenth switch 521 and the fourth capacitor 522 and the reference potential. The fourth capacitor 522 is connected between the tenth switch 521 and the twelfth switch 524. The twelfth switch 524 is connected between the second changeover switch 532 and the fourth capacitor 522. The thirteenth switch 525 is connected between a node between the twelfth switch 524 and the fourth capacitor 522 and the reference potential.

[0077] The eleventh switch 523 and the thirteenth switch 525 may be turned on when the first timing signal is high, and turned off when the first timing signal is low. The tenth switch 521 and the twelfth switch 524 may be turned on when the second timing signal is high, and turned off when the second timing signal is low.

[0078] For example, during the period φ2 when the second timing signal is high, one end of the fourth capacitor 522 is connected to the input terminal of the second integrator 130, and the other end is connected to the second changeover switch 532. When the second changeover switch 532 is ON, the analog signal A from the input terminal is... IN2 The signal is output to the fifth amplifier 540 without delay. Also, during the period φ1 when the first timing signal is high, both sides of the fourth capacitor 522 are connected to a reference potential and the charge is discharged to the reference potential. The fourth capacitor 522 repeatedly charges and discharges by repeating periods φ1 and φ2.

[0079] The first changeover switch 531 is connected between the first switched-capacitor circuit 510 and the fifth amplifier 540. The first changeover switch 531 is turned on / off in response to a control signal from the control circuit 180. The first changeover switch 531 may be turned on during the first period and turned off during the second period. The second changeover switch 532 is connected between the second switched-capacitor circuit 520 and the fifth amplifier 540. The second changeover switch 532 is turned on / off in response to a control signal from the control circuit 180. The second changeover switch 532 may be turned on during the second period and turned off during the first period.

[0080] Thus, in the first period, the control circuit 180 turns on the first changeover switch 531 and turns off the second changeover switch 532, discharging from the first switched capacitor circuit 510, thereby receiving the signal A from the first integrator 120. IN2 The output may be delayed. The control circuit 180 turns on the second changeover switch 532 and turns off the first changeover switch 531 during the second period, and discharges from the second switched capacitor circuit 520, thereby delaying the output of the signal A from the first integrator 120 during the second period. IN2 The output may be controlled to be output without delay.

[0081] The fifth amplifier 540 has one input terminal (negative terminal) to which one end of the first changeover switch 531 and the second changeover switch 532 are connected, the other input terminal (positive terminal) to which a reference potential is connected, and the output terminal of the second integrator 130 is connected to its output terminal. The second feedback capacitor 550 is connected between one input terminal (negative terminal) and the output terminal of the fifth amplifier 540. The second feedback capacitor 550 stores the signal input to one input terminal of the fifth amplifier 540. The second reset switch 560 is connected between one input terminal (negative terminal) and the output terminal of the fifth amplifier 540 and is connected in parallel with the second feedback capacitor 550. When the second reset switch 560 is turned on in response to the reset signal, the charge stored in the second feedback capacitor 550 is discharged, and the output of the second integrator 130 (fifth amplifier 540) can be set to 0V.

[0082] The third changeover switch 571 is connected between one input terminal (negative terminal) of the fifth amplifier 540 and the third switched-capacitor circuit 580. The third changeover switch 571 is turned on / off in response to a control signal from the control circuit 180. The fourth changeover switch 572 is connected between the output terminal of the fifth amplifier 540 and the third switched-capacitor circuit 580. The fourth changeover switch 572 is turned on / off in response to a control signal from the control circuit 180.

[0083] The third switched-capacitor circuit 580 is connected between the third changeover switch 571 and the fourth changeover switch 572, and is connected in parallel with the second feedback capacitor 550 when the third changeover switch 571 and the fourth changeover switch 572 are turned on. The third switched-capacitor circuit 580 has a 14th switch 581, a 15th switch 583, a 5th capacitor 582, a 16th switch 584, and a 17th switch 585.

[0084] The 14th switch 581 is connected between one input terminal of the 5th amplifier 540 and the 5th capacitor 582. The 15th switch 583 is connected between the node between the 14th switch 581 and the 5th capacitor 582 and the reference potential. The 5th capacitor 582 is connected between the 14th switch 581 and the 16th switch 584. The 16th switch 584 is connected between the 4th changeover switch 572 and the 5th capacitor 582. The 17th switch 585 is connected between the node between the 16th switch 584 and the 5th capacitor 582 and the reference potential.

[0085] Switch 15 583 and Switch 16 584 may be turned on when the first timing signal is high and turned off when it is low. Switch 14 581 and Switch 17 585 may be turned on when the second timing signal is high and turned off when it is low.

[0086] For example, when the third changeover switch 571 and the fourth changeover switch 572 are ON, during the period φ2 when the second timing signal is high, one end of the fifth capacitor 582 is connected to the input terminal of the fifth amplifier 540 and the other end is connected to the reference potential, thereby charging the signal input to the fifth amplifier 540. Also, during the period φ1 when the first timing signal is high, one end of the fifth capacitor 582 is connected to the reference potential and the other end is connected to the output of the fifth amplifier 540, thereby discharging the charge. The fifth capacitor 582 repeats charging and discharging by repeating periods φ1 and φ2.

[0087] For example, the third changeover switch 571 and the fourth changeover switch 572 are turned off during the first period and on during the second period by a control signal. When the third changeover switch 571 and the fourth changeover switch 572 are turned off, and the third switched-capacitor circuit 580 is disconnected from the feedback circuit of the second integrator 130, the second integrator 130 performs an integrating operation (feedback coefficient 1). When the third changeover switch 571 and the fourth changeover switch 572 are turned on, and the third switched-capacitor circuit 580 is connected to the feedback circuit, the second integrator 130 performs an amplification operation (feedback coefficient > 1).

[0088] In this embodiment, the delta-sigma modulator 10 receives a feedback signal A from the DA converter 170 in the second integrating unit 130. FB Signal A corresponding to this IN2 The signal A can be received via the first integrator 120 and integrated. At this time, the feedback signal A is sent to the second integrator 130 with substantially the same gain and error as when it is input to the first integrator 120. FB Signal A corresponding to this IN2 Since it can input, feedback signal A FB No additional adjustments are required. Furthermore, the delta-sigma modulator 10 of this embodiment is efficient because it can switch the operation of the second integrator 130 using a commonly used reset circuit 190. Accordingly, the delta-sigma modulator 10 can provide feedback to multiple integrators using only one DA converter 170, thereby reducing the circuit area and minimizing signal errors.

[0089] Figure 6 shows an example of a real circuit of the delta-sigma modulator 10 according to this embodiment. The delta-sigma modulator 10 uses the addition / subtraction unit 110 shown in Figure 1, a first integration unit 120, a second integration unit 130, a selection unit 140, a quantizer 150, a DA converter 170, a control circuit 180, and a reset circuit 190. That is, the delta-sigma modulator 10 shown in Figure 6 comprises the addition / subtraction unit 110, a first integration unit 120, a second integration unit 130, a selection unit 140, a quantizer 150, a DA converter 170, a control circuit 180, a reset circuit 190, and a multiplexer 160. In the delta-sigma modulator 10 shown in Figure 6, a configuration similar to that of the delta-sigma modulator 10 in Figure 1 may be used, and it may operate in the same way as the delta-sigma modulator 10 in Figure 1. The differences from the delta-sigma modulator 10 in Figure 1 will be mainly described below.

[0090] The addition / subtraction unit 110 is connected to the input terminal 100, the first integration unit 120, and the DA converter 170. The addition / subtraction unit 110 receives the analog signal Asig input to the input terminal 100 and the feedback signal A output by the DA converter 170. FB Analog signal A obtained by subtracting IN1 This is output to the first integrator 120 and the multiplexer 600.

[0091] The first integrator 120 is connected to the multiplexer 600 and receives analog signal A input to input terminal 100. sig The first integral unit 120 integrates the analog signal A. sig and feedbank signal A FB The difference is analog signal A IN1 Integrate the analog signal A out1 Output this to the Multiplexer 600.

[0092] The multiplexer 600 is connected to the second integration unit 130 and the selection unit 140, and the analog signal A output by the addition / subtraction unit 110 is processed. IN1 and the analog signal A output by the first integrator 120 out1 Select one of the following, and select signal A IN2The output is sent to the second integration unit 130 and the selection unit 140. The multiplexer 600 switches the selection according to the control signal from the control circuit 180.

[0093] The second integration unit 130 is connected to the selection unit 140 and receives signal A output by the multiplexer 600. IN2 The signal is integrated and the analog signal A is sent to the selection unit 140. out2 The output is given by the second integrator 130, which may be an analog integrator.

[0094] The selection unit 140 is connected to the input terminal 100 and the quantizer 150, and receives the analog signal A input to the input terminal 100. sig , Analog signal A output by Multiplexer 600 IN2 , and the analog signal A output by the second integrator 130 out2 Select at least one of the following, and an analog signal A corresponding to the selected signal. sum2 Outputs.

[0095] The control circuit 180 is connected to the multiplexer 600, the second integrator 130, and the selection unit 140, and outputs control signals to switch the operation of the multiplexer 600, the second integrator 130, and the selection unit 140. The control circuit 180 may switch the operation of the multiplexer 600, the second integrator 130, and the selection unit 140 at predetermined timings. The control circuit 180 may output different control signals to the multiplexer 600, the second integrator 130, and the selection unit 140. The control circuit 180 determines that the multiplexer 600 outputs the signal output by the first integrator 120 to the second integrator 130 and the selection unit 140 during the first period, and outputs the analog signal (i.e., the signal A output by the addition / subtraction unit 110) that is input to the first integrator during the second period. IN1 The control circuit 180 controls the output of the feedback signal A output by the DA converter 170 during the first period using a control signal. FB The multiplexer 600 is controlled to output the feedback signal A output by the DA converter during the second period to the second integrator 130 via the first integrator 120, and the feedback signal A output by the DA converter during the second period is controlled. FBThe multiplexer 600 can be controlled to output to the second integral unit 130 without going through the first integral unit 120.

[0096] In this embodiment, the delta-sigma modulator 10 receives a feedback signal A from the DA converter 170 in the second integrating unit 130. FB Signal A corresponding to this IN2 The signal is received directly and an integration operation is performed. The resulting output is A. OUT2 The value shown in equation 12 can also be obtained. In this embodiment, the feedback signal A from the DA converter 170 FB Signal A corresponding to this IN1 When is input to the first integral unit 120, and signal A IN2 This is effective when gain adjustment is unnecessary when the signal is input to the second integrator 130. Furthermore, the delta-sigma modulator 10 of this embodiment does not require a control signal from the control signal to the reset circuit 190, and its logic is simplified. Accordingly, the delta-sigma modulator 10 of this embodiment uses only one DA converter 170 to provide feedback to multiple integrators, which reduces the circuit area and minimizes signal errors.

[0097] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0098] It should be noted that the execution order of operations, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of Symbols]

[0099] 10 Delta-Sigma Modulator 100 input terminals 110 Addition and Subtraction Section 120 First Integral Part 130 Second Integral Section 140 Selection Section 150 Quantizer 170 DA converter 180 Control circuits 190 Reset Circuit 200 First Addition Section 201 First switching section 205 First delay element 210 First Amplifier 215 First Multiplexer 220 Second delay element 225 Second Multiplexer 203 Second switching section 240 Second Addition Section 245 Second Amplifier 250 Fourth Multiplexer 255 Fourth delay element 300 Second switch 310 The third switch 305 First Capacitor 320 The fourth switch 315 The fifth switch 325 The fourth amplifier 330 First feedback capacitor 335 First reset switch 510 First switched-capacitor circuit 511 The sixth switch 513 The 7th Switch 512 Third Capacitor 514 The 8th switch 515 The 9th switch 520 Second Switched Capacitor Circuit 521 The 10th switch 523 The 11th switch 522 The fourth capacitor 524 The 12th switch 525 The 13th switch 531 First changeover switch 532 Second changeover switch 540 Fifth Amplifier 550 Second feedback capacitor 560 Second reset switch 571 Third changeover switch 572 Fourth changeover switch 580 Third Switched Capacitor Circuit 581 The 14th switch 583 The 15th switch 582 The fifth capacitor 584 The 16th switch 585 The 17th switch 600 Multiplexer

Claims

1. A first integrator integrates the second analog signal, which is the difference between the input first analog signal and the feedback signal. A second integrator integrates the signal output by the first integrator, A quantizer that quantizes the signal output by the second integrator, A DA converter that performs DA conversion on the output of the quantizer and outputs the feedback signal to the first integrator, The system includes a control unit that controls the first and second integrating units to perform different integrating operations during a first period and a second period. The control unit controls the first integrator to operate as an integrator with a feedback coefficient of 1 during the first period and as an integrator with a feedback coefficient of 0 during the second period, and controls the second integrator to operate as an integrator with a feedback coefficient of 1 during the first period and as an integrator with a feedback coefficient greater than 1 during the second period. Delta-sigma modulator.

2. The first integrator outputs the second analog signal to the second integrator during the second period with the same gain as when the signal is input to the first integrator. The delta-sigma modulator according to claim 1.

3. The first integral part is, The summing unit to which the second analog signal is input, A first switching unit outputs the signal output by the summing unit with a gain of 1 during the first period, and alternately outputs it with gains of 1 and 0 during the second period. The system includes a feedback path that returns the output of the first switching unit to the input of the adding unit, The first integrator outputs a signal through the feedback path during both the first and second periods. The delta-sigma modulator according to claim 1.

4. The first switching unit includes a first delay element that delays the signal output by the summing unit, an amplifier that outputs the signal output by the summing unit with a gain of 0, and a multiplexer to which the output of the first delay element and the output of the amplifier are input. The delta-sigma modulator according to claim 3.

5. The delta-sigma modulator is an incremental AD converter that resets after each cycle of the AD conversion that converts the input first analog signal into a digital signal. The multiplexer outputs a signal that the amplifier outputs with a gain of 0 during the reset period. The delta-sigma modulator according to claim 4.

6. The second integrator has a second switching unit that outputs the signal from the first integrator with a delay during the first period, and outputs the signal from the first integrator without delay during the second period. The delta-sigma modulator according to claim 1.

7. The second switching unit described above is A first switched capacitor circuit connected to the output of the first integrator, A first changeover switch connected to the first switched-capacitor circuit, A second switched capacitor circuit connected in parallel with the first switched capacitor circuit, The second switching switch is connected to the second switched-capacitor circuit, The control unit controls the output of the signal from the first integrator unit with a delay by turning on the first changeover switch and discharging from the first switched-capacitor circuit during the first period, and by turning on the second changeover switch and discharging from the second switched-capacitor circuit during the second period, thereby outputting the signal from the first integrator unit without delay during the second period. The delta-sigma modulator according to claim 6.

8. A first integrator integrates the second analog signal, which is the difference between the input first analog signal and the feedback signal. A multiplexer that selects and outputs the signal output by the first integrator and the second analog signal, A second integrator that integrates the signal output by the multiplexer, A quantizer that quantizes the signal output by the second integrator, A DA converter that performs DA conversion on the output of the quantizer and outputs the feedback signal, The system includes a control unit that controls the first and second integrating units to perform different integrating operations during a first period and a second period. The control unit controls the second integrator to operate as an integrator with a larger feedback coefficient in the second period than in the first period. The control unit controls the multiplexer to output the signal output by the first integrator to the second integrator during the first period, and controls the multiplexer to output the second analog signal input to the first integrator to the second integrator during the second period. Delta-sigma modulator.

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