Semiconductor structure and method for manufacturing the same, memory and method for operating the same

Abstract

The present invention provides a semiconductor structure and a method for manufacturing the same, a memory and a method for operating the same, the semiconductor structure comprising: a substrate having a plurality of active regions close to a surface of the substrate; a gate structure disposed in a first structural layer above the substrate, the gate structure and the active regions constituting a select transistor; and an anti-fuse bit structure disposed in a second structural layer above the first structural layer and connected to the active region of one of the select transistors via a first connection structure, the breakdown state and the non-breakdown state of the anti-fuse bit structure being used to represent different stored data.

Description

Technical Field

[0001] [Cross-reference to Related Application] The present application is filed based on the Chinese patent application filed with the China National Intellectual Property Administration on June 24, 2022, with the application number 202210728734.6 and the title of the invention "Semiconductor structure and manufacturing method thereof, memory and operating method thereof", claims the priority of the said Chinese patent application, and the entire content of the said Chinese patent application is incorporated into the present application by reference.

[0002] The present invention relates to the technical field of semiconductors, and relates to, but is not limited to, a semiconductor structure and a manufacturing method thereof, and a memory and an operating method thereof.

Background Art

[0003] With the continuous development of current science and technology, the performance of semiconductor memory devices has become increasingly powerful, while the feature size has become increasingly smaller. Here, One Time Programmable (OTP) memory is a type of Non-Volatile Memory (NVM), which can retain stored data even when power is cut off. One time programmable memory can only be programmed once and cannot be electrically erased. It is applicable to program code memory, serial configuration memory, and System-on-Chip (SOC), and can play roles such as ID identification and memory repair.

[0004] Currently, one-time programmable memory (YEM) primarily employs a structure similar to dynamic random access memory (DRAM), comprising one selection transistor and one breakdownable capacitor (1T1C). Since the breakdown of the capacitor's dielectric layer is irreversible, solidified stored data can be obtained by reading the capacitor's breakdown state. However, YEM faces problems such as a large memory cell footprint, low integration density, complex manufacturing processes, and high manufacturing costs. [Overview of the project] [Problems that the invention aims to solve]

[0005] In view of this, embodiments of the present invention provide a semiconductor structure and a method for manufacturing the same, a memory and a method for operating the same. [Means for solving the problem]

[0006] According to a first aspect, an embodiment of the present invention provides a semiconductor structure comprising a substrate, a gate structure, and an antifuse bit structure. The substrate has a plurality of active regions near the surface of the substrate, the gate structure is arranged on a first structural layer on the substrate, the gate structure and active regions constitute a selection transistor, the antifuse bit structure is arranged on a second structural layer on the first structural layer, the antifuse bit structure is connected to the active region of one selection transistor via a first connection structure, and the breakdown state and non-breakdown state of the antifuse bit structure are used to represent different stored data.

[0007] In some embodiments, the antifuse bit structure comprises a first electrode, a second electrode, and an antifuse bit dielectric layer, wherein the first electrode is connected to an active region via a first connection structure, the second electrode is arranged in the same plane as the first electrode, and the plane on which the first and second electrodes are arranged is parallel to the surface of the substrate, and the antifuse bit dielectric layer is arranged between the first electrode and the second electrode and connects the first electrode and the second electrode, where the breakdown state is a state in which the antifuse bit dielectric layer is broken down, and the non-breakdown state is a state in which the antifuse bit dielectric layer is not broken down.

[0008] In some embodiments, the second electrodes of multiple antifuse bit structures, arranged parallel to the extending direction of the gate structure, are connected to one another.

[0009] In some embodiments, a protruding structure is provided on one side of the first electrode closer to the second electrode, and a recessed structure corresponding to the protruding structure is provided on one side of the second electrode closer to the first electrode.

[0010] In some embodiments, the projection of the antifuse bit structure on the substrate overlaps, at least partially, with the projection of the gate structure on the substrate.

[0011] In some embodiments, the first structural layer further includes a first isolation layer surrounding at least the bottom and sides of the gate electrode of the gate structure, the second structural layer further includes a second isolation layer surrounding at least the bottom and sides of the antifuse bit structure, and the first connection structure penetrates the first and second isolation layers.

[0012] In some embodiments, the first isolation layer is an oxide material, where a portion of the first isolation layer within the gate structure is used as the gate dielectric of the selected transistor.

[0013] In some embodiments, the active region includes a first doped region and a second doped region having the same doping type, the first doped region and the second doped region being located on opposite sides of the gate structure, the first doped region being connected to the antifuse bit structure via a first connection structure.

[0014] In some embodiments, the semiconductor structure further comprises a first metallic wire located in a third structural layer above a second structural layer, the first metallic wire being connected to a second doped region via a second connecting structure, and the direction of extension of the first metallic wire being perpendicular to the direction of extension of the gate structure.

[0015] In some embodiments, the third structural layer further includes a third separation layer that surrounds at least the bottom and sides of the first metal wire.

[0016] In some embodiments, two adjacent antifuse bit structures are arranged symmetrically, and the selected transistors connected to each of the two symmetrically arranged antifuse bit structures share the same second doped region.

[0017] In some embodiments, the semiconductor structure further includes a separation structure located between two adjacent first doped regions, where the two adjacent first doped regions are first doped regions corresponding to two adjacent selected transistors that do not share a second doped region.

[0018] According to a second aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor structure, the method comprising providing a substrate having a plurality of active regions near the surface of the substrate, forming a first structural layer on the substrate including a gate structure, wherein the gate structure and the active regions beneath the gate structure constitute a selection transistor, forming a second structural layer on the first structural layer including an antifuse bit structure, and forming a first connecting structure connecting the antifuse bit structure and the active regions of the selection transistor, wherein the breakdown state and non-breakdown state of the antifuse bit structure are used to represent different stored data.

[0019] In some embodiments, forming a second structural layer containing an antifuse bit structure on a first structural layer, and forming a first connection structure connecting the antifuse bit structure and the active region of a selected transistor, involves depositing an insulating material on the first structural layer, wherein the insulating material is used to form a second isolation layer within the second structural layer, forming a first trench and a second trench in the insulating material, forming a first connection hole penetrating the first structural layer within the first trench, filling the first connection hole with a conductive material to form a first connection structure, and filling the first trench and the second trench with a conductive material to form a first electrode and a second electrode, respectively, wherein the insulating material other than the first electrode and the second electrode is the second isolation layer, and a portion of the second isolation layer between the first electrode and the second electrode is used as the antifuse bit dielectric layer of the antifuse bit structure, where the breakdown state is the state in which the antifuse bit dielectric layer is broken down, and the non-breakdown state is the state in which the antifuse bit dielectric layer is not broken down.

[0020] In some embodiments, the extension directions of the first and second trenches are parallel to the extension direction of the gate structure.

[0021] In some embodiments, filling a first trench and a second trench with a conductive material to form a first electrode and a second electrode, respectively, includes filling the first trench and the second trench with a conductive material and removing at least a portion of the conductive material in the first trench to form a plurality of first electrodes separated from each other and a plurality of second electrodes connected to each other in a plurality of antifuse bit structures arranged in the same straight line parallel to the extending direction of the gate structure.

[0022] According to a third aspect, an embodiment of the present invention provides a method for operating a memory, the memory comprising a semiconductor structure as described in any of the above embodiments, the method comprising: breaking down one target antifuse bit structure of the memory's antifuse bit structure to switch the target antifuse bit structure from a non-breakdown state to a breakdown state, and maintaining the non-breakdown state of a non-target antifuse bit structure, wherein the non-target antifuse bit structure is an antifuse bit structure other than the target antifuse bit structure.

[0023] In some embodiments, breaking down one target antifuse bit structure of the memory's antifuse bit structure to switch the target antifuse bit structure from a non-breakdown state to a breakdown state includes applying a first voltage to the gate structure of a selection transistor connected to the target antifuse bit structure to make the selection transistor conduct, applying a second voltage to a first metal wire connected to the selection transistor, and applying a third voltage to the second electrode of the target antifuse bit structure to switch the target antifuse bit structure from a non-breakdown state to a breakdown state, where the voltage difference between the second voltage and the third voltage is greater than or equal to the breakdown voltage of the antifuse bit structure.

[0024] In some embodiments, maintaining a non-breakdown state of a non-target antifuse bit structure includes applying a first voltage to the gate structure of a selection transistor connected to the non-target antifuse bit structure to make the selection transistor conduct, applying a fourth voltage to a first metal wire connected to the selection transistor, and applying a third voltage to the second electrode of the non-target antifuse bit structure to maintain the non-breakdown state of the non-target antifuse bit structure, where the voltage difference between the fourth voltage and the third voltage is smaller than the breakdown voltage of the antifuse bit structure.

[0025] In some embodiments, maintaining a non-breakdown state of a non-target anti-fuse bit structure comprises applying a fifth voltage to a gate structure of a select transistor connected to the non-target anti-fuse bit structure to turn off the select transistor, so as to maintain the non-target anti-fuse bit structure in the non-breakdown state.

[0026] According to a fourth aspect, an embodiment of the present invention provides a memory, the memory comprising a memory array including the semiconductor structure according to any one of the above embodiments, and a peripheral circuit coupled to the memory array. Effects of the Invention

[0027] In the semiconductor structure according to an embodiment of the present invention, the gate structure is arranged on a first structure layer over a substrate, the anti-fuse bit structure is arranged on a second structure layer over the first structure layer, and the anti-fuse bit structure is connected to an active region of the substrate through a first connection structure. In this way, the anti-fuse bit structure does not need to occupy an additional area in the horizontal direction, which improves the integration density of the memory and reduces the number of mask processes required to form the anti-fuse bit structure, thereby simplifying the manufacturing process. Brief Description of the Drawings

[0028] [Figure 1] It is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. [Figure 2] It is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. [Figure 3] It is a schematic diagram of another semiconductor structure according to an embodiment of the present invention. [Figure 4] It is a schematic diagram of still another semiconductor structure according to an embodiment of the present invention. [Figure 5] It is a top view of still another semiconductor structure according to an embodiment of the present invention. [Figure 6] It is a schematic diagram of still another semiconductor structure according to an embodiment of the present invention. [Figure 7]This is a flowchart of the process for forming a semiconductor structure according to an embodiment of the present invention. [Figure 8A] This is a schematic diagram showing a process for forming a semiconductor structure according to an embodiment of the present invention. [Figure 8B] This is a schematic diagram showing a process for forming a semiconductor structure according to an embodiment of the present invention. [Figure 8C] This is a schematic diagram showing a process for forming a semiconductor structure according to an embodiment of the present invention. [Figure 9A] This is a schematic diagram showing a process for forming an anti-fuse bit structure according to an embodiment of the present invention. [Figure 9B] This is a schematic diagram showing a process for forming an anti-fuse bit structure according to an embodiment of the present invention. [Figure 9C] This is a schematic diagram showing a process for forming an anti-fuse bit structure according to an embodiment of the present invention. [Figure 10A] This is a top view showing a process for forming an antifuse bit structure according to an embodiment of the present invention. [Figure 10B] This is a top view showing a process for forming an antifuse bit structure according to an embodiment of the present invention. [Figure 10C] This is a top view showing a process for forming an antifuse bit structure according to an embodiment of the present invention. [Figure 10D] This is a top view showing a process for forming an antifuse bit structure according to an embodiment of the present invention. [Figure 11] This is a schematic diagram of a memory according to an embodiment of the present invention. [Figure 12] This is a schematic diagram of a memory array in a memory according to an embodiment of the present invention. [Modes for carrying out the invention]

[0029] To facilitate understanding of the present invention, exemplary embodiments of the invention will be described more comprehensively below with reference to the relevant drawings. While the drawings illustrate exemplary embodiments of the invention, it should be understood that the invention can be realized in various forms and is not limited to the specific embodiments shown herein. Rather, these embodiments are provided to give a more complete understanding of the invention and to fully convey its scope to those skilled in the art.

[0030] The following description provides numerous specific details to help fully understand the present invention. However, as will be obvious to those skilled in the art, the invention can be implemented without one or more of these details. In some embodiments, some technical features well known in the art are not described in order to avoid confusion with the present invention. That is, not all features of the actual embodiments are described herein, and well known functions and structures are not described in detail.

[0031] Generally, terms can be understood at least partially from their use in context. For example, at least partially depending on the context, the term “one or more” as used herein may be used to describe any feature, structure or characteristic in the singular, or to describe a combination of features, structures or characteristics in the plural. Similarly, terms such as “one” or “the said” can be understood, at least partially depending on the context, as conveying singular or plural use. Furthermore, the term “based on…” is not necessarily intended to refer to a set of exclusive factors, but rather may instead indicate the presence of additional factors that are not necessarily explicitly described, and this too is at least partially context-dependent.

[0032] Unless otherwise defined, the terms used herein are intended solely to describe specific embodiments and do not limit the invention. Where used herein, unless otherwise defined in context, the singular forms “1,” “one,” and “ / the said” are intended to include the plural forms as well. Furthermore, where used herein, the terms “components” and / or “including” mean that the described features, integers, steps, operations, elements, and / or parts exist, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or combinations. Where used herein, the terms “and / or” include any of the associated items and all combinations thereof.

[0033] To ensure a thorough understanding of the present invention, the technical solutions of the present invention will be explained below with detailed steps and detailed structures as examples. Preferred embodiments of the present invention will be described in detail below, but the present invention may have other embodiments in addition to those described in detail.

[0034] In some embodiments, semiconductor structures 10a and 10b having an anti-fuse bit structure are provided, as shown in Figures 1 and 2. Semiconductor structures 10a and 10b are used in one-time programmable memory. Here, semiconductor structure 10a is: The device comprises a base 100, an insulating layer 101 on the base 100, a P-type semiconductor layer 102 on the insulating layer 101, a first doped region 103, a second doped region 104 and a third doped region 105, all located on the P-type semiconductor layer 102, a first gate dielectric 111, a first gate 121, a second gate dielectric 112, and a second gate 122, wherein the first doped region 103, the second doped region 104 and the third doped region 105 may be N-type doped regions, the first doped region 103 is connected to a first metal wire 130, and the first metal wire 130 may be a bit line (BL). The first gate dielectric 111 is placed on the P-type semiconductor layer 102 between the first doped region 103 and the second doped region 104, and the first gate 121 is placed on the first gate dielectric 111, and the first gate 121 may be a word line (WL). The second gate dielectric 112 is placed on the P-type semiconductor layer 102 between the second doped region 104 and the third doped region 105, and the second gate dielectric 112 may also be an antifuse bit dielectric layer, and the breakdown state and non-breakdown state of the second gate dielectric 112 can be used to represent different stored data, i.e., "0" or "1", and the second gate 122 is placed on the second gate dielectric 112.

[0035] It should be noted that, in order to clearly show each structure in the diagram, the proportional relationships of the dimensions of each structure in the diagram may not match the actual structure. Thus, the first doped region 103, the second doped region 104, the first gate dielectric 111, and the first gate 121 constitute a selection transistor, and the second doped region 104, the third doped region 105, the second gate dielectric 112, and the second gate 122 constitute an antifuse bit structure, and one selection transistor and one antifuse bit structure constitute a memory cell.

[0036] In some embodiments, as shown in Figure 2, the thickness of the P-type semiconductor layer 102 in the semiconductor structure 10b may be greater than the depth of each doped region, and the semiconductor structure 10b further comprises a deep N-well (DNW) 106 and a P-type base 107 disposed below the deep N-well 106. In this way, by forming a reverse-biased PN junction between the P-type semiconductor layer 102 and the deep N-well 106, and between the deep N-well 106 and the P-type base 107, the insulating layer 101 in the semiconductor structure 10a is replaced, and an electrical isolation effect is achieved.

[0037] Therefore, the first gate 121 can control the conduction and disconnection of the selection transistor. When the selection transistor conducts, the voltage applied to the first metal wire 130 can be transmitted to the second doped region 104 through the channel of the selection transistor. At this time, the voltage difference between the second gate 122 and the second doped region 104 can be made greater than or equal to the breakdown voltage of the second gate dielectric 112, thereby permanently breaking down the second gate dielectric 112 and completing the write operation to the memory cell. As can be understood, the third doped region 105 is floating during the write operation.

[0038] In some embodiments, the first doped region 103, the second doped region 104, and the third doped region 105 may be highly concentrated N-type doped regions, i.e., N+-type doped regions, and the first gate dielectric 111 and the second gate dielectric 112 may be relatively thin oxide layers. This reduces the occupied area of ​​the memory cell and makes the second gate dielectric 112 more susceptible to breakdown, thereby satisfying the requirement for low power consumption of the memory.

[0039] To make it easier to understand, in semiconductor structures 10a and 10b, the selection transistor and antifuse bit structure are located adjacent to each other in the horizontal direction, thus occupying more area horizontally, and the memory cell size is also relatively large, resulting in a lower memory integration density.

[0040] As shown in Figure 3, an embodiment of the present invention provides a semiconductor structure 20 comprising a substrate 200, a gate structure 211, and an antifuse bit structure 250, wherein the substrate 200 has a plurality of active regions 201 near the surface of the substrate 200, the gate structure 211 is arranged on a first structural layer 210 on the substrate 200, the gate structure 211 and the active regions 201 constitute a selection transistor 240, the antifuse bit structure 250 is arranged on a second structural layer 220 on the first structural layer 210, and the antifuse bit structure 250 is connected to the active region 201 of one selection transistor 240 via a first connection structure 221, and the breakdown state and non-breakdown state of the antifuse bit structure 250 are used to represent different stored data.

[0041] In embodiments of the present invention, the material of the substrate 200 may include elemental semiconductor materials such as silicon (Si) and germanium (Ge), or compound semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP). In some embodiments, the substrate 200 may have well regions such as P wells and deep N wells located below the P wells, where the P wells can be used to form active regions 201 of the selected transistors 240, and the deep N wells can be used to isolate the P wells and reduce noise interference to the devices formed in the P wells. The active regions 201 may also be doped regions of the substrate 200, and the doping type of multiple active regions 201 may be the same, where the impurity ions doped by the P-type doped regions may be trivalent elements such as boron, and the impurity ions doped in the N-type doped regions may be pentavalent elements such as phosphorus and arsenic. For example, the active region 201 may be an N+-doped region within a P-well, and is used to constitute the source and drain electrodes of the selected transistor 240.

[0042] In an embodiment of the present invention, a first structural layer 210 is provided on a substrate 200, the first structural layer 210 includes a gate structure 211, and the gate structure 211 and the active region 201 beneath the gate structure 211 constitute a select transistor 240. The gate structure 211 may further include a gate electrode 2111 and a gate dielectric 2112, where the gate electrode 2111 may be a word line in memory, the material of the gate electrode 2111 may include a conductive material such as a metal or a doped semiconductor, the gate dielectric 2112 may be located on the side of the first structural layer 210 closer to the substrate 200, and the gate dielectric 2112 may be made of a material such as silicon oxide or hafnium oxide. As can be understood, the first structural layer 210 may also include other structures not shown in Figure 3.

[0043] In embodiments of the present invention, a second structural layer 220 is provided on a first structural layer 210, and the second structural layer 220 includes an antifuse bit structure 250, which may be a breakdownable capacitor structure. The antifuse bit structure 250 is connected to the active region 201 of at least one select transistor 240 via a first connection structure 221, where the first connection structure 221 penetrates the first structural layer 210, and the material of the first connection structure 221 may include a conductive material such as a metal or a doped semiconductor. In some embodiments, the antifuse bit structure 250 may include two electrodes arranged in the same plane and an antifuse bit dielectric layer disposed between the two electrodes. Exemplarily, the two electrodes may be made of a conductive material, and the antifuse bit dielectric layer may be made of a material such as silicon oxide. The breakdown state and non-breakdown state of the antifuse bit structure 250 can be used to represent different stored data, i.e., "0" or "1". To make it clear, the second structural layer 220 may also include other structures not shown in Figure 3.

[0044] In some embodiments, one selection transistor 240 and one antifuse bit structure 250 constitute one memory cell of the OTP memory, where a gate structure 211 connects multiple memory cells arranged in its extending direction. Conduction and interruption of the selection transistor 240 can be controlled by applying different voltages to the gate structure 211. In some embodiments, one end of the selection transistor 240 is further connected to a bit line, and when the selection transistor 240 conducts, a voltage on the bit line can be applied to one electrode of the antifuse bit structure 250. At this time, by applying an appropriate voltage to the other electrode, the voltage difference between the two electrodes of the antifuse bit structure 250 can be made greater than or equal to the breakdown voltage of the antifuse bit dielectric layer, thereby permanently breaking down the antifuse bit structure 250 and completing the one-time program operation on the memory cell.

[0045] Since the antifuse bit structure 250 is located on the second structural layer 220 above the first structural layer 210, that is, since the antifuse bit structure 250 is located above the selection transistor 240, the antifuse bit structure 250 does not need to occupy additional area horizontally, thus reducing the size of the memory cell and improving the integration density of the memory. Furthermore, the two electrodes of the antifuse bit structure 250 can be formed simultaneously on the second structural layer 220, reducing the number of masking steps required and thereby simplifying the manufacturing process. On the other hand, since the gate structure 211 is located on the first structural layer 210, the gate dielectric 2112 within the gate structure 211 can be made thicker, thereby making the programming voltage of the selection transistor 240 more stable and making the gate dielectric 2112 less likely to break down accidentally, thus improving the reliability of the memory.

[0046] In some embodiments, as shown in Figure 4, the antifuse bit structure 250 comprises a first electrode 251, a second electrode 252, and an antifuse bit dielectric layer 253, wherein the first electrode 251 is connected to an active region 201 via a first connection structure 221, the second electrode 252 is arranged in the same plane as the first electrode 251, the plane on which the first electrode 251 and the second electrode 252 are arranged is parallel to the surface of the substrate 200, and the antifuse bit dielectric layer 253 is arranged between the first electrode 251 and the second electrode 252 and connects the first electrode 251 and the second electrode 252, where the breakdown state is a state in which the antifuse bit dielectric layer 253 is broken down, and the non-breakdown state is a state in which the antifuse bit dielectric layer 253 is not broken down.

[0047] In an embodiment of the present invention, the antifuse bit structure 250 includes a first electrode 251, a second electrode 252, and an antifuse bit dielectric layer 253. The first electrode 251 and the second electrode 252 are arranged in the same plane in the second structural layer 220, and the plane in which the first electrode 251 and the second electrode 252 are arranged is parallel to the surface of the substrate 200. The antifuse bit dielectric layer 253 is arranged between the first electrode 251 and the second electrode 252, and by connecting the first electrode 251 and the second electrode 252, it forms a breakdownable capacitor structure. Here, the first electrode 251 is connected to an active region 201 located on the same selection transistor 240 via a first connection structure 221 that penetrates the first structural layer 210. In this way, if the voltage difference between the first electrode 251 and the second electrode 252 is greater than or equal to the breakdown voltage of the antifuse bit dielectric layer 253, the antifuse bit dielectric layer 253 is broken down, that is, the antifuse bit structure 250 is permanently broken down, thereby completing the one-time program operation for the memory cell.

[0048] In some embodiments, the first electrode 251 and the second electrode 252 may be made of a conductive material, and exemplary, the material of the first electrode 251 and the second electrode 252 may be tungsten (W), and the antifuse bit dielectric layer 253 may be made of a material such as silicon oxide. As can be understood, the first electrode 251 and the second electrode 252 can be formed simultaneously. Exemplarily, the trenches corresponding to the first electrode 251 and the second electrode 252 are formed in the same plane by only one masking step, and then the trenches are filled with a conductive material to form the first electrode 251 and the second electrode 252, thereby simplifying the manufacturing process.

[0049] In some embodiments, the projection of the antifuse bit structure 250 on the substrate 200 overlaps, at least partially, with the projection of the gate structure 211 on the substrate 200.

[0050] In an embodiment of the present invention, as shown in Figure 4, the projection of the antifuse bit structure 250 on the substrate 200 at least partially overlaps with the projection of the gate structure 211 on the substrate 200, i.e., the antifuse bit structure 250 is at least partially positioned above the gate structure 211, thus further reducing the area occupied horizontally by the antifuse bit structure 250 and the selection transistor 240, thereby improving the integration density of the semiconductor structure. Exemplarily, the second electrode 252 of the antifuse bit structure 250 is positioned above the gate structure 211 to reduce the horizontal area occupied, and at least a portion of the first electrode 251 is positioned offset from the gate structure 211, so that the first connection structure 221 can connect the first electrode 251 perpendicularly to the active region 201 below the first electrode 251, thereby simplifying the arrangement and manufacturing process of the first connection structure 221.

[0051] In some embodiments, Figure 5 shows a top view of a semiconductor structure 20, where the second electrodes 252 of a plurality of antifuse bit structures 250, arranged parallel to the extending direction of the gate structure 311, are connected to one another.

[0052] In an embodiment of the present invention, the gate electrode 2111 of the gate structure 211 may be a word line in the memory, and the gate structure 211 is connected to selection transistors 240 in a plurality of memory cells arranged in its extending direction. As shown in Figure 5, the second electrodes 252 of the antifuse bit structure 250 of the plurality of memory cells arranged parallel to the extending direction of the gate structure 211 are connected to each other. In this way, the conduction or interruption of the selection transistors 240 in the plurality of memory cells arranged in the extending direction of the gate structure 211 can be controlled via the gate structure 211, and at this time, by applying an appropriate voltage to the second electrodes 252, a voltage can be applied simultaneously to at least some of the second electrodes 252 in the antifuse bit structure 250 in the plurality of memory cells, thereby simplifying the operation of the memory. It should be noted that the first electrodes 251 of the antifuse bit structure 250 of the plurality of memory cells arranged parallel to the extending direction of the gate structure 211 are separated from each other.

[0053] In some embodiments, as shown in Figure 5, a protruding structure 254 is provided on one side of the first electrode 251 that is closer to the second electrode 252, and a recessed structure 255 corresponding to the protruding structure 254 is provided on one side of the second electrode 252 that is closer to the first electrode 251.

[0054] In embodiments of the present invention, the first electrode 251 and the second electrode 252 do not have to be simple rectangular structures, but can be arranged in a nested structure with respect to each other, for example, a recessed structure 255 partially encloses a protruding structure 254. In this way, the protruding structure 254 as a tip structure can enhance the surrounding electric field, thereby making it easier for the adjacent antifuse bit dielectric layer 253 to break down, thereby meeting the requirement of low power consumption for the semiconductor device. Furthermore, the protruding structure 254 and the recessed structure 255 increase the surface area of ​​the first electrode 251 and the second electrode 252, thereby making the breakdown and non-breakdown states of the antifuse bit structure 250 more stable and improving the reliability of the reading. As can be understood, the protruding structure 254 and the recessed structure 255 may also have shapes other than those shown in Figure 5, for example, the first electrode 251 may have multiple protruding structures 254, and the second electrode may have multiple recessed structures 252, which are nested with each other. The protruding structure 254 may also have a pointed shape, such as a triangular or zigzag shape.

[0055] In some embodiments, as shown in Figure 6, the first structural layer 210 further includes a first isolation layer 212 surrounding at least the bottom and sides of the gate electrode 2111 of the gate structure 211, the second structural layer 220 further includes a second isolation layer 222 surrounding at least the bottom and sides of the antifuse bit structure 250, and the first connection structure 221 penetrates the first isolation layer 212 and the second isolation layer 222.

[0056] In embodiments of the present invention, the first structural layer 210 further includes a first isolation layer 212 which can surround the bottom and sides of the gate electrode 2111, and the second structural layer 220 further includes a second isolation layer 222 which can surround the bottom and sides of the antifuse bit structure 250. Here, the first isolation layer 212 can be used to separate the gate electrode 2111 of the first structural layer 210 from the active region 201 of the substrate 200, and the second isolation layer 222 can be used to separate the antifuse bit structure 250 of the second structural layer 220 from the gate electrode 2111 of the first structural layer 210. The materials of the first isolation layer 212 and the second isolation layer 222 include, but are not limited to, silicon oxide (SiO2), spin-on dielectrics (SOD), silicon nitride (Si3N4), silicon oxynitride (SiON), etc. To make it clear, the material and thickness of the first isolation layer 212 and the second isolation layer 222 can be adjusted according to the memory performance requirements. In some embodiments, the portion of the first structural layer 210 other than the gate electrode 2111 is the first isolation layer 212, and a portion of the first isolation layer 212 located beneath the gate electrode 2111 can be used as the gate dielectric 2112. In some embodiments, the portion of the second structural layer 220 other than the first electrode 251 and the second electrode 252 is the second isolation layer 222, and a portion of the second isolation layer 222 located between the first electrode 251 and the second electrode 252 can be used as the antifuse bit dielectric layer 253. In this way, the manufacturing process can be simplified and manufacturing costs can be reduced.

[0057] In some embodiments, as shown in Figure 6, the first isolation layer 212 is an oxide material, where a portion of the first isolation layer 212 within the gate structure 211 is used as the gate dielectric 2112 of the selected transistor 240.

[0058] In embodiments of the present invention, the first isolation layer 212 is an oxide material such as silicon oxide. Here, a portion of the first isolation layer 212 placed on the gate structure 211 can be used as the gate dielectric 2112 of the selection transistor 240, thus simplifying the manufacturing process and reducing manufacturing costs. As can be understood, since the first isolation layer 212 can be placed on the first structural layer 210 and formed before the antifuse bit structure 250 is formed, a relatively thick oxide layer can be formed and used as the first isolation layer 212. Thus, because the gate dielectric 2112 of the selection transistor 240 is relatively thick, the program voltage of the selection transistor 240 becomes more stable, the gate dielectric 2112 is less likely to break down unintentionally, and the reliability of the semiconductor device is improved.

[0059] In some embodiments, as shown in Figure 6, the active region 201 includes a first doped region 202 and a second doped region 203 having the same doping type, the first doped region 202 and the second doped region 203 being located on opposite sides of the gate structure 211, where the first doped region 202 is connected to the antifuse bit structure 250 via a first connection structure 221.

[0060] In embodiments of the present invention, the active region 201 may include a first doped region 202 and a second doped region 203, respectively, located on either side of the gate structure 211. The doping type of the first doped region 202 and the second doped region 203 are the same and can be used as the source and drain electrodes of the selection transistor 240, and the gate structure 211 is used to control the conduction or interruption of the channel between the first doped region 202 and the second doped region 203. Exemplarily, the substrate 200 is provided with P-wells, and the first doped region 202 and the second doped region 203 are formed within the P-wells, and the first doped region 202 and the second doped region 203 are N-type doped regions or N+-type doped regions, i.e., the selection transistor 240 is an NMOS transistor, which has the advantages of low conduction resistance and ease of manufacture.

[0061] In some embodiments, the semiconductor structure 20 further comprises a first metal wire 231 located in a third structural layer 230 above a second structural layer 220, the first metal wire 231 being connected to a second doped region 203 via a second connecting structure 232, and the direction of extension of the first metal wire 231 being perpendicular to the direction of extension of the gate structure 211.

[0062] In an embodiment of the present invention, as shown in Figure 6, the semiconductor structure 20 further comprises a third structural layer 230 disposed on a second structural layer 220, the third structural layer 230 having a first metal wire 231, where the first metal wire 231 may be a bit line of the memory. When the selection transistor 240 is activated, the voltage of the first metal wire 231 can be applied to the first electrode 251 of the antifuse bit structure 250 via the selection transistor 240. At this time, by applying an appropriate voltage to the second electrode 252, the voltage difference between the first electrode 251 and the second electrode 252 can be made greater than or equal to the breakdown voltage of the antifuse bit dielectric layer 253, thereby permanently breaking down the antifuse bit structure 250, and thereby completing a one-time program operation for the memory cell. The extending direction of the first metal wire 231 may be perpendicular to the extending direction of the gate structure 211, that is, the extending directions of the bit lines and word lines in the memory are perpendicular to each other, thereby allowing memory cells to be placed at the intersection of the bit line and word line extending directions to form a memory cell array. In other embodiments, the extending direction of the first metal wire 231 intersects with, but is not perpendicular to, the extending direction of the gate structure 211. As can be understood, the third structural layer 230 may also include other structures not shown in Figure 6. The first metal wire 231 is connected to the second doped region 203 via a second connection structure 232, where the second connection structure 232 may be a conductive material such as a metal or a doped semiconductor, and exemplary, the material of the second connection structure 232 is tungsten.

[0063] In some embodiments, the third structural layer 230 further includes a third separation layer 233 that surrounds at least the bottom and sides of the first metal wire 231.

[0064] In an embodiment of the present invention, as shown in Figure 6, the third structural layer 230 further includes a third isolation layer 233, which can surround the bottom and sides of the first metal wire 231. The third isolation layer 233 is used to separate the first metal wire 231 of the third structural layer 230 from the antifuse bit structure 250 of the second structural layer 220. The material of the third isolation layer 233 includes, but is not limited to, silicon oxide, spin-on insulating dielectric, silicon nitride, silicon oxynitride, etc. The second connection structure 232 penetrates the first isolation layer 212, the second isolation layer 222, and the third isolation layer 233. The material and thickness of the third isolation layer 233 can be adjusted according to the memory performance requirements.

[0065] In some embodiments, two adjacent antifuse bit structures 250 are arranged symmetrically, and the selection transistors 240 connected to the two symmetrically arranged antifuse bit structures 250 share the same second doped region 203.

[0066] In an embodiment of the present invention, as shown in Figure 6, two adjacent antifuse bit structures 250 are provided symmetrically, and the selection transistors 240 connected to the two symmetrically provided antifuse bit structures 250 share the same second dope region 203. In this way, in a one-time programmable memory, two adjacent memory cells are provided symmetrically and share one second dope region 203, thereby reducing the area occupied by each memory cell. Furthermore, one bit line (first metal wire 231) is connected to two adjacent memory cells via one second connection structure 232, thereby enabling simultaneous read and write operations of the two memory cells and improving the operational efficiency of the memory.

[0067] In some embodiments, the semiconductor structure 20 further comprises a separation structure 204 located between two adjacent first doped regions 202, where the two adjacent first doped regions 202 are first doped regions 202 corresponding to two adjacent selected transistors 240 that do not share a second doped region 203.

[0068] In an embodiment of the present invention, as shown in Figure 6, the first doped regions 202 corresponding to two adjacent selection transistors 240 that do not share the second doped region 203 are close to each other. Therefore, by placing an isolation structure 204 between the two adjacent first doped regions 202, the two adjacent selection transistors 240 that do not share the second doped region 203 can be isolated, thereby preventing the occurrence of leakage current phenomena. Here, the depth of the isolation structure 204 is greater than the doping depth of the first doped region 202. Exemplarily, the isolation structure 204 may be a shallow trench isolation (STI), which has advantages such as low cost and good isolation effect, and the material of the isolation structure 204 includes, but is not limited to, silicon oxide.

[0069] As shown in Figures 7 and 8A to 8C, embodiments of the present invention further provide a method for manufacturing a semiconductor structure 30, the corresponding structure being as shown in Figures 8A to 8C, and the manufacturing method comprising the following steps.

[0070] In step S10, a substrate 300 is provided, and the substrate 300 has a plurality of active regions 301 close to the surface of the substrate 300. In step S20, a first structural layer 310 including a gate structure 311 is formed on the substrate 300, and the gate structure 311 and the active regions 301 below the gate structure 311 constitute a selection transistor 340. In step S30, a second structural layer 320 including an antifuse bit structure 350 is formed on the first structural layer 310, and a first connecting structure 321 is formed connecting the antifuse bit structure 350 and the active regions 301 of the selection transistor 340, and the breakdown state and non-breakdown state of the antifuse bit structure 350 are used to represent different stored data.

[0071] As shown in Figure 8A, a substrate 300 is provided, and the material of the substrate 300 may include elemental semiconductor materials such as silicon and germanium, or compound semiconductor materials such as gallium nitride, gallium arsenide, or indium phosphide. In some embodiments, the substrate 300 may be provided with well regions such as P wells and deep N wells located below the P wells, where the P wells may be used to form the active region 301 of the selection transistor 340, and the deep N wells may be used to isolate the P wells and reduce noise interference to the devices formed in the P wells. The active region 301 may also be a doped region within the substrate 300, and the doping type of multiple active regions 301 may be the same. Exemplarily, the active region 301 may be an N+ type doped region within a P well, and is used to form the source and drain electrodes of the selection transistor 340.

[0072] As shown in Figure 8B, a first structural layer 310 including a gate structure 311 can be formed on a substrate 300 by processes such as deposition, photolithography, and etching, where the gate structure 311 and the active region 301 beneath it constitute a select transistor 340. The formed gate structure 311 may include a gate electrode 3111 and a gate dielectric 3112, where the gate electrode 3111 may be a word line in the memory. Exemplarily, an insulating material is deposited on the substrate 300 by a deposition process, where the insulating material may be a material such as silicon oxide, then a trench corresponding to the gate electrode 3111 is formed in the insulating material by photolithography and etching processes, and then a conductive material is filled into the trench by a deposition process to form the gate electrode 3111, where a portion of the insulating material beneath the gate electrode 3111 is the gate dielectric 3112 of the gate structure 311. To ensure clarity, the first structural layer 310 may also form other structures not shown in Figure 8B. The deposition process here includes, but is not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). The etching process includes, but is not limited to, dry etching and wet etching. Here, dry etching may include ion beam milling etching, plasma etching, reactive ion etching, or laser ablation, while wet etching is etching using a solvent or solution such as an acid-base solution.

[0073] As shown in Figure 8C, a second structural layer 320 containing an antifuse bit structure 350 can be formed on the first structural layer 310 by processes such as deposition, photolithography, and etching, and a first connecting structure 321 can be formed that connects the antifuse bit structure 350 to the active region 301 of the selected transistor 340. The formed antifuse bit structure 350 may be a breakdownable capacitor structure and includes two electrodes arranged in the same plane and an antifuse bit dielectric layer between the two electrodes. Exemplary, an insulating material is deposited on a first structural layer 310 by a deposition process, the insulating material may be a material such as silicon oxide, and then, by photolithography and etching processes, trenches corresponding to the two electrodes of the antifuse bit structure 350 and a first connection hole penetrating the first structural layer 310 and connected to the active region 301 are formed in the insulating material, and then, by a deposition process, conductive material is filled into the trenches and the first connection hole to form the two electrodes of the antifuse bit structure 350 and the first connection structure 321, where a portion of the insulating material between the two electrodes is the antifuse bit dielectric layer. In some embodiments, a second structural layer 320 having the antifuse bit structure 350 can also be formed by self-aligned double patterning (SADP), which can reduce the number of exposures and improve manufacturing efficiency and productivity. The breakdown and non-breakdown states of the antifuse bit structure 350 can be used to represent different stored data, namely "0" or "1". To understand this, the second structural layer 320 can also form other structures not shown in Figure 8C.

[0074] The antifuse bit structure 350 is formed on the second structural layer 320 above the first structural layer 310, that is, the antifuse bit structure 350 is formed on the selection transistor 340. Therefore, the antifuse bit structure 350 does not need to occupy additional area horizontally, thus reducing the size of the memory cell and improving the integration density of the memory. Furthermore, the two electrodes of the antifuse bit structure 350 can be formed simultaneously on the second structural layer 320, meaning that the number of masking processes required is reduced, thus simplifying the manufacturing process. On the other hand, since the gate structure 311 is placed on the first structural layer 310, the gate dielectric 3112 within the gate structure 311 can be made thicker by controlling the etching depth. This makes the program voltage of the selection transistor 340 more stable and makes the gate dielectric 3112 less likely to break down accidentally, thereby improving the reliability of the memory.

[0075] In some embodiments, as shown in Figures 9A to 9C, forming a second structural layer 320 including an antifuse bit structure 350 on a first structural layer 310, and forming a first connection structure 321 connecting the antifuse bit structure 350 and the active region 301 of the selection transistor 340, involves depositing an insulating material on the first structural layer 310, wherein the insulating material is used to form a second separation layer 322 of the second structural layer 320, forming a first trench 3202 and a second trench 3203 in the insulating material, forming a first connection hole 3204 penetrating the first structural layer 310 within the first trench 3202, and filling the first connection hole 3204 with a conductive material. The method includes forming a first connection structure 321 and filling a first trench 3202 and a second trench 3203 with conductive material to form a first electrode 351 and a second electrode 352, respectively. The insulating material other than the first electrode 351 and the second electrode 352 is a second separation layer 322, and a portion of the second separation layer 322 between the first electrode 351 and the second electrode 352 is used as the antifuse bit dielectric layer 353 of the antifuse bit structure 350. Here, the breakdown state is the state in which the antifuse bit dielectric layer 353 has broken down, and the non-breakdown state is the state in which the antifuse bit dielectric layer 353 has not broken down.

[0076] As shown in Figure 9A, an insulating material can be deposited on the first structural layer 310 on which the gate structure 311 is formed by a process such as CVD. Exemplary examples of insulating materials here may be silicon oxide, spin-on insulating dielectric, silicon nitride, silicon oxynitride, etc. The insulating material on the first structural layer 310 can be used to form a second isolation layer 322 in the second structural layer 320, where the second isolation layer 322 can be used to separate the antifuse bit structure 350 in the second structural layer 320 from the gate electrode 3111 in the first structural layer 310.

[0077] As shown in Figure 9B, a first trench 3202 and a second trench 3203 can be formed in the insulating material by photolithography and etching processes, and a first connection hole 3204 penetrating the first structural layer 310 can be formed in the first trench 3202. Here, the first trench 3202 and the second trench 3203 are used to form the first electrode 351 and the second electrode 352, respectively, and the first connection hole 3204 is used to form the first connection structure 321. Exemplarily, a mask corresponding to the first trench 3202 and the second trench 3203 can be formed on the surface of the insulating material by only one masking process, and then the first trench 3202 and the second trench 3203 can be formed simultaneously by etching, and a first connection hole 3204 penetrating the first structural layer 310 and connected to the active region 301 can be formed in the first trench 3202. The depths of the first trench 3202 and the second trench 3203 may be the same, and both depths may be less than the thickness of the deposited insulating material.

[0078] As shown in Figure 9C, the deposition process allows for the formation of a first connection structure 321 by filling the first connection hole 3204 with conductive material, and the formation of a first electrode 351 and a second electrode 352 by filling the first trench 3202 and the second trench 3203 with conductive material. The conductive material here may be a metal or a material such as a doped semiconductor. As can be understood, the insulating material remaining after the formation of the first electrode 351 and the second electrode 352 is the second isolation layer 322, and a portion of the second isolation layer 322 placed between the first electrode 351 and the second electrode 352 can be used as an antifuse bit dielectric layer 353.

[0079] Thus, when the voltage difference between the first electrode 351 and the second electrode 352 is greater than or equal to the breakdown voltage of the antifuse bit dielectric layer 353, the antifuse bit dielectric layer 353 is broken down, that is, the antifuse bit structure 350 is permanently broken down, thereby completing the one-time program operation for the memory cell.

[0080] In some embodiments, the first electrode 351 and the second electrode 352 are formed simultaneously by the SADP process, thereby reducing the number of masking steps required, which simplifies the manufacturing process and reduces manufacturing costs.

[0081] Figures 10A to 10D are top views of the semiconductor structure 30 during the manufacturing process. In some embodiments, the extension directions of the first trench 3202 and the second trench 3203 are parallel to the extension direction of the gate structure 311.

[0082] In an embodiment of the present invention, as shown in Figure 10A, the gate electrode in the gate structure 311 may be the word line of the memory, that is, the extending directions of the first trench 3202 and the second trench 3203 are parallel to the extending direction of the word line. By forming a second electrode using the second trench 3203, the second electrodes in a plurality of antifuse bit structures arranged parallel to the extending direction of the gate structure 311 are connected to each other. In this way, the conduction or interruption of the selection transistors of a plurality of memory cells arranged in the extending direction can be controlled via the gate structure 311, and in this case, by applying an appropriate voltage to the second electrode, a voltage can be applied simultaneously to the second electrode of at least some of the antifuse bit structures of the plurality of memory cells, thereby simplifying the operation of the memory. It should be noted that the plurality of first electrodes formed in the first trench 3202 are separated from each other.

[0083] In some embodiments, the first trench 3202 and the second trench 3203 can be formed by self-aligned double patterning, and the first trench 3202 and the second trench 3203 can be filled with conductive material, and then a plurality of first electrodes separated from each other can be formed in the first trench 3202 by subsequent masking and etching processes.

[0084] In some embodiments, as shown in Figure 10B, a first electrode having a protruding structure 354 and a second electrode having a recessed structure 355 can be formed by self-aligned double patterning, where the recessed structure 355 partially surrounds the protruding structure 354. In this way, the protruding structure 354 as a tip structure can enhance the surrounding electric field, thereby making the adjacent antifuse bit dielectric layer 353 more easily broken down, thereby meeting the requirement of low power consumption for the semiconductor device. Furthermore, the protruding structure 354 and the recessed structure 355 increase the surface area of ​​the first and second electrodes, thereby making the breakdown and non-breakdown states of the antifuse bit structure more stable and improving the reliability of the reading.

[0085] In some embodiments, as shown in Figures 10B to 10D, filling the first trench 3202 and the second trench 3203 with conductive material to form the first electrode 351 and the second electrode 352, respectively, includes filling the first trench 3202 and the second trench 3203 with conductive material and removing at least a portion of the conductive material in the first trench 3202 to form a plurality of first electrodes 351 that are separated from each other and a plurality of second electrodes 352 that are connected to each other in a plurality of antifuse bit structures 350 that are arranged in the same straight line parallel to the extending direction of the gate structure 311. The gate structure 311 is not shown in Figures 10B to 10D.

[0086] As shown in Figure 10B, the deposition process can fill the first trench 3202 and the second trench 3203 with a conductive material, which may be a metal or a doped semiconductor. For example, filling the first trench 3202 and the second trench 3203 with tungsten by the deposition process facilitates the formation of the first and second electrodes in subsequent steps.

[0087] As shown in Figure 10C, a mask layer 3205 can be formed on the first trench 3202 and second trench 3203 filled with conductive material by a process such as photolithography or SADP. Here, the mask layer 3205 may be a hard mask and is used to shield the area beneath the hard mask in a subsequent etching process, thereby preventing the shielded area from being removed by etching. Exemplaryly, first, a layer of inorganic thin film material such as SiN or SiO2 can be formed on the first trench 3202 and second trench 3203 filled with conductive material by a CVD process. Then, a photoresist can be applied on the inorganic thin film material, and the pattern can be transferred to the inorganic thin film material by a photolithography process to form the mask layer 3205. As can be understood, the area not shielded by the mask layer 3205 is the area that will be removed by etching in a subsequent process.

[0088] As shown in Figure 10D, by etching the conductive material in the first trench 3202 and the second trench 3203 through the mask layer 3205, at least a portion of the conductive material in the first trench 3202 is separated, forming a plurality of first electrodes 351 that are separated from each other and a plurality of second electrodes 352 that are connected to each other in a plurality of antifuse bit structures 350 that are arranged in the same straight line parallel to the extending direction of the gate structure 311.

[0089] In some embodiments, after forming a plurality of first electrodes 351 that are separated from each other, some of the conductive material in the first trench 3202 and the second trench 3203 is removed by etching. Subsequently, by filling the first trench 3202 and the second trench 3203 with insulating material, the plurality of first electrodes 351 that are separated from each other can be isolated.

[0090] As shown in Figure 11, an embodiment of the present invention further provides a memory 40 comprising a memory array 41 including the semiconductor structure described in any of the above embodiments, and a peripheral circuit 42 coupled to the memory array 41.

[0091] In an embodiment of the present invention, the memory 40 comprises a memory array 41 and peripheral circuits 42 coupled to the memory array 41. Here, the memory array 41 includes the semiconductor structure described in any of the above embodiments. The peripheral circuits 42 comprises an address circuit for latching and decoding row / column address information, a sense circuit for monitoring and determining the information stored by the antifuse unit, and a control circuit for switching the operating mode. In this way, the area occupied by the antifuse bit structure is reduced, the size of the memory cell is reduced, the integration density of the memory 40 is improved, and the number of masking steps required to form the antifuse bit structure is reduced, thereby simplifying the manufacturing process of the memory 40. On the other hand, the gate dielectric can be made thicker, thereby stabilizing the program voltage of the selection transistor and improving the reliability of the memory 40.

[0092] Figure 12 is a schematic diagram of a memory array 41, in which one selection transistor 440 and one antifuse bit structure 450 constitute one memory cell 410, each word line 411 and second electrode 452 connects multiple memory cells 410 in their respective extending directions, and one first metal line 430 (bit line) connects two adjacent memory cells 410 that share a source electrode or drain electrode.

[0093] Embodiments of the present invention further provide a method for operating a memory 40, the memory 40 comprising the semiconductor structure described in any of the above embodiments, the method comprising: breaking down one target antifuse bit structure 450 of the antifuse bit structure 450 of the memory 40 to switch the target antifuse bit structure 450 from a non-breakdown state to a breakdown state, and maintaining the non-breakdown state of a non-target antifuse bit structure 450, wherein the non-target antifuse bit structure 450 is an antifuse bit structure 450 other than the target antifuse bit structure.

[0094] In an embodiment of the present invention, referring to Figure 12, the operation method of the memory 40 includes, when performing a write operation on a target memory cell, breaking down one target antifuse bit structure 450 in the memory array 41 according to the data to be written, switching the target antifuse bit structure 450 from a non-breakdown state to a breakdown state, and maintaining the non-breakdown state of the non-target antifuse bit structure 450 in a non-target memory cell. Here, the non-target antifuse bit structure 450 is an antifuse bit structure 450 other than the target antifuse bit structure 450.

[0095] Exemplary, by applying different voltages to the first electrode 451 and the second electrode 452, the voltage difference between them is made to be greater than or equal to the breakdown voltage Vblow, thereby achieving breakdown of the antifuse bit structure 450. If the voltage difference between them is less than the breakdown voltage Vblow, the antifuse bit structure 450 can be maintained in a non-breakdown state.

[0096] The operation method of the memory 40 will be described below with reference to the operating voltages shown in Table 1 and Figure 12. Here, the non-target memory cell 410b and the target memory cell 410a are connected to the same word line and the same second electrode, while the non-target memory cell 410c and the target memory cell 410a are not connected to the same word line, the same second electrode, or the same bit line.

[0097] [Table 1]

[0098] In some embodiments, breaking down one target antifuse bit structure 450a within the antifuse bit structure 450 of the memory 40 to switch the target antifuse bit structure 450a from a non-breakdown state to a breakdown state includes applying a first voltage V1 to the gate structure 440a of a selection transistor connected to the target antifuse bit structure 450a to make the selection transistor 440a conduct, and applying a second voltage V2 to a first metal wire 430 connected to the selection transistor 440a, wherein the second voltage V2 is applied to the first electrode 451a of the target antifuse bit structure 450a via the selection transistor 440a, and applying a third voltage V3 to the second electrode 452 of the target antifuse bit structure 450a to switch the target antifuse bit structure 450a from a non-breakdown state to a breakdown state, where the voltage difference between the second voltage V2 and the third voltage V3 is greater than or equal to the breakdown voltage of the antifuse bit structure 450.

[0099] In an embodiment of the present invention, data can be written by breaking down the target antifuse bit structure 450a within the target memory cell 410a. Specifically, as shown in Figure 12, a first voltage V1 is applied to the gate structure of the selection transistor 440a connected to the target antifuse bit structure 450a, i.e., a first voltage V1 is applied to the word line 411, and exemplary, in order to ensure conduction of the selection transistor 440a, the first voltage V1 here can be greater than half of the breakdown voltage Vblow. Simultaneously, a second voltage V2 is applied to the first metal wire 430 connected to the selection transistor 440a, and a third voltage V3 is applied to the second electrode 452 of the target antifuse bit structure 450a. In this way, the second voltage V2 is applied to the first electrode 451a of the target antifuse bit structure 450a via the conductive selection transistor 440a, and the voltage difference between the second voltage V2 and the third voltage V3 is greater than or equal to the breakdown voltage Vblow, so the target antifuse bit structure 450a is switched from a non-breakdown state to a breakdown state. Exemplarily, the second voltage V2 here may be 0V, and the third voltage V3 may be the breakdown voltage Vblow.

[0100] In some embodiments, maintaining the non-breakdown state of the non-target antifuse bit structure 450b includes applying a first voltage V1 to the gate structure of a selection transistor 440b connected to the non-target antifuse bit structure 450b to make the selection transistor 440b conduct, and applying a fourth voltage V4 to a first metal wire 430b connected to the selection transistor 440b, wherein the fourth voltage V4 is applied to the first electrode 451b of the non-target antifuse bit structure 450b via the selection transistor 440b, and applying a third voltage V3 to the second electrode 452 of the non-target antifuse bit structure 450b to maintain the non-breakdown state of the non-target antifuse bit structure 450b, where the voltage difference between the fourth voltage V4 and the third voltage V3 is smaller than the breakdown voltage of the antifuse bit structure 450.

[0101] In embodiments of the present invention, when the target antifuse structure 450a in the target memory cell 410a is broken down, it is necessary to maintain the non-breakdown state of the non-target antifuse bit structure 450b in the non-target memory cell 410b. Specifically, as shown in Figure 12, for the non-target memory cell 410b connected to the same word line 411 and the same second electrode 452 as the target memory cell 410a, it is necessary to ensure that the gate structure of the selection transistor 440b connected to the non-target antifuse bit structure 450b, i.e., the word line 411, is conductive because the first voltage V1 is applied, and therefore the voltage difference between the first electrode 451b and the second electrode 452 of the non-target antifuse bit structure 450b is smaller than the breakdown voltage Vblow. Therefore, a fourth voltage V4 is applied to the first metal wire 430b connected to the selection transistor 440b, and in this way, the fourth voltage V4 is applied to the first electrode 451b of the non-target antifuse bit structure 450b via the conducting selection transistor 440b, and the voltage difference between the third voltage V3 on the second electrode 452 and the fourth voltage V4 on the first electrode 451b is smaller than the breakdown voltage Vblow, thus keeping the non-target antifuse bit structure 450b in a non-breakdown state. Exemplarily, the third voltage V3 here may be the breakdown voltage Vblow, and the fourth voltage V2 may be half of Vblow.

[0102] In some embodiments, maintaining the non-breakdown state of the non-target antifuse bit structure 450c includes applying a fifth voltage V5 to the gate structure of the selection transistor 440c connected to the non-target antifuse bit structure 450c to shut off the selection transistor 440c and maintain the non-breakdown state of the non-target antifuse bit structure 450c.

[0103] In an embodiment of the present invention, when the target antifuse structure 450a in the target memory cell 410a is broken down, it is necessary to maintain the non-breakdown state of the non-target antifuse bit structure 450c in the non-target memory cell 410c. Specifically, as shown in Figure 12, since the non-target memory cell 410c and the target memory cell 410a are not connected to the same word line 411 or the same first metal line 430, the non-breakdown state of the non-target antifuse bit structure 450c can be maintained simply by shutting off the selection transistor 440c. Specifically, a fifth voltage V5 is applied to the gate structure (word line 411) of the selection transistor 440c connected to the non-target antifuse bit structure 450c to shut off the selection transistor 440c and maintain the non-breakdown state of the non-target antifuse bit structure 450c. Selectively, the fifth voltage V5 here may be 0V.

[0104] [Table 2]

[0105] In some embodiments, write / read operations can be performed on the memory 40 according to the operating voltages shown in Table 2. Here, Vblr is the read voltage of the first metal line 430, i.e., the bit line, and Vwlr is the read voltage of the word line 411.

[0106] It should be noted that the features disclosed in some of the embodiments of the methods or apparatus provided in this invention can be arbitrarily combined without conflict to obtain new embodiments of the methods or apparatus. The above description is merely a specific embodiment of the invention, and the scope of protection of the invention is not limited thereto. Any modification or substitution that can be easily conceived by a person skilled in the art within the technical scope of the invention should be included within the scope of protection of the invention. Accordingly, the scope of protection of the invention shall be subject to the scope of protection of the claims. [Industrial applicability]

[0107] In the semiconductor structure according to an embodiment of the present invention, the gate structure is arranged on a first structural layer on a substrate, the antifuse bit structure is arranged on a second structural layer on the first structural layer, and the antifuse bit structure is connected to an active region in the substrate via a first connection structure. In this way, the antifuse bit structure does not need to occupy additional area in the horizontal direction, improving the integration density of the memory, and reducing the number of masking steps required to form the antifuse bit structure, thereby simplifying the manufacturing process.

Claims

1. It is a semiconductor structure, A substrate having a plurality of active regions near the surface of the substrate, wherein the active regions include a first doped region and a second doped region having the same dope type, and the first doped region and the second doped region are each arranged on both sides of the gate structure, A gate structure disposed on a first structural layer on the substrate, wherein the gate structure and the active region constitute a selection transistor. An antifuse bit structure disposed on a second structural layer above the first structural layer and connected via a first connection structure to the active region of one of the selected transistors, wherein the breakdown state and non-breakdown state of the antifuse bit structure are used to represent different stored data, comprising: The aforementioned antifuse bit structure is A first electrode connected to the active region via the first connection structure, A second electrode is arranged in the same plane as the first electrode, wherein the plane on which the first and second electrodes are arranged is parallel to the surface of the substrate, the projection of the first electrode on the substrate does not overlap with the projection of the second electrode on the substrate, a protruding structure is provided on one side of the first electrode closer to the second electrode, and a recessed structure corresponding to the protruding structure is provided on one side of the second electrode closer to the first electrode, The device comprises an antifuse bit dielectric layer disposed between the first electrode and the second electrode and connecting the first electrode and the second electrode, wherein the breakdown state is a state in which the antifuse bit dielectric layer is broken down, and the non-breakdown state is a state in which the antifuse bit dielectric layer is not broken down. The aforementioned semiconductor structure further, The antifuse bit structure comprises a first metal wire positioned on the antifuse bit structure, the first metal wire being connected to the second doped region via a second connection structure, A semiconductor structure in which two adjacent antifuse bit structures are provided symmetrically, and the selected transistors connected to each of the two symmetrically provided antifuse bit structures share the same second doped region and are connected to the first metal wire by the same second connection structure.

2. The second electrodes of the plurality of antifuse bit structures arranged parallel to the extending direction of the gate structure are connected to each other. The semiconductor structure according to claim 1.

3. The projection of the antifuse bit structure on the substrate overlaps at least partially with the projection of the gate structure on the substrate. The semiconductor structure according to claim 1.

4. The first structural layer further includes a first separation layer that surrounds at least the bottom and side surfaces of the gate electrode of the gate structure. The second structural layer further includes a second isolation layer that surrounds at least the bottom and sides of the antifuse bit structure, and the first connection structure penetrates the first isolation layer and the second isolation layer. The first isolation layer is an oxide material, and a portion of the first isolation layer within the gate structure is used as the gate dielectric of the selected transistor. The semiconductor structure according to claim 1.

5. The first doped region is connected to the antifuse bit structure via the first connection structure. The semiconductor structure according to claim 1.

6. The first metal wire is arranged in a third structural layer on top of the second structural layer, and the direction of extension of the first metal wire is perpendicular to the direction of extension of the gate structure. The third structural layer further includes a third separation layer that surrounds at least the bottom and sides of the first metal wire. The semiconductor structure according to claim 5.

7. The aforementioned semiconductor structure further, It includes a separation structure positioned between two adjacent first doped regions, wherein the two adjacent first doped regions are first doped regions corresponding to two adjacent selected transistors that do not share the second doped region. The semiconductor structure according to claim 1.

8. A method for manufacturing a semiconductor structure, To provide a substrate, wherein the substrate has a plurality of active regions near the surface of the substrate, A first structural layer including a gate structure is formed on the substrate, wherein the gate structure and the active region constitute a selected transistor. The method includes forming a second structural layer containing an antifuse bit structure on the first structural layer, and forming a first connection structure that connects the antifuse bit structure and the active region of the selected transistor, wherein the breakdown state and non-breakdown state of the antifuse bit structure are used to represent different stored data. Forming a second structural layer including an antifuse bit structure on the first structural layer, and forming a first connection structure that connects the antifuse bit structure and the active region of the selected transistor, The method involves depositing an insulating material on the aforementioned first structural layer, wherein the insulating material is used to form a second separation layer within the aforementioned second structural layer. A first trench and a second trench are formed in the insulating material, and a first connection hole is formed in the first trench that penetrates the first structural layer. The first connection hole is filled with a conductive material to form the first connection structure, The method includes filling the first trench and the second trench with a conductive material, removing at least a portion of the conductive material in the first trench to form a second electrode and a plurality of first electrodes separated from each other, wherein the insulating material other than the first electrode and the second electrode is the second isolation layer, a portion of the second isolation layer between the first electrode and the second electrode is used as the antifuse bit dielectric layer of the antifuse bit structure, the breakdown state is a state in which the antifuse bit dielectric layer has broken down, and the non-breakdown state is a state in which the antifuse bit dielectric layer has not broken down. A method for manufacturing a semiconductor structure, wherein the extension directions of the first trench and the second trench are parallel to the extension direction of the gate structure.

9. Filling the first trench and the second trench with conductive material, and removing at least a portion of the conductive material in the first trench to form a second electrode and a plurality of first electrodes separated from each other, Filling the first trench and the second trench with conductive material, This includes removing at least a portion of the conductive material in the first trench to form a plurality of first electrodes separated from each other and a plurality of second electrodes connected to each other in a plurality of antifuse bit structures arranged in the same straight line parallel to the extending direction of the gate structure, A method for manufacturing a semiconductor structure according to claim 8.

10. A method for operating a memory, wherein the memory includes a semiconductor structure as described in any one of claims 1 to 7, and the method for operating the memory is: In accordance with the data to be written, the target antifuse bit structure in the memory's antifuse bit structure is broken down, and the target antifuse bit structure is switched from a non-breakdown state to a breakdown state. A method for operating a memory, comprising: maintaining a non-breakdown state of a non-target antifuse bit structure, wherein the non-target antifuse bit structure is an antifuse bit structure other than the target antifuse bit structure.

11. Breaking down the target antifuse bit structure in the antifuse bit structure of the memory and switching the target antifuse bit structure from a non-breakdown state to a breakdown state is, Applying a first voltage to the gate structure of the selection transistor connected to the target antifuse bit structure to cause the selection transistor to conduct, Applying a second voltage to the first metal wire connected to the selection transistor, The process includes applying a third voltage to the second electrode of the target antifuse bit structure to switch the target antifuse bit structure from a non-breakdown state to a breakdown state, wherein the voltage difference between the second voltage and the third voltage is greater than or equal to the breakdown voltage of the antifuse bit structure, and / or Maintaining the non-breakdown state of the aforementioned non-target antifuse bit structure means that A first voltage is applied to the gate structure of the selection transistor connected to the non-target antifuse bit structure to cause the selection transistor to conduct, a fourth voltage is applied to the first metal wire connected to the selection transistor, and a third voltage is applied to the second electrode of the non-target antifuse bit structure to maintain the non-target antifuse bit structure in a non-breakdown state, wherein the voltage difference between the fourth voltage and the third voltage is smaller than the breakdown voltage of the antifuse bit structure, or This includes applying a fifth voltage to the gate structure of the selection transistor connected to the non-target antifuse bit structure to shut off the selection transistor and maintain the non-target antifuse bit structure in a non-breakdown state. The method for operating the memory according to claim 10.

12. It is memory, A memory array comprising the semiconductor structure described in any one of claims 1 to 7, A memory comprising peripheral circuits coupled to the memory array.

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