Quantumizer Design

Abstract

To provide a method, a computer program, and a computer system for video coding.SOLUTION: Video data which includes one or more quantization coefficients is received. One or more index values associated with the quantization coefficients are mapped to one or more step values on the basis of an exponential mapping. Video data is decoded on the basis of one or more step values.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] (Reference to related applications) This application claims priority to U.S. Provisional Patent Application No. 63 / 035,642, filed with the U.S. Patent and Trademark Office on 5 June 2020, and U.S. Provisional Patent Application No. 17 / 098,825, filed on 16 November 2020, which are incorporated herein by reference in their entirety.

[0002] This disclosure generally relates to the field of data processing, and more specifically to video processing. [Background technology]

[0003] AOMedia Video 1 (AV1) was developed as a successor to VP9 by the Alliance for Open Media (AOMedia), a consortium founded in 2015 that includes semiconductor companies, video-on-demand providers, video content creators, software developers, and web browser vendors. Many of the components of the AV1 project were supplied from previous research efforts by alliance members. Individual contributors started experimental technology platforms many years earlier. Specifically, Xiph / Mozilla's Daala released its code as early as 2010, Google's experimental VP9 evolution project VP10 was announced on September 12, 2014, and Cisco's Thor was announced on August 11, 2015. Building on the VP9 codebase, AV1 incorporated additional technologies, some of which were developed in these experimental formats. The first version of the AV1 reference codec, 0.1.0, was released on April 7, 2016. The Alliance announced the release of the AV1 bitstream specification on March 28, 2018, along with references to software-based encoders and decoders. A verified version 1.0.0 of the specification was released on June 25, 2018. A verified version 1.0.0 with Errata1 was released on January 8, 2019. The AV1 bitstream specification includes reference video codecs. AOMedia Video2 (AV2) is currently under development. [Overview of the project]

[0004] Embodiments relating to a method for coding (encoding) video data, a computer program, and a computer system. According to one embodiment, a method for coding (encoding) video data is provided. The method may include receiving video data containing one or more quantization coefficients. One or more index values ​​associated with one or more quantization coefficients are mapped to one or more step values ​​based on exponential mapping. The video data is decoded based on one or more step values.

[0005] In another embodiment, a computer system for coding (encoding) video data is provided. The computer system may include one or more processors, one or more computer-readable memories, one or more computer-readable tangible storage devices, and program instructions stored in at least one of the storage devices for execution by at least one of the processors via at least one of the memories, thereby enabling the computer system to perform a method. The method may include receiving video data containing one or more quantization coefficients (quantized counts). One or more index values ​​associated with one or more quantization coefficients are mapped to one or more step values ​​based on exponential mapping. The video data is decoded based on one or more step values.

[0006] In yet another embodiment, a computer-readable medium for coding (encoding) video data is provided. The computer-readable medium may include one or more computer-readable storage devices and program instructions stored in at least one of the one or more tangible storage devices, the program instructions being executable by a processor. The program instructions are executable by a processor for performing a method which may include receiving video data containing one or more quantization coefficients accordingly. One or more index values ​​associated with one or more quantization coefficients are mapped to one or more step values ​​based on an exponential mapping. The video data is decoded based on one or more step values.

[0007] These and other purposes, configurations, and advantages will become apparent from the following detailed description of exemplary embodiments, which should be read in conjunction with the attached drawings. The various configurations in the drawings are not to scale, for the illustrations are for clarity to facilitate understanding for those skilled in the art, along with the detailed description. [Brief explanation of the drawing]

[0008] [Figure 1] A networked computer environment according to at least one embodiment is illustrated.

[0009] [Figure 2A] This is a diagram of the Q_index vs. Qstep mapping for DC&AC coefficients in AV1 according to at least one embodiment.

[0010] [Figure 2B] This is a diagram of a unified Q_index vs. Qstep linear mapping for AV2 according to at least one embodiment.

[0011] [Figure 2C] This is a diagram of a unified Q_index vs. QstepLog2 mapping for AV2 according to at least one embodiment.

[0012] [Figure 3] This is an operation flowchart illustrating the steps performed by a program that compresses a neural network model according to at least one embodiment.

[0013] [Figure 4] Figure 1 is a block diagram of the internal and external components of a computer and server according to at least one embodiment.

[0014] [Figure 5] This is a block diagram of an exemplary cloud computing environment, including the computer system shown in Figure 1, according to at least one embodiment.

[0015] [Figure 6] Figure 5 is a block diagram of the functional layer of an exemplary cloud computing environment according to at least one embodiment. [Modes for carrying out the invention]

[0016] Detailed embodiments of the claimed structures and methods are disclosed herein, but it should be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods, which may be embodied in various forms. However, these structures and methods may be embodied in many different forms and should not be construed as being limited to the exemplary embodiments described herein. Rather, these exemplary embodiments are provided to ensure that this disclosure is comprehensive and complete and fully conveys its scope to those skilled in the art. In the description, well-known configurations and technical details may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0017] The embodiments generally relate to the field of data processing, and more specifically to video encoding and decoding. The exemplary embodiments described below provide, among other things, systems, methods, and computer programs for encoding / decoding video data. Accordingly, some embodiments have the ability to improve the field of computing by enabling improved video coding efficiency through the use of AV2.

[0018] As mentioned above, AOMedia Video 1 (AV1) was developed as the successor to VP9 by Alliance for Open Media (AOMedia), a consortium founded in 2015 that includes semiconductor companies, video-on-demand providers, video content creators, software development companies, and web browser vendors. Many components of the AV1 project were sourced from prior research efforts by alliance members. Individual contributors launched experimental technology platforms years ago: specifically, Xiph / Mozilla's Daala already published its code in 2010, Google's experimental VP9 evolution project VP10 was announced on September 12, 2014, and Cisco's Thor was released on August 11, 2015. Based on the VP9 codebase, AV1 incorporates additional technologies, several of which were developed in these experimental formats. The first version 0.1.0 of the AV1 reference codec was released on April 7, 2016. The alliance announced the release of the AV1 bitstream specification along with the reference software-based encoder and decoder on March 28, 2018. The validated version 1.0.0 specification was released on June 25, 2018. The validated version 1.0.0 with the Errata 1 specification was released on January 8, 2019. The AV1 bitstream specification includes a reference video codec. Currently, AOMedia Video 2 (AV2) is under development.

[0019] In AV1, the quantization of transform coefficients may apply different quantization step sizes to DC and AC transform coefficients, and different quantization step sizes may apply to lumen and chroma transform coefficients. To specify the quantization step size, the frame header first signals the base_q_idx syntax element, which is an 8-bit fixed-length code specifying the quantization step size for lumen AC coefficients. The valid range of base_q_idx is [0, 255]. Subsequently, the delta value of base_q_idx for lumen DC coefficients, indicated as DeltaQYDc, is further signaled. Furthermore, if there are more than one color plane, the flag diff_uv_delta is signaled to indicate whether different quantization index values ​​are applied to Cb and Cr color components. If diff_uv_delta is transmitted as 0, only the delta values ​​for base_q_idx for the chrominance DC coefficient (indicated as DeltaQUDc) and the AC coefficient (indicated as DeltaQUAc) are transmitted. Otherwise, the delta values ​​for base_q_idx for both the DC coefficients of Cb and Cr (indicated as DeltaQUDc and DeltaQVDc) and the AC coefficients (indicated as DeltaQUAc and DeltaQVAC) are transmitted. However, the AV1 quantization step size has limited resolution.

[0020] Accordingly, it may be advantageous to increase the resolution of the quantization step size. In the ongoing AV2 development process, several tools may be used in quantizer design. For example, separate lookup tables Dc_Qlookup[3]

[0256] and Ac_Qlookup[3]

[0256] may be integrated. Ac_Qlookup[3]

[0256] is retained, and the DC quantization step size is obtained using an offset therefrom. The default offset is set to 8. In addition, separate lookup tables were used to obtain quantizer step sizes for 8-bit, 10-bit, and 12-bit internal bit depths, and the step sizes did not exhibit any mathematical relationship. This may be replaced with a modified lookup table for 8-bit internal bit depth. The quantization step size generation process is integrated for 10-bit and 12-bit internal bit depths in such a manner that the corresponding 8-bit step size (obtained using Q_index) is scaled by 4 and 16, respectively. Furthermore, the range of supported step sizes may be increased without increasing the range of Q_index.

[0021] Aspects are described herein with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer-readable media according to various embodiments. It will be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0022] Referring here to Figure 1, a functional block diagram of a networked computer environment illustrating a video coding system 100 (hereinafter referred to as the "System") for compressing a neural network model is shown. It should be understood that Figure 1 provides only an example of one implementation and does not imply any limitations on the environment in which different embodiments may be implemented. Many modifications to the illustrated environment may be made based on design and implementation requirements.

[0023] System 100 may include a computer 102 and a server computer 114. Computer 102 may communicate with the server computer 114 via a communication network 110 (hereinafter referred to as the "network"). Computer 102 may include a processor 104 and a software program 108 stored in a data storage device 106, which interfaces with a user and enables communication with the server computer 114. As discussed below with reference to Figure 4, computer 102 may include internal components 800A and external components 900A, respectively, and the server computer 114 may include internal components 800B and external components 900B, respectively. Computer 102 may be, for example, a mobile device, telephone, personal digital assistant, netbook, laptop computer, tablet computer, desktop computer, or any type of computing device capable of running programs, accessing networks, and accessing databases.

[0024] The server computer 114 may also operate in a cloud computing service model such as Software as a Service (SaaS), Platform as a Service (PaaS), or Infrastructure as a Service (IaaS), as discussed below with respect to Figures 5 and 6. The server computer 114 may also be located within a cloud computing deployment model such as a private cloud, community cloud, public cloud, or hybrid cloud.

[0025] A server computer 114, which may be used to compress a neural network model, is enabled to run a video coding program 116 (hereinafter referred to as the "program"), which may interact with a database 112. The video coding program method is described in more detail below with reference to Figure 3. In one embodiment, computer 102 may act as an input device including a user interface, while program 116 may run primarily on server computer 114. In an alternative embodiment, program 116 may run primarily on one or more computers 102, while server computer 114 may be used for processing and storing data used by program 116. It should be noted that program 116 may be a standalone program or may be integrated into a larger video coding program.

[0026] However, it should be noted that the processing for program 116 may, in some cases, be shared between computer 102 and server computer 114 in any ratio. In another embodiment, program 116 may run on more than one computer, server computer, or several combinations of computers and server computers, for example, multiple computers 102 communicating with a single server computer 114 over network 110. In another embodiment, for example, program 116 may run on multiple server computers 114 communicating with multiple client computers over network 110. Alternatively, the program may run on a network server communicating with servers and multiple client computers over a network.

[0027] Network 110 may include wired connections, wireless connections, fiber optic connections, or a combination thereof. Generally, network 110 can be any combination of connections and protocols that support communication between computer 102 and server computer 114. Network 110 may include various types of networks, such as local area networks (LANs), wide area networks (WANs) like the Internet, telecommunications networks like public switched telephone networks (PSTNs), wireless networks, public switched networks, satellite networks, cellular networks (e.g., fifth-generation (5G) networks, long-term evolution (LTE) networks, third-generation (3G) networks, code division multiple access (CDMA) networks, etc.), public land mobile networks (PLMNs), metropolitan area networks (MANs), private networks, ad-hoc networks, intranets, fiber optic-based networks, or equivalents, and / or combinations of these or other types of networks.

[0028] The number and arrangement of devices and networks shown in Figure 1 are provided as an example. In practice, there may be additional devices and / or networks, fewer devices and / or networks, different devices and / or networks, or devices and / or networks in different arrangements than those shown in Figure 1. Furthermore, two or more devices shown in Figure 1 may be implemented within a single device, or a single device shown in Figure 1 may be implemented as multiple distributed devices. Additionally or alternatively, a set of devices in system 100 (e.g., one or more devices) may perform one or more functions that are described as being performed by another set of devices in system 100.

[0029] Next, referring to Figure 2A, Figure 200A shows the Q_index mapping to Qstep for DC and AC coefficients in AV1. The decoded DeltaQYDc, DeltaQUAc, DeltaQUDc, DeltaQVAc, and DeltaQVDc values ​​may be appended to base_q_idx to derive the quantization index Q_index. These Q_indexes are further mapped to the quantization step size according to two tables. For DC coefficients, the mapping from quantization index to quantization step size for 8-bit, 10-bit, and 12-bit internal bit depths is specified by the lookup table Dc_Qlookup[3]

[0256] , and the mapping from quantization index to quantization step size for 8-bit, 10-bit, and 12-bit is specified by the lookup table Ac_Qlookup[3]

[0256] .

[0030] Next, referring to Figure 2B, we see Figure 200B, which shows the Q_index linear mapping to the integrated Qstep for AV2. The valid range of Q_index is [0, 255], which maps to the step size range [4, 6879]. The step size range is increasing, but the valid range of Q_index remains the same. This limitation in quantization step resolution is more apparent with 10-bit and 12-bit internal bit depths, where the corresponding 8-bit step sizes (obtained using q_idx) are scaled by 4 and 16, respectively. This can affect the bitrate granularity that can be achieved by the codec.

[0031] Next, referring to Figure 2C, we see Figure 200C, which shows the Q_indexLog2 mapping to the integrated Qstep for AV2. The mapping from Q_index to quantization step size does not always show a consistent mathematical relationship. While the initial entries of the step size show a linear relationship with Q_index, the rest of the mapping is almost exponential. The transition from linear to exponential mapping is not smooth. Moreover, at lower Q_indexes, there is a sudden jump in the step size, which is more evident for 10-bit and 12-bit internal bit depth coding, because they are scaled up by 4 and 16 respectively.

[0032] While the exponential mapping of Q_index to Qstep can be expressed as follows,

number

number

[0033] In one embodiment, the Q_index can be divided into multiple ranges, in each range, a, b, and c are kept constant (piecewise exponential). In one embodiment, the value for b may include, but is not limited to, 2. In one embodiment, the value for a may include, but is not limited to, 4, 8, 16, 19, 24, and 32. In one embodiment, c may be, but is not limited to, a factor of the range or upper limit of the Q_index. An example of a range of Q_index applied in AV1 is 256. In one embodiment, the value for c may include, but is not limited to, 3, 4, 5, 6, 7, 8, 9, 10, 11, ..., 32, ..., 64.

[0034] According to one or more embodiments, a combination of piecewise linear mapping and exponential mapping of Q_index to Qstep may be used. In one embodiment, the entire range of Q_index (e.g., [0, T) may be used. N ]) can be multiple ranges, for example, [0, T0], [T0+1, T1], ..., [T N-1 +1,T NIt can be divided into ]), and in each range, a linear or exponential mapping can be used. In one embodiment, the value for b may include, but is not limited to, 2. In one embodiment, the value for a may include, but is not limited to, 4, 8, 16, 19, 24, 32. In one embodiment, c may be, but is not limited to, a factor of the range or upper limit of Q_index. An example of the range of Q_index applied in AV1 is 256. In one embodiment, the value for x may include, but is not limited to, 1, 2, 4, 8. In one embodiment, the value for y may include, but is not limited to, 4, 8, 16, 32.

[0035] According to one or more embodiments, a Q_index mapping scheme for an extended Qstep may be used. In one embodiment, the Q_index range can be increased without increasing the Qstep range. In one embodiment, the extended Q_index range is available for 8, 10, 12, and 16-bit internal bit-depth codec configurations. In one embodiment, an 8-bit internal bit-depth codec configuration uses a subset of the extended Q_index. In one embodiment, the extended Q_index range can be flexibly allocated to a subset of the quantization step size range to achieve greater granularity over that range. In one embodiment, the extended Q_index range can be used to achieve greater granularity for very high bit rates (lower quantization step sizes). In one embodiment, the extended Q_index range can be used to achieve greater granularity for very low bit rates (higher quantization step sizes). In one embodiment, the extended Q_index range can be used to achieve greater granularity for bit rates other than very high and very low bit rates. In one embodiment, both the Q_index and the Qstep range are increased.

[0036] According to one or more embodiments, the range of Q_index values depends on the internal bit depth of the codec. In one embodiment, for a larger internal bit depth, the range of Q_index values is larger. In one embodiment, when an exponential mapping of Q_index to Qstep is used, for internal bit depth a and internal bit depth b, where b is greater than a, the ranges of Q_index values for internal bit depths a and b are denoted as [0, QA] and [0, QB], respectively, where QB = QA + (b-a) * c. In one example, the range of Q_index values is [0, 255] for an 8-bit internal bit depth, and in this case, the ranges of Q_index values are [0, 255+2 * c] and [0, 255+4 * c] for 10-bit and 12-bit internal bit depths, respectively. Exemplary values of c include, but are not limited to, 4, 5, 6, 7, 8, 9, 10, 11, ..., 32, ..., 64. In one embodiment, the available Qstep values for one internal bit depth setting a are a subset of the available Qstep values for a larger internal bit depth setting b (where b is greater than a). In one embodiment, the available Qstep values for one internal bit depth setting a are [Q0, Q1, ..., Q NA-1 , and the available Qstep values for one internal bit depth setting b are [Q0, Q1, ..., Q NA-1 , ..., Q NB-1 .

[0037] In one example, the available Qstep values for an internal bit depth setting of 8 are as follows. [[Formula]]

[0038] In one example, the available Qstep values for an internal bit depth setting of 10 are as follows.

number

[0039] Referring next to Figure 3, an operation flowchart illustrating the steps of method 300 for video coding is shown. In some implementations, one or more process blocks in Figure 3 may be executed by computer 102 (Figure 1) and server computer 114 (Figure 1). In some implementations, one or more process blocks may be executed by a separate device or group of devices separate from or including computer 102 and server computer 114.

[0040] In 302, method 300 includes receiving video data that includes one or more quantization coefficients (quantized coefficients).

[0041] In 304, method 300 includes mapping one or more index values ​​associated with one or more quantization coefficients (quantized coefficients) to one or more step values ​​based on exponential mapping.

[0042] In 306, method 300 includes decoding video data based on one or more step values.

[0043] It should be understood that Figure 3 merely provides an example of one implementation and does not imply any constraints on how different embodiments may be implemented. Many modifications to the illustrated environment may be made based on design and implementation requirements.

[0044] Figure 4 is a block diagram 400 of the internal and external components (configurations) of the computer shown in Figure 1, according to an exemplary embodiment. It should be understood that Figure 4 provides only an example of one implementation and does not imply any constraints regarding the environment in which different embodiments may be implemented. Many modifications to the illustrated environment may be made based on design and implementation requirements.

[0045] Computer 102 (Figure 1) and server computer 114 (Figure 1) may include sets of internal components 800A and B and external components 900A and B, respectively, as shown in Figure 4. Each set of internal components 800 includes one or more processors 820, one or more computer-readable RAMs 822, one or more computer-readable ROMs 824 on one or more buses 826, one or more operating systems 828, and one or more computer-readable tangible storage devices 830.

[0046] The processor 820 is implemented in hardware, firmware, or a combination of hardware and software. The processor 820 is a central processing unit (CPU), graphics processing unit (GPU), acceleration unit (APU), microprocessor, microcontroller, digital signal processor (DSP), field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), or another type of processing component. In some embodiments, the processor 820 includes one or more processors that can be programmed to perform functions. The bus 826 includes components that enable communication between internal components 800A and B.

[0047] One or more operating systems 828, software programs 108 (Figure 1), and video coding programs 116 (Figure 1) on the server computer 114 (Figure 1) are stored in one or more computer-readable tangible storage devices 830 for execution by one or more processors 820 via one or more RAMs 822 (typically including cache memory) each. In the embodiment shown in Figure 4, each of the computer-readable tangible storage devices 830 is a magnetic disk storage device of an internal hard drive. Alternatively, each of the computer-readable tangible storage devices 830 is a semiconductor storage device such as a ROM 824, EPROM, flash memory, optical disk, magneto-optical disk, solid-state disk, compact disk (CD), digital versatile disk (DVD), floppy disk, cartridge, magnetic tape, and / or another type of non-temporary computer-readable tangible storage device that can store computer programs and digital information.

[0048] Each set of internal components 800A and B also includes an R / W drive or interface 832 for reading from and writing to one or more portable computer-readable tangible storage devices 936, such as CD-ROMs, DVDs, memory sticks, magnetic tapes, magnetic disks, optical disks, or semiconductor storage devices. Software programs, such as software program 108 (Figure 1) and video coding program 116 (Figure 1), are stored in one or more of the respective portable computer-readable tangible storage devices 936, can be read via their respective R / W drives or interfaces 832, and loaded into their respective hard drives 830.

[0049] Each set of internal components 800A and B also includes a network adapter or interface 836, such as a TCP / IP adapter card, a wireless Wi-Fi interface card, or a 3G, 4G, or 5G wireless interface card, or other wired or wireless link. The software program 108 (Figure 1) and video coding program 116 (Figure 1) on the server computer 114 (Figure 1) can be downloaded from an external computer to computer 102 (Figure 1) and the server computer 114 via a network (e.g., the Internet, a local area network, or another wide area network) and the respective network adapter or interface 836. From the network adapter or interface 836, the software program 108 and video coding program 116 on the server computer 114 are loaded into their respective hard drives 830. The network may include copper, fiber optic, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers.

[0050] Each of the external component sets 900A and B may include a computer display monitor 920, a keyboard 930, and a computer mouse 934. External components 900A and B may also include a touchscreen, a virtual keyboard, a touchpad, a pointing device, and other human interface devices. Each of the internal component sets 800A and B also includes a device driver 840 for interface with the computer display monitor 920, the keyboard 930, and the computer mouse 934. The device driver 840, the R / W drive or interface 832, and the network adapter or interface 836 include hardware and software (stored in the storage device 830 and / or ROM 824).

[0051] This disclosure includes a detailed description of cloud computing, but it should be understood in advance that implementations of the teachings described herein are not limited to cloud computing environments. Rather, some embodiments can be implemented in any other type of computing environment that is known now or may be developed later.

[0052] Cloud computing is a service delivery model that enables convenient, on-demand network access to a shared pool of configurable computing resources (networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly delivered and released with minimal management effort or interaction with service providers. This cloud model may include at least five features, at least three service models, and at least four deployment models.

[0053] The features are as follows: On-demand self-service: Cloud consumers can unilaterally provide computing power, such as server time and network storage, automatically and without requiring human interaction with service providers, as needed. Broad network access: Capabilities are available over a network and accessed through standard mechanisms that facilitate use by heterogeneous thin or thick client platforms (e.g., mobile phones, laptops, and PDAs). Resource pooling: A provider's computing resources are pooled to serve multiple consumers using a multi-tenant model, with different physical and virtual resources dynamically allocated and reallocated according to demand. Consumers generally have a sense of location independence, in that they do not have control or knowledge of the exact location of the resources provided, but may be able to identify the location at a higher level of abstraction (e.g., country, state, or data center). Rapid elasticity: Capabilities can be provided quickly and elastically, sometimes automatically, to be rapidly released to scale out and scale in rapidly. To consumers, the capacity available for provisioning often appears unlimited and can be purchased at any time and in any quantity. Measured service: Cloud systems automatically control and optimize resource usage by leveraging metering capability at some level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported to provide transparency for both service providers and consumers.

[0054] The service model is as follows: Software as a Service (SaaS): The ability offered to consumers is the use of a provider's applications running on a cloud infrastructure. These applications are accessible from various client devices through thin client interfaces such as web browsers (e.g., web-based email). Consumers do not manage or control the underlying infrastructure, including the network, servers, operating systems, storage, and even the capabilities of individual applications, with the possible exception of configuring user-specific application settings. Platform as a Service (PaaS): The ability provided to consumers is to deploy consumer-created or acquired applications, written using programming languages ​​and tools supported by the provider, on a cloud infrastructure. Consumers do not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, or storage, but they have control over the applications they deploy and, in some cases, over the configuration of the environment hosting those applications. Infrastructure as a Service (laaS): The capability offered to consumers is to provide processing, storage, networking, and other basic computing resources that enable them to deploy and run any software, including operating systems and applications. Consumers do not manage or control the underlying cloud infrastructure, but they have control over the operating system, storage, and deployed applications, and possibly limited control over selected network components (e.g., host firewalls).

[0055] The deployment model is as follows: Private Cloud: Cloud infrastructure is operated exclusively for an organization. It may be managed by the organization or a third party, and may reside on or off-site. Community Cloud: Cloud infrastructure is shared by several organizations to support a specific community with common interests (e.g., mission, security requirements, policies, and compliance considerations). It may be managed by the organization or a third party and may reside on or off-site. Public cloud: Cloud infrastructure may be made available to the general public or large industry groups and is owned by an organization that sells cloud services. Hybrid Cloud: A cloud infrastructure consists of two or more clouds (private, community, or public) that remain unique entities but are connected by standardized or proprietary technologies that enable data and application portability (e.g., cloud bursting for load balancing between clouds).

[0056] Cloud computing environments are service-oriented, focusing on statelessness, low coupling, modularity, and semantic interoperability. At the heart of cloud computing is the infrastructure, which includes a network of interconnected nodes.

[0057] Referring to Figure 5, an exemplary cloud computing environment 500 is shown. As shown, the cloud computing environment 500 includes one or more cloud computing nodes 10, and local computing devices used by cloud consumers, such as personal digital assistants (PDAs) or mobile phones 54A, desktop computers 54B, laptop computers 54C, and / or automotive computer systems 54N, may communicate using the cloud computing nodes 10. The cloud computing nodes 10 may communicate with each other. The cloud computing nodes 10 may be physically or virtually grouped within one or more networks, such as private, community, public, or hybrid clouds, or a combination thereof, as described above (not shown). This enables the cloud computing environment 500 to provide infrastructure, platforms, and / or software as a service, eliminating the need for cloud consumers to maintain resources on their local computing devices. The types of computing devices 54A to 54N shown in Figure 5 are intended to be illustrative only, and it should be understood that the cloud computing node 10 and the cloud computing environment 500 may communicate with any type of computerized device through any type of network and / or network addressable connection (for example, using a web browser).

[0058] Referring to Figure 6, a set of functional abstraction layers 600 provided by the cloud computing environment 500 (Figure 5) is shown. The components, layers, and functions shown in Figure 6 are intended to be illustrative only, and it should be understood in advance that embodiments are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0059] The hardware and software layer 60 includes hardware components and software components. Examples of hardware components include a mainframe 61, RISC (Reduced Instruction Set Computer) architecture-based servers 62, 63, blade servers 64, storage devices 65, and networks and network components 66. In some embodiments, the software components include network application server software 67 and database software 68.

[0060] The virtualization layer 70 provides an abstraction layer that may provide the following examples of virtual entities: a virtual server 71, virtual storage 72, a virtual network 73 including a virtual private network, a virtual application and operating system 74, and a virtual client 75.

[0061] In one example, the management layer 80 may provide the following functions: Resource provisioning 81 provides the dynamic procurement of computing resources and other resources used to perform tasks within the cloud computing environment. Metering and pricing 82 provides cost tracking as resources are used within the cloud computing environment, and billing or invoicing for the consumption of these resources. In one example, these resources may include application software licenses. Security provides identity verification for cloud consumers and tasks, and protection for data and other resources. User portal 83 provides access to the cloud computing environment for consumers and system administrators. Service level management 84 provides the allocation and management of cloud computing resources to ensure that the required service levels are met. Service Level Agreement (SLA) planning and fulfillment 85 provides the arrangement and procurement of cloud computing resources in advance, where future requirements are anticipated in accordance with the SLA.

[0062] The workload layer 90 provides examples of functionality that may utilize a cloud computing environment. Examples of workloads and functions that may be provided from this layer include mapping and navigation 91, software development and lifecycle management 92, virtual classroom education delivery 93, data analysis processing 94, transaction processing 95, and video coding 96. Video coding 96 may encode and / or decode video data.

[0063] Some embodiments may relate to systems, methods, and / or computer-readable media in an aggregate of any possible level of technical detail. Computer-readable media may include computer-readable non-temporary storage media (or more media) having computer-readable program instructions thereon for causing a processor to perform an action.

[0064] A computer-readable storage medium can be a tangible device capable of holding and storing instructions for use by an instruction-executing device. A computer-readable storage medium may be, but is not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or a suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes, namely, portable computer diskettes, hard disks, random-access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random-access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital multipurpose disks (DVDs), memory sticks, floppy disks, mechanically encoded devices such as punch cards or grooved raised structures having recorded instructions thereon, or any suitable combination thereof. When used herein, computer-readable storage media should not be interpreted as transient signals in themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through optical fiber cables), or electrical signals transmitted through wires.

[0065] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing device / processing device, or to an external computer or external storage device, via a network, such as the Internet, a local area network, a wide network, and / or a wireless network. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface within each computing device / processing device receives computer-readable program instructions from the network and transfers the computer-readable program instructions for storage in the computer-readable storage medium within each computing device / processing device.

[0066] Computer-readable program code / instructions for performing calculations may be either assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuits, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++ or equivalent, and procedural programming languages ​​such as the "C" programming language or similar programming languages. Computer-readable program instructions may run entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or wide area network (WAN), or the connection may be made to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, an electronic circuit configuration, for example, including a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA), may execute computer-readable program instructions by personalizing the electronic circuit configuration using state information of computer-readable program instructions in order to perform an action or operation.

[0067] These computer-readable program instructions may be provided to a general-purpose computer, a dedicated computer, or a processor of another programmable data processing device for manufacturing a machine, such that instructions executed via the processor of a computer or other programmable data processing device generate means for implementing functions / actions specified in blocks or more of a flowchart and / or block diagram. These computer-readable program instructions may be stored in a computer-readable storage medium that can instruct a computer, a programmable data processing device, and / or other device to function in a particular way, such that the storage medium containing the stored instructions contains a manufactured article containing instructions for implementing modes of functions / actions specified in blocks or more of a flowchart and / or block diagram.

[0068] Computer-readable program instructions may be loaded into a computer, another programmable device, or another device to generate a computer implementation process by causing the computer, another programmable device, or another device to execute a series of operational steps so that the instructions executed by the computer, another programmable device, or another device implement a function / action identified in one or more blocks of a flowchart and / or block diagram.

[0069] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer-readable media according to various embodiments. In this regard, each block in a flowchart or block diagram may represent a module, segment, or part of an instruction containing one or more executable instructions for implementing a specified logical function. Methods, computer systems, and computer-readable media may include additional blocks, fewer blocks, different blocks, or blocks arranged differently than those shown in the drawings. In some alternative implementations, the functions shown in the blocks may occur outside the order shown in the figures. For example, two consecutively shown blocks may actually be executed simultaneously or substantially simultaneously, or blocks may be executed in reverse order depending on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented by a purpose-specific hardware-based system that performs a specified function or action, or a specific combination of purpose-specific hardware and computer instructions.

[0070] It will be apparent that the systems and / or methods described herein may be implemented in different forms of hardware, firmware, or combinations of hardware and software. The actual specialized control hardware or software code used to implement these systems and / or methods is not limiting to the implementation. Therefore, the operation and behavior of the systems and / or methods are described herein without reference to specific software code, and it is understood that software and hardware may be designed to implement the systems and / or methods based on the descriptions herein.

[0071] Any element, action, or instruction used herein should not be construed as important or essential unless expressly stated otherwise. Furthermore, when used herein, the singular article is intended to include one or more items and may be used interchangeably with "one or more." Furthermore, when used herein, the term "set" is intended to include one or more items (e.g., related items, unrelated items, a combination of related and unrelated items) and may be used interchangeably with "one or more." When only one item is intended, "one" or a similar term should be used. Furthermore, when used herein, the terms "has," "have," "having," or equivalent terms are intended to be open-end terms. Furthermore, "based on" is intended to mean "based, at least in part, on" unless expressly stated otherwise.

[0072] While descriptions of various aspects and embodiments are presented for illustrative purposes, they are not intended to exhaust or limit the disclosed embodiments. Where combinations of configurations are enumerated in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of possible implementations. In practice, many of these configurations may be combined in ways not specifically enumerated in the claims and / or disclosed in the specification. Each dependent listed below may depend directly on only one claim, but the disclosure of possible implementations includes each dependent in combination with any other claim in the set of claims. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best describe the principles of the embodiments, their practical application to marketable technologies or technical improvements, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for coding video data that can be executed by a processor, This method is Encode the video data into an encoded bitstream. This includes storing the encoded bitstream in a storage medium. The encoding includes quantizing using one or more step values ​​to generate quantization coefficients, The one or more step values ​​are mapped to one or more index values ​​associated with the quantization coefficients based on the extended mapping, the first range associated with the index values ​​is divided into one or more subranges, and one of linear mapping and exponential mapping is used for each of the subranges. The correspondence obtained by the linear mapping satisfies Qstep = x * Q_index + y, The correspondence obtained by the aforementioned exponential mapping is Qstep = a*b Q_index / c Satisfying the conditions, Here, Qstep is the step value, Q_index is the index value, and a, b, c, x, and y are constants within the sub-range. method.

2. The method according to claim 1, wherein the extended mapping is based on a combination of piecewise linear mapping and exponential mapping.

3. The method according to claim 1, wherein the first range associated with the index value is increased without increasing the second range associated with the step value.

4. The method according to claim 3, wherein the increased first range is increased based on the required granularity of the extreme bitrate.

5. The method according to claim 3, wherein the increased first range is flexibly allocated to a subset of the second range.

6. The method according to claim 1, wherein the first range depends on the internal bit depth associated with the video data.

7. The method according to claim 6, wherein the first range is greater for a larger internal bit depth.

8. The method according to claim 6, wherein the second range for the first internal bit depth is a subset of the second range for the second internal bit depth, based on the fact that the second internal bit depth is greater than the first internal bit depth.

9. The method according to any one of claims 1 to 8, wherein b is 2.

10. A computer system for coding video data, One or more computer-readable non-temporary storage media configured to store computer program code, A computer system comprising one or more computer processors configured to access the computer program code and to perform, as instructed by the computer program code, the method described in any one of claims 1 to 9.

11. A non-temporary computer-readable medium on which a computer program for coding video data is stored, The computer program is a non-temporary computer-readable medium that causes one or more computer processors to perform the method described in any one of claims 1 to 9.

12. A method for coding video data that can be executed by a processor, This method is Encode the video data into an encoded bitstream. This includes storing the encoded bitstream in a storage medium. The encoding includes quantizing using one or more step values ​​to generate quantization coefficients, The one or more step values ​​are mapped to one or more index values ​​associated with the quantization coefficients based on a piecewise exponential mapping, the first range associated with the index values ​​is divided into one or more subranges, and a certain exponential mapping is used for each of the subranges. method.

Images