Systems and methods for mitigating degeneracy in quantum processors

Abstract

To mitigate degeneracy in analog processor operation via use of floppy qubits or domains of floppy qubits, thereby significantly boosting hardware performance on certain problems.SOLUTION: Samples are drawn from an analog processor, and devices comprising the analog processor are evaluated for floppiness. A normalized floppiness metric is calculated, and an offset is added to advance the device in annealing. Degeneracy in a hybrid computing system that comprises a quantum processor is mitigated by determining a magnetic susceptibility of a qubit, and tuning a tunneling rate for the qubit based on a tunneling rate offset determined based on the magnetic susceptibility. Quantum annealing evolution is controlled by causing the evolution to pause for a determined pause duration.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] field This disclosure generally relates to quantum processors and related systems, devices, methods, and articles. [Background technology]

[0002] background Quantum devices Quantum devices are structures in which quantum mechanical effects can be observed. Quantum devices include circuits in which current transport is governed by quantum mechanical effects. Such devices include spintronics and superconducting circuits. Both spin and superconductivity are quantum mechanical phenomena. Quantum devices can be used as measuring instruments in computing machines and other applications.

[0003] quantum computing A quantum computer is a system that directly utilizes at least one quantum mechanical phenomenon, such as superposition, tunneling, or entanglement, to perform operations on data. The elements of a quantum computer are qubits. By simulating quantum physics, quantum computers can speed up several classes of computational problems, including computational problems.

[0004] Quantum annealing Quantum annealing is a computational method that can be used to find the low-energy state of a system (usually, preferably the ground state of the system). (Classical simulated annealing) Conceptually similar, this method is based on the fundamental principle that "natural systems move towards lower energy states because those lower energy states are more stable." While classical annealing utilizes classical thermal fluctuations to induce a system in a low energy state, quantum annealing can utilize quantum effects such as quantum tunneling as a source of delocalization to reach an energy minimum more precisely and / or more quickly than classical annealing.

[0005] Quantum processors can be designed to perform quantum annealing and / or adiabatic quantum computation. The evolutionary Hamiltonian is proportional to the sum of the first term, which is proportional to the problem Hamiltonian, and the second term, which is proportional to the delocalization Hamiltonian, as follows: It can be constructed. H E ∝A(t)H P +B(t)H D Here, H E is evolved Hamiltonian, H P The problem is the Hamiltonian, H D is delocalized Hamilton It is a nian, where A(t) and B(t) are coefficients that control the evolutionary rate and are usually within the range [0,1].

[0006] In some embodiments, the time-varying envelope function can be placed on the problem Hamiltonian. A suitable delocalized Hamiltonian is given by:

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number

[0007] The general problem Hamiltonian may be of the following form, comprising a first component proportional to a diagonal single-qubit term and a second component proportional to a diagonal multi-qubit term:

number

Number formula

[0008] Here,

Number formula

[0009] Throughout this specification, the terms "problem Hamiltonian" and "final Hamiltonian" are used interchangeably unless the context indicates otherwise. Certain states of the quantum processor are energetically favored or simply favored by the problem Hamiltonian. These include the ground state, but may also include excited states.

[0010] H in the above two formulas D and H P Hamiltonians such as these can each be physically implemented in a wide variety of ways. A specific example is implemented by embodiments of superconducting qubits.

[0011] Superconducting quantum processor for quantum annealing A superconducting quantum processor may be designed for quantum annealing (and / or adiabatic quantum computing; see below) components that may be used to implement the present systems and methods. The superconducting quantum processor comprises a plurality of superconducting qubits and tunable coupling between qubits

Number formula

[0012] A quantum processor may include multiple interfaces used to configure and control the state of the quantum processor. Each interface may be realized by its respective inductively coupled structure as part of a programming subsystem and / or an evolution subsystem.

[0013] During the operation of the quantum processor, the interface couples the magnetic flux signal to the composite Josephson junction of each qubit, thereby allowing for tuning of the Δ i (Item) System Hami This can be used to realize it within the Rutonian. This bond is the off-diagonal σ of the Hamiltonian. x This provides the term. These flux signals are examples of "delocalized signals".

[0014] Similarly, the interface couples the magnetic flux signal into each qubit loop of the qubit, thereby h i The term can be used to realize within the system Hamiltonian. This bond is formed by the diagonal σ z The term is provided within the system Hamiltonian. Furthermore, the inter The face couples the magnetic flux signal into the coupler, thereby simulating J ij This can be used to realize the term within the stem Hamiltonian. This connection is diagonal.

number

[0015] A quantum processor may include a readout device that reads out the final state of a qubit. Examples of superconducting qubits include superconducting flux qubits and superconducting charge qubits.

[0016] Adiabatic quantum computing One model of quantum computing is adiabatic quantum computing. Adiabatic quantum computing is well-suited for solving, for example, hard optimization problems. It is possible. Adiabatic quantum computing can be considered a special case of quantum annealing. In adiabatic quantum computing, the system ideally begins and remains in its ground state through adiabatic evolution. Those skilled in the art will understand that quantum annealing systems and methods can generally be implemented on adiabatic quantum computers. Throughout this specification and the appended claims, any reference to quantum annealing is intended to encompass adiabatic quantum computing unless the context requires otherwise.

[0017] Hybrid computing systems including quantum processors A hybrid computing system may include a digital computer that is communicatively coupled to an analog computer. In some embodiments, the analog computer is a quantum computer and the digital computer is a classical computer.

[0018] A digital computer may include a digital processor that can be used to perform the classic digital processing tasks described in this system and method. A digital computer may include at least one system memory that can be used to store various sets of computer or processor-readable instructions, application programs and / or data.

[0019] A quantum computer may include a quantum processor that includes programmable elements such as qubits, couplers, and other devices. Qubits can be read out via a readout system, and the results can be transmitted to a digital computer. The qubits and couplers can be controlled by a qubit control system and a coupler control system, respectively. In some embodiments, the qubit and coupler control systems perform quantum annealing on an analog computer. It can be used to carry out the task.

[0020] Degeneracy In quantum mechanical systems, an energy level is said to be degenerate if it can correspond to two or more different measurable states. Two or more different states in a quantum mechanical system are said to be degenerate if they can correspond to the same energy level. A quantum binary number, known as a qubit, is a two-state quantum mechanical system. The two states are said to be degenerate if flipping a qubit from its first state to its second state does not affect the system's energy.

[0021] Degenerate operations in qubits Dickson and Amin (arXiv 1104.2349) proposed an auxiliary qubit (i.e., constrained). This describes a method to avoid perturbative crossings by adding ) to the Hamiltonian. Dickson and Amin describe the "single qubit tunneling energy We proved that a simple adiabatic quantum algorithm based on a penalty to clusters of path minima by tuning the parameters can be effective in resolving perturbative crossovers that create minima.

[0022] Dickson and Amin discussed how, if the final ground state is degenerate, the corresponding eigenstates are opposite to each other. This explains whether the excitation can deviate from the final state. If the degeneracy in the final ground state can be introduced without significantly affecting the excited states, the ground state energy can deviate from the excited state energy.

[0023] Boixo et al. (arXiv 1212.1739) describe a 17-fold degenerate ground state Hamiltonian that can be constructed from ferromagnetic 4 cycles by imposing auxiliary constraints on each of the four original qubits. [Overview of the project] [Means for solving the problem]

[0024] overview A method for mitigating degeneracy in a hybrid computing system including a quantum processor and a digital processor, wherein the quantum processor and the digital processor are communicatively coupled to each other, and the quantum processor includes multiple devices and is operated as a sample generator that provides samples, can be summarized as including: sending a problem to the quantum processor; drawing multiple samples by the quantum processor until a termination criterion is satisfied; returning multiple samples to the digital processor; initializing a sample counter; initializing a device counter until the sample counter reaches a predetermined sample limit; determining whether a device indexed by the device counter is floppy until the device counter reaches a first predetermined device limit; incrementing the device counter, and repeating this process; incrementing the sample counter; initializing the device counter; calculating a normalized floppiness metric for a device indexed by the device counter until the device counter reaches a second predetermined device limit; adding an offset to advance the device during annealing; and incrementing the device counter.

[0025] This method may further include determining whether a termination condition has been satisfied. Determining whether a termination condition has been satisfied may include completing a predetermined number of iterations, reaching a predetermined upper limit on the allowable computation time, or determining that the change in the energy of the solution to the problem between consecutive iterations is below a predetermined threshold. Mitigating degeneracy in a hybrid computing system may include mitigating degeneracy in a hybrid computing system that includes a superconducting quantum processor. Determining whether a device indexed by a device counter is floppy may include determining whether a superconducting qubit indexed by a device counter is floppy. Determining whether a superconducting qubit indexed by a device counter is floppy may include determining that "the change in energy of the solution to the problem is below a predetermined threshold when the state of the superconducting qubit is inverted." Determining whether a superconducting qubit indexed by a device counter is floppy may include determining the prevalence of zero net bias from neighboring devices. Calculating a normalized floppyness metric for a device indexed by a device counter may include summing the number of times the device has been determined to be floppy and dividing this by a predetermined sample limit. The first predetermined device limit may be the same as the second predetermined device limit. Drawing multiple samples with a quantum processor may include drawing at least 1000 samples with a quantum processor. Determining whether a device indexed by a device counter is a floppy disk may include determining whether a region of qubits indexed by the device counter is a floppy disk. A region of qubits may include multiple coupled qubits. Sending a problem to a quantum processor may include sending a difficult problem to a quantum processor.

[0026] The hybrid computing system includes at least one quantum processor including multiple devices and a read subsystem; at least one digital processor-based device communicatively coupled to at least one quantum processor; and at least one non-temporary computer-readable storage medium storing processor-executable instructions to mitigate degeneracy, wherein the at least one non-temporary computer-readable storage medium, when executed, causes at least one processor-based device to: send a problem to the quantum processor; until termination criteria are satisfied; extract multiple samples by the quantum processor; return multiple samples to the digital processor via the read system; and initialize a sample counter. This can be summarized as repeatedly performing the following steps: initializing the device counter until the sample counter reaches a predetermined sample limit; determining whether the device indexed by the device counter is a floppy disk until the device counter reaches a first predetermined device limit; and incrementing the device counter; incrementing the sample counter; initializing the device counter; calculating the normalized floppyness metric for the device indexed by the device counter until the device counter reaches a second predetermined device limit; adding an offset to advance the device during annealing; and incrementing the device counter.

[0027] A quantum processor can be a superconducting quantum processor, and multiple devices may contain multiple superconducting qubits, and the quantum processor may further contain multiple coupling devices, each coupling device may provide a controllable transfer coupling between each pair of superconducting qubits within the multiple superconducting qubits. At least one processor device can determine whether a superconducting qubit indexed by a device counter is floppy, at least in part on whether the change in energy of the solution to the problem is below a predetermined threshold when the state of the superconducting qubit is inverted. At least one processor device can determine whether a superconducting qubit indexed by a device counter is floppy, at least in part on the prevalence of zero net bias from neighboring devices. The normalized floppyness metric may be the number of times a device has been determined to be floppy divided by a predetermined sample limit. The first predetermined device limit may be the same as the second predetermined device limit. Multiple samples may include at least 1000 samples. End The criteria may include at least one of completing a predetermined number of iterations, reaching a predetermined upper limit on the allowable computation time, or determining that the change in the energy of the problem's solution between consecutive iterations is below a predetermined threshold. A device can be a region of qubits containing multiple coupled qubits, and at least one processor may determine whether a region of qubits indexed by a device counter is a floppy in order to determine whether a device indexed by a device counter is a floppy. The problem can be a difficult problem.

[0028] A method for mitigating degeneracy in a hybrid computing system including a quantum processor and a digital processor, wherein the quantum processor and the digital processor are communicatively coupled to each other, and the quantum processor includes multiple qubits and is operated as a sample generator that provides samples. The method can be summarized as including: receiving a computation problem with the quantum processor; generating one or more samples with the quantum processor based on the problem; determining the susceptibility of each of one or more qubits of the multiple qubits based on one or more samples; determining the tunneling velocity offset of at least one qubit of the one or more qubits based on the susceptibility of one or more qubits; and tuning the tunneling velocity of at least one qubit based on the tunneling velocity offset.

[0029] The method may further include determining a subset of qubits to be tuned based on a target susceptibility, wherein the susceptibility of each qubit in the subset differs from the target susceptibility by a threshold amount; and at least one qubit is included in the subset. Determining the susceptibility of one or more qubits includes measuring the magnetic response of one or more qubits to a magnetic flux bias. Determining the susceptibility of one or more qubits, for each of the one or more qubits, may include: generating one or more estimates of the qubit based on one or more samples; refining one or more estimates of the qubit; and determining the susceptibility of the qubit based on one or more estimates of the qubit.

[0030] Refining one or more estimates of a qubit may involve generating an initial estimate and iteratively generating another estimate based on the initial estimate and at least one of one or more previously generated estimates. Iteratively generating another estimate may involve generating another estimate based on a mean-field model. Each other estimate may involve an estimate of at least one of the qubit's current and the qubit's magnetic flux, and generating another estimate based on a mean-field model may involve generating at least one estimate based on the expected value of the isolated-qubit's current based on the qubit's magnetic flux.

[0031] Determining the susceptibility of one or more qubits in a group of qubits may involve determining the derivative of the flux-current relationship for each of the one or more qubits based on at least one of one or more estimations. Determining the tunneling velocity offset for at least one qubit may involve, for each of the at least one qubit: determining the target tunneling velocity at which the isolated qubit model predicts the susceptibility corresponding to the qubit's susceptibility; and determining the tunneling velocity offset based on the target tunneling velocity.

[0032] Determining the target tunneling velocity may include determining the sample target tunneling velocity for each sample, and determining the target tunneling velocity based on a measure of the sample target tunneling velocity. Determining the target tunneling velocity based on a measure of the sample target tunneling velocity may include determining the average value of the sample target tunneling velocity.

[0033] For each of at least one qubit, the tunneling velocity offset can be determined based on the difference between the qubit's target tunneling velocity and the measure of multiple target tunneling velocities. The measure of multiple target tunneling velocities may be the median of multiple target tunneling velocities. For each of at least one qubit, determining the target tunneling velocity may involve reducing the magnitude of the target tunneling velocity to less than that predicted by the isolated qubit model.

[0034] A method for operating a digital processor to tune the annealing speed of at least one qubit of a quantum processor can be summarized as comprising: receiving an encoding of the problem, which includes one or more qubits; modifying the encoding by representing one of the one or more qubits as a logical qubit, thereby producing a modified encoding of the problem, wherein the logical qubit includes a plurality of internal qubits of the quantum processor coupled by internal coupling, and the logical qubit has an effective tunneling speed reduced compared to the tunneling speed of the qubit before modification; and causing the quantum processor to compute the problem based on the modified encoding. The method may further comprise selecting at least one of the number of internal qubits and the internal coupling strength of the logical qubits such that the effective tunneling speed approximates a target tunneling speed. The qubits may include initial logical qubits. The method may further comprise selecting a topology in which the logical qubits affect the effective tunneling speed. Selecting this topology may comprise selecting this topology from a plurality of topologies based on the minimum internal coupling strength associated with each of a plurality of topologies.

[0035] This method may include correcting the effective tunneling velocity of a logic qubit by determining the tunneling velocity offset based on the characteristics of the logic qubit, and correcting the effective tunneling velocity of the logic qubit by applying the tunneling velocity offset to the annealing schedule. The logic qubit may have a chain topology, and the characteristics of the logic qubit may include the chain length. Determining the tunneling velocity offset may include determining a scaling factor and scaling the offset value by the scaling factor. The offset value can be based on the following equation: 2^(k-1) / (k-1) Here, k is the length of the chain topology of logical qubits. The encoding may include a multiplication circuit that embeds the factorization problem.

[0036] The characteristics may include the position of a logic qubit in the graph relative to one or more other qubits. The graph may include an embedding graph. Determining the tunneling velocity offset may include determining the distance between the logic qubit and the origin and / or the distance between the logic qubit and the edge of the graph, and determining the tunneling velocity offset based on this distance. The tunneling velocity offset may be determined based on a gradient defined with respect to at least a portion of the graph. The gradient may include a radial gradient having a first region close to the origin, where the annealing schedule proceeds with respect to the annealing schedule in a second region. The second region is further from the origin compared to the first region.

[0037] The effective tunneling speed of a logical qubit can be determined based on the annealing subschedule specific to the logical qubit and the annealing schedule defined across multiple qubits. At least one of the multiple qubits is not included in the logical qubit.

[0038] Selecting a topology from multiple topologies based on minimum internal coupling strength may include selecting a topology based on the correspondence between minimum internal coupling strength and the number of internal qubits coupled with qubits outside of logical qubits.

[0039] A method for operating a hybrid computing system including a quantum processor and a digital processor, wherein the quantum processor and the digital processor are communicatively coupled to each other, and the quantum processor includes a plurality of qubits, can be summarized as including: receiving a pause start and pause duration as inputs via a user interface to the digital processor; controlling a quantum annealing evolution performed by the quantum processor using the digital processor, including initiating the quantum annealing evolution; pausing the quantum annealing evolution for the pause duration upon reaching the pause start; and completing the quantum annealing evolution; and reading the state of the plurality of qubits by the hybrid computing system.

[0040] Receiving the start of a pause may include receiving a measure of progress through quantum annealing evolution. Receiving the start of a pause and the duration of the pause may include receiving the start of a pause and the duration of the pause via an application programming interface. Controlling quantum annealing evolution performed by a quantum processor with a digital processor may include controlling quantum annealing evolution performed by multiple superconducting flux qubits with a digital processor.

[0041] Pausing quantum annealing evolution for a pause duration may include selecting a subset of qubits, pausing quantum annealing evolution with respect to one or more qubits not present in the subset, and reverse annealing the subset of qubits while one or more qubits are paused. The method may also include forward annealing the subset of qubits after reverse annealing and before completing the quantum annealing evolution.

[0042] A method for operating a digital processor to mitigate degeneracy in a hybrid computing system including a quantum processor, wherein the quantum processor and the digital processor are communicatively coupled to each other, and the quantum processor includes a plurality of qubits and is operated as a sample generator providing samples, the method can be summarized as including: transmitting a problem for computation to the quantum processor; receiving one or more samples generated by the quantum processor based on the problem; determining the susceptibility of each of one or more qubits of the plurality of qubits based on one or more samples; determining the tunneling velocity offset of at least one qubit of the one or more qubits based on the susceptibility of one or more qubits; and tuning the tunneling velocity of at least one qubit based on the tunneling velocity offset.

[0043] The operation method of a hybrid computing system including a digital processor communicatively coupled to a physical quantum annealer containing multiple qubits involves: encoding a computational problem within a first subset of multiple qubits using the digital processor; weakly coupling a second subset of multiple qubits, which has no common parts with the first subset, to the first subset; determining the magnetic resonance tunneling (MRT) peak width using the qubits of the second subset; and determining the MRT peak width at least This can also be summarized as including adjusting the annealing schedule of the physical quantum annealer based on partial considerations.

[0044] Encoding a computational problem into a first subset of multiple qubits using a digital processor may include encoding the computational problem into a first subset of multiple superconducting qubits using a digital processor, and weakly coupling a second subset of multiple qubits to the first subset may include weakly coupling a second subset of multiple superconducting qubits.

[0045] A method for operating a hybrid computing system including a digital processor communicatively coupled to a physical quantum annealer can be summarized as including: collecting one or more energy statistics by parallel tempering by the physical quantum annealer; evaluating the expected results by the digital processor; and determining a preferred annealing rate and a preferred annealing trajectory by the digital processor, at least partially based on one or more energy statistics and the expected results.

[0046] The method may further include repeatedly determining the preferred annealing rate and preferred annealing trajectory by a digital processor, at least partially based on one or more energy statistics and expected results, until the change in the preferred annealing rate and preferred annealing trajectory between iterations falls below a predetermined threshold.

[0047] Determining a preferred annealing rate may involve inverting the cumulative distribution. Determining a preferred annealing orbit may involve performing a local search. Collecting one or more energy statistics by parallel tempering using a physical quantum annealer may involve collecting one or more energy statistics by parallel tempering using a superconducting quantum processor.

[0048] A method for operating a hybrid computing system including a digital processor communicatively coupled to a quantum processor can be summarized as including: transmitting a computational problem to the quantum processor by the digital processor; generating one or more samples by the quantum processor; collecting one or more samples by the digital processor; determining by the digital processor whether a qubit is floppy with respect to a sample; if it is determined that a qubit is floppy with respect to a sample, incrementing the count of floppy qubits by the digital processor; calculating a metric by the digital processor based at least in part on the count of floppy qubits; defining auxiliary qubits in the quantum processor by the digital processor; and coupling the auxiliary qubits to at least one of the floppy qubits in the quantum processor by the digital processor.

[0049] Sending a computational problem to a quantum processor may include sending the computational problem to a superconducting quantum processor. Sending a computational problem to a superconducting quantum processor may include sending the computational problem to a physical quantum annealer. Determining by a digital processor whether a qubit is floppy with respect to a sample may include determining by a digital processor whether a superconducting qubit is floppy. Calculating a metric by a digital processor based at least partially on a count of floppy qubits may include calculating a normalized floppyness metric that describes the portion of one or more samples in which a qubit is floppy. Coupled an auxiliary qubit to at least one of the floppy qubits in the quantum processor by a digital processor may include selecting the strength of the coupling between the floppy qubit and the auxiliary qubit to adjust the tunneling amplitude of the floppy qubit.

[0050] A method for operating a hybrid computing system including a digital processor communicatively coupled to a quantum processor containing multiple qubits includes: receiving a first bias value of the first qubit of the multiple qubits; coupling an auxiliary qubit to the first qubit; determining whether the modulus of the first bias value is less than or equal to a predetermined threshold; if it is determined that the modulus of the first bias value is less than or equal to the predetermined threshold: providing the auxiliary qubit with a second bias value that is a negative bias value and whose modulus is greater than the modulus of the first bias value; setting the coupling strength between the first qubit and the auxiliary qubit to be approximately equal to the first bias value; and providing the first qubit with zero bias. It can be summarized as including setting the parameters.

[0051] Receiving the first bias value of the first qubit among multiple qubits may include receiving the bias value of a superconducting qubit. Coupled an auxiliary qubit to the first qubit may include coupling a superconducting qubit to the first qubit. Determining whether the modulus of the first bias value is less than or equal to a predetermined threshold may include determining whether the modulus of the first bias value is 1 or less.

[0052] A method for operating a hybrid computing system including a quantum processor and a digital processor, wherein the quantum processor and the digital processor are communicatively coupled to each other, and the quantum processor includes a plurality of qubits, can be summarized as: a method for receiving an annealing schedule by the digital processor; a method for controlling a quantum annealing evolution performed by the quantum processor by the digital processor, which includes initiating the quantum annealing evolution, performing the quantum annealing evolution at least partially based on the annealing schedule, and completing the quantum annealing evolution; and a method for reading the state of the plurality of qubits by the hybrid computing system, wherein the receiving of the annealing schedule by the digital processor includes receiving, for each qubit of the plurality of qubits, at least one of the respective tunneling rate or the respective persistent current as a single-valued function of time.

[0053] Receiving an annealing schedule by a digital processor may include receiving a first annealing schedule for a first subset of qubits of a plurality of qubits, the first annealing schedule including receiving, for each qubit of the first subset, at least one of a first tunneling velocity or a first persistent current as a single-valued function of time, and receiving a second annealing schedule for a second subset of qubits of a plurality of qubits, the second annealing schedule including receiving, for each qubit of the second subset, at least one of a second tunneling velocity or a second persistent current as a single-valued function of time, and performing quantum evolution at least partially based on the annealing schedule includes performing quantum evolution of the qubits of the first subset at least partially based on the first annealing schedule and performing quantum evolution of the qubits of the second subset at least partially based on the second annealing schedule. In some embodiments, each of the first and second subsets of qubits may include their respective first and second logical qubits.

[0054] Receiving an annealing schedule via a digital processor may include receiving a vector as a single-valued function of time. Receiving an annealing schedule via a digital processor may include receiving transverse and longitudinal energy measures as single-valued functions of time. Receiving an annealing schedule via a digital processor may include receiving a piecewise linear annealing schedule.

[0055] A method for operating a hybrid computing system including a quantum processor and a digital processor, wherein the quantum processor and the digital processor are communicatively coupled to one another, the quantum processor includes a plurality of qubits and a plurality of coupling devices, each of the plurality of coupling devices selectively communicatively coupling each pair of qubits, the method comprising: receiving an annealing schedule by the digital processor; controlling a quantum annealing evolution performed by the quantum processor by the digital processor, which includes: initiating the quantum annealing evolution; performing the quantum annealing evolution at least partially based on the annealing schedule; and completing the quantum annealing evolution. The readout can be summarized as including control and reading the state of multiple qubits by a hybrid computing system, receiving the annealing schedule by a digital processor, receiving the local bias for each qubit of the multiple qubits as a single function of time, and receiving the coupling strength for each coupled device of the multiple coupled devices as a single function of time.

[0056] A method for selecting an annealing schedule for a problem in a hybrid computing system including a quantum processor and a digital processor. The quantum processor and the digital processor are coupled to each other in a communicative manner. The quantum processor contains multiple qubits. The method can be summarized as including: generating one or more annealing schedules; receiving input annealing schedules and selecting an annealing schedule from one or more annealing schedules based on an objective function that provides a measure of at least one property of the input annealing schedules; transmitting the problem to the quantum processor via the digital processor; and executing the problem in the quantum processor according to the annealing schedule.

[0057] This method may involve selecting an objective function from a set of one or more objective functions. Generating one or more annealing schedules may involve performing an optimization algorithm based on the objective function. The optimization algorithm may include parallel tempering. The objective function may measure at least one of the models and the chains linking the models, which are generated by applying parallel tempering to the problem modified by the input annealing schedule. The objective function may at most involve calculating a threshold number of parallel tempering iterations. The threshold number may be less than the number of iterations required to solve the problem.

[0058] The optimization algorithm may include Bayesian optimization. The objective function may measure the ground state distribution of the problem according to the input annealing schedule. The objective function may provide at least one of the following: a measure of similarity between ground state distributions and a property of one or more outliers of the ground state distributions. The objective function may measure the entropy of the ground state distribution, the distance of the ground state distribution from a uniform distribution by a distance metric, the Gini coefficient of the ground state distribution, and / or the ratio of the maximum probability to the minimum probability of the ground state distribution.

[0059] Selecting an annealing schedule from one or more annealing schedules may include determining that an annealing schedule provides the best results compared to one or more other annealing schedules. Generating one or more annealing schedules may include generating multiple annealing schedules, selecting a provisional annealing schedule based on an objective function, and generating one or more annealing schedules based on the provisional annealing schedule.

[0060] A method for mitigating sample bias in a hybrid computing system including an analog processor and a digital processor, wherein the analog processor and the digital processor are communicatively coupled to each other, and the analog processor includes multiple qubits, can be summarized as including: transmitting a computation problem to an analog processor by the digital processor; generating one or more samples of a first set by the analog processor; collecting one or more samples of the first set by the digital processor; identifying one or more valleys, each containing a set of isoenergy samples, based on one or more samples of the first set; selecting one of the one or more valleys based on valley selection criteria; for each qubit in the valley: determining the degeneracy metric of the qubit; determining the annealing schedule of the qubit based on the degeneracy metric; and collecting one or more samples of a second set by the analog processor based on the annealing schedule of the qubits in the valley.

[0061] Identifying one or more valleys may involve determining that multiple qubits are related by a series of iso-energy qubit inversions. Identifying one or more valleys may involve determining the membership of multiple qubits based on the iso-energy Hamming distance metric. This may include determining the following: Selecting one valley from one or more valleys may include selecting a valley that has at least the same number of samples as each of the other valleys, based on the number of samples in one or more samples within the valley. The degeneracy metric may include the normalized floppyness metric. Determining the degeneracy metric of a qubit may include determining the normalized floppyness metric of a qubit based on the number of times the qubit was floppy within the samples of the valley.

[0062] Determining a qubit annealing schedule based on a degenerate metric may include determining that the annealing offset is proportional to the degenerate metric. Determining a qubit annealing schedule based on a degenerate metric may include advancing the qubit to the start of annealing. Advancing a qubit to the start of annealing may include delaying at least one other qubit so that at least one other qubit begins annealing after the qubit has completed its annealing. Determining a qubit annealing schedule based on a degenerate metric may include delaying the qubit to the end of annealing. At least one qubit in the valley may include a region of qubits.

[0063] The method according to claim 101 may include: identifying one or more other valleys, each containing a set of isoenergy samples, based on one or more samples from a second set; selecting another valley from one or more other valleys based on valley selection criteria; for each qubit in another valley: determining a different degeneracy metric for the qubit; determining a different annealing schedule for the qubit based on the degeneracy metric; and collecting one or more samples from a third set by an analog processor based on a different annealing schedule for the qubits in another valley.

[0064] Determining a qubit annealing schedule based on a degenerate metric may involve generating multiple annealing schedules and selecting one annealing schedule from those multiple schedules based on one or more selection criteria. Generating multiple annealing schedules may involve generating a first annealing schedule and generating multiple scaled annealing schedules based on multiple scaling factors.

[0065] A method for controllably simulating noise in an annealing schedule used in a hybrid computing system, the hybrid computing system comprising an analog processor and a digital processor, the analog processor and the digital processor being communicatively coupled to one another, can be summarized as comprising: receiving an input annealing schedule in the digital processor; generating pseudo-noise; modifying the input annealing schedule based on the pseudo-noise to generate an output annealing schedule; and providing the output annealing schedule to the analog processor.

[0066] Generating pseudo-noise may involve generating one or more pseudo-random modifications to be applied to the input annealing schedule. Generating pseudo-noise may involve generating one or more annealing pauses and one or more annealing ramps. One or more annealing pauses and ramps may be ordered as alternating pairs of pauses and ramps.

[0067] Generating pseudo-noise may involve applying one or more modifications to the pseudo-noise based on one or more constraints. One or more constraints may include requiring that the output annealing schedule deviates from the input annealing schedule by a threshold amount or less. The threshold amount may change over time and may be based on the time-dependent amplitude of the input annealing schedule. The threshold amount may be a predetermined constant. Applying one or more modifications may involve, for each modification, determining at least one of the amplitude and duration of the modification in a pseudo-random manner according to one or more constraints.

[0068] Brief explanation of the drawing In the attached drawings, the same reference number identifies similar elements or actions. The dimensions and relative positions of elements in the attached drawings are not necessarily drawn to scale. For example, the shapes and angles of various elements are not necessarily drawn to scale, and some of these elements are arbitrarily enlarged and positioned to improve the readability of the drawings. Furthermore, the specific shapes of the elements depicted are not necessarily intended to convey any information about the actual shape of the element, but were selected for ease of recognition in the attached drawings. [Brief explanation of the drawing]

[0069] [Figure 1A] This flowchart illustrates an exemplary method of operating a hybrid computing system including a quantum processor for mitigating degeneracy via "floppy qubits" using the System, Devices, Articles, and Methods. [Figure 1B] This flowchart illustrates an exemplary method of operating a hybrid computing system including a quantum processor for mitigating degeneracy via "floppy qubits" using the System, Devices, Articles, and Methods. [Figure 2] This flowchart illustrates exemplary operating methods for a hybrid computing system including a quantum processor for mitigating degeneracy through magnetic susceptibility by the system, devices, articles, and methods. [Figure 3] This plot shows that tuning the tunneling speed Δi can advance or delay the per-qubit annealing schedule. [Figure 4] This flowchart illustrates an exemplary operation method of a hybrid computing system including a quantum processor for mitigating degeneracy through the measurement of qubit evolution by this system, device, article, and method. [Figure 5] This is a flowchart illustrating an exemplary method for determining magnetic susceptibility. [Figure 6] This plot shows comparative results of exemplary implementations of degeneracy mitigation in quantum processors using this system, device, article, and method. [Figure 7] This plot shows comparative results of exemplary implementations of degeneracy mitigation in quantum processors using this system, device, article, and method. [Figure 8] This plot shows comparative results of exemplary implementations of degeneracy mitigation in quantum processors using this system, device, article, and method. [Figure 9] This plot shows comparative results of exemplary implementations of degeneracy mitigation in quantum processors using this system, device, article, and method. [Figure 10] This plot shows comparative results of exemplary implementations of degeneracy mitigation in quantum processors using this system, device, article, and method. [Figure 11A] This graph shows an exemplary annealing scenario with no pauses within the annealing schedule. [Figure 11B] This graph illustrates an exemplary annealing scenario that includes pauses within the annealing schedule. [Figure 11C] This graph illustrates an exemplary annealing scenario with an intermediate annealing ramp within the annealing schedule. [Figure 11D] This graph illustrates an exemplary annealing scenario using an annealing schedule operation that includes intermediate annealing pauses and intermediate annealing ramps within the annealing schedule. [Figure 11E] This graph illustrates an exemplary annealing scenario in which the local bias h of a qubit is changed during evolution. [Figure 11F] This graph illustrates an exemplary annealing scenario in which the coupling strength J of the coupling device between a pair of qubits changes during evolution. [Figure 12] This flowchart illustrates an exemplary method of operating a hybrid computer to adjust the quantum annealing schedule. [Figure 13] This flowchart illustrates an exemplary method for adjusting the annealing schedule based on equilibrium energy statistics. [Figure 14]This flowchart illustrates an exemplary method for mitigating the effects of degeneracy using auxiliary qubits. [Figure 15] This flowchart shows an exemplary method for mitigating h / J mismatch using an auxiliary qubit. [Figure 16] This is a schematic diagram of an exemplary hybrid computing system, which includes a digital computer coupled to an analog computer. [Figure 17] This is a schematic diagram of a portion of an exemplary superconducting quantum processor designed for quantum annealing (and / or adiabatic quantum computing) components that may be used to realize this system and device. [Figure 18] This is a schematic diagram of exemplary gradients defined on a graph, including Chimera-structured groups of qubits, by this system, device, article, and method. [Figure 19] This flowchart illustrates an exemplary method for annealing scheduling operations of logical qubits using this system, device, article, and method. [Figure 20] This flowchart illustrates an exemplary method for selecting an annealing schedule for a problem based on its objective function. [Figure 21] This flowchart shows an exemplary method for mitigating sampling bias. [Figure 22] This graph illustrates an exemplary annealing scenario in which noise is controlled and simulated and added to the input annealing schedule. [Modes for carrying out the invention]

[0070] General comments The following description includes several specific details to fully understand the various disclosed embodiments. However, those skilled in the art will recognize that embodiments may be carried out without one or more of these specific details, or by other methods, components, materials, etc. In other examples, well-known structures relating to quantum processors, couplers, and control systems including microprocessors and drive circuits, such as quantum devices, have not been shown or described in detail so as not to unnecessarily obscure the description of embodiments of the Method. Throughout this Specified and the accompanying claims, the terms “elements” and “group of elements” are used to encompass, but not limit, all such structures, systems, and devices relating to quantum processors and the programmable parameters associated therewith.

[0071] Unless otherwise required by context, throughout the following specification and claims, the term “including” and its conjugations shall be interpreted as having an open, inclusive meaning, i.e., “not limiting, but including.”

[0072] Throughout this specification, references to “one embodiment,” “embodiment,” “another embodiment,” “an example,” “example,” and “another example” mean that the specific reference features, structures, or characteristics described in relation to that embodiment or example are included in at least one embodiment or example. Therefore, occurrences of phrases such as “in one embodiment,” “in an embodiment,” or “in another embodiment” in various places throughout this specification do not necessarily all refer to the same embodiment. This does not necessarily refer to a state or example. Furthermore, specific features, structures, or characteristics may be combined in any preferred manner in one or more embodiments, examples, or implementations.

[0073] Note that, as used in this specification and the appended claims, singular and indefinite articles include multiple references unless otherwise specified. Therefore, for example, a reference to a problem-solving system including a "quantum processor" includes a single quantum processor or two or more quantum processors. It should also be noted that the term "or" is generally used to include "and / or" unless otherwise explicitly specified.

[0074] The subtitles provided herein are for convenience only and do not imply any interpretation of the scope or meaning of the embodiments.

[0075] Tunneling speed and degeneracy At least some quantum processors utilize the tunneling behavior of qubits to find the low-energy state of a problem encoded on the processor. The tunneling behavior is Δ i The single-qubit tunneling splitting parameter (also called the "tunneling velocity" or "annealing velocity" of the qubit) can be described for each qubit, represented by Δ. i It usually decreases over the annealing process. During the evolutionary process, a qubit may reach a low value that makes it highly resistant to changing its state, and therefore cease interacting with the problem. This behavior is called "freezing," and a frozen qubit can be thought to be effectively fixed for the remainder of its evolution.

[0076] Various qubits can be frozen at different times, and individual qubits can exhibit different tunneling behaviors in different problems. Typically, the tunneling speed Δ is slow. i Quantum Bits have a relatively fast tunneling speed Δ i Evolving faster than qubits that have It freezes. When different qubits in the same problem have different tunneling rates, the problem tends to exhibit degenerate-related behavior that tends to reduce the optimality of the generated solution. This behavior may include, for example, small-gap avoided level crossings and / or Landau-Zener transitions.

[0077] The techniques described herein are methods for mitigating degeneracy by tuning the tunneling speed, either directly or indirectly. Such techniques can, in preferred circumstances, significantly improve hardware performance for problems vulnerable to degeneracy and / or improve hardware performance for a wider set of general problems.

[0078] The impact of degradation on hardware performance In low-precision problem sets, experiments demonstrated a strong dependence of hardware performance on the parity of the qubits (i.e., the number of active couplers per qubit). In particular, for large sets of low-precision problems, even at the C2 scale, performance data can present "fat tails." The term "fat tails" refers to the hardware's performance. This refers to a particularly difficult set of low-precision problems. Fat tails may include problem instances that generate slow, low-energy solutions and / or problems that cannot generate low-energy solutions at all.

[0079] The behavior of problem sets in fat tails appears to be strongly related to degeneracy. Specifically, problems having a low-degenerate ground state and a high-degenerate first excited state seem to be at least partially responsible for fat tails.

[0080] One approach is to reduce the problem energy scale of difficult problems. C2 and C4 Regarding scaling problems, hardware performance for difficult problems can be improved by reducing the energy measure of the applied J by a coefficient of 2 × to 5 ×.

[0081] Unfortunately, reducing the problem energy scale of a difficult problem can have adverse effects. For example, reducing the energy scale can increase the impact of analog control errors, some of which do not scale down with the problem scale. Reducing the energy scale can also increase the effective temperature of the bathtub in which the qubits are coupled. These effects, among others, can reduce hardware performance at a given processor scale. Furthermore, reducing the energy scale can reduce desirable quantum behavior.

[0082] At least some embodiments of the technology described in this application provide methods that can not only significantly improve hardware performance for fat-tail problems but also improve hardware performance for a wider range of common problem sets.

[0083] Mitigating degeneracy via "floppy qubits" A "floppy qubit" is a qubit whose state can be reversed without any change in energy. Similarly, a floppy region is a set of multiple coupled qubits, all of which can be reversed simultaneously or all at once without any change in energy. In this specification, the term "floppy qubit" includes either a floppy qubit or a floppy region unless the context indicates otherwise.

[0084] For some problem instances, such as “fat tail” problem instances, there may be large isoenergy clusters of excited states that differ from each other by only a few qubit flips (e.g., one-qubit flips or two-qubit flips). The qubits responsible for movement around such isoenergy clusters are called “floppy” qubits. The technique described in this application uses a local major bias DA converter (DAC) to advance (or delay) the floppy qubits relative to the rest of the working graph during quantum annealing. In one embodiment, the local major bias DAC may bias a qubit compound-compound Josephson junction (CCJJ) main loop.

[0085] Figures 1A and 1B are flowcharts illustrating exemplary methods 100 for operating a hybrid computing system including a quantum processor to mitigate the degeneracy of the present system, device, article, and method. Figure 1A is a flowchart showing the first part 100a of exemplary method 100, and Figure 1B is a flowchart showing the second part 100b of exemplary method 100. Control of method 100 may move from the first part 100a to the second part 100b, and vice versa.

[0086] The operation method 100 shown in Figures 1A and 1B comprises several actions. One or more of these actions may be performed by (or via) one or more circuits, such as one or more processors (e.g., digital processors), analog processors such as quantum processors, or a hybrid computer that includes both digital and analog processors. For the purposes of describing Figures 1A and 1B, it is assumed that the actions are performed by a hybrid computer that includes a quantum processor. The first part 100a and the second part 100b of the method 100 are illustrative, and those skilled in the art will recognize that alternative embodiments may omit some actions and / or include additional actions.

[0087] Referring first to Figure 1A, the first part 100a of method 100 begins at 105, for example, in response to the submission of a problem or a call by another routine. At 110, the hybrid computer sends the problem to the hardware. For the purposes of this example, the hardware The wearer is a quantum processor that is communicatively coupled to a digital computer. In 115, the hybrid computer collects many samples. In some embodiments, the number of samples N is approximately 1000. In other embodiments, the number of samples N is 10. In actions 120-145 (including 120 and 145), the hybrid computer records for each of the N samples which of the M qubits in the quantum processor is the floppy disk.

[0088] At 120, the hybrid computer initializes the sample exponent, and at 125, the hybrid computer initializes the qubit exponent.

[0089] At step 130, the hybrid computer determines whether the qubit or region of qubits is a floppy disk (i.e., whether the state of the qubit or region of qubits can be reversed without changing its energy). If it determines at step 130 that the qubit or region of qubits is a floppy disk ("yes"), control in the first part 100a proceeds to step 135, where the floppy qubit or region of floppy qubits is recorded. If it determines at step 130 that the qubit or region of qubits is not a floppy disk ("no"), control in the first part 100a proceeds to step 140.

[0090] At step 140, the hybrid computer determines whether another qubit or region of qubits exists to check for floppyness. Depending on whether it determines at step 140 that another qubit exists ("yes"), control in the first part 100a returns to step 130. The loop from 130 to 145 is repeated until there are no more qubits or regions of qubits to check for floppyness.

[0091] This process can be repeated as long as there are further qubits or regions of qubits to check for floppyness. Depending on whether it is determined at 140 that there are no more qubits or regions of qubits to check for floppyness ("no"), control of the first part 100a moves to 145, where the hybrid computer checks if there are any other samples. Depending on whether it is determined at 145 that there are any other samples ("yes"), control of the first part 100a returns to 125. The loop from 125 to 145 is repeated until there are no more samples.

[0092] If it is determined at step 145 that no more samples exist ("no"), the control of method 100 proceeds to the second part 100b in Figure 1B.

[0093] At step 150, the hybrid computer initializes the qubit exponents. At step 155, the hybrid computer calculates the normalized floppyness metric for the current qubit or the region of the current qubit. Normalized floppyness metric μ for the i-th qubit i An illustrative definition of is as follows:

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[0094] In 160, the hybrid computer is based on the normalized floppyness metric. During quantum annealing, the current qubit or region of qubits is advanced. Advancing a qubit (or region of qubits) can be done in one of several ways, as will be described in more detail elsewhere in this specification. For example, in some embodiments, advancing a qubit or region of qubits involves adding an offset proportional to the normalized floppyness metric to the main loop (annealed) DAC. If it is a region of qubits, the offset is applied to all member qubits of the region of qubits. In exemplary embodiments where the qubits are flux qubits, the offset is μ i × It is equal to 2.5mΦ0.

[0095] At step 165, the hybrid computer determines whether there is another qubit or region of qubits to which the offset should be applied. Depending on whether it determines at step 165 that there is another qubit or region of qubits ("yes"), control in the second part 100b returns to step 155. The loop from 155 to 165 is repeated until there are no more qubits or regions of qubits to which the offset should be applied.

[0096] In response to determining at 165 that no more qubits or regions of qubits exist ("no"), control of the second part 100b moves to 170. At 170, the hybrid computer determines whether the termination criteria have been satisfied. The termination criteria may be a single criterion or a combination of two or more criteria. Exemplary criteria may include thresholds based on sample diversity, sample energy, degree or rate of convergence, and the number of unique ground states or first excited states. Exemplary criteria may also include thresholds based on computation time and the number of iterations.

[0097] If it is determined at 170 that the termination criteria have been met ("yes"), method 100 terminates at 175. If it is determined at 170 that the termination criteria have not been met ("no"), the control of method 100 returns to 115 in the first part 100a of Figure 1A.

[0098] In some embodiments, the hybrid computer advances only a subset of floppy qubits. Generally, a qubit or region of qubits is either floppy in a certain percentage of the samples drawn, rarely floppy in any sample, or rarely floppy in all samples. The floppyness metric (described above) can be used to determine which qubits or regions of qubits are floppy and which qubits should be advanced. In some embodiments, qubits or regions of qubits exceeding a threshold for the floppyness metric may be advanced. In other embodiments, other criteria themselves may be used, or in conjunction with the floppyness metric, to determine which qubits or regions of qubits should be advanced.

[0099] In some embodiments, the hybrid computer may employ an iterative approach in which a qubit or region of qubits is advanced and repeated within a small subset. In some embodiments, the hybrid computer may choose to advance only the most floppy qubit or region of qubits in each iteration. In other embodiments, the hybrid computer may perform a preferred combination of the embodiments described above to advance a qubit or region of qubits. The benefit of advancing and iterating with a small number of qubits or regions of qubits is that the approach can reduce overcorrection.

[0100] In some embodiments, the offset applied to each qubit or region of each qubit may be the same. In other embodiments, the offset applied to various qubits or regions of various qubits may be the same. The offset applied to a region can vary for each qubit. For example, a hybrid computer might choose to apply a large offset to one qubit or a region of one qubit rather than to a region of another qubit or another qubit.

[0101] Mitigation of degeneracy via magnetic susceptibility In some embodiments, the qubit is a quantity based on the magnetic susceptibility (represented by χ, and sometimes simply referred to as "susceptibility" herein) of the qubit. The susceptibility χ can be advanced or delayed during sub-annealing. The susceptibility χ is a property of several types of qubits (including flux qubits) that describes the degree of magnetization of a qubit in response to an applied magnetic field. This response can vary under various circumstances (e.g., depending on the strength and topology of its coupling with other qubits and the flux bias of other qubits). Therefore, the susceptibility χ of a qubit can differ for different problems. In some embodiments, the susceptibility χ of one or more qubits for a particular problem is measured and / or estimated, and at least one of the one or more qubits is advanced or delayed based on its susceptibility χ. For convenience, reference in this disclosure to "determine" the susceptibility includes measuring and / or estimating the susceptibility.

[0102] The inventors have found that the magnetic susceptibility χ of a qubit is equal to the tunneling velocity Δ of the qubit. i In opposite phase Experiments have shown that there is a tendency for association to occur. That is, qubits that freeze first during evolution (i.e., low Δ) i A qubit that reaches its target quickly has a high magnetic susceptibility χ. There is a tendency for qubits to freeze after evolution (i.e., low Δ). i A quantity that slowly reaches The child bits tend to have a relatively low susceptibility χ.

[0103] Figure 2 shows the tunneling velocity Δ of one or more qubits. i Exemplary methods for tuning This is a flowchart of method 200. Method 200, as shown in Figure 2, involves several actions. One or more of these actions may be performed by (or via) one or more circuits, such as one or more processors (e.g., digital processors), analog processors such as quantum processors, or a hybrid computer that includes both digital and analog processors. For the purposes of explaining Figure 2, it is assumed that the actions are performed by a hybrid computer that includes a quantum processor. Method 200 is illustrative. Those skilled in the art will recognize that alternative embodiments may omit some actions and / or include additional actions.

[0104] In 202, the problem is received by the hybrid computer and encoded on the quantum processor. In 204, the hybrid computer collects one or more samples based on the encoded problem. The hybrid computer may collect any number of samples depending on the requirements of various other actions of method 200 (for example, depending on the number of samples required to determine the susceptibility of one or more qubits in 206). For example, in some embodiments, the number of samples collected is 1. In another example, in other embodiments, the number of samples collected is 1000.

[0105] In 206, the susceptibility χ of one or more qubits is determined by a hybrid computer. Various methods can be used to determine the susceptibility χ of each qubit. For example, the susceptibility χ of each qubit can be measured by directly measuring the magnetization response of each qubit to a magnetic flux bias. Alternatively, the susceptibility χ of each qubit can be estimated based on a numerical method applied to one or more samples (and / or other data). Several methods for determining the susceptibility χ of one or more qubits are discussed in more detail below, but those skilled in the art will understand that other methods may be used alternatively or additionally.

[0106] In some embodiments, the susceptibility χ is measured directly. This is used, for example, in a quantum processor to perform the evolution of the first set of qubits in question, along with the flux bias Φ of one or more qubits. X That's strange This can be done in situ by instructing the system to perform the evolution of a second set of problems to be modified. Next, the difference in the resulting magnetization responses of one or more qubits between the first and second sets can be measured to determine the susceptibility χ of each of the one or more qubits. For example, the susceptibility χ is the flux bias Φ between the evolutions of the first and second sets. X Permanent current I in response to changes P It can be proportional to the change in . Here, each of the first and second sets of evolutions includes multiple evolutions, thereby providing multiple sample measurement results and the persistent current I P The mean (or other estimators) and / or magnetic flux bias Φ X The following can be used. For example, the magnetic susceptibility χ of a qubit is based on the following equation. Possible to judge:

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[0107] Quantum bit magnetic flux bias ΦX Fixing this will correct the problem during the calculation, so evolution Modifying fewer qubits is likely to yield results that more accurately describe the original problem. In some embodiments, the flux bias Φ of just one qubit is used. X This is changed in each set of evolutions, and therefore multiple sets of evolutions (and thus more time) are required to determine the susceptibility χ of multiple qubits. In some embodiments, the flux bias group {Φ} of multiple qubits is changed in each set of evolutions. X} is changed in a given evolution, and to this This reduces the number of evolutionary sets required (though it may result in a loss of precision compared to single-qubit measurements in some cases). In some embodiments, a global flux bias Φ is applied uniformly to all qubits of the processor in the evolution of a second set.

[0108] The evolution of the first and second sets may occur in any order, or may be optionally interleaved (for example, the evolution of the second set may occur during the evolution of the first set, and / or vice versa). In some embodiments, each of the evolutions of the first and / or second sets includes a single evolution. In some embodiments, each of the evolutions of the first and / or second sets includes multiple evolutions. The evolutions of the first and second sets may include different numbers of evolutions.

[0109] In some embodiments, the susceptibility χ is estimated, for example, through post-processing techniques. For example, in some embodiments, the susceptibility χ of one or more qubits is estimated via a mean-field method (for example, via some embodiments of the susceptibility estimation method shown in Figure 5). .

[0110] In 208, one or more subsets D of qubits are arbitrarily selected for tuning. Such subset D may have, for example, a target susceptibility χ. T This refers to the threshold quantity T. It may include one or more qubits having different magnetic susceptibility χ. That is, a qubit X having magnetic susceptibility χ may be included in subset D if the following inequality is satisfied: |χ-χ T |>T

[0111] In some embodiments, the target magnetic susceptibility χ T This is based on the magnetic susceptibility χ of one or more qubits. For example, the target magnetic susceptibility χ T This is the mean, median, or maximum value of the magnetic susceptibility χ of one or more qubits. It may be determined to be a frequency. T may be a predetermined and / or user-provided value. Alternatively or in addition, T may be the susceptibility χ of one or more qubits and / or the target susceptibility χ T This can be determined based on the following: For example, T is the target magnetic susceptibility χ. T It can be a certain percentage (for example, 0.1χ T , 0.5χ T , 1.0χ T (or any other suitable value).

[0112] As another example, subset D is a set of N qubits with ultimate susceptibility χ (e.g., |χ-χ). T We recognize the N qubits (where N is a positive integer) that maximize | It can be determined by separating them.

[0113] In some embodiments, only the qubits to be advanced are included in subset D. In some embodiments, only the qubits to be delayed are included in subset D.

[0114] In 210, the Δ tuning offset ω is determined for each qubit in D. This offset can be determined in various ways, and Δ is determined for each qubit. i To tune it Therefore, it may depend at least in part on the method taken in 212. In some embodiments, the qubit has an approximately equivalent tunneling velocity Δ i It is tuned to have, As a result, the qubits freeze almost simultaneously (such qubits are said to be "synchronized"). In some embodiments, the Δ-tuning offset ω of a particular qubit X is equal to the susceptibility χ of qubit X and the threshold susceptibility χ. T It is judged based on the normalized difference with respect to ΔTu. The ming offset ω can be determined according to the following equation.

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[0115] In 212, the tunneling rate Δ per qubit of subset D i is a qubit It is tuned according to the associated Δ tuning offset ω. As discussed elsewhere in this specification, for example, the DA converter (DAC) offset for compound-compound Josephson junctions (CCJJs) of qubits is modified. By correcting, by forming logical qubits, and so on, Δ i Tuning There are various ways to do this. In some embodiments, the tunneling rate Δ per qubit of subset D i It is scaled in proportion to the Δ tuning offset ω. For example, offset ω = 0.2 is the Δ of the qubit. i This can accommodate an increase of approximately 20% (therefore (This slows down the annealing speed of the qubit and delays freezing), while offset ω=0.1 is the Δ of the qubit. i This can accommodate an increase of approximately 10% (and therefore, qubit annealing) (Increase the ring velocity and accelerate freezing). For example, each qubit in subset D is given by the following equation New Δ i It may be given: Δ new =(1+ω)Δ old Here, Δ oldis Δ of the qubit prior to Δ tuning i and Δ new is Δ tuning Δ of the qubit after i .

[0116] Figure 3 shows a chart illustrating an exemplary Δ tuning scenario. The vertical axis corresponds to the instantaneous tunneling rate Δ of a given qubit. The horizontal axis corresponds to time, and in particular corresponds to progress in evolution, represented by s. Line 302 corresponds to the tunneling rate of an exemplary qubit (not shown), and point 304 is the initial tunneling rate Δ of the qubit i shows. 0 corresponds to a scenario where the evolution of an exemplary qubit is delayed by applying an offset 312, which may for example be represented by a positive number, resulting in an initial tunneling rate Δ corresponding to point 314 i . , which may be represented by a negative number), corresponding to a scenario where the evolution of an exemplary qubit is advanced by applying the offset, resulting in an initial tunneling rate Δ corresponding to point 324 i . In the scenario of line 310, the evolution of the qubit freezes later than it would originally freeze (that is, in the pre-Δ tuning scenario corresponding to line 302). In the scenario of line 320, the evolution of the qubit freezes earlier than it would originally freeze.

[0117] Returning to FIG. 2, at 214, the hybrid computer performs computation on the problem, which may have been modified by the Δ tuning operation at 212, and determines a solution.

[0118] Estimation of magnetic susceptibility In some embodiments, the magnetic susceptibility of a qubit is estimated by using a model to infer one or more properties of the qubit and estimate the magnetic susceptibility of the qubit based on those properties. Such estimation of magnetic susceptibility may be used, for example, at 206 of method 200. As discussed in further detail below, models that may be used in such estimation include, but are not limited to, mean-field models.

[0119] FIG. 5 is a flowchart of an exemplary magnetic susceptibility determination method 500. At 502, a sample

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[0120] At 504, an initial estimation or guess regarding one or more characteristics of a qubit is obtained from a sample

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[0121] ​ In 505, the initial estimate is refined in order to generate a refined estimate using a circuit system. For example,

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[0122] In some embodiments, the estimation is based on the magnetic flux Φ applied to the superconducting quantum processor and the Debye This can be refined by utilizing a clear relationship with the derived current I flowing within the superconducting quantum processor. For example, for at least some superconducting quantum processors, the equilibrium state of the processor can be the following set of coupling equations:

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[0123] In some embodiments,

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[0124] In some embodiments,

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[0125] In some embodiments,

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[0126] In some embodiments,

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[0127] Based on the above description, the inventors of the present invention have made the following determination. In such an embodiment, the expected value of the persistent current of an isolated qubit (⟨I p ⟩) can be determined based on the following formula: [Mathematical formula] Here, k B is the Boltzmann constant. Therefore, the estimated [Mathematical formula] can be generated by a circuit system by calculating its element I i according to the following formula: [Mathematical formula] Here, Φ i is [Mathematical formula] is the i-th element of.

[0128] In some embodiments, the temperature T is modeled as a restriction that it is close to zero. This can be done, for example, by omitting the tanh term from the above equation. Temperature may be considered separately (e.g., through a subsequent adjustment step) or not considered at all.

[0129] In some embodiments,

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[0130] Magnetization rate of each qubit

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[0131] In 506, the estimated problematic magnetic susceptibility

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[0132] In some embodiments, the estimated problem magnetic susceptibility

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[0133] Predicted problem magnetic susceptibility of a specific qubit

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[0134] To understand the above relationship, it may be helpful to consider one possible derivative. Elaborate Estimation

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[0135] In some embodiments, method 500 may output the estimated susceptibility generated as described above, and method 500 may terminate. In some embodiments, method 500 may repeat acts 502-506 to generate multiple estimated susceptibility values ​​for each qubit by a circuit system. The multiple estimates are composite estimates for each qubit.

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[0136] In 508, the target tunneling rate per qubit j

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[0137] Since magnetic susceptibility can change depending on magnetic flux / current (as noted above, these are related properties), the isolated qubit model can also be based on magnetic flux and / or current. For example, Δ j value This can be determined according to the following formula:

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[0138] Tunneling speed

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[0139] Optionally, in 510, actions 502-508 (based on another sample received from the hardware) tunneling rate

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[0140] Tunneling speed

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[0141] In 514, the tunneling velocity Δ of one or more qubits iAdjustment of (for example, ΔTu The tunneling offset is one or more target tunneling speeds.

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[0142] In some embodiments, the Δ tuning offset ω j This involves multiple objective tunneling. speed

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[0143] In some embodiments, reduced offset ω j (i.e., reduced compared to the above) An offset (with a certain magnitude) is used. In some situations, such a reduction is Δ j This can help compensate for the nonlinear and dispersion effects encountered when tuning. , offset ω j It is determined as described above, and then can be reduced by a certain coefficient (for example, ω j(It can be halved), can be reduced exponentially and / or reduced in other ways It is possible.

[0144] Optionally, method 500 generates offset ω in 514. j Based on 51 In 6, actions 502-514 can be repeatedly repeated. In some embodiments, the qubit tunneling rate is offset ω j After being adjusted based on that, another hardware sample A sample is received. In some embodiments, another hardware sample is not necessarily received at 502, and instead (or additionally) a modified sample is received at 502 with the hardware sample previously received and offset ω j And the tunneling speed Δ j Changes and samples

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[0145] Another iteration may involve further homogenization at 514, which offsets ω j This is refined through multiple iterations.

[0146] At 518, offset ω j This is output by the circuit system. Such an output is, for example However, as described elsewhere in this specification, the tunneling velocity Δ of one or more qubits j offset ω j Adjust based on the offset ω j To restore it using software, Offset ω via signal linkj Transmitting offset ω j To display to the user, and / or otherwise offset ω j hardware and / or software This may include providing it to the interface.

[0147] Mitigation of degeneracy through measurement during evolution In some embodiments, the state of a qubit is measured during evolution prior to completion. Such measurements may provide information about the time-dependent quantum annealing dynamics over the course of evolution (e.g., approximate freeze time, state correlation as a function of time, and / or other information). Such information may be used to manipulate the annealing process via (e.g.) Δ tuning. In some embodiments, a flux detector is used to measure the expectation values ​​of one or more qubits one or more times during evolution, and the measurement results from the flux detector are one One or more Δ of the above qubits i It is used to tune it.

[0148] Figure 4 shows the tunneling velocity Δ of one or more qubits. i Exemplary methods for tuning This is a flowchart of method 400. Method 400, as shown in Figure 4, involves several actions. One or more of these actions may be performed by (or via) one or more circuits, such as one or more processors (e.g., digital processors), analog processors such as quantum processors, or a hybrid computer that includes both digital and analog processors. For the purposes of explaining Figure 4, we assume that the actions are performed by a hybrid computer that includes a quantum processor. Method 400 is illustrative, and those skilled in the art will recognize that alternative embodiments may omit some actions and / or include additional actions.

[0149] In 402, the problem is received by a hybrid computer and encoded on a quantum processor. In 404, the hybrid computer couples a flux detector to a qubit (hereinafter referred to as the “problem qubit”). The problem qubit may be an individual hardware qubit or a logical qubit comprising multiple hardware qubits. Method 400 may include any number of flux detectors and problem qubits. While the “problem qubit” and “flux detector” are used as general terms in this disclosure, it is understood that multiple flux detectors and problem qubits may be measured and / or tuned simultaneously and / or sequentially according to Method 400.

[0150] The flux detector can be any quantum flux parametron that can be annealed separately from the problem qubit. For example, the flux detector may include qubits adjacent to (i.e., sharing a coupler with) the problem qubit. As another example, the flux detector may be a calibration device provided by a processor and configured to measure the problem qubit. The coupling strength J between the flux detector and the problem qubit may be problem-dependent. Generally, the coupling strength J should be strong enough to reliably replicate the qubit state to the flux detector, but weak enough not to disturb the dynamical properties of the problem qubit. Determining an appropriate strength will depend in part on the coupling of the problem qubit with other qubits.

[0151] At 406, the quantum processor initiates evolution, which includes annealing the problem qubit and the flux detector. In some embodiments, the problem qubit and the flux detector begin annealing almost simultaneously. In some embodiments, the flux detector begins annealing after the problem qubit has begun annealing.

[0152] At 408, the flux detector is rapidly annealed compared to the problem qubit. This is done, for example, by any preferred method described herein, or otherwise by known methods (present or future methods), by the flux detector being annealed at a low tunneling speed Δ i possess This can be done by configuring the device in such a way. Thus, the flux detector completes its annealing process before evolution is complete and, in some cases, before the problem qubit is frozen. By the time the flux detector's annealing is complete, the expected value of the problem qubit's state throughout the flux detector's annealing process is replicated to the flux detector.

[0153] In 410, the state of the magnetic flux detector is read out. In some embodiments, the state of the magnetic flux detector is stored in a buffer, and multiple states are read out together.

[0154] In step 412, the hybrid computer determines whether to perform another measurement of the problem qubit. In some embodiments, the hybrid computer continues to perform measurements of the problem qubit until evolution is complete. In some embodiments, the hybrid The hybrid computer performs a predetermined number of measurements and then stops performing such measurements. In some embodiments, the hybrid computer stops measuring the problem qubit after determining that the problem qubit is frozen (for example, based on measurement information read from a magnetic flux detector). In some embodiments, the hybrid computer stops measuring various problem qubits at various times.

[0155] If the hybrid computer determines that another measurement should be performed, method 400 returns to 408. The hybrid computer may optionally incorporate delays in 412 and / or 408 so that a predetermined amount of time elapses between measurements. The hybrid computer may return to 408 once or more times throughout the evolutionary process to obtain measurement results for the problem qubit at various points in the evolution.

[0156] If the hybrid computer determines that further measurements of the problem qubit are no longer necessary during this evolution, it continues on to 414. At 414, the quantum processor completes its evolution.

[0157] In 416, the information read from the flux detector in 410 is processed to determine (at least approximately) information about the evolutionary behavior of the qubit in question. For example, the approximate freeze time of the qubit in question may be determined by observing the approximate time at which the expected value of the qubit's state stopped changing between measurements (and / or, in some embodiments, stopped changing beyond a threshold amount). As another example, avoided level crossings may be identified based on the change in the expected value of the state between measurements.

[0158] In 418, the Δ tuning offset ω is determined with respect to the problem qubit, at least in part, based on the information determined in 416. For example, based on the approximate freeze time determined in 416, the evolution of the problem qubit may be advanced or delayed to nearly synchronize their freeze times (as described elsewhere in this specification, for example). Alternatively or in addition, the tunneling rate Δ i For example, the problem qubit The process can be modified to reduce the occurrence of level crossover avoidance by delaying it. In some embodiments, the processor's global annealing speed can be delayed to reduce the occurrence of level crossover avoidance (for example, the problem qubit that experienced level crossover avoidance does not freeze before the synchronous freeze time).

[0159] Actions 420 and 422 generally correspond to 212 and 214 in Figure 2, respectively. In 420, the problem qubit is tuned according to the Δ-tuning offset ω determined in 418. In 422, the hybrid computer performs the calculation of the problem (which may have been modified by the Δ-tuning operation in 420) and determines the solution.

[0160] Logical qubit strategy As noted elsewhere in this specification, the per-qubit annealing schedule Δ i At least some techniques to correct this can fix the problem so that it can be computed effectively. For example, correcting the persistent current of a flux qubit can fix the qubit's annealing schedule Δ i This will change the qubit's magnetic flux, and will generally also be modified. To make the problem more manageable and resolvable.

[0161] In some embodiments, Δ tuning (e.g., at 160 and / or 212) can be performed by modifying the encoding of the problem so that the problem is effectively solved (although the problem may be represented differently by the processor). With respect to flux qubit-based systems, such embodiments involve the persistent current (and / or other parameters defining the problem) and the tunneling speed Δ i It could be said that it provides orthogonal control.

[0162] In some embodiments, the persistent current and tunneling speed Δ i Orthogonal control with "logic" The problem is provided by encoding it with an intermediate formula that employs qubits. A logical qubit consists of multiple qubits (referred to herein as “internal” qubits) that are linked together to behave effectively as a single qubit. A logical qubit represents a single variable of the problem. Techniques for forming logical qubits (e.g., as a qubit chain) are described, for example, in U.S. Patents 7,984,012, 8,244,662, and 8,174,305.

[0163] Each internal qubit within a logical qubit has a tunneling velocity Δ i and persistent currents It has its own associated qubit parameters. The logical qubit itself has an effective tunneling velocity Δeff and effective permanent current I eff It may have "effective" qubit parameters such as: The effective qubit parameters of a logical qubit are determined by the qubit parameters of the internal qubits, the number of internal qubits within the logical qubit, and the coupling J between internal qubits. i of The strength (referred to herein as “internal coupling strength”), the internal topology of the logic qubit (i.e., the topology of the internal qubits and the coupling between them), and the strength and arrangement of couplings between internal qubits and qubits not present within the logic qubit are all influenced by these parameters of the logic qubit. Therefore, these parameters of the logic qubit are influenced by the desired (or “target”) effective tunneling velocity Δ eff It can be chosen to obtain.

[0164] For example, N superconducting qubits and N-1 coupling J i Having a chain topology that has The effective tunneling speed Δ of the logical qubit eff (Each individual qubit is Δ i The tunneling speed is such that the processor operates within a perturbation region of Δ≪J, and the result is as follows:

number

number

[0165] Logical qubits with various topologies can exhibit a variety of behaviors. For example, the effective tunneling velocity Δ effAlternatively, one could increase the number of internal couplers. More and / or inner bond J i It can be suppressed by increasing its intensity. This is the Δ of a logical qubit. eff However, any internal qubit Δ i This also allows for suppression without necessarily requiring modification (i.e., it can be tuned to advance annealing), thereby reducing the effective persistent current I eff (Permanent current of internal qubit I P Δ orthogonal to the control of (as well as) eff It provides control.

[0166] Therefore, in some embodiments, Δ tuning of a particular qubit is performed by modifying the representation of the problem on the processor so that the qubit is represented as a logical qubit. Next, the qubit-by-qubit annealing schedule Δ of the logical qubit is performed. eff teeth This can proceed in proportion to the number of qubits, the strength of the coupling, and the topology of the logical qubits.

[0167] In some embodiments, the qubit to be tuned may already be represented as a logical qubit, and the Δ tuning of the logical qubit is the qubit-by-qubit annealing schedule Δ eff To delay it, the number of qubits, the strength of the coupling, and / or This may include modifying the topology of logical qubits.

[0168] In some embodiments, the topology of a logic qubit is determined based on connectivity to external qubits (i.e., qubits outside the logic qubit). For example, if only a single internal qubit is coupled to one or more external qubits, any coupling strength J is possible. i Internal bond It can be provided for (i.e., the coupler has a bond strength J) i The entire range (usually zero or A minimum internal coupling strength (up to a certain maximum coupling strength) can be used. However, if multiple internal qubits are coupled to an external qubit, a problem-dependent minimum internal coupling strength J must be maintained to prevent the logic qubit from "breaking" (i.e., to prevent the internal qubit from taking various values). min In some embodiments, the logical qubits A topology is chosen such that only one internal qubit is coupled to one or more external qubits. This topology may be preferred over other topologies (where multiple internal qubits are coupled to one or more external qubits).

[0169] Depending on the problem and / or processor topology, the minimum internal coupling strength J of a logical qubit is determined. min This can be reduced by selecting a specific topology for logical qubits. Example For example, a topology that reduces the number of internal qubits coupled to external qubits may be selected.

[0170] Auxiliary qubit strategy In one method, the result can be obtained using a C2 graph configured to form a 32-qubit 4-regular graph. A hybrid computer can send a 1-BOP (1-bit of precision) problem with a zero local qubit bias to hardware. A 1-BOP problem is one with a coupling strength J = ±1. Some couplers can also be disabled by "making them unavailable". While such problems are generally easy, a hybrid computer could, for example, first generate 17,000 instances with two ground states and over 400 first excited states, and then find 100 hard instances by taking 100 instances with the lowest hardware probability of success (usually less than 5%). By using a C2 structure embedded in a larger graph, auxiliary qubits can be attached to each of the 32 qubits.

[0171] A hybrid computer can implement this technique by applying an iterative method. First, the hybrid computer can extract multiple samples (e.g., 1,000 samples) using hardware. Next, the hybrid computer can impose auxiliary constraints on qubits within the multiple samples that are rarely floppy and do not yet have attached auxiliary qubits. The auxiliary constraints may be directed away from the current mean spin (or magnetization). The hybrid computer can iterate this process, and the probability of success may change between iterations. Other variations of this technique (e.g., applying a local bias to the qubit instead of auxiliary constraints) may be used.

[0172] A method for eliminating perturbation crossovers may be based on adding auxiliary qubits such that the global minimum degeneracy increases compared to the competition minimum degeneracy (see, for example, U.S. Patent Application No. 2015 / 0032994).

[0173] advancing a qubit during quantum annealing. Another method involves advancing some qubits relative to other qubits during quantum annealing. To achieve this, the energy spectrum is modified by using a local CCJJ (composite-composite Josephson junction) DAC (digital-to-analog converter). This may cause a degradation of the persistent current equilibrium across the entire C2 set, but the primary effect may be the modification of some transverse magnetic fields of the qubits during quantum annealing.

[0174] Exemplary comparative results of degeneracy mitigation Degeneracy mitigation is related to domain freezing. Domain freezing is usually correlated with degeneracy mitigation, although the relationship is generally not one-to-one.

[0175] Figures 6–10 are plots showing comparative results of exemplary implementations of degeneracy mitigation in quantum processors by this system, device, article, and method. The method used to generate Figures 6–10 was as follows: 1. Program a difficult C2 problem instance. 2. Extract 1000 samples from the hardware. 3. For a given sample, the net bias from neighboring qubits is calculated for each qubit as follows:

number

[0176] Figures 6 to 10 were generated using the methods described above (Actions 1 to 7) and specific variations of the methods described below with reference to Figures 6 to 10.

[0177] Figure 6 is a histogram of the probabilities of finding the ground state for a selected hard problem instance. The problem was run using a modified form of the method described above, with 10 samples in action 2 instead of 1000 samples. The problem was run without local CCJJ DAC adjustments. This is the baseline case (i.e., no degeneracy mitigation). The median is approximately 0.04.

[0178] Figure 7 shows the effect of degeneracy mitigation. Even with only 10 samples, the chance of finding the ground state is significantly increased compared to the baseline case as a result of degeneracy mitigation. The median in Figure 7 is approximately 0.49.

[0179] Figure 8 is a histogram of the probabilities of finding the ground state for a selected hard problem instance. The problem was run using 1000 samples with the method described above. Figure 8 shows the effect of using more samples in degeneracy mitigation. The chances of finding the ground state are increased compared to the 10-sample case in Figure 7. The median in Figure 8 is approximately 0.66.

[0180] Figure 9 is a histogram of the probabilities of finding the ground state for a selected hard problem instance. The problem is b i Five random qubits rather than a qubit with the maximum prevalence of =0 The process was carried out using a variation of the above method for advancing bits. The results were similar to the baseline case, indicating that "random degeneracy mitigation has little to no favorable effect on the opportunity to find the ground state." The results are explained in the above method. This reinforces the importance of selecting qubits in order to proceed according to criteria such as those mentioned above. The median value in Figure 9 is approximately 0.03.

[0181] Figure 10 is a histogram of the probabilities of finding the ground state for a selected hard problem instance. The problem was solved using the method described above, but by delaying the qubits by performing an inverse CCJJ DAC adjustment instead of advancing them. The results for this example show the negative impact on the chance of finding the ground state compared to the baseline case without degeneracy mitigation. The results demonstrate the importance of advancing rather than delaying the qubits. The median in Figure 10 is approximately 0.001.

[0182] In some embodiments, another suitable metric may be used to determine floppyness, such as a metric that can be used in conjunction with a non-zero bias value. For example, instead of summing the bias values, the method may determine with respect to a given qubit whether the energy of a given state changes when the qubit's state is inverted. If the method determines that the energy of a given state does not change, the qubit may be counted as a floppy qubit.

[0183] This technique improves performance by algorithmically (and iteratively) modifying the annealed orbital. While it has been theoretically proposed to use a set of initial samples to guide the modification to the annealed orbital, this technique is considered to be the first practical embodiment. In addition, this system and method can be implemented to improve sampling diversity (e.g., diversity of ground state and / or excited state samples).

[0184] The benefit of this technology is that it can make the hardware sample probability distribution closer to the Boltzmann distribution (which may be desirable for sampling).

[0185] This technique is not limited to the floppyness metric. For example, one or more "frozen" regions of a qubit (regions where a qubit is locked into the same configuration across many samples) can be identified, and then other metrics can be used to delay these regions during quantum annealing.

[0186] Intermediate annealing pause It may be beneficial to suspend the annealing schedule.

[0187] Figure 11A shows chart 1100a illustrating an exemplary annealing scenario with no pauses within the annealing schedule. The horizontal axis 1110 corresponds to time. The vertical axis 1112 corresponds to the persistent current i. P Corresponds to the tunneling speed Δ of the qubit. i The qubit can be tuned according to the associated Δ tuning offset ω. As will be discussed elsewhere in this specification, Δ i This can be tuned by changing the persistent current of the qubit. (Line 1115) This shows the temporal variation of the persistent current over the duration of annealing. In the example shown, the persistent current changes linearly over time.

[0188] Figure 11B shows Chart 1100b illustrating an exemplary annealing scenario with pauses within the annealing schedule. The horizontal axis 1120 corresponds to time. The vertical axis 1122 corresponds to the persistent current i. P It corresponds to.

[0189] Lines 1125, 1130, and 1135 show the temporal variation of the persistent current over the duration of annealing. Line 1125 shows the increase in the persistent current until the start of the pause. Line 1130 shows the pause. The start of the pause is during the progress of evolution. P It begins with... For example, the start of the pause is in the middle of the annealing. If so, s P =0.5. s P The start of the pause corresponds to time t1. The pause is t P Suspension It ends at time t2 after the duration. Line 1135 is the permanent from the end of the pause to the end of the annealing. This indicates an increase in current.

[0190] In some embodiments, the annealing schedule has a single pause. In other embodiments, the annealing schedule has two or more pauses.

[0191] In some embodiments, the user initiates pauses via the user interface. P and rest duration of stop t P It can be defined as a graphic user interface. It can be a interface, remote interface, and / or application programming interface. For example, to implement a 100μs pause in the middle of annealing, the user can s P =0.5 and t P = 100 μs can be specified.

[0192] During testing, the applicant observed an improvement in quantum annealing performance resulting from the inclusion of pauses within the annealing schedule. For example, in the case of a quantum processor containing 16 qubits, an improvement of approximately 30 times in performance can be achieved in a 10 μs annealing schedule by incorporating a 100 μs pause at a favorable stage of annealing during the total 110 μs annealing time. The same improvement without pauses would require an annealing time of approximately 1000 μs.

[0193] Fast and / or slow annealing The annealing time can be adjusted. In some embodiments of the systems and methods described herein, the user may specify a desired annealing time. The annealing time may be provided through a user interface (e.g., an application programming interface) (API). The annealing time may be faster or slower than the pre-adjusted annealing time.

[0194] Intermediate annealing lamp In some embodiments of the systems and methods described herein, the annealing schedule may include an intermediate annealing ramp. Standard annealing (e.g., linear increase of the persistent current) may be interrupted by a sudden acceleration of annealing by steeply increasing the persistent current at some point during evolution.

[0195] Figure 11C shows chart 1100c illustrating an exemplary annealing scenario with an intermediate annealing ramp 1150 within the annealing schedule. The horizontal axis 1140 corresponds to time. The vertical axis 1142 corresponds to the persistent current i P It corresponds to the standard annealing schedule. It starts with Neil 1145, followed by the intermediate annealing ramp 1150.

[0196] In some embodiments, parameters defining the intermediate annealing ramp may be provided via a user interface (e.g., an API).

[0197] Annealing Schedule Operation In some embodiments of the systems and methods described herein, the annealing schedule may include a preferred combination of one or more intermediate annealing pauses and / or one or more intermediate annealing ramps.

[0198] Figure 11D shows Chart 1100d illustrating an exemplary annealing scenario with an annealing schedule operation that includes intermediate annealing pauses and intermediate annealing ramps within the annealing schedule. The horizontal axis 1160 corresponds to time. The vertical axis 1162 corresponds to the persistent current i P It corresponds to.

[0199] The annealing schedule begins with standard annealing 1165, followed by the first intermediate annealing. The ramp 1170 follows. The annealing schedule proceeds with the first intermediate annealing pause 1175, followed by the second intermediate annealing ramp 1180 (this time in the opposite direction (a rapid decrease in the permanent current)). After ramp 1180, the second intermediate annealing pause 1185 and the third ramp 1190 follow.

[0200] In some embodiments, annealing scheduling operations may be provided via a user interface (e.g., an API). Parameters defining the annealing scheduling operations may include, for example, the start and duration of each segment of the schedule. The start of the first intermediate annealing ramp 1170 may be defined by a measure of evolutionary progress. The timing of other ramps and pauses may be defined, for example, by duration.

[0201] Figures 11A to 11D show the persistent current i on the vertical axis for convenience. P This indicates the other terms used in this specification. As explained elsewhere, in at least some circumstances it is possible to change the tunneling rate of one or more qubits to be orthogonal to the variation in the persistent current. Therefore, it is understood that the intermediate annealing pause, intermediate annealing ramp, and fast annealing operations of the annealing schedule described herein can be implemented by any suitable technique (or combination of techniques) for changing the tunneling rate.

[0202] Generalized annealing schedule Figure 11D shows Chart 1100d, which illustrates an exemplary annealing scenario having an annealing schedule operation that includes intermediate annealing pauses and intermediate annealing ramps within the annealing schedule. While Figure 11D shows an exemplary annealing schedule, those skilled in the art will recognize that other annealing schedules may be used to achieve the desired evolution.

[0203] An annealing schedule can be expressed using a suitable single-valued function of time. The function may be linear or nonlinear. The function may be injective or nonjective. The function can be expressed as a series of segments, each having the same or different suitable single-valued function of time.

[0204] Piecewise linear annealing schedule A piecewise linear annealing schedule is an example of an annealing schedule. A piecewise linear annealing schedule contains one or more segments, each of which is a linear function of time. Figure 11D shows an example of a piecewise linear annealing schedule. In the example in Figure 11D, the persistent current i p Each of these is a linear function of time or progress through evolution s. The sequence changes in piecewise linear segments that are linear as a function. For example, the first linear segment is ramp 1165. The schedule has five other linear segments 1170, 1175, 1180, 1185, and 1190, respectively. Those skilled in the art will recognize that linear segments of any preferred sequence can be synthesized to generate the annealing schedule.

[0205] Annealing scheduling using programmable parameters As mentioned above, quantum processors can be designed to perform quantum annealing and / or adiabatic quantum computation. An evolutionary Hamiltonian proportional to the sum of a first term proportional to the problem Hamiltonian and a second term proportional to the delocalized Hamiltonian can be constructed as follows: H E ∝A(t)H P +B(t)H D

[0206] In some embodiments, the time-varying envelope function can be placed on the problem Hamiltonian. A suitable delocalized Hamiltonian is given by:

number

number

number

[0207] The general problem Hamiltonian has a first component proportional to a diagonal single-qubit term and a second component proportional to a diagonal multi-qubit term, and may take the following form:

number

number

[0208] During the operation of the quantum processor, the interface couples the magnetic flux signal into the composite Josephson junction of each qubit, thereby allowing for a tunable term (Δ i (Item) to System H This can be used to realize within the Miltonian. This bond is the off-diagonal σ of the Hamiltonian. x These terms provide examples of "delocalized signals" for magnetic flux signals.

[0209] Similarly, the interface couples the magnetic flux signal into each qubit loop of the qubit, thereby h i The term can be used to realize within the system Hamiltonian. This bond is formed by the diagonal σ z The term is provided within the system Hamiltonian. Furthermore, the inter The face couples the magnetic flux signal into the coupler, thereby J ij The term can be used to realize the system Hamiltonian. This connection is diagonal.

number

[0210] In one approach to quantum annealing, the system uses a programmable parameter h to advance or slow down regions of qubits, logical qubits, chains, and / or qubits. i , J ijThe system can manipulate the delay, for example, using a programmable parameter. These can be provided separately, in combination with each other, and in combination with transverse magnetic fields.

[0211] When the transverse magnetic field becomes zero at the end of annealing, the programmable parameter h i , J ij This achieves their final values. In the method described here, the envelope functions A(t) and B(t) are the Hamiltonian and its associated parameter Δ i h i , J ij It is effectively absorbed internally. The system can be flexible with respect to the annealing schedule (for example, h i , J ij It is fixed Δ i (This can evolve). Other methods may produce similar results. In some cases, One method for manipulating the annealing schedule may yield better results than another.

[0212] In one exemplary embodiment, the envelope function A(t) is fixed for each qubit, and the bias value h i It is fixed and bonded to J ij It can be set to zero, and the envelope function B(t) is used for annealing. Me to J ij It can be changed each time. A i , B i , B ij The value for each qubit is, for each qubit q i progress It can be used to accelerate or slow down the process.

[0213] In another example, A i , B i This can be the same for all qubits, and B ij This is the central joint J of the graph. ij Further advance the bond J, which is located further away from the center. ijThis can be used to progressively delay the process. Related techniques are described elsewhere in this application and are called annealing scheduling operations based on the position of qubits in a graph. More generally, B ij This is a coupling J that starts from a selected location in the graph or processor topology. ij It can be used to gradually advance or slow down something.

[0214] In another example, B i Term and B ij Both terms can be manipulated to achieve similar effects.

[0215] In another exemplary implementation of quantum annealing, the system has a set of bonds J for other bonds in the graph. ij Clusters, regions, and / or chains of qubits can be advanced or delayed by advancing or slowing down their movement.

[0216] Figure 11E shows Chart 1100e, which illustrates an exemplary annealing scenario in which the local bias h of the qubit is changed during evolution.

[0217] The horizontal axis 1191 corresponds to time. The vertical axis 1192 corresponds to the qubit bias h. The value of the qubit bias h over time is represented by line 1193.

[0218] Figure 11F shows a chart illustrating an exemplary annealing scenario in which the coupling strength J of the coupling device between a pair of qubits changes during evolution.

[0219] The horizontal axis 1194 corresponds to time. The vertical axis 1195 corresponds to bond strength J. The value of bond strength J over time is represented by line 1196.

[0220] Annealing scheduling operation of logical qubits In some embodiments of the systems and methods described herein, the annealing schedule of a logic qubit, which includes multiple hardware qubits, is determined based on the properties of the logic qubit. The effective tunneling rate (Δ) depends on various properties of the logic qubit (including (partially) the number of constituent qubits, internal and external coupling, etc.). eff It has been observed elsewhere in this specification that it has ) and explained elsewhere. One strategy is to aim for the desired Δ eff or by manipulating these properties to obtain an approximation thereof. And so it is.

[0221] In some embodiments, the Δ of the logical qubit eff This is one of the properties of logical qubits. The operation is performed based on the above (which may or may not include modifying the properties themselves). For example, in embodiments having logic qubits having a chain topology (as described elsewhere in this specification), a chain significantly shorter than another chain has a smaller Δ than a longer chain. eff It is highly likely that Therefore, the dynamical properties of logical qubits have a potentially useful heuristic. ) is the length of the chain (i.e., the number of constituent qubits). In at least some situations, the Δ of the chain eff This can be modified based on the length of the chain (with or without considering any other properties of the chain). (Unchanged).

[0222] As explained elsewhere in this specification, Δ eff The correction is accomplished through one or more strategies. It is possible. For example, Δ eff This extends the chain (and therefore delays it during annealing). This can be increased by shortening the chain (and thus by allowing it to proceed during annealing). Alternatively or in addition, the Δ of the chain eff Its constituent quantum bits This can be corrected by modifying the flux bias and / or coupling strength of the DAC and / or coupler, by modifying the DAC parameters (such as CCJJ DAC), or by any other available strategy.

[0223] In some embodiments, with respect to the problem embedded using a representation that includes multiple variable-length chains, each of the Δ eff The values ​​are as described in this specification for their annealing Synchronization can be achieved by modifying the schedule. In some embodiments, the Δ of the chain at a specific energy level eff Harmony occurs by synchronizing them. The inventors have found that Through experimentation, we discovered that this modification strategy can yield impressive results in some situations. For example, a 100-fold increase in resolution speed was observed in several instances of factoring a 2n-bit semiprime into separate n-bit primes (compared to attempting the same problem without modifying the annealing schedule).

[0224] Example of annealing scheduling operation for logical qubits An example of such an experiment is shown in Figure 19 as Method 1900. In 1905, a factorization problem (e.g., finding the solution (a,b) to a × b = 35) is generated. In 1910, an embedding for a multiplication circuit to encode the problem is generated (e.g., as described in U.S. Patent No. 8,700,689). Optionally, in 1915, one or more scaling factors are selected. For example, multiple scaling factors within the range [0,1] (e.g., a set of coefficients {0,0.1,0.2,...1}) may be selected. More or fewer scaling factors may be selected.

[0225] In 1920, an annealing schedule offset strategy is generated based on one or more scaling factors. Any suitable offset can be selected. Chains of varying lengths may be assigned different offsets to synchronize their dynamical properties at a given energy scale. In at least exemplary experiments, the CCJJ offset was selected based on the following equation.

number

number

[0226] At 1925, the quantum processor executes the problem and generates a sample solution. 1925 can be iterated with the same and / or different scaling factors (e.g., each scaling factor may have multiple corresponding executions). Optionally, method 1900 can return to 1915 to generate additional scaling factors. Alternatively (or in addition), method 1900 may generate multiple scaling factors at 1915, and does not necessarily return from 1925 to 1915.

[0227] Optionally, in 1930, results generated in 1925 can be compared with those generated in 1930, for example, by applying a performance metric and ranking the scaling factors with respect to that metric. For example, scaling factors with a high success rate and / or short time to reach a solution may be ranked higher than scaling factors with a relatively low success rate and / or long time to reach a solution. One or more of the highest-ranking scaling factors can be stored and recalled later for use in similar problems.

[0228] Method 1900 may be carried out by other annealing scheduling strategies described herein and may utilize any available annealing offset techniques (such as manipulation of logical qubit properties or programmable parameters).

[0229] Annealing scheduling operation based on the position of qubits in the graph In some embodiments of the systems and methods described herein, the annealing schedule of a qubit and / or a pair of qubits may be determined based on the position of the qubit and / or pair of qubits relative to one or more other qubits. For example, one or more qubits located on or near the outer edge of a graph of qubits may be advanced or delayed compared to other qubits in the graph. The graph may be, for example, a working graph of hardware qubits, a virtual graph that simulates a particular working graph of hardware qubits (e.g., as described in U.S. Provisional Patent Application No. 62 / 375785), and / or an embedding graph of logical qubits where each logical qubit corresponds to one or more hardware qubits.

[0230] For example, the annealing schedule can be modified according to a defined gradient on the graph. Figure 18 shows an example defined on graph 1810 containing a Chimera structured group 1812 of qubits 1814a, 1814b, etc. (collectively and individually referred to as "qubit 1814") The empirical gradient 1800 is shown. Due to the numerous groups 1812 and qubits 1814 in graph 1800, most of their labels are omitted for clarity of explanation. The systems and methods described herein are not limited to Chimera structured graphs, and graph 18 It is understood that 10 is illustrative and non-restrictive.

[0231] The gradient 1800 associates each qubit 1814 with a value (visually depicted by the shading intensity corresponding to Legend 1820). The qubits 1814 in the first region 1802 are advanced during annealing (e.g., by applying a Δ offset as described elsewhere in this specification), the qubits 1814 in the third region 1806 are delayed during annealing (e.g., by applying a Δ offset with the opposite polarity of the Δ offset applied in the first region), the qubits 1814 in the second region 1804 are neither advanced nor delayed, and / or advanced or delayed only slightly compared to the qubits 1814 in the first and third regions 1802 and 1806. In some embodiments, the gradient 1800 only advances (or delays) qubit 1814, but different qubits 1814 may be advanced (or delayed) by different amounts, and / or some qubits 1814 may not be advanced (or delayed).

[0232] The inventors have observed that, for at least some problems executable on at least some quantum processors, qubits 1814 near the outer edges tend to freeze earlier than other qubits 1814 located relatively far from the edges of the graph. In some embodiments, a gradient is defined that corresponds to an annealing schedule modification that delays qubits 1814 near the outer edges of graph 1810 and advances qubits 1814 far from the outer edges of graph 1810. While gradient 1800 is a non-restrictive example of such a gradient, it is understood that other gradients exhibiting this behavior may be defined (e.g., a gradient where each qubit 1814 has an annealing offset determined by its distance from the outer edge (larger distances correspond to earlier annealing times)).

[0233] The gradient 1800 is an exemplary radial gradient. Each qubit 1814 is associated with an offset value that decreases proportionally to the distance of qubit 1814 from point 1822. Other gradients are possible. For example, the gradient may be a linear gradient in which each qubit 1814 is associated with an offset value based on the distance from a line defined across the entire graph 1810 (e.g., based on the distance between qubit 1814 and one of the edges of the graph 1810 (edge ​​1822, for example)). In some embodiments, the gradient extends across the entire graph 1810. In alternative or additional embodiments, the gradient is defined on a portion of the graph 1810.

[0234] One or more gradients may be defined on graph 1810. If multiple gradients are defined, they may be disproportionate and / or superimposed. A qubit 1814 for which multiple gradients are defined may have an annealing schedule defined by a combination of the associated values ​​of the overlapping gradients of the qubit 1814. For example, the annealing schedule of the qubit 1814 may be based on the sum, product, or other function of the overlapping gradient associated values.

[0235] Annealing scheduling operations within logical qubits In some embodiments of the systems and methods described herein, the annealing schedule of logical qubits can be manipulated such that the qubits constituting the logical qubit have the same or different annealing schedule offsets. For example, all qubits within a logical qubit may have the same annealing offset, qubits with external coupling may be assigned a different offset than qubits with internal coupling only (and / or may be assigned offsets based on various criteria), and / or qubits with different positions in the graph may be assigned different offsets (and / or may be assigned offsets based on various criteria). This annealing schedule manipulation can be added to (or may be a substitute for) other annealing schedule manipulation strategies described elsewhere in this specification. Logical qubit-level scheduling is sometimes referred to as “subscheduling” to distinguish it from broad (e.g., processor-wide) annealing schedules.

[0236] For example, in some embodiments where the broad annealing schedule is directional, logic qubits may follow a directional annealing subschedule that modifies the broad annealing schedule. For instance, given an annealing schedule based on a linear gradient across all logic qubits in an embedding graph (e.g., so that a qubit anneals faster than other qubits if it lies along an axis across the entire embedding graph), the corresponding gradient can be determined within the logic qubit. The constituent qubits of a logic qubit (which may be hardware qubits) may anneal faster than other qubits within the same logic qubit based on the gradient. The logic qubit-level gradient may have a different slope than the gradient of the broader annealing schedule (e.g., a qubit within a logic qubit may anneal more densely in time than a similarly adjacent qubit somewhere else in the graph that is not part of the same logic qubit).

[0237] Selective annealing In some embodiments of the systems and methods described herein, one subset of qubits is annealed, while another subset of qubits is not. The subset of qubits may include hardware qubits, logical qubits, and / or any other qubit representations. For example, a subset of qubits may be selected for annealing, an annealing schedule may be assigned to those qubits, and the remaining qubits may be clamped or otherwise prevented from changing their dynamical properties (e.g., by programming their corresponding CCJJ DAC biases). Such prevention is referred to herein as “pausing” the remaining qubits. The selected qubits may then be annealed according to their annealing schedule. The remaining qubits may then be unpaused (i.e., allowed to resume annealing).

[0238] For example, a subset of qubits may be selected for reverse annealing at some point in evolution. The remaining qubits may be paused, and the subset may be reverse annealed (e.g., as described in U.S. Patent Application Publication 2015 / 363708). Then, while the remaining qubits remain paused, the selected qubits may be forward annealed (resulting in a different outcome state than what they could have previously been), and the remaining qubits may be allowed to anneal when they return to the point in the annealing that the qubits occupied before the reverse annealing occurred. Alternatively or in addition, some or all of the remaining qubits may be allowed to anneal after the reverse annealing is complete and before the selected qubits are forward annealed again.

[0239] Intentional detuning of the annealing schedule. Another embodiment of the systems and methods of the present disclosure for advancing (or delaying) qubits during annealing identifies constraints and backpropagates them across the entire logic circuit, for example, from the circuit output to the circuit input. For example, qubits closer to the circuit output may be frozen early in their evolution. This can be achieved by starting to reduce the tunneling amplitude of a subset of qubits earlier than that of another subset of qubits, or by reducing the tunneling amplitude at a faster rate. For example, a time-dependent gradient of the tunneling amplitude may be established across the entire logic circuit. The gradient of the tunneling amplitude may correspond to the annealing schedule.

[0240] A modified annealing schedule can be generated by intentionally detuning the tunneling amplitude and problem Hamiltonian energy measure of a selected subset of qubits. In one embodiment, as described elsewhere in this disclosure, the detuning is achieved by adjusting the qubit parameters via a DAC within a quantum processor, such as a CCJJ DAC.

[0241] Controllable simulation of noise within the annealing schedule. Analog processors tend to be susceptible to noise, and considerable effort is generally made in existing systems to reduce the amount and impact of such noise. For example, at least some analog processors are operated in cryogenic environments (e.g., below 1°K) to reduce thermal noise. However, even in such environments, noise can still be present. For instance, communication lines connecting a supercooled analog processor may also connect to devices in much warmer environments (e.g., room temperature), thereby introducing potential pathways for noise to affect the analog processor.

[0242] However, in at least some situations, further noise reduction can negatively impact some performance metrics of the analog processor. For example, at least some In this case, the inventors observed that operating the analog processor even at sub-normal temperatures resulted in sample diversity and / or a reduced success rate for optimizing certain problems compared to the same metric when the same problems were performed at higher temperatures (and therefore with more noise).

[0243] One potential effect of noise is that it can cause small, random (and / or quasi-random) fluctuations in the annealing schedule. For example, in at least some quantum processors, noise on the annealing control line can cause small, short-lived increases and / or decreases in the persistent current, which in turn introduces some jitter in the qubit's annealing schedule.

[0244] In some embodiments, noise can be simulated in a controllable manner by a digital computer by applying short-duration ramps and pauses to the annealing schedule, which is performed by an analog computer in relation to the problem. Figure 22 shows Chart 2200 illustrating an exemplary annealing scenario in which noise is controllably added to the annealing. The horizontal axis 2202 corresponds to time. The vertical axis 2204 corresponds to the tunneling speed Δ. As described elsewhere in this specification, the tunneling speed is one or more of several techniques (persistent current i P This may be judged or affected by (such as by changing) the terms.

[0245] Line 2210 corresponds to an exemplary input annealing schedule. The input annealing schedule could be, for example, an ideal noise-free annealing schedule for the qubits in the problem. Alternatively, the input annealing schedule may already contain some noise (either intentionally or unintentionally). In the illustrated example, line 2210 is shown as a dashed line (and thus partially obscured) that coincides with a portion of line 2222 (2222).

[0246] Line 2220 corresponds to an exemplary output annealing schedule. The output annealing schedule is generated by a digital computer based on the input annealing schedule and a controllable noise addition algorithm. For example, the output annealing schedule corresponding to line 2220 can be determined by applying dithering techniques to the input annealing schedule 2210.

[0247] In some embodiments, the output annealing schedule is determined by a digital computer by modifying the input annealing schedule by adding intermediate annealing ramps and pauses. For example, line 2220 includes a portion 2222 that coincides with line 2210, thus indicating the duration of annealing when the input annealing schedule and the output annealing schedule are the same. In portion 2224 of line 2220, a ramp is added, causing line 2220 to deviate from line 2210 (in this case, the deviation corresponds to the advancement of the output annealing schedule relative to the input annealing schedule). In portion 2226 of line 2220, a pause is added, causing line 2220 to reduce its deviation from line 2210.

[0248] In the example shown in Figure 22, the pause in portion 2226 is long enough to cause line 2220 to intersect line 2210 at intersection 2230. The pause ends at intersection 2230, thereby allowing line 2220 to coincide with line 2210 again (similar to portion 2222), or the pause continues, thereby causing line 2220 to deviate from line 2210 again (for example, as shown in Figure 22). Subsequent ramps may cause line 2220 to intersect line 2210 again, for example, as shown by portion 2228 of line 2220. In some embodiments, additional pauses or ramps may be added to reduce deviations from the input annealing schedule but to end before the input and output annealing schedules intersect.

[0249] Other modifications are possible. For example, the output annealing schedule may include a portion where reverse annealing occurs. Another example is that the output annealing schedule may include non-piecewise linear modifications. For example, the output annealing schedule may be based on the product of the input annealing schedule with a low-amplitude sinusoid and / or some other continuous function. Another example is that fast and / or slow annealing may be provided instead of (or in addition to) ramps and / or pauses, respectively. For example, the output annealing schedule may slowly anneal during the period corresponding to some or all of section 2226 (this would be graphically represented as section 2226 having a positive slope less than the slope of line 2210). Thus, lines 2210 and 2220 will intersect at a later time than intersection point 2230 unless further modifications are added to advance the intersection of lines 2210 and 2220.

[0250] In some embodiments, modifications to the input annealing schedule (such as pauses and ramps) are applied randomly and / or pseudo-randomly by a digital computer. In some embodiments, pauses and ramps (and / or slow and fast annealing) are applied in alternating pairs (e.g., pause first, then ramp, followed by either pause-ramp pairs or ramp-pause pairs). In some embodiments, the duration and amplitude of the modifications are determined randomly or semi-randomly.

[0251] In some embodiments, modifications are applied to the output annealing schedule by a digital computer according to one or more constraints. For example, the duration and / or amplitude of the modifications may be constrained so that the modifications and / or deviations of the output annealing schedule from the input annealing schedule do not exceed a threshold. As an example, each 0.1 millisecond period of annealing may be modified randomly (and / or pseudo-randomly), thereby constraining each modification to 0.1 milliseconds. Optionally, some periods may not have any modifications.

[0252] As another example, the duration and / or amplitude of one or more modifications may be randomly or pseudo-randomly selected by a digital computer, subject to the constraint that "each modification must not cause the output annealing schedule to deviate from the input annealing schedule by an amount exceeding a threshold." For example, the amplitude of the output annealing schedule may be constrained to deviate from the input annealing schedule by an amount greater than the amount proportional to the amplitude of the input annealing schedule at the same temporal point in the input annealing schedule (e.g., within 1%, 5%). Alternatively or in addition, the amplitude of the output annealing schedule may be constrained to deviate from the input annealing schedule by an amount greater than a certain threshold (e.g., an amount corresponding to 0.1%, 0.5%, 1%, etc., of the maximum persistent current).

[0253] Corrective pseudo-noise can be applied on a per-qubit basis and / or on a multi-qubit basis. For example, an initial set of corrections may be determined and applied uniformly to the annealing schedule of all qubits on the analog processor (and / or all qubits in question). Another set of corrections may be determined and applied individually to each qubit. An intermediate set of corrections may be determined and applied to a group of qubits (for example, by grouping qubits that co-receive the annealing control signal on a shared annealing line and applying the intermediate set of corrections uniformly to the group).

[0254] Reducing sampling bias The techniques of this disclosure for manipulating annealing schedules are not limited to optimization problems. For example, the techniques of this disclosure may also be applied to improve the performance of an analog processor (and / or hybrid computer) during a sampling operation. As will become widely known, analog processors can be used to extract samples from a distribution defined by the input problem.

[0255] Certain problems may be vulnerable to sampling bias, where certain groups of solutions are sampled more frequently than others. For example, problems with highly degenerate ground states and / or initially excited states can exhibit strong sampling bias, resulting in high-degeneracy "valleys" being sampled more frequently than others (perhaps to the point where "samples from high-degeneracy valleys tend to dominate over samples from other valleys"). A "valley" is a group of one or more solutions (or samples) that occupy a low-energy region of the energy landscape defined by the Hamiltonian of the problem, between which analog processors (and / or hybrid computers) can transition during annealing without energy change. In other words, a valley is a low-energy isoenergy cluster of solutions (or samples).

[0256] In some embodiments of the systems and methods disclosed herein, sampling bias is mitigated by modifying the annealing schedule in question, thereby allowing samples from other valleys to be acquired at a greater frequency.

[0257] A flowchart illustrating an exemplary method 2100 for mitigating the sampling bias of an analog processor is shown in Figure 21. In 2105, the problem is received by a processor (e.g., a digital processor). In 2110, N samples are collected from the analog processor (e.g., as described above with respect to Figure 1).

[0258] In 2115, N samples are analyzed and one or more valleys are identified. Valleys can be identified by a digital processor by grouping samples into clusters based, for example, isoenergy qubit flips. For example, two samples may occupy the same valley if there is a series of qubit flips that can be applied to one sample to acquire the other sample without any flips that result in an energy change (or without a change exceeding an energy threshold). Each qubit flip may involve flipping one or more qubits. In some embodiments, only samples related to each other by a determined (e.g., predetermined) number of isoenergy qubit flips or less are grouped as identified valleys. Such embodiments are sometimes said to use the isoenergy Hamming distance as the metric for valley membership.

[0259] In some embodiments, all valleys are identified by the digital processor 2115. In some embodiments, only a subset of valleys are identified. For example, valleys having more than a certain number of degenerate states, valleys from which at least a threshold number of samples have been collected, a subset containing valleys with the largest integer v, valleys having less than the minimum energy, and / or other valleys may be identified.

[0260] In 2120, the valley v i The digital processor selects one or more valleys. For example, the valley with the highest probability (i.e., the valley from which the largest number of samples were drawn) may be selected.

[0261] In 2125, the qubit q i However, selected from the valleys chosen by the digital processor Selected. In 2130, the qubit q i Degeneracy metric μ i This is determined. The degeneracy metric is the qubit q. i We give a measure of the contribution of the corresponding valley to the degeneracy. For example, the degeneracy Trick μ iThis refers to normalized floppyness as described with respect to action 130 of method 100. It may include metrics (see Figure 1). For example, the normalized floppyness metric may be determined according to the following formula: μ i =n i / S Here, n i is a qubit q i ga tani v i The number of times it was a floppy disk within S samples be.

[0262] Acts 2125 and 2130 can be performed by a digital processor on multiple qubits (e.g., all available qubits, all qubits in the domain of interest, etc.), thereby generating multiple degenerate metrics corresponding to multiple qubits.

[0263] In 2135, the annealing schedule is determined per qubit by a digital processor based on its corresponding degenerate metric. In some embodiments, the annealing schedule is determined by the degenerate metric μ i Based on the quantum bit q i The annealing offset ω determined for each i Includes offset ω i The degenerate metric μ i It is proportional to the number of qubits. For example, each qubit q i Offset ω i =μ i A can be assigned, where A is a constant annealing offset coefficient (in at least some embodiments, the maximum offset that can be assigned during one iteration of method 2100). The annealing coefficient A may represent either advancing or delaying the qubit during annealing, and therefore may be positive or negative in at least some embodiments.

[0264] As explained elsewhere in this specification, the term “qubit” can refer to a single qubit or a region of qubits (a qubit can be a hardware device, a logical qubit, etc.). qubit q i If this corresponds to the domain of qubits, annealing offset The bit can be applied to each qubit in the same domain. For example, domain q i Each qubit inside is the same Offset ω i It can receive. Apply the annealing schedule to the qubits in the region. Alternative or additional methods may be used as described elsewhere in this specification.

[0265] In some embodiments, the corresponding degeneracy metric μ is greater than (and / or greater than or equal to) the threshold T. i qubit q i Therefore, non-zero annealing offset ω i is allocated In some embodiments, Δ i Each qubit q is like this i It is the same as the opposite.

[0266] In some embodiments, the valley v i Each qubit q within i In the annealing schedule, this is advanced to the beginning of annealing or delayed to the end of annealing. For example, the determined annealing schedule is for qubit q. i to, at least some other quantity The annealing process is terminated before the child bits begin their own annealing and / or after at least some other qubits have finished their respective annealings. For example, qubit q i It is advanced (later) before (after) all other qubits. (It can be made to as another example, qubit q i This has already been carried out by method 2100. Only other qubits that were not advanced or delayed may be advanced (delayed). In some embodiments, the selected valley v i One or more other quantum bits that are not present inside Before the other qubits begin their annealing, the selected valley v i The qubit is It is delayed to allow time for the annealing process to complete.

[0267] Optionally, action 2135 is performed by a digital processor on a qubit q i Each of multiple A This may include determining the kneeling schedule. For example, action 2135 is qubit q i One or more annealing schedules to advance the process, and the qubit q i It may generate one or more annealing schedules that delay the process. Additionally or instead, act 2135 may include first determining one or more annealing schedules and then generating multiple annealing schedules by applying a set of scaling factors to each of the one or more annealing schedules. For example, annealing schedule This can be determined as described above, and then the product of the annealing schedule and each scaling factor {α i ,α2,...,α n Determine}(e.g., 0.1, 0.2, ..., 1) It is possible. For example, action 2135 is qubit q i Annealing offset ω i To generate a qubit q i Multiple scaled annealing offsets , {α i ω i ,α2ω i ,...,α n ω i This may include generating}.

[0268] Act 2135 may involve the digital processor selecting one of several determined annealing schedules based on one or more selection criteria, such as an objective function and / or one or more constraints. For example, the annealing schedule may be selected based on avoiding inconsistencies, minimizing floppyness, and / or several other criteria.

[0269] In 2140, an additional M samples are collected by running the problem with an analog processor having the determined annealing schedule of act 2135. Optionally, method 2100 is repeated by returning to act 2115 and performing acts 2115-2135 based on the M samples, thereby refining the determined annealing schedule. In such embodiments, act 2120 is performed on valley v that were not selected during previous iterations of method 2100. i This may include making a choice. In the application form, the same valley v selected in the previous iteration i It can be used. Repeating is the end of the sentence. The process may terminate once certain criteria are met. For example, method 2100 may be repeated until the results converge, until the threshold number of iterations is reached, until all valleys are repeated and terminated, until no eligible valleys remain (where "eligible valley" refers to the valleys that can be selected in act 2120), and / or until some other criteria are met.

[0270] In step 2145, one or more samples generated by method 2100 are returned by at least one of a digital processor and an analog processor. In some embodiments, M samples collected in the last iteration of method 2100 are returned. In some embodiments, samples collected in multiple iterations are returned. For example, all samples collected by method 2100 may be returned. In some embodiments, a set of annealing schedules determined in one iteration of act 2135 is selected based on an optimality metric (e.g., the objective function of an optimization algorithm), and M samples generated according to these annealing schedules are returned.

[0271] Detection of quantum fluctuations using probe qubits To determine an improved or optimized annealing schedule, it may be beneficial to measure quantum fluctuations at different points in time during annealing. Quantum fluctuations tend to be high or maximum near quantum phase transitions, and it may be beneficial to slow down annealing when quantum fluctuations are high.

[0272] The systems and methods of this disclosure include techniques in which quantum fluctuations are measured directly via hardware and the results are used to improve or optimize the annealing schedule. In one embodiment, determining the improved or optimized annealing schedule is based on macroscopic resonant tunneling (MRT) noise measurement of quantum fluctuations.

[0273] In one embodiment, the one or more computational problems are encoded in a first subset of qubits available in the quantum processor. The qubits within the first subset are known as computational qubits. The qubits of a second subset (which have no common parts with the qubits of the first subset) include probe qubits that can operate to perform MRT noise measurements of quantum fluctuations during annealing. The probe qubit may be weakly coupled to the computational qubit, and the signal from the computational qubit detected by the probe qubit may be noisy.

[0274] The MRT peak width measurable by each probe qubit may depend on the integral of the noise spectrum and may vary according to quantum fluctuations arising from the computational qubit. As mentioned above, quantum fluctuations may increase near the phase transition point or the many-body localization point. An increase in the quantum fluctuations of the computational qubit coupled to the probe qubit may expand the MRT peak measurable by the probe qubit.

[0275] The annealing schedule can be adjusted, at least partially, based on the width of the MRT peak.

[0276] Figure 12 is a flowchart illustrating an exemplary method 1200 of operating a hybrid computer to adjust a quantum annealing schedule. Method 1200 as shown in Figure 12 involves several actions. One or more of these actions may be performed by (or via) one or more circuits, such as one or more processors (e.g., digital processors), analog processors such as quantum processors, or a hybrid computer that includes both digital and analog processors. For the purposes of describing Figure 12, it is assumed that the actions are performed by a hybrid computer that includes a quantum processor. Method 1200 describes an exemplary embodiment. Those skilled in the art will recognize that alternative embodiments may omit some actions and / or include additional actions.

[0277] At 1205, method 1200 is initiated. At 1210, the hybrid computer encodes the computation problem in a first subset of qubits within the quantum processor. In one embodiment, the qubits are superconducting flux qubits. At 1220, the hybrid computer allocates a second subset of qubits as probe qubits. The probe qubits may be weakly coupled to the qubits of the first subset. At 1230, the hybrid computer measures the MRT peak width. At 1240, the hybrid computer adjusts the annealing schedule at least in part based on one or more measurements of the MRT peak width. Method 1200 is terminated at 1245, for example, until called again.

[0278] Selection of annealing schedule using equilibrium energy statistics An annealing device (such as a physical quantum annealing device) can proceed according to an annealing schedule through a series of models between a prepared model and a target model. The prepared model may be, for example, a uniform superposition of states or a uniform distribution over classical states. The target model may be, for example, a distribution concerning the minimum value of the energy function or a Boltzmann distribution at low system temperatures. Physical (or Markov Chain Monte Carlo (MCMC)) dynamical properties may modify the state during annealing.

[0279] The goal of annealing is typically to sample from a final distribution that is as close as possible to the distribution of the target model. If the target distribution is a Boltzmann distribution described by an energy function E(x) or an energy operator (classical or quantum), it may be beneficial to select an annealing schedule that can improve or maximize the approximation of the final distribution to the target distribution.

[0280] The annealing schedule selected in this way is usually specific to a particular problem. However, there may be many large-scale problems that share statistical characteristics such that a single schedule can be sufficiently (practically) good for two or more problems. It may be beneficial to determine an improved or optimal schedule for the problem. A set of schedules can be presented to expert users, who can select them based on their evaluation. This method can also be adapted to select a suitable model (a set of discrete intermediate models preferred or optimized for parallel tempering) for multiple canonical MCMC procedures.

[0281] A thermal annealing apparatus can be programmed by a classical Hamiltonian H(x) and a set of inverse temperatures β. A function Γ(t) can be used to describe the time dependence of β, where Γ(0) = β min is the initial state, and Γ(1)=1 is the target state.

[0282] The quantum annealing device is a Hamiltonian operator.

number

[0283] The classical Hamiltonian can be defined as follows for the classical, semiclassical, or quantum case: H(x) = Γ T Φ(x)

[0284] Φ(x) is the vector when the schedule has two or more components. In the quantum case, the classical Hamiltonian can be constructed by the Trotter slice trick. Quantum (or In the semi-classical case, the first component Φ i (x) is a classical energy statistic, and energy It is conjugate to the energy scale (E) and models the variable that is a diagonal component in the operator expression. The second component Φ2(x) is conjugate to logΔ and does not exist in the diagonalized operator, so it is the quantum energy function.

[0285] The equilibrium energy distribution along the path within the orbit can be evaluated. The distribution can be approximated by a Gaussian distribution and modeled by its mean and covariance Σ. The quality of the schedule can be judged by multiplying the integral of the energy fluctuations along the orbit by the velocity at which the annealing instrument moves along the orbit. One approach is to maximize the following objective function, subject to the boundary conditions.

number

[0286] In the case where Γ(t) is a scalar or a function of one parameter (e.g., the presented classical case), a simple and straightforward solution to the above equation may exist, for example, using the following equation:

number

[0287] In the case where Γ(t) is a vector or a function of two or more parameters (e.g., the presented quantum case), one approach is to perform a local search method to find Γ. Another approach is to try to optimize a weighted combination of functions that satisfy the boundary conditions.

[0288] The Gaussian approximation can be suitable for a wide variety of distributions because the distribution error can accumulate over many steps or iterations, and the central limit theorem applies to the accumulation of errors.

[0289] If the target model has a zero transverse magnetic field (or a large energy scale), the Gaussian approximation may no longer be applicable. Optimization of at least part of the schedule may be possible. When the energy variance approaches zero sufficiently, the schedule can be terminated by quenching (i.e., by proceeding very rapidly), and the above procedure is no longer necessary at this stage.

[0290] Energy statistics used for model optimization can be collected, for example, by annealed importance sampling or parallel tempering.

[0291] Energy dispersion can be used to determine the schedule for thermal annealing (see, e.g., Kone and Kofke, 2005). The systems and methods of this disclosure address the challenge of determining the schedule for quantum annealing.

[0292] Energy statistics of a physical quantum annealer can be estimated. In one embodiment, the quantum hardware can be modeled as stoquastic (i.e., a function of transverse magnetic field, energy scale, and physical temperature). In this case, the equilibrium state characteristics of the hardware can be measured using quantum Monte Carlo methods.

[0293] Hardware dynamics can influence the degree of success. The systems and methods disclosed herein are likely to yield beneficial results for many problem classes using the optimized schedule described above. The degree of success can be measured, for example, by generating two different schedules, predicting the quality of samples for many problems, and determining whether there is a positive correlation with the quality of the output samples. The quality of the output samples can be measured, for example, by using the KL divergence, ground state frequency, or another suitable metric.

[0294] The benefits of this disclosure system and method may include some or all of the following: ● Selection of a suitable Hamiltonian annealing schedule that can be implemented without relying on dynamic insights; ● Selection of an annealing schedule based on estimated equilibrium energy statistics; ● Selection of the annealing schedule for a physical quantum annealer based on input from quantum simulations.

[0295] Figure 13 is a flowchart illustrating an exemplary method 1300 for adjusting the annealing schedule based on equilibrium energy statistics. In 1305, method 1300 begins. In 1310, the hybrid computer collects energy statistics by parallel tempering with respect to the classical Hamiltonian, Hamiltonian operator, or classical approximation of the Hamiltonian operator of the problem. The problem may be a problem selected to represent a specific problem or a group of problems.

[0296] In step 1320, the hybrid computer evaluates a fixed Γ equation to determine the expected quality of the results for a selected problem or a set of problems. In step 1330, the hybrid computer determines a preferred or optimized velocity (given a fixed trajectory in Γ) by inverting the cumulative distribution function. In step 1340, the hybrid computer determines a preferred or optimized trajectory by performing a local search. As described above, the local search in step 1340 can be replaced by a method that attempts to optimize a weighted combination of functions that satisfy the boundary conditions.

[0297] At 1345, the hybrid computer determines whether to repeat actions 1330 and 1340. If it determines at 1345 to repeat, method 1300 proceeds to 1330. If it determines at 1345 not to repeat, method 1300 proceeds to 1350, for example, until it is called again, and the method terminates. Repeating is optional, as shown by the dashed line in Figure 13.

[0298] Selecting an annealing schedule based on the objective function In some embodiments, the annealing schedule for a problem executable by an analog processor is selected by a digital processor based on an objective function. An example of such a selection method is shown as a flowchart in Figure 20. In 2005, the problem is received by the digital processor from which the annealing schedule is generated.

[0299] In 2010, the objective function is selected by a digital processor. The objective function may be determined (e.g., predetermined (considered a kind of selection in this disclosure)), selected by the user, selected depending on the characteristics of the problem, selected based on other actions in the Method (e.g., techniques applicable in 2015 and / or 2020), and / or selected in other ways. The objective function may measure at least partially one or more characteristics of an annealing schedule and provide various measures based on these characteristics to various annealing schedules (although various annealing schedules may not necessarily receive the same measures in every instance).

[0300] For example, the objective function might provide a measure of how the annealing schedule improves, degrades, or otherwise alters the performance of the problem. For example, the objective function might provide a measure of sample quality (if the problem involves sampling), computation success rate (e.g., the problem is associated with constraints that can be violated due to the analog nature of the computation), computational efficiency (e.g., a time-versus-solution metric), and / or several other measures relating to the performance of the problem as it is run according to the candidate annealing schedule.

[0301] In 2015, one or more annealing schedules are generated by a digital processor. For example, a set of candidate annealing schedules may be generated by a user or a remote computing system and received by a digital processor, and / or a set of candidate annealing schedules may be generated by a series of calculations performed by the digital processor. In some embodiments, the annealing schedules are generated by a computing system by performing an optimization algorithm based on an objective function. Exemplary implementations of Method 2000 using such optimization algorithms are described in further detail below.

[0302] In 2020, the annealing schedule is selected by a digital processor based on the objective function. For example, in 2020, the annealing schedule may be selected from a set of candidate annealing schedules by determining which of the annealing schedules in the group provides the best result (in this disclosure, “best” is used to mean “best of the choices considered,” and not necessarily the single most ideal annealing schedule that is possible). For example, if the objective function provides a measure of time versus solution, an annealing schedule that minimizes the objective function may be selected. In some embodiments, an annealing schedule that maximizes the objective function may be selected. In some embodiments, act 2020 may select an annealing schedule, which is then used in 2015 to generate another annealing schedule, which may then give rise to a variety of annealing schedules that are subsequently selected.

[0303] In at least some embodiments, generating and selecting annealing schedules may be performed sequentially and otherwise by a digital processor through a single act or operation, as alternating or superimposed acts or operations. For example, method 2000 may include performing an optimization algorithm that includes iteratively generating and evaluating annealing schedules to generate an optimized annealing schedule. Thus, acts 2015 and 2020 are not necessarily clearly separated in some embodiments. For convenience, acts 2015 and 2020 may be referred to collectively as act 2022, whether acts 2015 and 2020 are considered separately in a particular embodiment or not.

[0304] An annealing schedule may be selected for the optimality of its measure compared to other candidate annealing schedules, but it does not necessarily have to provide better computational results than each of the other candidate annealing schedules (for example, here the objective function provides a heuristic measure that is not perfectly correlated with the quality of the computational results). For example, an objective function that is relatively easy to compute and provides relatively consistent improvements to the computational results may be preferable in some situations to an objective function that is relatively expensive to compute and provides only slight (and / or inconsistent) improvements.

[0305] In 2025, the optimal annealing schedule (selected in 2020) is returned. This optimal annealing schedule can then be used by the analog processor in the process of computing the problem and / or related problems received in 2005.

[0306] The inventors have identified, through experimentation and theory, several combinations of optimization algorithms and objective functions that provide annealing schedules that tend to result in improvements to the computation of corresponding problems in at least some situations and with respect to at least some problems. These examples include optimizations and Bayesian optimizations for avoiding phase transitions (e.g., via parallel tempering). Embodiments thereof are described in further detail below.

[0307] In some embodiments, the objective function selected in 2010 measures the ability of the annealing schedule to reduce floppyness during annealing and / or avoid phase transitions. The objective function directly measures the ability to avoid phase transitions (e.g., by running the problem with the annealing schedule many times and determining the frequency of phase transitions) and / or indirectly (e.g., by proxying that ability to avoid phase transitions during annealing). This can be measured by measuring the characteristics of the annealing schedule.

[0308] For example, the objective function could describe the many models (also called replicas) and / or chains linking these models, generated in 2022 by a parallel tempering algorithm (e.g., a quantum parallel tempering algorithm). Parallel tempering can be performed on the problem (modified by a described annealing schedule) by a digital processor, thereby generating many models linked by a chain.

[0309] Parallel tempering algorithms are sometimes described as arranging models along a path that exists in a two-dimensional space whose dimensions are energy scale and temperature. Annealing schedules that tend to reduce floppyness and / or avoid phase transitions tend, in at least some situations, to require fewer models at the ends of the path in the higher energy region of this space to obtain a certain efficiency between adjacently placed models. Thus, such an annealing schedule can result in a parallel tempering algorithm that produces fewer models overall. Thus, in at least some situations, many of the models produced by a parallel tempering algorithm can An annealing schedule that minimizes the objective function describing the model (and / or the chain linking the model) tends to reduce floppyness during annealing and / or avoid phase transitions.

[0310] The objective function based on the model placement in a parallel tempering algorithm can be computed relatively efficiently by performing a limited number of iterations (or "sweeps") of the parallel tempering algorithm. While it is understood that parallel tempering algorithms can be used to directly solve the problem received in 2005, this can require many iterations (often hundreds of thousands or millions). However, finding an efficient model placement usually requires far fewer iterations (at least thousands or tens of thousands in some cases). Therefore, a modified (partial) parallel tempering algorithm that terminates after fewer iterations than might be possible to solve the problem can be used.

[0311] In some embodiments, action 2022 involves Bayesian optimization. In some such embodiments, the objective function selected in 2010 provides a measure of the ground state distribution of the problem (modified by a measured annealing schedule) performed by a digital processor. Such measures may correlate with the uniformity of the distribution and / or the outlier properties within the distribution. For example, the objective function may provide an entropy measure of the ground state distribution, the distance of the ground state distribution from a uniform distribution, the Gini coefficient of the ground state distribution, the width of the ground state distribution (e.g., the ratio of the minimum probability to the maximum probability), and / or several other measures of the ground state distribution. In at least some embodiments, the Bayesian optimization algorithm aims to maximize an entropy-based objective function and minimize other objective functions.

[0312] Any suitable acquisition function and surrogate model may be used. In some embodiments, the Bayesian optimization algorithm is performed by using the expected improvement acquisition function and Gaussian process of the surrogate model. The alternative (or additional) acquisition function includes the probability and confidence upper bound of improvement. The alternative (or additional) surrogate model includes linear models, regression trees and random forests, and neural networks. Once a suitable objective function, acquisition function, and surrogate model are selected, Bayesian optimization may be performed to generate and select an optimal annealing schedule.

[0313] Auxiliary qubit delta tuning By advancing or delaying the floppy qubit or the floppy region of the qubit during quantum annealing, the effects of degeneracy can be mitigated and hardware performance can be improved. Mitigation can be achieved by using a local CCJJ DAC bias. By advancing or delaying the floppy qubit, the tunneling speed Δ q Quantum hardware that reduces The persistent current can then be desynced, leading to errors in the qubit bias and coupling term (h and J, respectively). While these errors can be corrected all at once during the quantum annealing process, advancing or delaying the floppy qubit can introduce time-dependent errors in h and J in the mitigated device. Consequently, the final Hamiltonian can be distorted by the mitigation process.

[0314] The systems and methods of this disclosure include alternative mitigation techniques that use auxiliary qubits instead of local CCJJ DAC biases. In this technique, qubits within a quantum processor may have associated auxiliary qubits that can be tunably coupled to an intensity J. In one embodiment, the auxiliary qubit is a dedicated auxiliary device accompanying a processor qubit. In another embodiment, the auxiliary qubit is a processor qubit reserved for use as an auxiliary qubit rather than being used as a computation qubit.

[0315] A floppy qubit or floppy region can be identified using a small number of samples via an initial Hamiltonian. Auxiliary qubits can be coupled to the floppy qubit or region by a coupling strength J designed to modify the dynamical properties of the floppy qubit or region. In some cases, the coupling strength J is designed to slow down the dynamical properties of the floppy qubit or region.

[0316] By coupling a floppy qubit with an auxiliary qubit, the tunneling amplitude of the floppy qubit can be modified as follows:

number

[0317] In one embodiment, the auxiliary device resides on a separate annealing line to the floppy qubit. In another embodiment, the CCJJ DAC within the quantum processor is Δ ancilla reduction This can be used to further modify the dynamic characteristics of the auxiliary device. floppy and |I p Orthogonal control with | eliminates or at least reduces the time-dependent errors of h and J. This can be achieved in this way.

[0318] Figure 14 is a flowchart illustrating an exemplary method 1400 for mitigating the effects of degeneracy using auxiliary qubits. Method 1400 as shown in Figure 14 involves several actions. One or more of these actions may be performed by (or via) one or more circuits (e.g., one or more processors (e.g., digital processors) and analog processors such as quantum processors, or a hybrid computer including both digital and analog processors). For the purposes of describing Figure 14, it is assumed that the actions are performed by a hybrid computer including a quantum processor. Method 1400 describes an exemplary embodiment. Those skilled in the art will recognize that alternative embodiments may omit some actions and / or include additional actions.

[0319] Method 1400 begins at 1405. At 1410, the hybrid computer sends the computation problem to the quantum hardware. At 1415, the hybrid computer collects a set of samples from the quantum hardware. At 1420, the hybrid computer determines whether a qubit (or region of qubits) is floppy within the sample by inverting the qubit state and determining whether this changes the energy of the sample.

[0320] At step 1425, the hybrid computer determines whether another sample exists. If the hybrid computer determines at step 1425 that another sample exists, method 1400 returns to step 1420. If the hybrid computer determines at step 1425 that no other sample exists, method 1400 proceeds to step 1430.

[0321] In 1430, the hybrid computer uses a "normalized floppyness metric" μ to describe a portion of the samples where the qubits are floppies. i Generate as follows do: μ i =n i / N Here, n i is the number of times a qubit is floppy disk, and N is the number of times the metric is generated. This is the number of samples used for analysis.

[0322] The floppyness metric is an exemplary metric that may be used. In other embodiments, other preferred metrics may be used. More generally, the systems and methods disclosed herein may include collecting a sample and processing the sample to determine which qubit should be advanced (or delayed) next and by how much. Processing is not limited to determining floppyness or the floppyness metric. Other preferred processing methods may be used to determine which qubit should be advanced (or delayed) next and by how much.

[0323] In 1435, the hybrid computer adds an auxiliary qubit to the floppy qubit and then couples it with the intensity J as described above to modify the tunneling amplitude. In one embodiment, an auxiliary qubit is added for each floppy qubit. In another embodiment, an auxiliary qubit is added for each subset of floppy qubits. In one embodiment, Δ floppy ≒Δ q (1-μ i ).

[0324] At step 1440, the hybrid computer determines whether another qubit exists. If the hybrid computer determines at step 1440 that another qubit exists, method 1400 returns to step 1420. If the hybrid computer determines at step 1440 that no other qubit exists, method 1400 proceeds to step 1445.

[0325] At step 1445, the hybrid computer determines whether to collect another set of samples. If the hybrid computer determines at step 1445 that it should collect another set of samples, method 1400 returns to step 1415. If the hybrid computer determines at step 1445 that it should not collect another set of samples, method 1400 proceeds to step 1450.

[0326] Use an auxiliary qubit to correct the h / J mismatch. Quantum annealing can involve evolving a time-dependent Hamiltonian from a simple superposition to a useful classical problem. A drawback of quantum annealing is that the annealer can be biased towards an undesirable state if that state is undesirable to the final Hamiltonian but still desirable to earlier intermediate Hamiltonians during annealing. This can occur, for example, if both the h (qubit bias) term and the J (coupling) term are used. The bias term can be given a relatively higher priority than the coupling term earlier in annealing. This can lead to a time-dependent h / J mismatch that pushes the annealer towards an undesirable subspace (or valley in the energy landscape). To find a desirable or correct solution, the annealer tunnels from the undesirable subspace to another valley.

[0327] A mismatch occurs when the join term in the Ising Hamiltonian has an expected value that is fast during annealing. This can occur because it is weighted by the product of at least two Pauli matrices of smaller size at a given time. In contrast, the bias term is typically weighted by a single Pauli matrix with a higher expected size than the combined term at an earlier stage of annealing, as follows:

number

[0328] The system and methods disclosed herein provide techniques for mitigating the aforementioned h / J mismatch. This method uses local bias h i This includes shifting the qubit to an auxiliary qubit. tq i and input bias h i Regarding =x, the auxiliary qubit q' i This can be added, and a large negative Ias (for example, h' i =-2) is the auxiliary qubit q' i It can be provided to. The bias is usually the auxiliary qubit q'. i The above bias is large enough so that it does not interfere in the ground state. It is selected in such a way that it becomes less desirable. Next, the qubit q i and auxiliary qubit q' i The connection between them is set to x, and the qubit q i The above bias can be set to 0. Input bias |x| ≤ 1 Therefore, this falls within the range of acceptable coupler values.

[0329] In one embodiment, if |x|≪1, the qubit and the auxiliary qubit may be coupled by a coupler having a value of -1, and the bias of x is used to ensure that the coupler does not interfere in the ground state by using the auxiliary qubit (h' i In another embodiment, |x|≪ If it is 1, the state is handled in the same way as described in the previous paragraph for the general case of |x|.

[0330] If |x|>1, then bias hi Part of it is an auxiliary qubit q' i It can be shifted to coupling with a single auxiliary qubit. In one embodiment, a portion of the bias is shifted to coupling with a single auxiliary qubit. In another embodiment, a portion of the bias is shifted to two or more auxiliary qubits.

[0331] Figure 15 is a flowchart illustrating an exemplary method 1500 for mitigating h / J mismatch using auxiliary qubits. The method 1500 shown in Figure 15 comprises several actions. One or more of these actions may be performed by (or via) one or more circuits (e.g., one or more processors (e.g., digital processors) and analog processors such as quantum processors, or a hybrid computer including both digital and analog processors). For the purposes of describing Figure 15, it is assumed that the actions are performed by a hybrid computer including a quantum processor. Method 1500 describes an exemplary embodiment. Those skilled in the art will recognize that alternative embodiments may omit some actions and / or include additional actions.

[0332] Method 1500 begins at 1505. At 1510, the hybrid computer receives the qubit bias. At 1515, the hybrid computer adds an auxiliary qubit. At 1520, the hybrid computer determines whether the bias is less than or equal to 1. If the hybrid computer determines at 1520 that the bias is less than or equal to 1, Method 1500 proceeds to 1525. At 1525, the hybrid computer determines whether the bias is much less than 1. If the hybrid computer determines at 1525 that the bias is much less than 1, Method 1500 proceeds to 1530. At 1530, the hybrid computer couples the qubit and the auxiliary qubit with a coupler of value -1. At 1535, the hybrid computer gives the qubit bias to the auxiliary qubit, and Method 1500 proceeds to 1540.

[0333] If the hybrid computer determines at 1525 that the bias is not significantly less than 1, then method 1500 proceeds to 1545. At 1545, the hybrid computer assigns a large negative bias (e.g., -2) to the auxiliary qubit. At 1550, the hybrid computer sets the coupling between the qubit and the auxiliary qubit to the input bias value. At 1555, the hybrid computer sets the bias of the qubit to zero, and method 1500 proceeds to 1540.

[0334] If the hybrid computer determines at 1520 that the bias is greater than 1, then method 1500 proceeds to 1560. At 1560, the hybrid computer moves a portion of the input bias to the coupling to the auxiliary qubits, and method 1500 proceeds to 1540.

[0335] In step 1540, the hybrid computer determines whether there is another qubit that can be bias-tuned. If the hybrid computer determines in step 1540 that there is another qubit that can be bias-tuned, then method 1500 returns to step 1510.

[0336] If the hybrid computer determines at 1540 that there are no other qubits that can be bias-adjusted, method 1500 returns to 1565 and proceeds. At 1565, method 1500 terminates.

[0337] Hybrid computing systems including quantum processors Figure 16 shows an exemplary hybrid computing system 1600, which includes a digital computer 1605 coupled to an analog computer 1651. In some embodiments, the analog computer 1651 is a quantum computer, and the digital computer 1605 is a classical computer. The exemplary digital computer 1605 includes a digital processor that may be used to perform the classical digital processing tasks described in this system and method. Those skilled in the art will understand that this system and method, once properly configured or programmed to form a dedicated machine and / or communicatively coupled to control an analog computer (e.g., a quantum computer), can be implemented by other digital computer configurations, including portable devices, multiprocessor systems, microprocessor-based or programmable consumer electronics, personal computers (PCs), network PCs, minicomputers, mainframe computers, etc.

[0338] The digital computer 1605 will be referred to singly herein, but this is not intended to limit the application to a single digital computer. The system and method may also be implemented in a distributed computing environment in which a task or a set of processor-readable instructions is performed or executed by remote processing devices linked over a communication network. In a distributed computing environment, computers or processor-readable instructions (sometimes known as program modules), application programs and / or data may reside in both local and remote storage devices (e.g., non-temporary computers or processor-readable media).

[0339] The digital computer 1605 may include at least one digital processor (such as a central processor unit) 1610, at least one system memory 1620, and at least one system bus 1617 that connects various system components, including the system memory 1620, to the digital processor 1610.

[0340] The digital processor(s) 1610 includes, for example, one or more cores (for example, one or more central processing units (CPUs), graphics processing units) ( This can be any logic processing unit having a GPU (graphics processing unit), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA). Unless otherwise stated, the structure and operation of the various blocks shown in Figure 16 are of conventional design. As a result, such blocks are understood by those skilled in the art and do not need to be described in further detail herein.

[0341] The digital computer 1605 may include a user input / output subsystem 1611. In some embodiments, the user input / output subsystem may include a display 1612, a mouse 1 613 and / or one or more user input / output components such as a keyboard 1614. The system bus 1617 may employ any known bus structure or architecture, including a memory bus with the memory controller, peripheral buses, and local buses. The system memory 1620 may include non-volatile memory such as read-only memory (ROM), static random access memory (SRAM), and flash NAND, and volatile memory such as random access memory (RAM) (not shown). All of these are examples of non-temporary computer or processor-readable media. A basic input / output system (BIOS) 1621, which may form part of the ROM, is used during the boot period, etc. It includes basic routines that help transfer information between elements within the digital computer 1605.

[0342] The digital computer 1605 may also include other non-volatile memory 1615. The non-volatile memory 1615 may take various forms, including a hard disk drive for reading from and writing to a hard disk, an optical disk drive for reading from and writing to a removable optical disk, and / or a magnetic disk drive for reading from and writing to a magnetic disk. All of these are examples of non-temporary computer or processor-readable media. The optical disk may be a CD-ROM or DVD, while the magnetic disk may be a magnetic floppy disk or diskette. The non-volatile memory 1615 may communicate with the digital processor via the system bus 1617 and may include a suitable interface or controller 1616 coupled to the system bus 1617. The non-volatile memory 1615 may function as a long-term storage device for computer or processor-readable instructions, data structures, or other data (also called program modules) of the digital computer 1605.

[0343] While the digital computer 1605 was described as employing hard disks, optical disks, and / or magnetic disks, those skilled in the art will understand that other types of non-volatile computer-readable media may be employed, such as magnetic cassettes, flash memory cards, flash memory, ROM, and smart cards. All of these are other examples of non-volatile computer or processor-readable media. Those skilled in the art will understand that some computer architectures combine volatile and non-volatile memory. For example, data in volatile memory may be cached in non-volatile memory, or a solid disk employing an integrated circuit to provide non-volatile memory. Some computers place data that would traditionally be stored on disks into memory. Similarly, some media traditionally considered volatile may have a non-volatile form (e.g., a non-volatile dual in-line memory module, which is a variation of a dual in-line memory module).

[0344] Various sets of computer or processor-readable instructions (also called program modules), application programs, and / or data may be stored in system memory 1620. For example, system memory 1620 may store an operating system 1623 and a set of computer or processor-readable server instructions (i.e., server modules) 1625. In some embodiments, the server module 1625 includes instructions for communicating with remote clients and scheduling the use of resources, including resources on the digital computer 1605 and the analog computer 1651. For example, a web server application and / or a web client or browser application that allows the digital computer 1605 to exchange data not only with sources but also with other server applications running on the server computer via the Internet, a corporate intranet, or other network.

[0345] In some embodiments, the system memory 1620 is used for calculation instructions, analog computing It may store other sets of computer or processor-readable instructions 1627, such as interface instructions.

[0346] Although shown in Figure 16 as being stored in system memory 1620, the shown modules and other data may also be stored elsewhere, including in non-volatile memory 1615 or in one or more other non-temporary computer or processor-readable media.

[0347] The analog computer 1651 may be placed in an isolated environment (not shown). For example, if the analog computer 1651 is a quantum computer, the environment shields the internal elements of the quantum computer from heat, magnetic fields, and other external noise (not shown), and / or cools the analog processor to a temperature below which the circuitry of the analog processor exhibits superconductivity (i.e., a critical temperature). In contrast, the digital computer 1605 typically operates at much higher temperatures (e.g., room temperature) where superconductivity does not occur, and / or the digital computer 1605 may employ materials that do not superconduct even below a critical temperature. The analog computer 1651 includes an analog processor 1640. An example of the analog processor 1640 includes a quantum processor, such as those described below with reference to Figure 13.

[0348] The quantum processor includes programmable elements such as qubits, couplers, and other devices. Qubits are read out via a readout system 1660. These results are sent to various sets of computer- or processor-readable instructions of a digital computer 1605, including a server module 1625 or other modules 1627, stored in non-volatile memory 1615, and returned over a network or the like. Qubits are controlled via a qubit control system 1665. Couplers are controlled via a coupler control system 1670. In some embodiments, the qubit control system 1665 and the coupler control system 1670 are used to perform quantum annealing on an analog processor 1640 as described herein.

[0349] In some embodiments, the digital computer 1605 may operate within a networking environment using a logical connection to at least one client computer system. In some embodiments, the digital computer 1605 is connected to at least one database system via a logical connection. These logical connections can be formed using any means of digital communication over a network, such as a local area network (LAN) or a wide area network (WAN), such as the Internet. This may be achieved. The networking environment may include wired or wireless enterprise-scale computer networks, intranets, extranets, and / or the Internet. Other embodiments may include other types of communication networks, such as telecommunications networks, cellular networks, paging networks, and other mobile networks. Information transmitted or received over a logical connection may or may not be encrypted. When used in a LAN networking environment, the digital computer 1605 may be connected to the LAN via an adapter or network interface card (NIC) (communically coupled to the system bus 1617). When used in a WAN networking environment, the digital computer 1605 may include an interface and devices such as a modem (not shown) or NIC for establishing communication over the WAN. Non-network communication may be employed in addition or alternatively.

[0350] Exemplary Superconducting Quantum Processor in Quantum Annealing Figure 17 is a schematic diagram of a portion of an exemplary superconducting quantum processor 1700 designed for quantum annealing (and / or adiabatic quantum computing) components that may be used to realize this system and device. The portion of the superconducting quantum processor 1700 shown in Figure 17 includes two superconducting qubits 1701 and 1702. A tunable coupling (diagonal coupling) between 02 via the coupler 1710 (i.e., providing two local interactions) is also shown. While the quantum processor 1700 shown in Figure 17 includes only two qubits 1701, 1702 and one coupler 1710, those skilled in the art will recognize that the quantum processor 1700 may include any number of qubits and any number of couplers coupling the information between them.

[0351] A portion of the quantum processor 1700 shown in Figure 17 may be implemented to physically realize quantum annealing and / or adiabatic quantum computing. The quantum processor 1700 includes a number of interfaces 1721-1725 used to configure and control the state of the quantum processor 1700. Each of the interfaces 1721-1725 may be realized by their respective inductively coupled structures as shown, as part of a programming subsystem and / or evolution subsystem. Such programming subsystems and / or evolution subsystems may be separate from the quantum processor 1700 or may be locally included (i.e., on-chip with the quantum processor 1700).

[0352] During the operation of the quantum processor 1700, interfaces 1721 and 1724 couple the magnetic flux signals into the composite Josephson junctions 1731 and 1732 of the qubits 1701 and 1702, respectively, thereby creating a tunable tunneling term (Δ i (Item) to the system This can be used to realize it within the Hamiltonian. This bond is the off-diagonal σ of the Hamiltonian. x These terms provide examples of "delocalized signals" for magnetic flux signals.

[0353] In some embodiments, the tunneling term is selected to make the first portion of the qubits on the quantum processor more classical compared to the second portion of the qubits. For example, qubit 1701 is a hidden unit in the Boltzmann machine and may have a smaller tunneling term compared to qubit 1702.

[0354] Similarly, interfaces 1722 and 1723 can be used to apply the flux signal to the respective qubit loops of qubits 1701 and 1702, thereby realizing the hi term within the system Hamiltonian. This coupling is diagonal σ z The term is in the system It is provided within the Hamiltonian. Furthermore, interface 1725 couples the magnetic flux signal into coupler 1710, thereby J ij The term can be used to realize the system Hamiltonian. This connection is diagonal.

number

[0355] In Figure 17, the respective contributions of interfaces 1721–1725 to the evolutionary Hamiltonian are shown in boxes 1721a–1725a, respectively. As shown, in the example in Figure 17, boxes 1721a–1725a are elements of the time-varying Hamiltonian for quantum annealing and / or adiabatic quantum computing.

[0356] Throughout this specification and the appended claims, the term “quantum processor” is used to generally describe a set of physical qubits (e.g., qubits 1701, 1702) and a coupler (e.g., coupler 1710). The physical qubits 1701, 1702 and coupler 1710 are called “programmable elements” of the quantum processor 1700, and their corresponding parameters (e.g., qubit h i Value, coupler J ij The value is the "program" of the quantum processor. This is called the "programmable parameter." In the context of quantum processors, the term "programming subparameter" is used. The term "system" is used to generally describe the interface used to apply programmable parameters to the programmable elements of the quantum processor 1700 and other associated control circuits and / or instructions (e.g., "programming interface" 1722, 1723, 1725).

[0357] As previously explained, the programming interface of the programming subsystem may communicate with other subsystems that may be separate from the quantum processor or locally contained on the quantum processor. As will be described in more detail later, the programming subsystem may be configured to receive and execute machine language program instructions of the quantum processor in order to program programmable elements according to the program instructions. Similarly, in the context of a quantum processor, the term “evolutionary subsystem” is used to generally describe interfaces (e.g., “evolutionary interfaces” 1721 and 1724) used to evolve the programmable elements of the quantum processor 1700 as well as other related control circuits and / or instructions. For example, the evolutionary subsystem may include interfaces (1721, 1724) to annealing signal lines and their corresponding qubits (1701, 1702).

[0358] The quantum processor 1700 also includes readout devices 1751 and 1752. Readout device 1751 is associated with qubit 1701, and readout device 1752 is associated with qubit 1702. In some embodiments, such as those shown in Figure 17, each of the readout devices 1751 and 1752 includes a DC-SQUID inductively coupled to the corresponding qubit. In the context of the quantum processor 1700, the term “readout subsystem” is generally used to describe the readout elements 1751 and 1752 used to read the final state of qubits (e.g., qubits 1701 and 1702) in the quantum processor in order to generate bit sequences. The readout subsystem also includes other elements such as routing circuits (e.g., latch elements, shift registers, or multiplexer circuits) and / or may be arranged in alternative configurations (e.g., XY addressable arrays, XYZ addressable arrays, etc.). Qubit readout can also be performed using alternative circuits, such as those described in PCT Patent Application International Publication No. 2012064974.

[0359] Figure 17 shows only two physical qubits 1701, 1702, one coupler 1710, and two readout elements 1751, 1752, but a quantum processor (e.g., processor 1700) may employ any number of qubits, couplers, and / or readout elements, including a large number (e.g., hundreds, thousands, or more). The application of the teachings herein to processors with a different (e.g., larger) number of computer components should be readily apparent to those skilled in the art.

[0360] Examples of superconducting qubits include superconducting flux qubits and superconducting charge qubits. In superconducting flux qubits, the Josephson energy is greater than or equal to the charge energy. In charge qubits, the opposite is true. Examples of flux qubits that can be used include rf-SQUIDs, which contain a superconducting loop blocked by one Josephson junction, and persistent current qubits, which contain a superconducting loop blocked by three Josephson junctions.

[0361] The qubits and coupling devices within a quantum processor can be arranged within a topology based on the architecture such that a certain number of qubits can be arranged in a subtopology of qubits (hereinafter simply referred to as a "subtopology"). A subtopology is part of the quantum processor topology, including the qubits and coupling devices. Multiple subtopologies are repeated across the entire domain of the quantum processor to generate a given quantum processor topology. They may be tiled (or otherwise coupled together so that they can communicate directly with each other).

[0362] In some embodiments, each subtopology within a topology is identical to each other subtopology within the same topology. In other embodiments, one or more subtopologies within a topology include qubits and coupling devices with a different configuration from other subtopologies within the same topology.

[0363] The above description of the embodiments shown, including those described in the abstract, is not intended to be exhaustive or to limit embodiments to the exact form disclosed. While specific embodiments and examples have been described herein for illustrative purposes, various equivalent modifications can be made without departing from the spirit and scope of this disclosure, as will be recognized by those skilled in the art. The teachings described herein for various embodiments may be applicable to other analog processors and not necessarily to the exemplary quantum processors outlined above.

[0364] The various embodiments described above may be combined to provide other embodiments. Unless otherwise specified in relation to the specific teachings and definitions herein, all U.S. patent application publications, U.S. patent applications, U.S. patents, foreign patents, and foreign patent applications referenced herein and / or enumerated in the application datasheet, which are commonly assigned to D-Wave Systems, Inc., are incorporated herein by reference in their entirety: U.S. No. 7,984,012; U.S. No. 8,244,662; U.S. No. 8,174,305; U.S. No. 8,670,807; U.S. No. 8,700,689; PCT Patent Application Publication International Publication No. 2012064974; U.S. Patent Application U.S. Provisional Patent Application No. 2015 / 0032994; U.S. Provisional Patent Application No. 62 / 247,085 filed October 27, 2015; U.S. Provisional Patent Application No. 62 / 324,210 filed April 18, 2016; U.S. Provisional Patent Application No. 62,331,288 filed May 3, 2016; U.S. Provisional Patent Application No. 62 / 399,764 filed September 26, 2016; U.S. Provisional Patent Application No. 62 / 375,785; and U.S. Provisional Patent Application No. 62 / 399,683 (Agent Reference Number 240105.581P1), which is the enclosed file titled "System, Method and Device for Sampling from a Sampling Server". The aspects of the embodiments may be modified as necessary to adopt systems, circuits and concepts from various patents, applications and publications in order to provide yet another embodiment.

[0365] These and other modifications may be made to the embodiments described above in light of the detailed description above. In general, the terms used in the following claims should not be interpreted as limiting the claims to this specification and the specific embodiments disclosed herein, but rather to include all possible embodiments together with the entire scope of equivalents to which such claims are granted. Thus, the claims are not limited by this disclosure.

Claims

1. A method used by a digital processor to tune the annealing speed of at least one qubit of a quantum processor, The first encoding of the problem is to receive the first encoding which includes one or more qubits, The first encoding is modified by representing one of the one or more qubits as a logical qubit, thereby generating a second encoding of the problem, wherein the logical qubit includes a plurality of internal qubits of the quantum processor coupled by internal coupling, and the logical qubit has an effective tunneling speed reduced compared to the tunneling speed of the qubit among the one or more qubits before modification. Based on the second encoding, the problem is to be computed by the quantum processor, A method that includes this.

2. The method according to claim 1, comprising selecting at least one of the number of internal qubits and the internal coupling strength of the logic qubits such that the effective tunneling speed approximates the target tunneling speed.

3. The method according to claim 1, wherein the qubit among the one or more qubits includes an initial logic qubit.

4. The method according to claim 1, comprising selecting a topology in which the logical qubits affect the effective tunneling speed.

5. The method according to claim 4, wherein the selection of a topology includes selecting the topology from the plurality of topologies based on the minimum internal coupling strength associated with each of the plurality of topologies.

6. The method according to claim 5, wherein selecting the topology from a plurality of topologies based on the minimum internal coupling strength includes selecting the topology based on the correspondence between the minimum internal coupling strength and the number of internal qubits coupled with qubits outside the logical qubit.

7. The method according to claim 1, further comprising: correcting the effective tunneling speed of the logic qubit by determining a tunneling speed offset based on the characteristics of the logic qubit; and correcting the effective tunneling speed of the logic qubit by applying the tunneling speed offset to an annealing schedule.

8. The method according to claim 7, wherein the logical qubit has a chain topology, and determining the tunneling velocity offset based on the characteristics of the logical qubit includes determining the tunneling velocity offset based on the chain length.

9. The method according to claim 7, wherein determining the tunneling velocity offset includes determining a scaling factor and scaling the offset value by the scaling factor.

10. The method according to claim 9, wherein scaling the offset value by the scaling coefficient includes scaling the offset value based on the following formula, [Math 1] Here, k is the length of the chain topology of the logical qubit.

11. The method according to claim 8, wherein receiving a first encoding of a problem includes receiving the first encoding as a multiplication circuit embedding a factorization problem.

12. The method according to claim 7, wherein the characteristics include the position of the logical qubit in a graph relative to one or more other qubits, and determining the tunneling velocity offset based on the characteristics of the logical qubit includes determining the tunneling velocity offset based on the position of the logical qubit in a graph relative to one or more other qubits.

13. The method according to claim 12, wherein the graph includes an embedding graph, and determining the tunneling velocity offset includes determining the tunneling velocity offset based on the position of the logical qubit in the embedding graph relative to one or more other qubits.

14. The method according to claim 12, wherein determining the tunneling velocity offset includes determining the distance between the logic qubit and the origin and determining the tunneling velocity offset based on the distance.

15. The method according to claim 12, wherein determining the tunneling velocity offset includes determining the distance between the logic qubit and the edge of the graph and determining the tunneling velocity offset based on the distance.

16. The method according to claim 12, wherein determining the tunneling velocity offset includes determining the tunneling velocity offset based on a gradient defined with respect to at least a portion of the graph.

17. The method according to claim 16, wherein the gradient includes a radial gradient having a first region close to the origin, the annealing schedule is advanced relative to the annealing schedule in a second region, the second region being further from the origin than the first region.

18. A method according to claim 1, further comprising determining the effective tunneling rate of the logical qubit based on an annealing subschedule specific to the logical qubit and an annealing schedule defined across the entire set of qubits, wherein at least one of the set of qubits is not contained within the logical qubit.

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