Power supply unit and image processing unit

Abstract

To provide a power supply device and an image processing device for preventing output voltage malfunction after recovery when the output voltage drops due to a drop, instantaneous interruption, momentary power outage in AC input voltage, and the like.SOLUTION: A power supply device 10A includes: a FET_Q1 that switches a logical output (5 V output) to OFF when the power supply device 10A transitions to an energy-saving mode and switches the 5 V output, which is turned OFF when transiting to the energy-saving mode, to ON when canceling the energy-saving mode; and a drive circuit 7A that generates a gate voltage to operate the FET_Q1. The drive circuit 7A has a photocoupler PC1 used as a discharge-promoting unit that promotes discharging the gate potential of the FET_Q1 and switches the FET_Q1 to OFF when the voltage of the 5 V output capable of switching ON / OFF by the FET_Q1 is lower than the potential of the gate voltage of the FET_Q1.SELECTED DRAWING: Figure 10

Description

Technical Field

[0001] The present invention relates to a power supply device and an image processing apparatus.

Background Art

[0002] From the perspective of environmental protection, it has become standard for many electronic devices to employ a power supply device provided with an energy-saving mode that reduces power consumption as much as possible when the device is not in use.

[0003] In such a power supply device, if an instantaneous interruption or the like of an AC input voltage occurs in an actual operating state where the energy-saving mode is canceled, a malfunction may occur in the output voltage when recovering from the instantaneous interruption or the like.

[0004] Patent Document 1 discloses a configuration that discharges or forcibly reduces a secondary output voltage in order to prevent malfunction of the output voltage (overcurrent or limitation due to the maximum duty of a converter) caused by a drop, instantaneous interruption, or voltage sag of the AC input voltage.

Summary of the Invention

Problem to be Solved by the Invention

[0005] However, in the conventional methods described in Patent Document 1 and the like, there is room for improvement in terms of preventing malfunction after recovery from an instantaneous interruption or the like, depending on conditions such as the load state of the device and the duration of the instantaneous interruption.

[0006] An object of the present invention is to prevent malfunction of an output voltage after recovery when the output voltage drops due to influences such as a drop, instantaneous interruption, or momentary outage of an AC input voltage.

Means for Solving the Problem

[0007] To solve the above-mentioned problems, a power supply device according to one aspect of the present invention includes a first FET that switches a logic system output or a drive system output to OFF when the power supply device transitions to an energy-saving mode, and switches the output that was OFF when transitioning to the energy-saving mode to ON when the energy-saving mode is released, and a drive circuit that generates a gate voltage to operate the first FET, wherein the drive circuit is switched ON / OFF by the first FET. but Switchable The drive system output that is not present When the voltage falls below the potential of the gate voltage of the first FET, the gate of the first FET Connect to ground The device has a discharge promotion unit that turns off the first FET. [Effects of the Invention]

[0008] This system can prevent malfunctions in the output voltage after it has been restored when the output voltage drops due to effects such as a decrease in AC input voltage, momentary interruption, or momentary power outage. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a block diagram showing the schematic configuration of the power supply unit for the reference configuration. [Figure 2] This diagram shows the normal transition when switching to energy-saving mode in a power supply unit of the reference configuration. [Figure 3] A diagram showing an example of the circuit configuration of a drive circuit related to the reference form. [Figure 4] This figure shows the change in gate potential during the transition to energy-saving mode in a power supply circuit of the reference configuration. [Figure 5] This diagram shows the normal status of the 5V output during a momentary interruption of the AC input voltage in a power supply unit of the reference configuration. [Figure 6] This diagram shows the progression of abnormalities in the 5V output when an AC input voltage interruption occurs in a power supply unit of the reference configuration. [Figure 7] This diagram shows the change in gate potential during momentary interruptions and shutdowns of the AC input voltage in a power supply circuit of the reference configuration. [Figure 8] This diagram illustrates overcurrent protection control when the AC input voltage is turned off in a power supply unit of the reference configuration. [Figure 9] A diagram explaining malfunction caused by overcurrent protection control when an AC input voltage is momentarily interrupted in a power supply device according to a reference embodiment [Figure 10] A diagram showing an example of a circuit configuration of a drive circuit according to the first embodiment [Figure 11] A diagram showing a transition of 5V output when a momentary interruption of an AC input voltage occurs, corresponding to FIG. 5 of the reference embodiment, in the power supply device according to the first embodiment [Figure 12] A diagram showing a transition of 5V output when a momentary interruption of an AC input voltage occurs, corresponding to FIG. 6 of the reference embodiment, in the power supply device according to the first embodiment [Figure 13] A diagram explaining a transition when an AC input voltage is turned off, corresponding to FIG. 8 of the reference embodiment, in the power supply device according to the first embodiment [Figure 14] A diagram explaining a transition when an AC input voltage is momentarily interrupted, corresponding to FIG. 9 of the reference embodiment, in the power supply device according to the first embodiment [Figure 15] A block diagram showing a schematic configuration of a power supply device according to the second embodiment [Figure 16] A diagram showing an example of a circuit configuration of a drive circuit according to the third embodiment Mode for Carrying Out the Invention

[0010] Embodiments will be described below with reference to the accompanying drawings. To facilitate understanding of the description, the same constituent elements are denoted by the same reference numerals as much as possible in each drawing, and duplicate descriptions are omitted.

[0011] In the following description, an image forming apparatus 100 will be exemplified as an example of an electronic device to which the power supply devices 10A and 10B according to the embodiments are applied.

[0012] [Reference Embodiment] First, the configuration and problems of a conventional power supply device 10 as a reference embodiment will be described with reference to FIGS. 1 to 9.

[0013] FIG. 1 is a block diagram showing a schematic configuration of a power supply device 10 according to a reference embodiment. The power supply device 10 is applied to an image forming apparatus 100, which is an image processing apparatus as an example of an electronic device. The power supply device 10 is electrically connected to a logic system load (controller) 8, which is an image processing unit of the image forming apparatus 100, and a drive system load (motor or the like) 9, is supplied with electric power, and operates an image forming unit.

[0014] The power supply device 10 includes a rectifier circuit unit 1, a PFC circuit unit 2, a drive system converter 3, a logic system converter 4, a transmission photocoupler 5, an FET 6, and a drive circuit 7.

[0015] The rectifier circuit unit 1 is connected to a commercial power supply 11, and performs full-wave rectification on the commercial power supply 11 by a bridge diode.

[0016] The PFC circuit unit 2 is connected to the rectifier circuit unit 1, and converts an input current to the power supply device 10 into a sine wave to perform harmonic current suppression and power factor improvement.

[0017] The drive system converter 3 is connected to the PFC circuit unit 2, steps down an output of the PFC circuit unit 2 to a 24V output, and supplies the 24V output to the drive system load 9 of the image forming apparatus 100.

[0018] The logic system converter 4 is connected to the PFC circuit unit 2, steps down the output of the PFC circuit unit 2 to a 5V output, and supplies the 5V output to the logic system load 8 of the image forming apparatus 100.

[0019] The transmission photocoupler 5 is connected to the PFC circuit unit 2, the drive system converter 3, and the controller 8, and turns ON / OFF the PFC circuit unit 2 and the drive system converter 3 in accordance with a signal from the controller 8.

[0020] The FET 6 (Q1) is turned ON / OFF from the 5V output output from the logic system converter 4 in accordance with a state (energy saving / energy saving cancellation) of the image forming apparatus 100.

[0021] Here, we define the logic output that continues to output even during energy saving as 5VX, and the logic output that is turned OFF during energy saving and ON when energy saving is disabled by FET6 as 5V. In recent years, due to the increasing diversification of functions in actual devices, the 5V output current has increased, and it is desirable to have a low voltage drop across FET6. Also, because semiconductor manufacturers have a limited lineup of P-channel FETs, FET6 is often equipped with an N-channel FET.

[0022] The drive circuit 7 is a circuit for driving the FET 6. In order to drive the N-ch FET 6, the drive circuit 7 generates a gate potential higher than the source terminal potential (5V) by dividing the 24V output output from the drive system converter 3 with a resistor. The drive circuit 7 switches the FET 6 ON / OFF using the energy-saving transition / return signal PONENG from the controller 8 of the image forming apparatus 100.

[0023] The controller 8 of the image forming apparatus 100 generates an energy-saving transition / return signal PONENG to control the ON / OFF state of the FET 6, and also switches the PFC circuit section 2 and the drive system converter 3 ON / OFF using a transmission photocoupler 5 that provides isolation between the primary and secondary and transmits signals.

[0024] Figure 2 shows the normal transition during energy-saving mode switching in the power supply unit 10 of the reference configuration. Figure 2 shows the state of the 5VX output of the logic converter 4, the 5V output switched ON / OFF by FET 6, the 24V output of the drive converter 3, and the Gate potential of FET 6 controlled by the drive circuit 7, when the power supply transition and deactivation occur under normal conditions where the input voltage is stable within the operating range. In the graph of Figure 2, the vertical axis represents voltage and the horizontal axis represents time. In Figure 2, the graph is divided into two parts. The upper graph (A) shows the 5VX output (dotted line), 5V output (thick solid line), and 24V output (thin solid line), while the lower graph (B) shows the Gate voltage of FET 6 (Q1) (solid line) and the energy-saving transition signal PONENG (dotted line). Note that the line types of similar graphs shown in subsequent Figures such as Figure 5 are the same as those in Figure 2.

[0025] In the example shown in Figure 2, the ON / OFF state of FET6 quickly follows the switching of the energy-saving transition signal PONENG from H to L, allowing for the ON / OFF switching of 5V and 24V outputs as intended by the design. For example, in section t1 of Figure 2, when the energy-saving transition signal PONENG switches from H to L and the energy-saving mode is deactivated, the drive system converter 3 starts up and the 24V output rises. Also, the gate potential of FET6 rises, FET6 turns ON, and the 5V output rises.

[0026] Furthermore, in section t2 of Figure 2, when the energy-saving transition signal PONENG switches from L to H and the system switches to energy-saving mode, the gate potential of FET6 drops, FET6 turns OFF, and the 5V output stops. Also, the drive system converter 3 stops, and the 24V output stops.

[0027] Figure 3 shows an example of the circuit configuration of the drive circuit 7 according to the reference configuration. The FET indicated by the symbol Q1 in Figure 3 corresponds to FET6 in Figure 1. The drive circuit 7 also has another FET indicated by the symbol Q2. In the following description, FET6 indicated by the symbol Q1 may also be referred to as "FET_Q1 (first FET)," and the other FET indicated by the symbol Q2 may also be referred to as "FET_Q2 (second FET)."

[0028] The gate potential of FET_Q1 is supplied via resistor R3, after the voltage is divided from the 24V output by resistors R1 and R2, noise reduction and smoothing are performed by capacitor C1.

[0029] FET_Q2 is driven by a voltage generated by a voltage divider from the 5VX line through resistors R5, R6, and R7, and is switched ON / OFF by the energy-saving transition / return signal PONENG.

[0030] When the PONENG signal is L (power saving mode deactivated), the drive of Q2 is turned OFF, and the voltage generated by the resistors R1 and R2 and capacitor C1 mentioned above is supplied to the Gate of Q1, causing Q1 to turn ON and supply a 5V output.

[0031] When the PONENG signal is H (energy-saving mode transition), Q2 is driven ON. Resistor R4 has a much lower resistance than resistor R2, and the GATE potential of Q1 becomes Low via resistor R4 and Q2, causing Q1 to turn OFF and the 5V output supply to be cut off.

[0032] Figure 4 shows the change in the gate potential of FET_Q1 during the transition to energy-saving mode in the power supply unit 10 of the reference configuration. The graph in Figure 4 corresponds to, for example, an enlarged view of the change in gate voltage in interval t2 of Figure 2. In the graph of Figure 4, the vertical axis represents voltage (V), and the horizontal axis represents time (μs (microseconds)).

[0033] As shown in Figure 4, under normal conditions, when transitioning to energy-saving mode via the energy-saving transition / recovery signal PONENG, the gate potential of FET_Q1 (i.e., the residual potential of capacitor C1) rapidly decreases to the off-threshold level. For example, as shown by the dotted line in the graph of Figure 4, if the gate off-threshold potential of FET_Q1 is 7.5V, the time to reach the off-threshold level is slightly less than 2μs, allowing FET_Q1 to be quickly turned off.

[0034] Figure 5 shows the normal transition of the 5V output during a momentary interruption of the AC input voltage in the power supply unit 10 of the reference configuration. The outlines of the graphs shown in Figure 5(A) and (B) are the same as those in Figure 2(A) and (B). Figure 5(C) shows the AC input voltage.

[0035] Consider the case where, in the actual operating state with the energy-saving mode deactivated as shown in Figure 5(B), a momentary interruption of the AC input voltage occurs as shown in Figure 5(C), resulting in a decrease and stoppage of the 5VX output at time T1, as shown in Figure 5(A). In this case, the controller board 8, which controls the H and L states of the energy-saving transition signal PONENG, maintains the state before the AC interruption when the AC is restored. That is, as shown in Figure 5(B), the energy-saving transition signal PONENG remains L (energy-saving deactivated state).

[0036] If the energy-saving transition signal PONENG remains L, as shown in Figure 5(A), even though the 5VX output and 24V output are reduced, the gate (C1) potential of FET_Q1 remains at an intermediate potential for a period of time (for example, the interval from time T1 to T3 in Figure 5) due to the gradual discharge by resistor R2 (high resistance) (see Figure 3), and FET_Q1 remains in the ON state.

[0037] When the AC power is momentarily interrupted and restored (time T2), as shown in Figure 5(A), the 5V output is initially output simultaneously with the 5VX startup. However, the rise time of the 24V output lags behind the startup of the 5VX output by about 100-200ms, so there is a period of time (for example, the interval from time T2 to T3 in Figure 5) during which the gate potential of FET_Q1 continues to decrease.

[0038] As shown in Figures 5(B) and (C), in the case of an AC power interruption that occurs for a duration such that the 24V output voltage returns before the gate potential of FET_Q1 crosses the threshold potential at time T3, for example, there is no abnormality in the behavior when the 5V output voltage returns, as shown in Figure 5(A).

[0039] Figure 6 shows the progression of abnormal 5V output during a momentary interruption of the AC input voltage in the power supply unit 10 of the reference configuration. The outlines of each figure in Figure 6 are the same as in Figure 5.

[0040] As shown in Figures 6(B) and (C), for example, in the case of an AC power interruption that occurs for a duration such that the 24V output voltage is restored when the gate potential of FET_Q1 crosses the threshold at time T4, as shown in Figures 6(A) and (B), at time T5, when 5VX restarts, the gate potential of FET_Q1 has not yet crossed the OFF threshold, so the 5V output voltage is output simultaneously. However, the Q1gate potential continues to decrease at this time, and at time T6, when FET_Q1 reaches the OFF threshold, the 5V output stops.

[0041] Subsequently, at time T4, as the 24V output voltage restarts, FET_Q1 turns ON again and outputs a 5V voltage again. In other words, in the example in Figure 6, a malfunction occurs during the momentary interruption and recovery of the AC input voltage (the interval from time T5 to T6 to T4), in which the 5V output voltage repeatedly turns ON → OFF → ON.

[0042] Figure 7 shows the change in the gate potential of FET_Q1 during momentary interruption and shutdown of the AC input voltage in the power supply unit 10 of the reference configuration. The graph in Figure 7 corresponds to an enlarged view of the change in gate voltage during the interval T1 to T3 in Figure 5, and the interval T1 to T4 in Figure 6. In the graph in Figure 7, the vertical axis represents voltage (V), and the horizontal axis represents time (sec (seconds)). The graph in Figure 7 shows the characteristics when the resistor R2 in the drive circuit 7 shown in Figure 3 is 1.5 MΩ and the capacitor C2 is 0.1 uF.

[0043] As shown in Figure 7, when a momentary interruption occurs, the gate potential of Q1 (i.e., the residual potential of capacitor C1) decreases slowly. For example, as shown by the dotted line in the graph of Figure 7, if the gate off-thresh potential of FET_Q1 is set to 7.5V, as in Figure 4, it takes more than 0.1 seconds to reach the off-thresh point.

[0044] Figure 8 illustrates the overcurrent protection control of the power supply unit 10 in the reference configuration when the AC input voltage is OFF. Graph (A) in Figure 8 shows the 5VX output (dotted line), 5V output (thick solid line), and 24V output (thin solid line), similar to Figures 2(A) and 5(A). Graph (B) in Figure 8 shows the input voltage (dotted line) and input current (solid line) of the logic converter 4. Graph (C) in Figure 8 shows the overcurrent protection operation of the power supply unit 10, and graph (D) shows the AC input voltage. Note that graph (C), which shows overcurrent protection, switches between L and H, and when it shifts to the H side, it indicates that the power supply unit 10 is in overcurrent protection operation (latching). Overcurrent protection operates, for example, by detecting the current value flowing to the primary side of the converter.

[0045] As shown in Figure 8(D), at time T7, when the AC input voltage turns OFF, FET_Q1 remains ON for a period of time. As a result, as shown in Figure 8(B), the input current of the logic converter 4 continues to be the sum of (5VX + 5V). Consequently, as the converter input voltage decreases and the primary input current increases, at time T8, the converter input current reaches the overcurrent protection threshold OCP_th, making the protection function more likely to activate. As a result, as shown in Figure 8(C), the overcurrent protection function of the power supply 10 shifts to the H side, the overcurrent protection operation is performed, and the logic converter 4 enters a latched state. After a predetermined time has elapsed (time T9), the overcurrent protection function is reset and shifts to the L side.

[0046] In other words, a converter supplies a constant power to the output side equal to the output voltage multiplied by the output current. Therefore, if the converter input voltage drops, the input current increases to maintain the power supplied to the secondary side. For example, if (5VX+5V) has an output current of 10[A] and an output power of 50[W], and the converter efficiency is 80%, then when the converter input voltage is 140Vdc (100Vac*1.414), the converter input current = 50W / 140V / 0.8 = 0.446[A]. Also, when the converter input voltage is 71Vdc (50Vac*1.414), the converter input current = 50W / 71V / 0.8 = 0.88[A]. For this reason, when the input voltage is low, the input current increases, making it more likely to trigger overcurrent protection.

[0047] Figure 9 illustrates the malfunction caused by overcurrent protection control during momentary AC input voltage interruption in the power supply unit 10 of the reference configuration. The outlines of each figure in Figure 9 are the same as in Figure 8.

[0048] As shown in Figure 9(D), if a momentary interruption occurs in the AC input voltage at time T10, the converter input current reaches the overcurrent protection threshold OCP_th at time T11, similar to when the AC input voltage is OFF in Figure 8 (time T7). As a result, as shown in Figure 9(C), the overcurrent protection function of the power supply 10 shifts to the H side, and the logic converter 4 enters a latched state. Subsequently, even after the AC input voltage recovers from the momentary interruption at time T12, if a malfunction occurs in which the latched state of the logic converter 4 is maintained as shown in Figure 9(C), a malfunction occurs in which each output is not output, as shown in Figure 9(A).

[0049] As described above, in the power supply unit 10 according to the reference embodiment, when the AC input voltage is momentarily interrupted and restored, malfunctions such as the 5V output voltage restarting → stopping → restarting (ON → OFF → ON) may occur, as explained with reference to Figure 6, or a malfunction in the output stop state may occur due to the increased likelihood of the logic converter 4 stopping due to overcurrent protection, as explained with reference to Figure 9. The purpose of this embodiment is to suppress the occurrence of such malfunctions. The following describes each embodiment.

[0050] [First Embodiment] The first embodiment will be described with reference to Figures 10 to 14.

[0051] Figure 10 shows an example of the circuit configuration of the drive circuit 7A according to the first embodiment. The configuration of the power supply unit 10A according to the first embodiment is the same as that of the reference power supply unit 10 shown in Figure 1, with only the drive circuit 7A being different, so it is omitted from the illustration.

[0052] As shown in Figure 10, the drive circuit 7A of the first embodiment further includes a photocoupler PC1 (discharge acceleration unit) compared to the reference drive circuit 7 shown in Figure 3. In the drive circuit 7A, the anode side of the light-emitting diode PC1-D (photodiode) of the photocoupler PC1 is connected to the gate line of FET_Q1, and the cathode side is connected to the 24V line. In addition, the collector side of the light-receiving transistor PC1-T (phototransistor) of the photocoupler PC1 is connected to the drain line of FET_Q2, and the emitter side is connected to the source line of FET_Q2.

[0053] In the drive circuit 7A shown in Figure 10, when a power outage, voltage drop, or momentary interruption occurs in the AC power supply, causing the 24V output of the power supply unit 10A to drop and the gate potential of FET_Q1 to become lower than the 24V output potential, current flows from the gate of FET_Q1 to the 24V line, causing the light-emitting diode PC1-D of the photocoupler PC1 to conduct. This turns on the light-receiving transistor PC1-T, short-circuiting the drain-source (DS) terminals of FET_Q2. As a result, the gate of Q1 is quickly discharged by resistor R4 (see Figures 11 and 12), allowing FET_Q1 to be turned OFF, thus preventing malfunctions such as the 5V output voltage repeatedly turning ON→OFF→ON during any AC momentary interruption.

[0054] Figures 11 and 12 show the transition of the 5V output during a momentary interruption of the AC input voltage in the power supply unit 10A of the first embodiment, corresponding to the reference embodiment shown in Figures 5 and 6. The outlines of the graphs shown in (A), (B), and (C) of Figures 11 and 12 are the same as those in (A), (B), and (C) of Figures 5 and 6. Also, the occurrence pattern of the momentary interruption of the AC input voltage in Figure 11 and Figure 12 (C) is the same as that in Figures 5 and 6 (C), respectively.

[0055] In the example in Figure 11, the transitions of the 24V output and 5VX output shown in (A) and the energy-saving transition signal PONENG shown in (B) are the same as in Figure 5. On the other hand, in the power supply unit 10A of this embodiment, when a momentary interruption with the same pattern as in the example in Figure 5 occurs, and the 24V output drops at time T1, the gate potential of FET_Q1 discharges rapidly as described above, unlike the transition in Figure 5, as shown in Figure 11(B), and falls below the threshold potential, causing FET_Q1 to turn OFF. In accordance with the transition of the gate potential, the 5V output also rapidly decreases and stops at time T13.

[0056] Furthermore, after the momentary power interruption is restored, as the 24V output is restored at time T3, the Gate potential also increases rapidly as shown in Figure 11(B), exceeding the threshold potential and turning FET_Q1 ON. As shown in Figure 11(A), the 5V output also increases rapidly, and the system recovers from the stopped state.

[0057] In the example in Figure 12, when a momentary interruption occurs with a pattern similar to that in the example in Figure 6, as shown in Figures 12(A) and (B), when 5VX restarts at time T5 after the interruption is resolved, the GATE potential of FET_Q1 is below the threshold potential and is OFF, unlike the progression in Figure 5. Therefore, the 5V output voltage is not output and the system remains in a stopped state.

[0058] Subsequently, at time T4, as the 24V output voltage restarts, the gate potential of FET_Q1 increases, exceeding the threshold potential and switching to ON. As a result, the 5V output voltage also increases, recovering from the stopped state. In other words, in this embodiment, as shown in Figure 12, even in a momentary interruption pattern where the 5V output voltage may malfunction by repeatedly going ON→OFF→ON as in the reference embodiment, the 5V output can continuously maintain a stopped state in the interval between times T13 and T4, thus preventing the occurrence of the 5V output malfunction seen in the reference embodiment.

[0059] Figure 13 is a diagram illustrating the transition of the AC input voltage when it is OFF in the power supply unit 10A of the first embodiment, corresponding to Figure 8 of the reference embodiment. Figure 14 is a diagram illustrating the transition of the AC input voltage when it is momentarily interrupted in the power supply unit 10A of the first embodiment, corresponding to Figure 9 of the reference embodiment.

[0060] The outlines of the graphs shown in (A), (B), (C), and (D) in Figures 13 and 14 are the same as those in (A), (B), (C), and (D) in Figures 8 and 9. Also, the occurrence patterns of AC input voltage OFF in Figure 13(D) and the occurrence patterns of momentary interruption of AC input voltage in Figure 14(D) are the same as those in (D) in Figures 8 and 9, respectively.

[0061] As shown in Figure 13(D), when the AC input voltage turns OFF at time T7, FET_Q1 remains ON for a period of time (T7~T14). As a result, the input current of the logic converter 4 continues to be the sum of (5VX + 5V), as shown in Figure 13(B). Therefore, as the converter input voltage decreases and the primary input current increases, it increases similarly to Figure 8. However, unlike the progression in Figure 8, the gate potential of FET_Q1 discharges quickly and Q1 turns OFF, so the 5V output rapidly decreases and stops at time T14, as shown in Figure 13(A). Consequently, as shown in Figure 13(B), the rate of increase of the converter input current decreases after time T14, and it does not exceed the overcurrent protection threshold OCP_th, which was exceeded at time T8 in Figure 8. For this reason, in this embodiment, as shown in Figure 13(C), the overcurrent protection function of the power supply 10A remains on the L side, and the overcurrent protection operation is not performed.

[0062] As shown in Figure 14(D), when a momentary interruption occurs in the AC input voltage at time T10, the 5V output stops at time T15, similar to when the AC input voltage is OFF in Figure 13 (time T14). As a result, the rate of increase of the converter input current decreases after time T15, and it does not exceed the overcurrent protection threshold OCP_th, which was exceeded at time T11 in Figure 9. Therefore, in this embodiment, as shown in Figure 14(C), the overcurrent protection function of the power supply 10A remains on the L side, and the overcurrent protection operation is not performed. Consequently, after the AC input voltage recovers from the momentary interruption at time T12, unlike the transition in Figure 9, a malfunction in which the latched state of the logic converter 4 is maintained does not occur, and each output is output from time T16 onwards, as shown in Figure 9(A).

[0063] In other words, in this embodiment, as shown in Figure 14, even in a momentary interruption pattern where a malfunction in the output stop state may occur due to the logic converter 4 being more likely to stop due to overcurrent protection in the reference embodiment, it is possible to prevent a transition to overcurrent protection operation, and a latch stop state of the logic converter 4 does not occur, thus preventing the occurrence of a malfunction in the output stop state after recovery from a momentary interruption, as in the reference embodiment.

[0064] As described above, the power supply unit 10A according to the first embodiment includes an FET_Q1 that switches the logic output (5V output) OFF when the power supply unit 10A transitions to energy-saving mode, and switches the 5V output, which was OFF when transitioning to energy-saving mode, ON when the energy-saving mode is released, and a drive circuit 7A that generates a gate voltage to operate FET_Q1. The drive circuit 7A has a discharge promotion unit that promotes the discharge of the gate potential of FET_Q1 and turns FET_Q1 OFF when the voltage of the 5V output, which can be switched ON / OFF by FET_Q1, falls below the potential of the gate voltage of FET_Q1. The drive circuit 7A also has an FET_Q2 that is driven to supply gate potential to FET_Q1 when transitioning to energy-saving mode, and is driven to stop supplying gate potential to FET_Q1 when the energy-saving mode is released. In the first embodiment, the drive circuit 7A has a photocoupler PC1 that connects the light-emitting side PC1-D in the direction of discharge from the gate of FET_Q1 to the 5V output line, and connects the light-receiving side PC1-T in parallel with FET_Q2, and this photocoupler PC1 functions as the "discharge promotion unit" described above.

[0065] This configuration allows for faster switching to OFF by promoting the discharge of FET_Q1 when switching FET_Q1 to OFF. This suppresses malfunctions that may occur in the reference configuration when the AC input voltage is momentarily interrupted and restored, such as the 5V output voltage restarting → stopping → restarting (ON → OFF → ON), and malfunctions that cause the logic converter 4 to stop due to overcurrent protection, resulting in an output stop state. In other words, the power supply unit 10A according to the first embodiment can prevent malfunctions in the output voltage after recovery when the output voltage drops due to the effects of a drop in AC input voltage, momentary interruption, momentary power outage, etc.

[0066] [Second Embodiment] Figure 15 is a block diagram showing the schematic configuration of the power supply unit 10B according to the second embodiment. During equipment operation, even in the standby state where energy saving is disabled, unnecessary power may be supplied and consumed to loads such as motors and motor drive boards that are not in use. The power supply unit 10B shown in Figure 15 is an example of a configuration that cuts off the 24V output supply in a configuration similar to the reference form in Figure 1, with the aim of reducing power consumption in the standby state.

[0067] The drive system converter 13 supplies a 24V output to the drive system load 9. In the example in Figure 15, the output that is always supplied during standby, copy, and print operations is designated as 24V1, and the output that is switched ON / OFF by FET_Q1 of the drive circuit 7B is designated as 24V2.

[0068] Converter 14 is a converter that generates an FET drive voltage for switching 24V ON / OFF, and an example of this is a 24V to 34V boost DC / DC converter.

[0069] The drive circuit 7B switches FET_Q1 ON / OFF based on the ON / OFF signal 24V2 from the controller (logic load) 8 of the image forming apparatus 100. This switches the 24V output (24V2) to the drive load 9, which is not used during standby, ON / OFF.

[0070] As described above, the power supply unit 10B according to the second embodiment includes an FET_Q1 that switches the drive system output (24V2 output) OFF when the power supply unit 10B transitions to energy-saving mode, and switches the 24V2 output, which was OFF when transitioning to energy-saving mode, ON when the energy-saving mode is released, and a drive circuit 7B that generates a gate voltage to operate the FET_Q1. The drive circuit 7B has a discharge promotion unit that promotes the discharge of the gate potential of the FET_Q1 and turns the FET_Q1 OFF when the voltage of the 24V2 output, which can be switched ON / OFF by the FET_Q1, falls below the potential of the gate voltage of the FET_Q1. In the second embodiment, the drive circuit 7B has a photocoupler PC1 that connects the light-emitting side PC1-D in the direction of discharge from the gate of the FET_Q1 to the 24V2 output line, and connects the light-receiving side PC1-T in parallel with the FET_Q2, and this photocoupler PC1 functions as the "discharge promotion unit" described above.

[0071] The configuration of the power supply unit 10B of the second embodiment shown in Figure 15 may also cause the same problems as the power supply unit 10 of the reference embodiment. However, by applying the drive circuit 7B as described above, this problem can be solved in the same way as the drive circuit 7A of the power supply unit 10A of the first embodiment. In other words, it is possible to suppress malfunctions such as the 24V2 output voltage restarting → stopping → restarting (ON → OFF → ON) when the AC input voltage is momentarily interrupted and restored, and malfunctions such as the output stopping state due to the increased likelihood of the drive system converter 13 stopping due to overcurrent protection. In short, the power supply unit 10B according to the second embodiment can also prevent malfunctions in the output voltage after recovery when the output voltage drops due to the effects of a drop in AC input voltage, momentary interruption, momentary power outage, etc.

[0072] [Third Embodiment] Figure 16 shows an example of the circuit configuration of the drive circuit 7C according to the third embodiment. The drive circuit 7C is a configuration in which the photocoupler PC1 is not applied instead of the drive circuit 7A in the power supply device 10A of the first embodiment.

[0073] The drive circuit 7C includes an operational amplifier IC1 (discharge acceleration section). The midpoint potential obtained by dividing the GATE and GND of FET_Q1 by resistors R10 (first resistor) and R11 (second resistor) is connected to the non-inverting input terminal of the operational amplifier IC1. In addition, the midpoint potential obtained by dividing the 24V output line (the drive system output that cannot be switched ON / OFF by FET_Q1) and GND by resistors R12 (third resistor) and R13 (fourth resistor) is connected to the inverting input terminal of the operational amplifier IC1.

[0074] In the drive circuit 7C shown in Figure 16, when the gate potential of FET_Q1 becomes greater than the potential of the 24V output (Gate potential > 24V potential), the output of op-amp IC1 becomes high, and transistor Q3 connected to the output of op-amp IC1 turns on, short-circuiting the drain-source (DS) terminals of FET_Q2. As a result, resistor R4 quickly discharges the gate of FET_Q1, allowing FET_Q1 to be turned off.

[0075] Therefore, the drive circuit 7C of the third embodiment can achieve the same effects as the drive circuit 7A of the first embodiment. In other words, in the power supply unit 10A to which the drive circuit 7C is applied, when the AC input voltage is momentarily interrupted and restored, it is possible to suppress malfunctions such as the 5V output voltage restarting → stopping → restarting (ON → OFF → ON) that may occur in the reference configuration, and malfunctions such as the output stopping state due to the logic converter 4 being more likely to stop due to overcurrent protection. In other words, the power supply unit 10A according to the third embodiment can also prevent malfunctions in the output voltage after restoration when the output voltage drops due to the effects of a decrease in AC input voltage, momentary interruption, momentary power outage, etc. Note that the drive circuit 7C is also applicable to the power supply unit 10B of the second embodiment.

[0076] The embodiments have been described above with reference to specific examples. However, this disclosure is not limited to these specific examples. Modifications made to these specific examples by those skilled in the art are also included within the scope of this disclosure, as long as they retain the features of this disclosure. The elements, their arrangement, conditions, shapes, etc., of each of the aforementioned specific examples are not limited to those illustrated and can be modified as appropriate. The elements of each of the aforementioned specific examples can be combined in different ways as appropriate, as long as no technical inconsistencies arise. [Explanation of symbols]

[0077] 10, 10A, 10B power supply 1 Rectifier circuit section 2 PFC circuit section 3.13 Drive System Converter 4. Logic Converters 5. Transmission Photocoupler 6. Q1 FET (First FET) 7, 7A, 7B, 7C drive circuit Q2 FET (Second FET) PC1 Photocoupler (Discharge Acceleration Section) PC1-D Photodiode PC1-T Phototransistor IC1 Operational amplifier (discharge acceleration section) Q3 Transistor 14 Converters 100 Image forming equipment (electronic equipment) 8. Logic-related load 9. Drivetrain load 11 Commercial power supply 5V logic output 24V2 drive system output [Prior art documents] [Patent Documents]

[0078] [Patent Document 1] Japanese Patent Publication No. 2019-205234

Claims

1. A power supply device, A first FET that switches a logic system output or drive system output OFF when the power supply unit transitions to energy-saving mode, and switches the output that was OFF when transitioning to energy-saving mode ON when the energy-saving mode is deactivated, A drive circuit that generates a gate voltage to operate the first FET, Equipped with, The drive circuit includes a discharge promotion unit that turns off the first FET by connecting the gate of the first FET to ground when the voltage of the output that cannot be switched ON / OFF by the first FET falls below the potential of the gate voltage of the first FET. power supply.

2. The drive circuit includes a second FET which is driven to supply a gate potential to the first FET when the energy-saving mode is deactivated, and which is driven to stop supplying the gate potential to the first FET when the transition to the energy-saving mode is initiated. The discharge promotion unit has a photocoupler that connects the light-emitting side to the output line that cannot be switched ON / OFF by the first FET from the gate of the first FET, and the light-receiving side to the light-receiving side that is arranged in parallel with the second FET and connects the light-receiving side to the ground from the gate of the first FET. The power supply device according to claim 1.

3. The drive circuit includes a second FET which is driven to supply a gate potential to the first FET when the energy-saving mode is deactivated, and to stop supplying the gate potential to the first FET when the transition to the energy-saving mode is initiated. The device comprises a transistor connected in parallel with the second FET and positioned between the first FET and ground, The discharge promotion unit has an operational amplifier, A node with a midpoint potential obtained by dividing the gate and ground of the first FET by a first resistor and a second resistor is connected to the non-inverting input terminal of the operational amplifier. A node with a midpoint potential obtained by dividing the output line that cannot be switched ON / OFF by the first FET and the ground using a third resistor and a fourth resistor is connected to the inverting input terminal of the operational amplifier. The transistor is connected to the output terminal of the operational amplifier. The power supply device according to claim 1.

4. An image processing apparatus comprising a power supply device according to any one of claims 1 to 3.

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