Manufacturing method for semiconductor devices

Abstract

To provide a manufacturing method of a semiconductor apparatus, capable of accurately observing a position detection mark.SOLUTION: There is provided a manufacturing method of a semiconductor apparatus, which includes: a position detection step of detecting the positional deviation of an upper surface mark and a lower surface mark by acquiring an upper surface image obtained by observing the upper surface mark from above the upper surface of a semiconductor substrate and a lower surface image obtained by observing the lower surface mark through the semiconductor substrate from above the upper surface of the semiconductor substrate; and an element formation step of forming a semiconductor element in the semiconductor substrate. In a top view in which the upper surface mark and the lower surface mark are projected onto a plane parallel to the upper surface, one of the upper surface mark and the lower surface mark is larger than the other, and the one entirely covers the other.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device. [Background Art]

[0002] In the manufacturing process of semiconductor devices, a technique of forming position detection marks on a semiconductor substrate is known (see, for example, Patent Documents 1 and 2). Patent Document 1: Japanese Unexamined Patent Publication No. 2012-253145 Patent Document 2: Japanese Unexamined Patent Publication No. 2019-120769 [Summary of the Invention] [Problem to be Solved by the Invention]

[0003] It is preferable that the position detection mark can be observed with high accuracy. [Means for Solving the Problem]

[0004] In order to solve the above problem, according to one aspect of the present invention, there is provided a method for manufacturing a semiconductor device. The manufacturing method may include a mark forming step of forming an upper surface mark on an upper surface of a semiconductor substrate and a lower surface mark on a lower surface of the semiconductor substrate. The manufacturing method may include a position detection step of detecting positional displacement between the upper surface mark and the lower surface mark by acquiring an upper surface image obtained by observing the upper surface mark from above the upper surface of the semiconductor substrate, and a lower surface image obtained by observing the lower surface mark through the semiconductor substrate from above the upper surface of the semiconductor substrate. The manufacturing method may include an element forming step of forming a semiconductor element on the semiconductor substrate. In any of the above manufacturing methods, in a top view in which the upper surface mark and the lower surface mark are projected onto a plane parallel to the upper surface, one of the upper surface mark and the lower surface mark may be larger than the other, and the one may cover the entire other.

[0005] In any of the above manufacturing methods, in the mark forming step, a cover portion covering the lower surface mark may be formed of a material having higher reflectance than the lower surface mark.

[0006] In any of the above manufacturing methods, the top mark may be larger than the bottom mark when viewed from above.

[0007] In any of the above manufacturing methods, the cover portion may be larger than the bottom mark and smaller than the top mark when viewed from above.

[0008] In any of the above manufacturing methods, the distance between the end of the cover portion and the end of the bottom mark may be smaller than the distance between the end of the cover portion and the end of the top mark when viewed from above.

[0009] In any of the above manufacturing methods, the bottom mark may be larger than the top mark when viewed from above.

[0010] In any of the above manufacturing methods, the distance between the end of the bottom mark and the end of the top mark in the top view may be 20 μm or more.

[0011] In any of the above manufacturing methods, the wavelength of light irradiated onto the semiconductor substrate when acquiring the top image and the wavelength of light irradiated onto the semiconductor substrate when acquiring the bottom image may be the same during the position detection step.

[0012] In any of the above manufacturing methods, the upper surface mark may be a recess located on the upper surface of the semiconductor substrate.

[0013] In any of the above manufacturing methods, the upper surface mark may be a protrusion located on the upper surface of the semiconductor substrate.

[0014] In any of the above manufacturing methods, when viewed from above, a region without irregularities may be provided extending outward from the edge of the top mark over a range of at least 20 μm.

[0015] In any of the above manufacturing methods, the lower surface mark may have two or more linear portions whose respective longitudinal directions intersect each other in the top view.

[0016] The above summary of the invention does not list all of the features of the present invention. Subcombinations of these feature groups may also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] [Figure 1] FIG. 1 is a diagram illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 2] FIG. 1 is a top view showing an example of a semiconductor substrate 10. [Figure 3] FIG. 2 is an enlarged view of region A in FIG. 2. [Figure 4] FIG. 3 is a diagram illustrating an example of a position detection step S102. [Figure 5] FIG. 4 is a diagram showing an example of a top surface image 202 and a bottom surface image 204 according to a reference example. [Figure 6] FIG. 5 is a diagram showing an example of a top surface image 206-1 and a bottom surface image 208-1 according to a reference example. [Figure 7] FIG. 6 is a diagram showing an example of a top surface image 206-2 and a bottom surface image 208-2 according to a reference example. [Figure 8] FIG. 7 is a diagram showing an example of a top surface image 206-3 and a bottom surface image 208-3 according to a reference example. [Figure 9] FIG. 8 is a cross-sectional view showing a configuration example of the semiconductor substrate 10 according to an example. [Figure 10] FIG. 9 is a diagram showing an example of a top surface image 212 and a bottom surface image 214. [Figure 11] FIG. 10 is a diagram showing an example of a top surface image 216-1 and a bottom surface image 218-1 according to an example. [Figure 12] FIG. 11 is a diagram showing an example of a top surface image 216-2 and a bottom surface image 218-2. [Figure 13] FIG. 12 is a diagram illustrating an example of the shapes of an upper surface mark 30 and a lower surface mark 50 in a top view. [Figure 14]This is a table showing mark position measurement results for a plurality of samples obtained by changing the shapes and sizes of top marks and bottom marks. [Figure 15] This is a diagram showing the film thickness of each member. [Figure 16] This is a diagram showing another structural example of the bottom mark 50. [Figure 17] This is a diagram showing another structural example of the bottom mark 50. Mode for Carrying Out the Invention

[0018] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention covered by the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention. In the present specification and the drawings, elements having substantially the same functions and configurations are denoted by the same reference numerals to omit redundant description, and illustration of elements not directly related to the present invention is omitted. Furthermore, in one drawing, among elements having the same functions and configurations, reference numerals are representatively assigned, and reference numerals for other elements may be omitted.

[0019] In the present specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". Of the two main surfaces of a substrate, a layer or another member, one surface is referred to as an upper surface, and the other surface is referred to as a lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction when a semiconductor module is mounted.

[0020] In this specification, technical matters may be described using the Cartesian coordinate axes X, Y, and Z. The Cartesian coordinate axes merely specify the relative position of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. The +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and it is simply referred to as the Z axis direction, it means the direction parallel to the +Z axis and the -Z axis. In this specification, the Cartesian axes parallel to the top and bottom surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X and Y axes, may be referred to as the horizontal direction.

[0021] In this specification, the terms "identical" or "equal" may include cases where there are errors due to manufacturing variations, etc. Such errors are, for example, within 10%.

[0022] Figure 1 illustrates an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 1 shows some of the manufacturing steps in the manufacturing method. The semiconductor device includes semiconductor elements formed on a semiconductor substrate such as a silicon substrate. The semiconductor elements are, for example, power semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors), but are not limited thereto.

[0023] A semiconductor device may have a structure on the upper surface of a semiconductor substrate and a structure on the lower surface. For example, the lower surface of the semiconductor substrate may have an emitter region of a transistor element such as an IGBT and an anode region of a diode element such as a freewheeling diode, while the upper surface may have a collector region of a transistor element and a cathode region of a diode element. As an example, the semiconductor device is a vertical device through which current flows between the upper and lower surfaces of the semiconductor substrate. The semiconductor device may be a reverse-conducting IGBT (RC-IGBT).

[0024] The manufacturing method in this example comprises a mark formation step S101, a position detection step S102, and an element formation step S103. In the mark formation step S101, an upper surface mark is formed on the upper surface of the semiconductor substrate, and a lower surface mark is formed on the lower surface of the semiconductor substrate. The semiconductor substrate in this example is a disc-shaped semiconductor wafer. The upper and lower surfaces of the semiconductor substrate are two main surfaces that are arranged opposite each other on the semiconductor substrate.

[0025] The top and bottom marks may be recesses or protrusions formed in a resist, oxide film, nitride film, or other film provided on the top or bottom surface of a semiconductor substrate. The recesses may or may not penetrate these films. The top or bottom marks may also be recesses or protrusions in the semiconductor substrate itself, formed by removing a portion of the top or bottom surface of the semiconductor substrate.

[0026] In position detection step S102, images of the top and bottom marks are acquired, and the positional misalignment of the top and bottom marks in the top view is detected. Top view refers to observing each component from a direction perpendicular to the top surface of the semiconductor substrate. In the top view, the position of each component may be observed when each component is projected onto a plane parallel to the top surface of the semiconductor substrate.

[0027] In the device formation step S103, at least a portion of the structure of the semiconductor device is formed on the semiconductor substrate. In the device formation step S103, at least a portion of the structure of the semiconductor device may be formed using a resist patterned according to the pattern of the structure to be formed. In the device formation step S103, based on the resist pattern, impurities may be injected into the semiconductor substrate, the semiconductor substrate may be etched, an insulating film may be formed on the semiconductor substrate, or other processing may be performed.

[0028] In the mark formation step S101, an upper mark or a lower mark may be formed on the resist formed on the upper or lower surface of the semiconductor substrate. In the mark formation step S101, an upper mark or a lower mark may be formed on the resist on which the element pattern corresponding to the structure of the semiconductor element to be formed is formed. The relative positions of the marks and element patterns formed on the same resist are predetermined. Therefore, by detecting the misalignment of the upper and lower marks, the misalignment between the upper and lower element patterns can be detected. If the amount of misalignment exceeds the allowable range, the resist may be removed and a new resist may be applied. Marks and element patterns may be formed on the new resist so as to reduce the amount of misalignment between the marks.

[0029] As an example, the gate structure and n-type emitter region of a transistor element and the p-type anode region of a diode element are formed on the lower surface of the semiconductor substrate. The p-type collector region of a transistor element and the n-type cathode region of a diode element are formed on the upper surface of the semiconductor substrate. In this example, the collector region and cathode region of the upper surface are formed after the structures on the lower surface of the semiconductor substrate are formed. The steps shown in Figure 1 are examples of steps for forming the collector region and cathode region. In the mark formation step S101, the structure of the upper surface mark and the structure of either the collector region or the cathode region are patterned onto the resist formed on the upper surface of the semiconductor substrate. In the element formation step S103, one of the collector region and the cathode region is formed by injecting impurities using the resist as a mask. Here, in the position detection step S102, the positional misalignment between the upper surface mark and the lower surface mark can be detected, thereby detecting the positional misalignment between the collector region and cathode region formed using the resist and the structure on the lower surface of the substrate.

[0030] The manufacturing process for semiconductor devices is not limited to the above. For example, in the device formation step S103, the position of impurities injected into the upper surface of the semiconductor substrate may be controlled using the position of the upper surface mark as a reference position, and the position of impurities injected into the lower surface of the semiconductor substrate may be controlled using the position of the lower surface mark as a reference position. In this case, in the device formation step S103, the position of the structure formed with respect to the upper surface mark and the position of the structure formed with respect to the lower surface mark may be adjusted based on the positional misalignment of the upper surface mark and the lower surface mark detected in the position detection step S102. In either manufacturing step, the detection accuracy of the positional misalignment of the upper surface mark and the lower surface mark affects the positional misalignment between the upper surface structure and the lower surface structure of the semiconductor device, so it is preferable to be able to detect the positional misalignment with high accuracy in the position detection step S102.

[0031] In the manufacturing method, the mark formation step S101, the position detection step S102, and the element formation step S103 may be repeated for each semiconductor element structure. For example, when forming a first structure and a second structure that differ in position or shape, the mark formation step S101, the position detection step S102, and the element formation step S103 may be performed when forming the first structure and when forming the second structure, respectively.

[0032] Figure 2 is a top view showing an example of a semiconductor substrate 10. Multiple semiconductor chips 22 may be formed on the semiconductor substrate 10. A semiconductor chip 22 is an example of a semiconductor device. Each semiconductor chip 22 can be cut out by cutting the semiconductor substrate 10 along a scribe line 20 on the top surface 12 of the semiconductor substrate 10. In this specification, two orthogonal axes parallel to the top surface 12 of the semiconductor substrate 10 are defined as the X-axis and Y-axis, and the axis orthogonal to the top surface 12 is defined as the Z-axis. The scribe line 20 may have a portion parallel to the X-axis and a portion parallel to the Y-axis.

[0033] Figure 3 is an enlarged view of region A in Figure 2. Region A includes a scribe line 20 and two semiconductor chips 22 separated by the scribe line 20. In the mark formation step S101, an upper surface mark 30 may be formed on the scribe line 20 on the upper surface 12 of the semiconductor substrate 10. In addition, a lower surface mark 50 may be formed on the lower surface of the semiconductor substrate 10 at a position overlapping with the upper surface mark 30. In Figure 3, the lower surface mark 50 is shown with a dashed line.

[0034] Figure 4 illustrates an example of the position detection step S102. In this example, a top mark 130 is formed instead of the top mark 30 described in Figure 3. In this example, the top mark 130 is formed on the resist 32. The resist 32 is applied to the top surface 12 of the semiconductor substrate 10. In this example, the top mark 130 is a groove 132 formed in the resist 32. As described above, in addition to the pattern of the top mark 130, the resist 32 may also be provided with a pattern for forming a semiconductor element. The resist 32 may be formed on both the scribe line 20 and the semiconductor chip 22.

[0035] In this example, the bottom mark 50 is formed on the film 54. The film 54 is formed on the bottom surface 14 of the semiconductor substrate 10. The film 54 may be an insulating film such as an oxide film, a nitride film, or a resist. In this example, the bottom mark 50 has a groove 52 formed on the film 54. The film 54 may also be formed on the semiconductor chip 22 as part of the structure of the semiconductor device. For example, the film 54 may also be formed on the semiconductor chip 22 as an insulating film of the semiconductor device. The groove 52 may be provided on the semiconductor substrate 10 itself.

[0036] In the mark formation step S101, a cover portion 56 may be formed to cover the lower surface mark 50. The cover portion 56 is made of a material with a higher reflectivity than the lower surface mark 50 (film 54 in this example). For example, the cover portion 56 is made of a metal material such as aluminum. By providing the cover portion 56, the difference between the reflectivity of the irradiated light in the groove portion 52 of the lower surface mark 50 and the reflectivity of the irradiated light in areas other than the groove portion 52 can be increased. As a result, the contrast between the groove portion 52 and the other parts in the image of the lower surface mark 50 can be increased.

[0037] In the position detection stage S102, an upper image is obtained by observing the upper surface mark 130 from above the upper surface 12 of the semiconductor substrate 10, and a lower image is obtained by observing the lower surface mark 50 by passing through the semiconductor substrate 10 from above the upper surface 12 of the semiconductor substrate 10. In the example in Figure 4, the upper image and the lower image are obtained by the imaging unit 200 located above the upper surface 12.

[0038] The imaging unit 200 includes an image sensor, a light source that generates illumination light to irradiate the semiconductor substrate 10, and an optical system that allows the illumination light to pass towards the semiconductor substrate 10 and the reflected light from the semiconductor substrate 10 to pass towards the image sensor. The optical system may include an adjustment unit for adjusting the focal position of the image sensor.

[0039] The imaging unit 200 may irradiate the semiconductor substrate 10 with light of the same wavelength when acquiring a top image and when acquiring a bottom image. The irradiated light includes wavelength components that can penetrate the semiconductor substrate 10. The irradiated light may include infrared wavelength components as an example.

[0040] When acquiring a top image, the imaging unit 200 may focus on the top surface 12 of the semiconductor substrate 10. When acquiring a top image, the imaging unit 200 receives reflected light from the top surface mark 130. However, since the imaging unit 200 also receives light that has passed through the semiconductor substrate 10 and reflected at the bottom surface mark 50, the top image may include the bottom surface mark 50 in addition to the top surface mark 130.

[0041] When acquiring a bottom image, the imaging unit 200 may focus on the position of the bottom surface 14 of the semiconductor substrate 10. When acquiring a bottom image, the imaging unit 200 receives reflected light that has passed through the semiconductor substrate 10 and reflected off the bottom mark 50. However, since the imaging unit 200 also receives light reflected off the top mark 130, the bottom image may include the top mark 130 in addition to the bottom mark 50.

[0042] Figure 5 shows examples of top image 202 and bottom image 204 related to a reference example. The top image 202 and bottom image 204 shown in Figure 5 are images of the same region in a top view. Top image 202 includes top mark 130, and bottom image 204 includes bottom mark 50. As mentioned above, top image 202 may include bottom mark 50, but it is omitted in top image 202 of Figure 5. Similarly, bottom image 204 may include top mark 130, but it is omitted in bottom image 204 of Figure 5.

[0043] In this example, the top mark 130 has a groove 132 positioned around the bottom mark 50 when viewed from above. In this example, the groove 132 surrounds the bottom mark 50 when viewed from above. Let Wt be the minimum width of the groove 132 when viewed from above. The width Wt may be less than 20 μm.

[0044] In this example, the lower mark 50 has a groove 52. The width of the groove 52 in a top view may be 10 μm or less, or 5 μm or less. The groove 52 may have two or more intersecting straight portions 51 in a top view. In the example of Figure 5, the groove 52 has one or more straight portions 51-1 extending in the Y-axis direction and one or more straight portions 51-2 extending in the X-axis direction. In this example, the straight portions 51-1 and 51-2 intersect at their respective central portions. Multiple straight portions 51-1 may be arranged side by side in the X-axis direction. A film 54 remains between the straight portions 51-1. Multiple straight portions 51-2 may be arranged side by side in the Y-axis direction. A film 54 remains between the straight portions 51-2.

[0045] The bottom view image 204 may also include the cover portion 56. The cover portion 56 is larger than the bottom mark 50 when viewed from above. The cover portion 56 covers the entire bottom mark 50.

[0046] Figure 6 shows an example of the top image 206-1 and bottom image 208-1 related to the reference example. As described above, the top image 206-1 includes an image of the top mark 130, and the bottom image 208-1 includes an image of the bottom mark 50.

[0047] The top image 206-1 in this example also includes images of the bottom mark 50 and cover portion 56. In Figure 6, the bottom mark 50 and cover portion 56 reflected in the top image 206-1 are shown by dashed lines. Since the bottom mark 50 and cover portion 56 are positioned away from the focal point when the top image 206-1 is captured, the images of the bottom mark 50 and cover portion 56 in the top image 206-1 appear wider and blurred than the actual size of the structure. The degree to which the images of the bottom mark 50 and cover portion 56 are widened changes according to the thickness T1 of the semiconductor substrate 10 (see Figure 4). Also, the reflected light from the bottom mark 50 and cover portion 56 passes through the semiconductor substrate 10 and is attenuated. Therefore, the intensity of the images of the bottom mark 50 and cover portion 56 changes according to the thickness T1 of the semiconductor substrate 10. The thickness T1 of the semiconductor substrate 10 in this example is 60 μm.

[0048] In this example, the bottom image 208-1 also includes an image of the top mark 130. In Figure 6, the top mark 130 reflected in the bottom image 208-1 is shown by a dashed line. Since the top mark 130 is located away from the focal point when the bottom image 208-1 was captured, the image of the top mark 130 in the bottom image 208-1 appears wider and blurred than the actual size of the structure. The degree to which the image of the top mark 130 is widened varies depending on the thickness T1 of the semiconductor substrate 10. Since the reflected light from the top mark 130 does not pass through the semiconductor substrate 10, the image of the top mark 130 in the bottom image 208-1 may appear clearer than the images of the bottom mark 50, etc., in the top image 206-1.

[0049] Figure 7 shows an example of top image 206-2 and bottom image 208-2 related to a reference example. In this example, top image 206 and bottom image 208 were captured under the same conditions as in Figure 6, except that the thickness T1 of the semiconductor substrate 10 is 120 μm. As described above, as the thickness T1 of the semiconductor substrate 10 increases, the images of the bottom mark 50 etc. in top image 206-2 expand further, and the image of the top mark 130 in bottom image 208-2 expands further.

[0050] In each image (for example, the bottom image 208-2), if the image of the mark to be observed (for example, the bottom mark 50) and the image of the reflected mark (for example, the top mark 130) overlap, it becomes impossible to accurately observe the position of the mark to be observed. In particular, if the edge positions of the images of the marks are close together, it becomes impossible to accurately observe the edges of the mark to be observed, and the accuracy of detecting the position of the mark to be observed deteriorates. In this example, when the top mark 130 is formed by a groove 132, the groove 132 has two edges (two side walls that constitute the groove 132 in the resist 32) that are close together. Therefore, if the image of the top mark 130 is blurred and the groove 132 overlaps with the bottom mark 50, the images of the two edges of the groove 132 strongly interfere with the image of the bottom mark 50, making it impossible to accurately detect the image of the bottom mark 50. The same is true in the top image 206-2. However, as described above, in the top image 206-2, the intensity of images such as the bottom mark 50, which are not the object of observation, is attenuated according to the thickness T1 of the semiconductor substrate 10. On the other hand, in the bottom image 208-2, the intensity of images such as the bottom mark 50, which are the object of observation, is attenuated according to the thickness T1 of the semiconductor substrate 10. For this reason, the interference between the mark images described above often occurs in the bottom image 208-2.

[0051] Figure 8 shows an example of top image 206-3 and bottom image 208-3 related to a reference example. In this example, top image 206 and bottom image 208 were captured under the same conditions as in Figure 6, except that the thickness T1 of the semiconductor substrate 10 is 180 μm. As described above, as the thickness T1 of the semiconductor substrate 10 increases, the images of the bottom mark 50 etc. in top image 206-2 expand further, and the image of the top mark 130 in bottom image 208-2 expands further. In addition, in bottom image 208-2, the intensity of the images of the observed object, such as the bottom mark 50, decreases according to the thickness T1 of the semiconductor substrate 10, making it even more difficult to observe the bottom mark 50. In this example, as shown in Figure 6, when the thickness T1 of the semiconductor substrate 10 was 60 μm, the position of each mark could be detected with high accuracy. However, in the examples where the thickness T1 was 120 μm and 180 μm, the bottom surface marks 50 could not be detected by computer image processing of the bottom surface image 208.

[0052] Figure 9 is a cross-sectional view showing an example of the configuration of a semiconductor substrate 10 according to an embodiment. In this example, the semiconductor substrate 10 is provided with a top surface mark 30 instead of the top surface mark 130 shown in Figures 4 to 8. The other structures are the same as those described in Figures 4 to 8. In this example, the top surface mark 30 is a recess provided in the resist 32.

[0053] Figure 10 shows examples of top image 212 and bottom image 214. The top image 212 and bottom image 214 shown in Figure 10 are images of the same region in a top view. Top image 212 includes top mark 30, and bottom image 214 includes bottom mark 50. As mentioned above, top image 212 may include bottom mark 50, but it is omitted in top image 212 of Figure 10. Similarly, bottom image 214 may include top mark 30, but it is omitted in bottom image 214 of Figure 10.

[0054] In a top view, one of the top mark 30 and the bottom mark 50 is larger than the other, and the mark that is larger covers the entire other mark. In the examples in Figures 9 and 10, the top mark 30 is larger than the bottom mark 50, and the top mark 30 covers the entire bottom mark 50. In other examples, the structures of the top mark 30 and the bottom mark 50 may be reversed. That is, the bottom mark 50 may be larger than the top mark 30, and the bottom mark 50 may cover the entire top mark 30.

[0055] In this example, the top mark 30 is a recess located on the top surface 12 of the semiconductor substrate 10. For example, the recess is a space formed by partially removing the resist 32. The recess of the top mark 30 covers the entire bottom mark 50 when viewed from above. The top mark 30 may also be a protrusion located on the top surface 12 of the semiconductor substrate 10. For example, the protrusion is the resist 32 remaining after removing the resist 32 other than the top mark 30. In this case as well, the protrusion of the top mark 30 covers the entire bottom mark 50 when viewed from above. By forming the entire top mark 30 as a recess or protrusion to cover the bottom mark 50 in this way, interference between the mark images in the top image 212 and the bottom image 214 can be reduced. In other words, since the top mark 30 is a uniform recess or protrusion, it has fewer edges compared to the top mark 130 having a groove 132 as shown in Figure 5, etc. Therefore, interference between mark images can be reduced.

[0056] In a top view, it is preferable that the upper surface 12 of the semiconductor substrate 10 is free from irregularities over a predetermined distance Dt from the end of the recess or protrusion of the upper surface mark 30 covering the lower surface mark 50 toward the outside of the upper surface mark 30. This distance Dt may be 20 μm or more, 30 μm or more, 40 μm or more, or 50 μm or more.

[0057] As shown in Figure 10, when the top mark 30 is a recess in the resist 32, the resist 32 is provided over a range of distance Dt or more from the edge of the top mark 30. The resist 32 may be provided continuously without irregularities from the edge of the top mark 30 to the edge of the scribe line 20. When the top mark 30 is a recess, the attenuation of the illumination light when capturing the bottom image 214 can be suppressed. Therefore, the bottom mark 50 can be observed with greater accuracy in the bottom image 214, where mark images are prone to interference.

[0058] If the top mark 30 is a remaining resist 32, then the resist 32 is not provided in an area extending at a distance Dt or more from the edge of the top mark 30. The resist 32 does not need to be present from the edge of the top mark 30 to the edge of the scribe line 20.

[0059] Figure 11 shows an example of the top image 216-1 and bottom image 218-1 according to the embodiment. The thickness T1 of the semiconductor substrate 10 in this example is 60 μm. As described above, the top image 216-1 includes an image of the top mark 30, and the bottom image 218-1 includes an image of the bottom mark 50.

[0060] The top view image 216-1 of this example also includes images of the bottom mark 50 and cover portion 56. The bottom view image of this example. 218-1 This also includes an image of the top mark 130. (Bottom image) 218-1 In this case, the image of the bottom mark 50 and the reflected image of the top mark 30 overlap, but since the image of the top mark 30 is an almost uniform image that covers the entire bottom mark 50, it has little effect on the edges of the image of the bottom mark 50. For this reason, the position of the bottom mark 50 can be detected with high accuracy.

[0061] Figure 12 shows an example of the top image 216-2 and the bottom image 218-2. In this example, the top image 216 and the bottom image 218 were captured under the same conditions as in Figure 11, except that the thickness T1 of the semiconductor substrate 10 was 380 μm. As described above, as the thickness T1 of the semiconductor substrate 10 increases, the intensity of images such as the bottom mark 50 in the top image 216-2 decreases. In this example, the reflection of the bottom mark 50 on the top image 216-2 was hardly observed.

[0062] As the thickness T1 of the semiconductor substrate 10 increases, the image of the top mark 30 in the bottom image 208-2 expands further. However, since the image of the top mark 30 is a nearly uniform image that covers the entire bottom mark 50, it has little effect on the edges of the bottom mark 50 image. In this example, even when the thickness T1 of the semiconductor substrate 10 was 380 μm, the bottom mark 50 could be detected accurately by computer image processing. Similarly, the bottom mark 50 could be detected accurately when the thickness T1 of the semiconductor substrate 10 was 120 μm or 180 μm. According to this example, even if the thickness T1 of the semiconductor substrate 10 is increased, the position of the bottom mark 50 can be detected accurately, so semiconductor devices can be manufactured with high precision.

[0063] Figure 13 illustrates examples of the shapes of the top mark 30 and bottom mark 50 in a top view. Figure 13 shows the top mark 30 in top image 212 and the bottom mark 50 in bottom image 214. Since each mark is located at the focal point, the size of the marks in each image represents the actual size of the marks.

[0064] In this example, the top mark 30 is larger than the bottom mark 50. By making the bottom mark 50 smaller, the cover portion 56 can be made smaller. Let W1 be the width of the top mark 30 in the X-axis direction, and W2 be the width of the bottom mark 50 in the X-axis direction. For example, the X-axis direction is the direction perpendicular to the extension direction of the scribe line 20 on which these marks are provided. In this example, the width W1 is larger than the width W2. The width W1 may be 40 μm or more larger than the width W2, 50 μm or more larger, or 60 μm or more larger. The width W1 is smaller than the width of the scribe line 20 in the X-axis direction. By making the width W1 larger, the distance D1 between the edge of the top mark 30 and the edge of the bottom mark 50 in the top view can be increased, and interference between the edges of the marks in the image can be suppressed. The distance D1 may be 20 μm or more, 25 μm or more, or 30 μm or more. The greater the thickness T1 of the semiconductor substrate 10, the more the marks that are not the object of observation spread in each image, so the distance D1 may be determined according to the thickness T1. For example, the distance D1 may be 30% or more of the thickness T1, 40% or more, or 50% or more. The distance D1 may be less than or equal to the thickness T1. In another example, the bottom mark 50 may be larger than the top mark 30 in the top view. The bottom mark 50 explained in Figure 13 may be used as the top mark, and the top mark 30 may be used as the bottom mark.

[0065] In a top view, the cover portion 56 is larger than the bottom mark 50 and smaller than the top mark 30. The cover portion 56 only needs to cover the bottom mark 50, so it only needs to be slightly larger than the bottom mark 50. In a top view, the distance D2 between the end of the cover portion 56 and the end of the bottom mark 50 may be smaller than the distance D3 between the end of the cover portion 56 and the end of the top mark 30. Distance D2 may be half or less of distance D3, 1 / 4 or less, or 1 / 10 or less. Distance D2 may be 5 μm or less. However, if the distance between the ends of the cover portion 56 and the bottom mark 50 is too small, it may be difficult to observe the position of the end of the bottom mark 50. Distance D2 may be 1 μm or more, or 3 μm or more. Distance D3 may be 20 μm or more, 30 μm or more, or 40 μm or more.

[0066] Preferably, the shape of the cover portion 56 in a top view is neither identical nor similar to the shape of the bottom mark 50. This makes it easier to distinguish between the cover portion 56 and the bottom mark 50. In this example, the cover portion 56 is rectangular in a top view.

[0067] For example, the width W1 of the top mark 30 is 80 μm or more. The width W1 is smaller than the width of the scribe line 20. The width W1 may be 100 μm or less. The width W2 of the bottom mark 50 is 20 μm or more and 40 μm or less. The width W3 of the cover portion 56 is 40 μm or more and 60 μm or less.

[0068] It is preferable that the top mark 30 and the bottom mark 50 do not have the same or similar shapes when viewed from above. This suppresses interference between the edges of the mark images. In this example, the top mark 30 is a rectangle with four sides. In this example, the bottom mark 50 has a shape formed by two intersecting rectangles. Since the bottom mark 50 has two intersecting rectangles, it has more sides than the top mark 30. As described above, the intensity of the image of the top mark 30 in the bottom image 214, etc., becomes relatively strong and is prone to interference with the image of the bottom mark 50. For this reason, by making the top mark 30 a simple shape with a small number of sides (edges), such as a rectangle, interference of the image of the top mark 30 in the bottom image 214, etc., can be suppressed.

[0069] Figure 14 is a table showing the measurement results of the mark positions for multiple samples in which the shape and size of the top and bottom marks were changed. The unit of measurement for the numerical values ​​in the table in Figure 14 is μm. In Figure 14, measurement results in which the position of the top mark could be detected in the top image and the position of the bottom mark could be detected in the bottom image are indicated by circles.

[0070] Sample A has a top surface mark 130 as shown in Figure 5. The width W1 of the top surface mark 130 is 160 μm, and the width Wt of the groove 132 is 5 μm. The width W1 of the top surface mark 130 is the width of the area enclosed by the groove 132 of the top surface mark 130. Sample A also has a cover portion 56 and does not have a bottom surface mark 50. For Sample A, the cover portion 56 is used as the bottom surface mark. For Sample A, the measurement results when the cover portion 56 can be detected in the bottom image and the top surface mark 130 can be detected in the top image are indicated by circles.

[0071] In Sample A, the top surface mark 130 has a narrow groove 132, resulting in relatively large interference in the bottom surface image. Furthermore, a cover portion 56 similar in shape to the top surface mark 130 is used as the bottom surface mark. Therefore, the image of the cover portion 56 and the reflected image of the top surface mark 130 in the bottom surface image are prone to interference. In Sample A, when the width W1 of the top surface mark 130 was increased to 160 μm and the distance D3 between the top surface mark 130 and the cover portion 56 was increased to 55 μm, each mark could be detected in the semiconductor substrate 10 thickness T1 range of 60 μm to 380 μm. However, when the width W1 was reduced to less than 160 μm and the distance D3 was reduced to less than 55 μm, it became difficult to detect each mark.

[0072] Sample B has the top mark 30 shown in Figure 10. The width W1 of the top mark 30 is 80 μm, the width W2 of the bottom mark 50 is 36 μm, and the distance D1 between the top mark 30 and the bottom mark 50 is 22 μm. In this example, since the top mark 30 is a uniform recess, the interference with the bottom image is relatively small. Therefore, each mark can be detected more easily than in Sample A. When the distance D1 is approximately 20 μm or more, each mark could be detected even when the thickness T1 of the semiconductor substrate 10 was increased to 180 μm. However, when the thickness T1 of the semiconductor substrate 10 is greater than 380 μm, it may be difficult to detect each mark.

[0073] Sample E has the top mark 30 shown in Figure 10. The width W1 of the top mark 30 is 90 μm, the width W2 of the bottom mark 50 is 30 μm, and the distance D1 between the top mark 30 and the bottom mark 50 is 30 μm. In this example, the distance D1 is increased by making the top mark 30 larger and the bottom mark 50 smaller compared to Sample B. In this example, each mark could be detected even when the thickness T1 of the semiconductor substrate 10 was increased to 380 μm. The distance D1 may be 30 μm or more. Alternatively, the distance D1 may be 7% or more, 8% or more, or 10% or more of the thickness T1 of the semiconductor substrate 10.

[0074] Samples C and D both have the top surface mark 130 shown in Figure 5. However, the width Wt of the groove 132 in sample C is 10 μm, while the width Wt of the groove 132 in sample D is 5 μm. The distance D1 of sample C is 22 μm, and the distance D1 of sample D is 30 μm. Since the distance D1 of sample C is smaller than the distance D1 of sample D, it can be considered that the images between marks are more prone to interference in sample C. However, when the substrate thickness T1 is 60 μm, the bottom surface mark was detected in sample C, but not in sample D. This is thought to be because the width Wt of the groove 132 in sample C is larger, suppressing interference. The distance Dt shown in Figure 10 may be 20 μm or more.

[0075] Samples D and E have the same distance D1. However, in sample D, the marks could not be detected at any substrate thickness T1, whereas in sample E, the marks could be detected at any substrate thickness T1. Therefore, it can be seen that using the top surface marks 30, as explained in Figures 9 to 13, makes it easier to detect the marks than using the top surface marks 130, as explained in Figures 4 to 8. Also, compared to sample A, the top surface marks 30 can be made smaller in samples B and E. For example, in samples B and E, the marks can be made smaller than the scribe lines 20. Therefore, the marks can be placed at various positions on the semiconductor substrate 10. Multiple sets of top surface marks 30 and bottom surface marks 50 may be placed on the semiconductor substrate 10.

[0076] In this example, both the top mark 30 and the bottom mark 50 are observed from the top surface of the semiconductor substrate 10. When observing the top mark 30 from the top surface of the semiconductor substrate 10 and the bottom mark 50 from the bottom surface, an observation hole for observing the bottom mark 50 must be provided on the stage on which the semiconductor substrate 10 is placed. If the semiconductor substrate 10 is warped due to the manufacturing process, providing an observation hole on the stage may cause the semiconductor substrate 10 to warp on the stage in the area where the observation hole is provided, potentially degrading the measurement accuracy. Also, the position where the marks can be placed is limited to the position of the observation hole. In this example, since it is not necessary to provide an observation hole on the stage, the deterioration of measurement accuracy can be reduced by firmly adhering the semiconductor substrate 10 to the stage and making it flat. In addition, the top mark 30 and the bottom mark 50 can be placed in various positions. Therefore, even if the semiconductor substrate 10 is warped, the misalignment between the marks can be detected. Furthermore, the misalignment between the marks can be detected at any point on the semiconductor substrate 10.

[0077] Figure 15 shows the film thickness of each component. In Figure 15, the thickness T1 of the semiconductor substrate 10, the film thickness T2 of the resist 32, the film thickness T3 of the film 54, and the film thickness T4 of the cover portion 56 are shown. As an example, the thickness T1 of the semiconductor substrate 10 is 60 μm or more and 380 μm or less. The thickness T1 may be determined according to the withstand voltage that the semiconductor device should have.

[0078] For example, the film thickness T2 of the resist 32 is 1 μm or more and 6 μm or less. That is, the height of the top mark 30 is 1 μm or more and 6 μm or less. For example, the film thickness T3 of the film 54 is 0.3 μm or more and 1.2 μm or less. That is, the height of the bottom mark 50 is 0.3 μm or more and 1.2 μm or less. For example, the film thickness T4 of the cover portion 56 is 0.5 μm or more and 6 μm or less. Film thickness T4 may be the thickness of the portion formed below film 54. Also, if a groove is formed in the semiconductor substrate 10 itself to form any of the marks, the depth of the groove may be 5 μm or more and 6 μm or less.

[0079] Figure 16 shows another example of the structure of the bottom mark 50. In this example, the structure of the groove 52 differs from that of the bottom mark 50 in Figures 1 to 15. The other structures are the same as those of the bottom mark 50 in any of the examples described in Figures 1 to 15.

[0080] The lower surface mark 50 in this example has grooves 52-1, 52-2, and 52-3. Groove 52-1 is arranged along the outer shape of two straight sections 51. In this example, groove 52-1 is arranged along the outer shape of a rectangle whose longitudinal side is in the X-axis direction and a rectangle whose longitudinal side is in the Y-axis direction intersect.

[0081] Grooves 52-2 and 52-3 are located in the region enclosed by groove 52-1. In this example, groove 52-2 extends in the Y-axis direction, and groove 52-3 extends in the X-axis direction. Grooves 52-2 and 52-3 intersect at their central portions.

[0082] In the examples shown in Figures 1 to 15, both ends of groove 52-2 in the Y-axis direction and both ends of groove 52-3 in the X-axis direction are connected to groove 52-1. In this example, both ends of groove 52-2 in the Y-axis direction and both ends of groove 52-3 in the X-axis direction are separated from groove 52-1. A film 54 remains between grooves 52-2 and 52-3 and groove 52-1. According to this example, the number of intersections between grooves 52 can be reduced.

[0083] When forming grooves 52 by etching using a resist, the resist is shaped according to the pattern of grooves 52 to be formed. If there are intersections between grooves 52, the resist will be divided into small regions, making the resist prone to peeling. In this example, the number of intersections between grooves 52 can be reduced, thereby suppressing peeling of the resist and enabling the grooves 52 to be formed with high precision.

[0084] When forming grooves 52 by etching or the like, the width of the grooves 52 may be wider at the intersections of the grooves 52 compared to other parts. When embedding a material such as polysilicon in the grooves 52, the material may not be able to be sufficiently embedded in the wider parts of the grooves 52. If there are parts of the grooves 52 where the material is not sufficiently embedded, resist or the like may get into those parts and remain. Furthermore, these parts may become a source of foreign matter. In this example, the number of intersections of the grooves 52 can be reduced, so the embedding of the grooves 52 can be performed with high precision.

[0085] Figure 17 shows another example of the structure of the lower mark 50. In this example, the structure of grooves 52-2 and 52-3 of the lower mark 50 differs from that of the example in Figure 16. The other structures are the same as those of the example in Figure 16.

[0086] In this example, groove 52-2 is separated into two by a membrane 54 positioned in the central part in the Y-axis direction. Groove 52-3 is separated into two by a membrane 54 positioned in the central part in the X-axis direction. Grooves 52-2 and 52-3 are also separated from each other by membranes 54 positioned at their intersections. According to this example, the number of intersections in groove 52 can be further reduced.

[0087] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention. [Explanation of symbols]

[0088] 10...Semiconductor substrate, 12...Top surface, 14...Bottom surface, 20...Scribing line, 22...Semiconductor chip, 30...Top surface mark, 32...Resist, 50...Bottom surface mark, 51...Straight section, 52...Groove section, 54...Film, 56...Cover section, 130...Top surface mark, 132...Groove section, 200...Imaging section, 202, 206, 212, 216...Top surface image, 204, 208, 214, 218...Bottom surface image

Claims

1. A method for manufacturing a semiconductor device, A mark forming step in which an upper mark is formed on the upper surface of the semiconductor substrate, a lower mark is formed on the lower surface of the semiconductor substrate, and a cover portion is formed on the lower mark using a material with a higher reflectivity than the lower mark, A position detection step in which a positional misalignment of the upper mark and the lower mark is detected by obtaining an upper image obtained by observing the upper mark from above the upper surface of the semiconductor substrate, and a lower image obtained by observing the lower mark from above the upper surface of the semiconductor substrate by passing through the semiconductor substrate, The element formation step of forming a semiconductor element on the semiconductor substrate Equipped with, In a top view where the upper mark and the lower mark are projected onto a plane parallel to the top surface, the upper mark is larger than the lower mark, and the upper mark completely covers the lower mark. In the aforementioned top view, the cover portion is larger than the bottom mark and smaller than the top mark. A method for manufacturing a semiconductor device.

2. In the above top view, the distance between the end of the cover portion and the end of the bottom mark is smaller than the distance between the end of the cover portion and the end of the top mark. A method for manufacturing a semiconductor device according to claim 1.

3. A method for manufacturing a semiconductor device, A mark formation step in which an upper mark is formed on the upper surface of the semiconductor substrate and a lower mark is formed on the lower surface of the semiconductor substrate, A position detection step in which a positional misalignment of the upper mark and the lower mark is detected by obtaining an upper image obtained by observing the upper mark from above the upper surface of the semiconductor substrate, and a lower image obtained by observing the lower mark from above the upper surface of the semiconductor substrate by passing through the semiconductor substrate, The element formation step of forming a semiconductor element on the semiconductor substrate Equipped with, In a top view where the upper mark and the lower mark are projected onto a plane parallel to the upper surface, one of the upper mark and the lower mark is larger than the other, and the one covers the entirety of the other. In the position detection step, the wavelength of light irradiated onto the semiconductor substrate when acquiring the upper image is the same as the wavelength of light irradiated onto the semiconductor substrate when acquiring the lower image. A method for manufacturing a semiconductor device.

4. A method for manufacturing a semiconductor device, A mark formation step in which an upper mark is formed on the upper surface of the semiconductor substrate and a lower mark is formed on the lower surface of the semiconductor substrate, A position detection step to detect misalignment of the upper and lower marks by obtaining an upper image obtained by observing the upper mark from above the upper surface of the semiconductor substrate, focusing according to the position of the upper surface, and a lower image obtained by observing the lower mark from above the upper surface of the semiconductor substrate, focusing according to the position of the lower surface, and passing through the semiconductor substrate; The element formation step of forming a semiconductor element on the semiconductor substrate Equipped with, In a top view where the upper mark and the lower mark are projected onto a plane parallel to the upper surface, one of the upper mark and the lower mark is larger than the other, and the one covers the entirety of the other. The aforementioned lower surface image further includes an image of the upper surface mark that is superimposed on the image of the lower surface mark. A method for manufacturing a semiconductor device.

5. In the above top view, the bottom mark is larger than the top mark. A method for manufacturing a semiconductor device according to claim 3 or 4.

6. In the above top view, the distance between the end of the bottom mark and the end of the top mark is 20 μm or more. A method for manufacturing a semiconductor device according to any one of claims 1 to 4.

7. The aforementioned upper surface mark is a recess located on the upper surface of the semiconductor substrate. A method for manufacturing a semiconductor device according to any one of claims 1 to 4.

8. The aforementioned lower mark has two or more straight sections in the top view where their respective longitudinal directions intersect. The method for manufacturing a semiconductor device according to claim 7.

9. The aforementioned upper surface mark is a protrusion located on the upper surface of the semiconductor substrate. A method for manufacturing a semiconductor device according to any one of claims 1 to 4.

10. In the aforementioned top view, a region without irregularities is provided extending outward from the edge of the top mark, covering a range of at least 20 μm. The method for manufacturing a semiconductor device according to claim 9.

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