Light-emitting components, light-emitting devices, and measuring devices

Abstract

To suppress other thyristors from being turned on by light emitted from a thyristor compared to the case where a substrate on which a light emitting element and the plurality of thyristors are provided does not absorb light emitted from the thyristor.SOLUTION: A light emitting component has a substrate, a plurality of light emitting elements provided on the substrate, each of which has a light emitting region, and a plurality of thyristors provided on each of the light emitting elements and including a gate layer and that are turned on to cause the light emitting regions of the respective light emitting elements to emit light or increase the amount of light emitted from the light emitting regions, in which the substrate absorbs light emitted from the thyristors and emits light that is not absorbed by the gate layer.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to light-emitting components, semiconductor multilayer substrates, light-emitting devices, and measuring devices. [Background technology]

[0002] Patent Document 1 discloses a light-emitting component comprising a substrate, a plurality of light-emitting elements each consisting of a vertical-cavity surface-emitting laser provided on the substrate, and setting thyristors stacked on each light-emitting element and used to drive the light-emitting elements. In this light-emitting component, when the setting thyristor is turned on, a current flows between the setting thyristor and the light-emitting element, causing the light-emitting element to emit light. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2018-6502 [Overview of the project] [Problems that the invention aims to solve]

[0004] Incidentally, a thyristor that is turned on may emit light. In light-emitting components that have multiple thyristors, if light emitted from one thyristor that is turned on propagates to other thyristors, the propagated light may cause the other thyristors to turn on. In this case, the other thyristors that are now turned on may cause light-emitting elements that are not intended to emit light to emit light, making it difficult to control the light emission of the light-emitting elements. The present invention aims to suppress the activation of other thyristors by light emitted from one thyristor, compared to a case where a substrate on which a light-emitting element and multiple thyristors are provided does not absorb light emitted from a thyristor. [Means for solving the problem]

[0005] The invention described in claim 1 comprises a substrate, a plurality of light-emitting elements provided on the substrate, each having a light-emitting region, and a plurality of thyristors provided on each of the light-emitting elements, each including a gate layer, which, when turned on, cause the light-emitting region of the light-emitting element to emit light or increase the amount of light emitted in the light-emitting region, wherein the substrate is a light-emitting component that absorbs light emitted from the thyristors and emits light that is not absorbed by the gate layer. The invention described in claim 2 is a light-emitting component according to claim 1, characterized in that the light-emitting element transmits light emitted from the thyristor. The invention described in claim 3 is a light-emitting component according to claim 2, characterized in that the light-emitting element has a semiconductor layer containing Al, and the gate layer of the thyristor is made of a semiconductor that contains Al and has a lower Al content ratio compared to the semiconductor layer of the light-emitting element. The invention described in claim 4 is a light-emitting component according to claim 3, characterized in that the semiconductor layer of the light-emitting element is a multilayer reflective layer in which a first semiconductor layer made of AlGaAs and a second semiconductor layer made of AlGaAs with a higher Al content ratio than the first semiconductor layer are alternately stacked, and the gate layer of the thyristor is made of AlGaAs with a lower Al content ratio than the first semiconductor layer of the multilayer reflective layer. The invention described in claim 5 is a light-emitting component according to claim 2, wherein the light-emitting element comprises a lower semiconductor layer laminated on the substrate, a light-emitting layer laminated on the lower semiconductor layer, and an upper semiconductor layer laminated on the light-emitting layer, wherein the upper semiconductor layer has a higher transmittance of light emitted from the thyristor compared to the lower semiconductor layer. The invention described in claim 6 is a light-emitting component according to claim 1, characterized in that the substrate emits light with a longer wavelength than the light emitted from the thyristor towards the light-emitting element. The invention described in claim 7 is a light-emitting component according to claim 6, characterized in that the gate layer of the thyristor is made of a semiconductor containing Al, and the substrate is made of GaAs. Claim 8The invention described herein is a light-emitting device comprising a substrate, a plurality of light-emitting elements provided on the substrate and each having a light-emitting region, a plurality of thyristors provided on each of the light-emitting elements and including a gate layer, which, when turned on, cause the light-emitting region of the light-emitting element to emit light or increase the amount of light emitted in the light-emitting region, and a drive unit that individually drives the plurality of thyristors to switch them to the ON state, wherein the substrate is a light-emitting device that absorbs light emitted from the thyristors and emits light that is not absorbed by the gate layer. Claim 9 The invention described herein is a measuring device comprising a substrate, a plurality of light-emitting elements provided on the substrate and each having a light-emitting region, a plurality of thyristors provided on each of the light-emitting elements and including a gate layer, which, when turned on, cause the light-emitting region of the light-emitting element to emit light or increase the amount of light emitted in the light-emitting region, a drive unit that individually drives the plurality of thyristors and causes each of the light-emitting regions to emit light at a predetermined timing, and an acquisition unit that acquires information about an object based on the reflected light from the light-emitting region of the object reflected by the object, wherein the substrate is a measuring device that absorbs light emitted from the thyristors and emits light that is not absorbed by the gate layer. [Effects of the Invention]

[0006] Claims 1 and 8 、9 According to the invention described above, compared to a case where the substrate on which the light-emitting element and multiple thyristors are provided does not absorb the light emitted from the thyristors, it is possible to suppress the turning on of other thyristors due to the light emitted from one thyristor. According to the invention described in claim 2, the temperature rise of the light-emitting element can be suppressed compared to the case in which the light-emitting element does not transmit light emitted from the thyristor. According to the invention described in claim 3, compared to the case where the Al content ratio of the gate layer of the thyristor is higher than that of the semiconductor layer of the light-emitting element, the light emitted from the thyristor is less likely to be absorbed by the light-emitting element. According to the invention of claim 4, compared to a case where the gate layer of the thyristor is made of AlGaAs having a higher Al content ratio than the first semiconductor layer, light emitted from the thyristor is less likely to be absorbed by the light-emitting element. According to the invention of claim 5, compared to a case where the upper semiconductor layer has lower transmittance for light emitted from the thyristor than the lower semiconductor layer, deterioration of characteristics of the light-emitting element due to temperature rise is suppressed. According to the invention of claim 6, compared to a case where the substrate emits light having the same wavelength as light emitted from the thyristor, light emitted from the substrate is less likely to be absorbed by the thyristor. According to the invention of claim 7, compared to a case where the substrate contains Al, light emitted from the substrate is less likely to be absorbed by the thyristor. [BRIEF DESCRIPTION OF THE DRAWINGS]

[0007] [Figure 1] FIG. 1 is a diagram illustrating an example of a measurement device to which the present embodiment is applied. [Figure 2] FIG. 2 is a diagram illustrating a light source device to which the present embodiment is applied. [Figure 3] (a) and (b) are an example of a plan layout view and a cross-sectional view of a light-emitting chip to which the present embodiment is applied. [Figure 4] FIG. 3 is an example of an enlarged cross-sectional view of an island in which a VCSEL and a setting thyristor are stacked. [Figure 5] FIG. 4 is a timing chart illustrating an example of operations of the light source device and the light-emitting chip. [Figure 6] FIG. 5 is a diagram illustrating an example of behavior of light emitted from a setting thyristor when the substrate does not absorb the light emitted from the setting thyristor. [Figure 7] FIG. 6 is a diagram illustrating an example of behavior of light emitted from a setting thyristor in a light-emitting chip to which the present embodiment is applied. [DESCRIPTION OF EMBODIMENTS]

[0008] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Here, we will explain, as an example, how a light source device 1, which includes a light-emitting chip 10 as an example of a light-emitting component, can be applied to a measuring device that measures the three-dimensional shape (hereinafter referred to as 3D shape) of an object to be measured.

[0009] (Measuring device 100) Figure 1 shows an example of a measuring device 100 to which this embodiment is applied. The measuring device 100 of this embodiment measures the three-dimensional shape (hereinafter referred to as 3D shape) of an object to be measured. The measuring device 100 is a device that measures the 3D shape based on the so-called ToF (Time of Flight) method, which is based on the time of flight of light. The measuring device 100 comprises a light source device 1, which is an example of a light-emitting device that includes a light-emitting chip 10 and a control unit 110, and a three-dimensional sensor (hereinafter referred to as 3D sensor) 5. In the ToF method, the time from the moment light is emitted from the light source device 1 to the moment it is reflected by the object to be measured and received by the 3D sensor 5 is measured. Then, the distance to the object to be measured is calculated from the time acquired from the 3D sensor 5, and the 3D shape of the object to be measured is determined. Furthermore, the measurement of 3D shape may be referred to as three-dimensional measurement, 3D measurement, or 3D sensing.

[0010] The light source device 1 emits light toward the object to be measured. The 3D sensor 5 acquires the light reflected back from the object to be measured (reflected light). The 3D sensor 5 outputs distance information to the object to be measured (distance information) based on the time from emission to reception of reflected light, measured by the Time of Flight (ToF) method. The measurement device 100 may also include a measurement control unit 200. The measurement control unit 200 is configured as a computer including a CPU, ROM, RAM, etc., and identifies the 3D shape of the object to be measured based on the distance information acquired from the 3D sensor 5.

[0011] Furthermore, the measuring device 100 can be applied to recognizing an object to be measured from its identified 3D shape. For example, the measuring device 100 can be mounted on a portable information processing device and used to recognize the face of a user attempting to access it. In other words, it acquires the 3D shape of the accessing user's face, identifies whether or not access is permitted, and only permits the use of the device (portable information processing device) if it is recognized that the user is authorized to access it. Furthermore, the measuring device 100 can also be applied to situations where the 3D shape of an object to be measured is to be continuously measured, such as in augmented reality (AR).

[0012] (Light source device 1) Figure 2 illustrates the light source device 1 to which this embodiment is applied. In Figure 2, the rightward direction on the paper is defined as the +x direction. Note that the positions of the terminals (φ1 terminal, φ2 terminal, Vga terminal, φI terminal) in the light source device 1 shown in Figure 2 are not necessarily precise. The light source device 1 shown in Figure 2 comprises a light-emitting chip 10 and a control unit 110.

[0013] (Control Unit 110) The control unit 110 includes a transfer signal generation unit 120, a lighting signal generation unit 140, a reference potential supply unit 160, and a power supply potential supply unit 170. The transfer signal generation unit 120 generates transfer signals φ1 and φ2 to sequentially transfer the ON state to a plurality of transfer thyristors T, which will be described later. The lighting signal generation unit 140 generates a lighting signal φI that supplies current to light up (emit light) a plurality of VCSELs, which will be described later. The reference potential supply unit 160 supplies the reference potential Vsub. The power supply potential supply unit 170 supplies the power supply potential Vga.

[0014] (Light-emitting chip 10) The light-emitting chip 10 comprises a light-emitting section 11 and a data transfer section 12. The light-emitting chip 10 also comprises a φ1 terminal, a φ2 terminal, a Vga terminal, a φI terminal, and a Vsub terminal. The light-emitting unit 11 is equipped with a Vertical Cavity Surface Emitting Laser (VCSEL). Hereafter, the Vertical Cavity Surface Emitting Laser (VCSEL) will be referred to as VCSEL. In the example shown in Figure 2, there are six VCSELs, from VCSEL1 to VCSEL6 (referred to as VCSEL unless otherwise distinguished). The light-emitting unit 11 is also equipped with six setting thyristors, from S1 to S6 (referred to as setting thyristors unless otherwise distinguished). The anodes of the VCSELs are connected to the cathodes of the setting thyristors S. In other words, VCSELs and setting thyristors S of the same number are connected in series. Furthermore, as shown in Figure 4, which will be described later, the setting thyristors S are stacked on top of the VCSELs formed on the substrate 80. Hereafter, setting thyristors S may be referred to as thyristors. In this embodiment, each VCSEL is an example of a light-emitting element. Also, each setting thyristor S is an example of a thyristor.

[0015] The transfer unit 12 comprises six transfer thyristors T1 to T6 (referred to as transfer thyristor T unless otherwise specified) and six lower diodes UD1 to UD6 (referred to as lower diode UD unless otherwise specified). The transfer thyristors T1 to T6 and lower diodes UD1 to UD6 are arranged in series with the same numbered transfer thyristor T and lower diode UD. Furthermore, as shown in Figure 3(b) later, the transfer thyristors T are stacked on lower diodes UD formed on the substrate 80.

[0016] Furthermore, the transfer unit 12 is equipped with two transfer thyristors T1 to T6 in numerical order, and coupling diodes D1 to D5 (referred to as coupling diode D if not distinguished) between each pair. Furthermore, the transfer unit 12 includes power line resistors Rg1 to Rg6 (or Rg if not distinguished).

[0017] Furthermore, the transfer unit 12 is equipped with one start diode SD. Furthermore, the transfer unit 12 includes current limiting resistors R1 and R2 provided to prevent excessive current from flowing through the first transfer signal line 72 to which the first transfer signal φ1 (described later) is supplied and the second transfer signal line 73 to which the second transfer signal φ2 is supplied.

[0018] The VCSEL1 to VCSEL6 and setting thyristors S1 to S6 of the light-emitting section 11, the transfer thyristors T1 to T6 of the transfer section 12, the lower diodes UD1 to UD6, the coupling diodes D1 to D5, and the power line resistors Rg1 to Rg6 are arranged in numerical order on the light-emitting chip 10, from one side (-x direction side, left side in Figure 2) to the other side (+x direction side, right side in Figure 2).

[0019] In this embodiment, the number of VCSELs in the light-emitting section 11, the setting thyristor S, the transfer thyristor T in the transfer section 12, the lower diode UD, and the power line resistor Rg are each set to 6. The number of coupling diodes D is 5, which is one less than the number of transfer thyristors T. The number of VCSELs, setting thyristors S, transfer thyristors T, lower diode UD, power line resistor Rg, and coupling diodes D is not limited to the above and may be set to a predetermined number. Also, the number of transfer thyristors T may be greater than the number of VCSELs.

[0020] The VCSEL, lower diode UD, coupling diode D, and start diode SD described above are two-terminal semiconductor elements with an anode terminal and a cathode terminal. The thyristors (setting thyristor S, transfer thyristor T) are three-terminal semiconductor elements with an anode terminal, a gate terminal, and a cathode terminal. Note that terminals may be abbreviated and enclosed in parentheses below.

[0021] In the light-emitting chip 10 of this embodiment, the VCSEL, setting thyristor S, lower diode UD, transfer thyristor T, coupling diode D, power line resistor Rg, and start diode SD are configured as an integrated circuit by a semiconductor stack epitaxially grown on a common semiconductor substrate (hereinafter referred to as substrate 80). Here, the semiconductor stack is composed of a III-V compound semiconductor such as GaAs, AlGaAs, or AlAs as an example.

[0022] Next, we will explain the electrical connections of each element in the light-emitting chip 10. The anodes of the VCSEL and the lower diode UD are connected to board 80 (common anode). These anodes are supplied with a reference potential Vsub via a back electrode 91, which is a Vsub terminal located on the back surface of the substrate 80. Each cathode of the VCSEL is connected to the anode of the setting thyristor S. Additionally, each cathode of the lower diode UD is connected to the anode of the transfer thyristor T. Note that this connection is the configuration when using a p-type substrate 80. When using an n-type substrate, the polarity is reversed, and when using an intrinsic (i) type substrate without added impurities, a terminal for supplying the reference potential Vsub is provided on the side of the substrate where the light-emitting section 11 and the transfer section 12 are located.

[0023] Along the arrangement of the transfer thyristors T, the cathodes of the odd-numbered transfer thyristors T1, T3, and T5 are connected to the first transfer signal line 72. The first transfer signal line 72 is then connected to the φ1 terminal via a current limiting resistor R1. The first transfer signal φ1 is supplied to this φ1 terminal from the transfer signal generation unit 120 of the control unit 110. Meanwhile, along the arrangement of the transfer thyristors T, the cathodes of the even-numbered transfer thyristors T2, T4, and T6 are connected to the second transfer signal line 73. The second transfer signal line 73 is connected to the φ2 terminal via a current limiting resistor R2. The second transfer signal φ2 is supplied to this φ2 terminal from the transfer signal generation unit 120 of the control unit 110.

[0024] Each cathode of the setting thyristor S is connected to the illumination signal line 75. The illumination signal line 75 is connected to the φI terminal. In the light-emitting chip 10, the illumination signal φI is supplied to the φI terminal from the illumination signal generation unit 140 of the control unit 110 via a current limiting resistor RI provided on the outside of the light-emitting chip 10. The illumination signal φI supplies current to the VCSEL for illumination.

[0025] Each of the transfer thyristors T1 to T6 (Gt1 to Gt6, referred to as gate Gt if not distinguished) is connected one-to-one to the gates Gs1 to Gs6 (referred to as gate Gs if not distinguished) of the setting thyristors S1 to S6 with the same number. Therefore, gates Gt1 to Gt6 and gates Gs1 to Gs6 with the same number are electrically at the same potential. Thus, for example, gate Gt1 (gate Gs1) is used to indicate that they have the same potential.

[0026] The gates Gt1 to Gt6 of the transfer thyristors T1 to T6 are paired in numerical order, and coupling diodes D1 to D5 are connected between each of these gates. In other words, coupling diodes D1 to D5 are directly connected so that they are sandwiched between the gates Gt1 to Gt6. The orientation of coupling diode D1 is such that current flows from gate Gt1 to gate Gt2. The same applies to the other coupling diodes D2 to D5.

[0027] The gate Gt (gate Gs) of the transfer thyristor is connected to the power line 71 via a power line resistor Rg, which is provided corresponding to each transfer thyristor T. The power line 71 is connected to the Vga terminal. The power potential Vga is supplied to the Vga terminal from the power potential supply unit 170 of the control unit 110.

[0028] The gate Gt1 of the transfer thyristor T is connected to the cathode of the start diode SD. On the other hand, the anode of the start diode SD is connected to the second transfer signal line 73.

[0029] Figures 3(a) and 3(b) are examples of plan layout and cross-sectional views of the light-emitting chip 10 to which this embodiment is applied. Figure 3(a) is an example of a plan layout of the light-emitting chip 10, and Figure 3(b) is an example of a cross-sectional view along line IIIB-IIIB in Figure 3(a). Note that in Figures 3(a) and 3(b), the protective layer (protective layer 90 in Figure 4, described later) and the light-shielding layer (light-shielding layer 95 in Figure 4, described later) are omitted. Also, in Figure 3(b), the connection wiring shown in Figure 3(a) is omitted.

[0030] First, the cross-sectional structure of the light-emitting chip 10 will be explained with reference to Figure 3(b). The light-emitting chip 10 has a p-type substrate 80 (substrate 80) on which a p-type anode layer 81, a light-emitting layer 82, and an n-type cathode layer 83, which constitute the VCSEL and lower diode UD, are arranged in order. As will be described in detail later, in the light-emitting chip 10 of this embodiment, the p-type anode layer 81 and the n-type cathode layer 83 are composed of a distributed Bragg reflector (DBR) (hereinafter referred to as the DBR layer), which is made up of multiple semiconductor layers having a refractive index difference stacked on top of each other. Therefore, below, the p-type anode layer 81 will be referred to as the p-anode (DBR) layer 81. Similarly, the n-type cathode layer 83 will be referred to as the n-cathode (DBR) layer 83.

[0031] Furthermore, the light-emitting chip 10 has a tunnel junction (tunnel diode) layer 84 (tunnel junction layer 84) provided on the n cathode (DBR) layer 83. Furthermore, the light-emitting chip 10 has a set thyristor S, a transfer thyristor T, a coupling diode D, a p-type anode layer 85 (p-anode layer 85), an n-type gate layer 86 (n-gate layer 86), a p-type gate layer 87 (p-gate layer 87), and an n-type cathode layer 88 (n-cathode layer 88) arranged in order on the tunnel junction layer 84, which constitute a set thyristor S, a transfer thyristor T, a coupling diode D, and a power line resistor Rg. In the following, the notation in parentheses will be used. The same applies to other cases.

[0032] Components such as VCSELs, lower diodes UD, setting thyristors S, transfer thyristors T, and coupling diodes D are composed of multiple islands separated by etching, which removes a portion of each of the above layers. These islands are sometimes referred to as mesas, and the etching process that forms these islands (mesas) is sometimes referred to as mesa etching. In the light-emitting chip 10, these islands and the wiring such as the power line 71, the first transfer signal line 72, the second transfer signal line 73, and the lighting signal line 75 are connected via through-holes (indicated by circles in Figure 3(a)) provided in the protective layer (protective layer 90 in Figure 4, which will be described later). The explanation of the protective layer and through-holes will be omitted in the following description.

[0033] Furthermore, as shown in Figure 3(b), a back electrode 91, which serves as a Vsub terminal, is provided on the back surface of the substrate 80.

[0034] Here, the notations p-anode (DBR) layer 81 and n-cathode (DBR) layer 83 correspond to their functions when forming a VCSEL and lower diode UD. That is, the p-anode (DBR) layer 81 functions as the anode, and the n-cathode (DBR) layer 83 functions as the cathode. Furthermore, the notations p-anode layer 85, n-gate layer 86, p-gate layer 87, and n-cathode layer 88 correspond to their functions when forming the setting thyristor S and transfer thyristor T. That is, p-anode layer 85 functions as an anode, n-gate layer 86 and p-gate layer 87 function as gates, and n-cathode layer 88 functions as a cathode. Furthermore, when each of the above layers constitutes a coupling diode D and a power line resistor Rg, they have different functions, as will be described later.

[0035] As will be explained below, the multiple islands of the light-emitting chip 10 include those that lack a portion of the following layers: p-anode (DBR) layer 81, light-emitting layer 82, n-cathode (DBR) layer 83, tunnel junction layer 84, p-anode layer 85, n-gate layer 86, p-gate layer 87, and n-cathode layer 88. For example, islands 301 and 302, described later, lack a portion of the n-cathode layer 88.

[0036] Next, an example of a planar layout of the light-emitting chip 10 will be explained using Figure 3(a). Island 301 is provided with VCSEL1 and setting thyristor S1. Island 302 is provided with lower diode UD1, transfer thyristor T1, and coupling diode D1. Island 303 is provided with power line resistor Rg1. Island 304 is provided with start diode SD. Island 305 is provided with current limiting resistor R1, and island 306 is provided with current limiting resistor R2. Furthermore, multiple islands similar to islands 301, 302, and 303 are formed in parallel on the light-emitting chip 10. These islands are equipped with VCSEL2 to VCSEL6, setting thyristors S2 to S6, lower diodes UD2 to UD6, transfer thyristors T2 to T6, coupling diodes D2 to D5, etc., in the same way as islands 301, 302, and 303.

[0037] Here, we will explain Islands 301 to 306 in detail using Figures 3(a) and 3(b). As shown in Figure 3(b), the VCSEL1 provided on the island 301 consists of a p-anode (DBR) layer 81, an emissive layer 82, and an n-cathode (DBR) layer 83. The setting thyristor S consists of a p-anode layer 85, an n-gate layer 86, a p-gate layer 87, and an n-cathode layer 88, which are stacked via a tunnel junction layer 84 stacked on the n-cathode (DBR) layer 83 of the VCSEL1.

[0038] The n-cathode (DBR) layer 83 of the VCSEL includes a current-constricting layer (current-constricting layer 83a in Figure 4, described later) that narrows the current, as shown in black in Figure 3(b). The current-constricting layer is a current-blocking region β where current is difficult to flow, as a portion of the semiconductor layer constituting the n-cathode (DBR) layer exposed by mesa etching is oxidized from the outer edge. On the other hand, the central portion where a portion of the semiconductor layer constituting the n-cathode (DBR) layer is not oxidized is a current-passing region α where current flows easily. As shown in VCSEL1 in Figure 3(a), the area inside the dashed line is the current-passing region α, and the area outside the dashed line is the current-blocking region β. Note that the current-blocking region β does not need to completely block the flow of current; it is sufficient that the current can be concentrated in the current-passing region α. ​​In other words, the current-blocking region β only needs to be less permeable to current than the current-passing region α. By providing the current-blocking section β, the power consumed for non-luminescent recombination is suppressed. The current-blocking section β also contributes to lower power consumption and improved light extraction efficiency. Light extraction efficiency refers to the amount of light that can be extracted per unit of power.

[0039] In the configured thyristor S1, the n-type ohmic electrode 321 (n-ohmic electrode 321) provided on region 311 of the n-cathode layer 88 is used as the cathode terminal. In addition, the p-type ohmic electrode 331 (p-ohmic electrode 331) provided on the p-gate layer 87 exposed by removing the n-cathode layer 88 is used as the gate Gs1 terminal.

[0040] The lower diode UD1 located on island 302 is composed of a p-anode (DBR) layer 81, an emitting layer 82, and an n-cathode (DBR) layer 83, similar to a VCSEL. The transfer thyristor T1 is composed of a p-anode layer 85, an n-gate layer 86, a p-gate layer 87, and an n-cathode layer 88, which are stacked via a tunnel junction layer 84 stacked on the n-cathode (DBR) layer 83 of the lower diode UD1, similar to a setting thyristor S1. Then, the n-ohmic electrode 323 provided on region 313 of the n-cathode layer 88 is used as the cathode terminal. Furthermore, the p-ohmic electrode 332 provided on the p-gate layer 87 exposed by removing the n-cathode layer 88 is used as the terminal of the gate Gt1. Similarly, the coupled diode D1 provided on island 302 is composed of a p-gate layer 87 and an n-cathode layer 88. The n-ohmic electrode 324 provided on region 314 of the n-cathode layer 88 serves as the cathode terminal. Furthermore, the p-ohmic electrode 332 provided on the p-gate layer 87, which is exposed after removing the n-cathode layer 88, serves as the anode terminal. In this case, the anode terminal of the coupled diode D is the same as that of the gate Gt1.

[0041] The power line resistor Rg1 provided on island 303 is composed of a p-gate layer 87. In other words, the power line resistor Rg1 is provided with the p-gate layer 87 between the p-ohmic electrode 333 and the p-ohmic electrode 334, which is located on the p-gate layer 87 that is exposed after removing the n-cathode layer 88, as the resistor.

[0042] The start diode SD provided on island 304 is composed of a p-gate layer 87 and an n-cathode layer 88. In other words, the start diode SD uses an n-ohmic electrode 325 provided on region 315 of the n-cathode layer 88 as its cathode terminal. Furthermore, the p-ohmic electrode 335 provided on the p-gate layer 87, which is exposed after removing the n-cathode layer 88, serves as the anode terminal. The current limiting resistors R1 on island 305 and R2 on island 306 are provided in the same way as the power line resistor Rg1 on island 303, and each of them makes the p-gate layer 87 between the two p-ohmic electrodes (unsigned) a resistor.

[0043] Next, the connection relationships between each element will be explained in Figure 3(a). The illumination signal line 75 comprises a main branch 75a and several branch sections 75b. The main branch 75a is provided to extend in the direction of the row of setting thyristors S / VCSEL. The branch sections 75b branch off from the main branch 75a and are connected to the n-ohmic electrodes 321, which are the cathode terminals of the setting thyristor S1 provided on the island 301. The same applies to the cathode terminals of the other setting thyristors S. The illumination signal line 75 is connected to the φI terminal provided on the setting thyristor S1 / VCSEL1 side.

[0044] The first transfer signal line 72 is connected to the n-ohmic electrode 323, which is the cathode terminal of the transfer thyristor T1 located on island 302. The cathode terminals of other odd-numbered transfer thyristors T, located on islands similar to island 302, are also connected to the first transfer signal line 72. The first transfer signal line 72 is connected to the φ1 terminal via a current-limiting resistor R1 located on island 305. On the other hand, the second transfer signal line 73 is connected to the n-ohmic electrode (unsigned), which is the cathode terminal of an even-numbered transfer thyristor T located on an unsigned island. The second transfer signal line 73 is connected to the φ2 terminal via a current-limiting resistor R2 located on island 306.

[0045] Power line 71 is connected to the p-ohmic electrode 334, which is one terminal of power line resistor Rg1 located on island 303. Another terminal of power line resistor Rg is also connected to power line 71. Power line 71 is connected to the Vga terminal.

[0046] Furthermore, the p-ohmic electrode 331 (gate terminal Gs1) of the setting thyristor S1 located on island 301 is connected to the p-ohmic electrode 332 (gate terminal Gt1) of island 302 by a connection wire 76.

[0047] Then, the p-ohmic electrode 332 (gate terminal Gt1) is connected to the p-ohmic electrode 333 of the island 303 (the other terminal of the power line resistor Rg1) by a connection wire 77. The n-ohmic electrode 324 (cathode terminal of coupling diode D1) located on island 302 is connected by a connection wire 79 to the p-type ohmic electrode (unsigned), which is the gate terminal Gt2 of the adjacent transfer thyristor T2. The same applies to other VCSELs, setting thyristors S, transfer thyristors T, coupling diodes D, etc., although the explanation will be omitted here.

[0048] The p-ohmic electrode 332 (gate terminal Gt1) of island 302 is connected to the n-ohmic electrode 325 (cathode terminal of start diode SD) provided on island 304 by a connection wire 78. The p-ohmic electrode 335 (anode terminal of start diode SD) is connected to the second transfer signal line 73. Note that the above connection and configuration are for when a p-type substrate 80 is used; when an n-type substrate is used, the polarity will be reversed. Also, when an i-type substrate is used, a terminal for supplying the reference potential Vsub is provided on the side of the substrate where the light-emitting section 11 and the transfer section 12 are located. The connection and configuration will then be the same as when using either a p-type substrate or an n-type substrate.

[0049] (Stacked structure of VCSEL and setting thyristor S) Figure 4 is an example of an enlarged cross-sectional view of an island in which VCSELs and setting thyristors S are stacked. Figure 4 corresponds to a view of the cross-section of the island in which VCSELs and setting thyristors S are stacked, viewed from the -y direction. Figure 4 also shows island 301, in which VCSEL1 and setting thyristor S1 are stacked, and island (unsigned), in which VCSEL2 and setting thyristor S2 are stacked. In Figure 4, VCSEL1 and VCSEL2 are not distinguished and are simply referred to as VCSELs. Similarly, setting thyristors S1 and S2 are not distinguished and are simply referred to as setting thyristors S. As mentioned above, the setting thyristor S is stacked on the VCSEL via a tunnel junction layer 84. In other words, the VCSEL and the setting thyristor S are connected in series. Furthermore, "on the VCSEL" does not only refer to a state where the VCSEL is in direct contact with it, but also includes a state where it is located above it without direct contact. The same applies to similar expressions such as "on the substrate."

[0050] As shown in Figure 4, the VCSEL is composed of a semiconductor stack on a p-type substrate 80, in which a p-anode (DBR) layer 81, an emissive layer 82, and an n-cathode (DBR) layer 83 are epitaxially grown in that order. The p-anode (DBR) layer 81 and the n-cathode (DBR) layer 83 are DBR layers in which multiple layers of relatively high refractive index layers and relatively low refractive index layers are alternately stacked. The p-anode (DBR) layer 81 and the n-cathode (DBR) layer 83 are configured to reflect the light emitted by the VCSEL. The p-anode (DBR) layer 81 and the n-cathode (DBR) layer 83 will be described in more detail later.

[0051] Furthermore, the n-cathode (DBR) layer 83 is composed of a current-constricting layer 83a. In this example, the current-constricting layer 83a is provided on the side of the n-cathode (DBR) layer 83 facing the light-emitting layer 82. The current-constricting layer 83a is composed of a current-passing portion α and a current-blocking portion β. As shown in Figure 4, the current-passing portion α is provided in the central part of the VCSEL, and the current-blocking portion β is provided in the peripheral part of the VCSEL. In other words, the portion of the current-constricting layer 83a is the current-blocking portion β, and the portion where the current-constricting layer 83a is not provided is the current-passing portion α. The current constriction layer may also be provided in the p-anode (DBR) layer 81.

[0052] The light-emitting layer 82 is a quantum well structure in which well layers and barrier layers are alternately stacked. The light-emitting layer 82 may also be an intrinsic (i) type layer (i layer) without added impurities. Furthermore, the light-emitting layer 82 may be a structure other than a quantum well, for example, a quantum beam (quantum wire) or a quantum box (quantum dot).

[0053] The tunnel junction layer 84 is made of n-type impurities (dopants) added at a high concentration. ++ The layer and p with a high concentration of p-type impurities added. ++ It is a junction with a layer, and even with a reverse bias, current flows due to the tunnel effect. The tunnel junction layer 84 suppresses the current flow that would otherwise be hindered by a reverse bias between the n-cathode (DBR) layer 83 of the VCSEL and the setting thyristor S. Even with a reverse bias, current flows due to the tunnel effect.

[0054] The configured thyristor S consists of a p-anode layer 85, an n-gate layer 86, a p-gate layer 87, and an n-cathode layer 88, which are stacked on top of the tunnel junction layer 84. In other words, it has a four-layer pnpn structure.

[0055] These semiconductor layers are stacked using methods such as metal-organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE) to form a semiconductor stack. The configurations of the substrate 80, the p-anode (DBR) layer 81, light-emitting layer 82, n-cathode (DBR) layer 83 that constitute the VCSEL, and the p-anode layer 85, n-gate layer 86, p-gate layer 87, and n-cathode layer 88 that constitute the setting thyristor S will be explained in more detail later.

[0056] The n-ohmic electrode 321 is, for example, Au (AuGe) containing Ge, which readily forms ohmic contact with n-type semiconductor layers such as the n-cathode layer 88. The p-ohmic electrode 331 (see Figure 3(b)) is, for example, Au (AuZn) containing Zn, which is easily able to form ohmic contacts with p-type semiconductor layers such as the p-gate layer 87. The back electrode 91 is made of, for example, AuZn, similar to the p-ohmic electrode 331.

[0057] In the above example, an ohmic electrode 331 was provided in the p-gate layer 87 to form the gate Gs of the set thyristor S, but an n-ohmic electrode may also be provided in the n-gate layer 86 to form the gate Gs of the set thyristor S.

[0058] Furthermore, the light-emitting chip 10 is provided with a protective layer 90 made of a translucent insulating material that covers the surface and sides of the island. The protective layer 90 is made of, for example, SiO2, SiN, or SiN. Furthermore, the light-emitting chip 10 is provided with a light-shielding layer 95 to suppress light emitted from the setting thyristor S from leaking out between the islands onto the surface of the light-emitting chip 10. The light-shielding layer 95 may be the wiring described above.

[0059] (Relationship between adjacent thyristors S and between VCSELs) As described above, in the light-emitting chip 10 of this embodiment, each island is formed by removing a portion of the semiconductor layers stacked on the substrate 80 in the thickness direction by mesa etching. For example, in the island (island 301) where the VCSEL and the setting thyristor S are stacked, the n-cathode layer 88, p-gate layer 87, n-gate layer 86, p-anode layer 85, tunnel junction layer 84, n-cathode (DBR) layer 83, and light-emitting layer 82 are removed from the top of the semiconductor layers stacked on the substrate 80, and a portion of the p-anode (DBR) layer 81 is also removed. As a result, each setting thyristor S is composed of a p-anode layer 85, an n-gate layer 86, a p-gate layer 87, and an n-cathode layer 88 that are separated from adjacent setting thyristors S. In other words, the p-anode layer 85, n-gate layer 86, p-gate layer 87, and n-cathode layer 88 that make up each setting thyristor S are not continuous with adjacent setting thyristors S.

[0060] On the other hand, in this embodiment, at least a portion of the semiconductor layer constituting a VCSEL (e.g., VCSEL1) corresponding to one thyristor S (e.g., thyristor S1) among the plurality of thyristors S is continuous with the semiconductor layer constituting a VCSEL (e.g., VCSEL2) corresponding to an adjacent thyristor S (e.g., thyristor S2). The semiconductor layer constituting the VCSEL corresponding to one thyristor S is an example of the first region, and the semiconductor layer constituting the VCSEL corresponding to the other thyristor S is an example of the second region. Specifically, in this embodiment, a portion of the lowest layer, the p-anode (DBR) layer 81, is continuous between adjacent VCSELs. However, in VCSELs, the light-emitting layer 82 and the n-cathode (DBR) layer 83, which are stacked on the p-anode (DBR) layer 81, are not continuous between adjacent VCSELs. Furthermore, the VCSEL of this embodiment includes a p-anode (DBR) layer 81, which is an example of a lower semiconductor layer that is stacked on the substrate 80 and continuous across adjacent VCSEL1 and VCSEL2. In addition, the VCSEL of this embodiment includes an n-cathode (DBR) layer 83, which is an example of an upper semiconductor layer that is separated between adjacent VCSEL1 and VCSEL2.

[0061] (Thyristor) Next, we will explain the basic operation of thyristors (transfer thyristor T, setting thyristor S). As mentioned above, a thyristor is a semiconductor element having three terminals: an anode terminal (anode), a cathode terminal (cathode), and a gate terminal (gate). For example, it is constructed by stacking p-type semiconductor layers (p-anode layer 85, p-gate layer 87) and n-type semiconductor layers (n-gate layer 86, n-cathode layer 88) made of GaAs, AlGaAs, AlAs, etc., on a substrate 80. In other words, a thyristor has a pnpn structure. Here, we will explain using 1.5V as an example of the forward potential (diffusion potential) Vd of the pn junction composed of a p-type semiconductor layer and an n-type semiconductor layer.

[0062] In the following explanation, as an example, the reference potential Vsub supplied to the back electrode 91, which is the Vsub terminal (see Figures 3(b) and 4), will be described as a high-level potential (hereinafter referred to as "H") at 0V, and the power supply potential Vga supplied to the Vga terminal will be described as a low-level potential (hereinafter referred to as "L") at -5V. Therefore, they may be written as "H" (0V) and "L" (-5V).

[0063] First, let's explain the operation of a thyristor alone. Here, we assume that the anode of the thyristor is 0V. A thyristor in the off state, where no current flows between the anode and cathode, will turn on when a potential lower than the threshold voltage (a negative potential with a large absolute value) is applied to the cathode. Here, the threshold voltage of the thyristor is the gate potential minus the forward potential Vd (1.5V) of the pn junction. When the thyristor is turned on, its gate potential is close to the potential of the anode terminal. Here, since the anode is 0V, the gate is assumed to be 0V. Also, the cathode of the turned-on thyristor is close to the potential obtained by subtracting the forward potential Vd (1.5V) of the pn junction from the potential of the anode. Here, since the anode is 0V, the cathode of the turned-on thyristor is close to -1.5V (a negative potential with an absolute value greater than 1.5V). Note that the cathode potential is set in relation to the power supply that provides current to the turned-on thyristor.

[0064] A thyristor in the ON state will switch to the OFF state (turn off) when the cathode reaches a potential higher than the potential required to maintain the ON state (a potential close to -1.5V as mentioned above) (a negative potential with a small absolute value, 0V or a positive potential). On the other hand, if a potential lower than the potential required to maintain the ON state (a negative potential with a large absolute value) is continuously applied to the cathode of an ON-state thyristor, and a current capable of maintaining the ON state (maintenance current) is supplied, the thyristor will remain ON.

[0065] Next, we will explain the operation when the VCSEL and the setting thyristor S are stacked together. The setting thyristor S is stacked with the VCSEL and connected in series. Therefore, the potential of the illumination signal φI is divided between the VCSEL and the setting thyristor S. Here, we will assume that the voltage applied to the VCSEL is -1.7V. Then, when the setting thyristor S is in the off state, -3.3V is applied to the setting thyristor S. As described above, if the threshold voltage of the off-state setting thyristor S is greater than -3.3V in absolute value, the potential applied to the cathode of the setting thyristor S is lower than the threshold voltage, causing the setting thyristor S to turn on. Then, current flows between the series-connected VCSEL and the setting thyristor S, and the VCSEL lights up. On the other hand, if the threshold voltage of the setting thyristor S is less than -3.3V in absolute value, the setting thyristor S does not turn on and remains in the off state. When the setting thyristor S turns on, the voltage applied to the series-connected VCSEL and setting thyristor S decreases in absolute value due to the current limiting resistor RI (see Figure 2). However, if the voltage applied to the setting thyristor S is sufficient to maintain the setting thyristor S in the ON state, the setting thyristor S remains ON. As a result, the VCSEL also continues to emit light.

[0066] Note that the voltage shown above is just an example and will need to be changed depending on the emission wavelength and light intensity of the VCSEL. In that case, you should adjust the potential ("L") of the ignition signal φI.

[0067] (Operation of light source device 1) Next, we will explain the operation of the light source device 1. <Timing Chart> Figure 5 is a timing chart illustrating an example of the operation of the light source device 1 and the light-emitting chip 10. Figure 5 is a timing chart for the part that controls the illumination (light emission) / de-illumination (non-illumination) of the four VCSELs, VCSEL1 to VCSEL4, of the light-emitting chip 10. In Figure 5, VCSEL1, VCSEL2, and VCSEL3 are illuminated, while VCSEL4 is de-illuminated.

[0068] In Figure 5, assume that time progresses alphabetically from time a to time k. VCSEL1 is controlled to be lit or not lit (referred to as lit control) during period T(1), VCSEL2 during period T(2), VCSEL3 during period T(3), and VCSEL4 during period T(4). Here, periods T(1), T(2), T(3), ... are assumed to be periods of the same length, and when they are not distinguished, they are simply referred to as period T.

[0069] The first transfer signal φ1 transmitted to terminal φ1 (see Figures 2 and 3) and the second transfer signal φ2 transmitted to terminal φ2 (see Figures 2 and 3) are signals having two potentials: "H" (0V) and "L" (-5V). The waveforms of the first transfer signal φ1 and the second transfer signal φ2 are repeated in units of two consecutive periods T (for example, period T(1) and period T(2)). In the following, "H" (0V) and "L" (-5V) may be abbreviated as "H" and "L".

[0070] The first transmission signal φ1 transitions from "H" (0V) to "L" (-5V) at the start time b of period T(1), and from "L" to "H" at time f. Then, at the end time i of period T(2), it transitions from "H" to "L". The second transfer signal φ2 is "H" (0V) at the start time b of period T(1), and transitions from "H" (0V) to "L" (-5V) at time e. Then, at the end time i of period T(2), it transitions from "L" to "H". Comparing the first transfer signal φ1 and the second transfer signal φ2, the second transfer signal φ2 corresponds to the first transfer signal φ1 shifted backward by a period T on the time axis. On the other hand, the waveform of the second transfer signal φ2 in period T(1), shown by the dashed line, and the waveform in period T(2) are repeated from period T(3) onward. The reason why the waveform of the second transfer signal φ2 in period T(1) is different from that in period T(3) onward is that period T(1) is the period when the light source device 1 starts operating.

[0071] As described later, the set of transfer signals, consisting of the first transfer signal φ1 and the second transfer signal φ2, propagates the ON state of the transfer thyristor T in numerical order, thereby designating the VCSEL with the same number as the ON transfer thyristor T as the target for ON or OFF (lighting control).

[0072] Next, we will explain the ignition signal φI supplied to the φI terminal (see Figures 2 and 3). The ignition signal φI is a signal that has two potentials: "H" (0V) and "L" (-5V). Here, we will explain the lighting signal φI during the lighting control period T(1) for VCSEL1. The lighting signal φI is "H" (0V) at the start time b of period T(1), and transitions from "H" (0V) to "L" (-5V) at time c. Then, it transitions from "L" to "H" at time d, and remains "H" at time e.

[0073] Referring to Figure 2, the operation of the light source device 1 and the light-emitting chip 10 will be explained according to the timing chart shown in Figure 5. The periods T(1) and T(2) for controlling the illumination of VCSEL1 and VCSEL2 will be explained below.

[0074] (1) Time a At time a, the reference potential supply unit 160 of the control unit 110 of the light source device 1 sets the reference potential Vsub to "H" (0V). The power supply potential supply unit 170 of the control unit 110 sets the power supply potential Vga to "L" (-5V). The transfer signal generation unit 120 of the control unit 110 sets the first transfer signal φ1 and the second transfer signal φ2 to "H" (0V). As a result, the φ1 terminal and φ2 terminal of the light-emitting chip 10 become "H". The potential of the first transfer signal line 72 connected to the φ1 terminal via the current limiting resistor R1 also becomes "H", and the second transfer signal line 73 connected to the φ2 terminal via the current limiting resistor R2 also becomes "H" (see Figure 2).

[0075] Then, the lighting signal generation unit 140 of the control unit 110 sets the lighting signal φI to "H" (0V). As a result, the φI terminal of the light-emitting chip 10 becomes "H" via the current limiting resistor RI, and the lighting signal line 75 connected to the φI terminal also becomes "H" (0V).

[0076] The anode of the setting thyristor S (p-anode layer 85) is connected to the cathode of the VCSEL (n-cathode (DBR) layer 83) via the tunnel junction layer 84, and the anode of the VCSEL (p-anode (DBR) layer 81) is connected to the Vsub terminal set to "H". The anode of the transfer thyristor T (p-anode layer 85) is connected to the cathode of the lower diode UD (n-cathode (DBR) layer 83) via the tunnel junction layer 84, and the anode of the lower diode UD (p-anode (DBR) layer 81) is connected to the Vsub terminal set to "H".

[0077] The cathodes of the odd-numbered transfer thyristors T1, T3, and T5 are connected to the first transfer signal line 72 and are set to "H" (0V). The cathodes of the even-numbered transfer thyristors T2, T4, and T6 are connected to the second transfer signal line 73 and are set to "H". Therefore, both the anode and cathode of the transfer thyristors T are "H", and they are in the off state. Similarly, both the anode and cathode of the lower diode UD are "H", and it is in the off state.

[0078] The cathode terminal of the setting thyristor S is connected to the "H" (0V) illumination signal line 75. Therefore, both the anode and cathode of the setting thyristor S are "H", and it is in the off state. Similarly, both the anode and cathode of the VCSEL are "H", and it is in the off state.

[0079] As mentioned above, gate Gt1 is connected to the cathode of start diode SD. Gate Gt1 is connected to power line 71 at power supply potential Vga ("L" (-5V)) via power line resistor Rg1. The anode terminal of start diode SD is connected to the second transfer signal line 73 and to the "H" (0V) φ2 terminal via current limiting resistor R2. Therefore, start diode SD is forward biased, and the cathode (gate Gt1) of start diode SD is at the anode potential ("H" (0V)) of start diode SD minus the forward potential Vd (1.5V) of the pn junction (-1.5V). Also, when gate Gt1 is at -1.5V, coupling diode D1 is forward biased because its anode (gate Gt1) is at -1.5V and its cathode is connected to power line 71 ("L" (-5V)) via power line resistor Rg2. Therefore, the potential of gate Gt2 is -3V, which is the potential of gate Gt1 (-1.5V) minus the forward potential Vd (1.5V) of the pn junction. Furthermore, coupling diode D2 is forward biased because its anode (gate Gt1) is -3V and its cathode is connected to power line 71 ("L" (-5V)) via power line resistor Rg2. Therefore, the potential of gate Gt3 is -4.5V, which is the potential of gate Gt2 (-3V) minus the forward potential Vd (1.5V) of the pn junction. However, gates Gt with numbers 4 and above are not affected by the fact that the anode of start diode SD is "H" (0V), and the potential of these gates Gt is "L" (-5V), which is the potential of power line 71.

[0080] Since gate Gt is gate Gs, the potential of gate Gs is the same as the potential of gate Gt. Therefore, the threshold voltages for transfer thyristor T and setting thyristor S are the potentials of gate Gt and Gs minus the forward potential Vd (1.5V) of the pn junction. That is, the threshold voltage for transfer thyristor T1 and setting thyristor S1 is -3V, the threshold voltage for transfer thyristor T2 and setting thyristor S2 is -4.5V, the threshold voltage for transfer thyristor T3 and setting thyristor S3 is -6V, and the threshold voltage for transfer thyristor T and setting thyristor S with numbers 4 or higher is -6.5V.

[0081] (2) Time b At time b shown in Figure 5, the first transfer signal φ1 transitions from "H" (0V) to "L" (-5V). As a result, the light source device 1 starts operating. When the first transfer signal φ1 transitions from "H" to "L", the potential of the first transfer signal line 72 transitions from "H" (0V) to "L" (-5V) via the φ1 terminal and the current limiting resistor R1. As a result, the voltage applied to the transfer thyristor T1 is -3.3V, and the transfer thyristor T1, which has a threshold voltage of -3V, turns on. At this time, current flows through the lower diode UD1, causing it to transition from the off state to the on state. With the transfer thyristor T1 turning on, the potential of the first transfer signal line 72 becomes close to -3.2V (a negative potential with an absolute value greater than 3.2V), which is the anode potential of the transfer thyristor T1 (the potential applied to the lower diode UD1, which is -1.7V) minus the forward potential Vd (1.5V) of the pn junction. Note that the threshold voltage for transfer thyristor T3 is -6V, and the threshold voltage for transfer thyristor T5 is -6.5V. The voltage applied to transfer thyristors T3 and T5 is -1.5V, which is the sum of the voltage applied to the VCSEL (1.7V) and -3.2V. Therefore, transfer thyristors T3 and T5 do not turn on. On the other hand, even-numbered transfer thyristors T cannot be turned on because the second transfer signal φ2 is "H" (0V) and the second transfer signal line 73 is "H" (0V).

[0082] When the transfer thyristor T1 turns on, the potential of gate Gt1 / Gs1 becomes "H" (0V), which is the potential of the anode of the transfer thyristor T1. Then, the potential of gate Gt2 (gate Gs2) becomes -1.5V, the potential of gate Gt3 (gate Gs3) becomes -3V, the potential of gate Gt4 (gate Gs4) becomes -4.5V, and the potential of gates Gt (gate Gl) numbered 5 or higher becomes "L". As a result, the threshold voltage for setting thyristor S1 becomes -1.5V, the threshold voltage for transfer thyristor T2 and setting thyristor S2 becomes -3V, the threshold voltage for transfer thyristor T3 and setting thyristor S3 becomes -4.5V, the threshold voltage for transfer thyristor T4 and setting thyristor S4 becomes -6V, and the threshold voltage for transfer thyristors T5, T6 and setting thyristors S5 and S6 becomes -6.5V. However, the first transfer signal line 72 is -1.5V due to the ON transfer thyristor T1, so the OFF odd-numbered transfer thyristors T do not turn on. The second transfer signal line 73 is "H" (0V), so the even-numbered transfer thyristors T do not turn on. The illumination signal line 75 is "H" (0V), so none of the VCSELs light up.

[0083] Immediately after time b (here, this refers to the time when a steady state is reached after changes in thyristors, etc., have occurred due to the change in signal potential at time b), the transfer thyristor T1 and lower diode UD1 are in the ON state, while the other transfer thyristor T, lower diode UD, setting thyristor S, and VCSEL are in the OFF state.

[0084] (3) Time c At time c, the lighting signal φI transitions from "H" (0V) to "L" (-5V). When the illumination signal φI transitions from "H" to "L", the illumination signal line 75 transitions from "H" (0V) to "L" (-5V) via the current limiting resistor RI and the φI terminal. As a result, -3.3V, which is the voltage applied to the VCSEL plus 1.7V, is applied to the setting thyristor S1. The setting thyristor S1, which has a threshold voltage of -1.5V, turns on, and the VCSEL1 lights up (illuminates). This brings the potential of the illumination signal line 75 to a potential close to -3.2V. Note that the setting thyristor S2 has a threshold voltage of -3V, but the voltage applied to the setting thyristor S2 is -1.5V, which is the voltage applied to the VCSEL plus -3.2V, so the setting thyristor S2 does not turn on. Immediately after time c, the transfer thyristor T1, lower diode UD1, and setting thyristor S1 are in the ON state, and VCSEL1 is lit (emitting light).

[0085] (4) Time d At time d, the lighting signal φI transitions from "L" (-5V) to "H" (0V). When the illumination signal φI transitions from "L" to "H", the potential of the illumination signal line 75 transitions from -3.2V to "H" (0V) via the current limiting resistor RI and the φI terminal. As a result, both the cathode of the setting thyristor S1 and the anode of VCSEL1 become "H", causing the setting thyristor S1 to turn off and VCSEL1 to turn off (become unlit). The illumination period for VCSEL1 is the period from time c when the illumination signal φI transitions from "H" to "L" to time d when the illumination signal φI transitions from "L" to "H", during which the illumination signal φI is "L". Immediately after time d, the transfer thyristor T1 is in the ON state.

[0086] (5) Time e At time e, the second transfer signal φ2 transitions from "H" (0V) to "L" (-5V). At this point, the period T(1) for controlling the illumination of VCSEL1 ends, and the period T(2) for controlling the illumination of VCSEL2 begins. When the second transfer signal φ2 transitions from "H" to "L", the potential of the second transfer signal line 73 transitions from "H" to "L" via the φ2 terminal. As mentioned above, the transfer thyristor T2 turns on because the threshold voltage is -3V. At this time, current flows through the lower diode UD2, causing it to transition from the off state to the on state. As a result, the potential of gate terminal Gt2 (gate terminal Gs2) becomes "H" (0V), the potential of gate Gt3 (gate Gs3) becomes -1.5V, the potential of gate Gt4 (gate Gs4) becomes -3V, the potential of gate Gt5 (gate Gs5) becomes -4.5V, and the potential of gate Gt6 (gate Gs6) becomes -5V. Immediately after time e, the transfer thyristors T1 and T2, and the lower diodes UD1 and UD2 are in the ON state.

[0087] (6) Time f At time f, the first transfer signal φ1 transitions from "L" (-5V) to "H" (0V). When the first transfer signal φ1 transitions from "L" to "H", the potential of the first transfer signal line 72 transitions from "L" to "H" via the φ1 terminal. As a result, the ON transfer thyristor T1 turns off, with both its anode and cathode becoming "H". At this time, both the anode and cathode of the lower diode UD1 also become "H", transitioning from the ON state to the OFF state. As a result, the potential of gate Gt1 (gate Gs1) changes toward the power supply potential Vga ("L" (-5V)) of power supply line 71 via the power supply line resistor Rg1. This causes the coupling diode D1 to be in a state where a potential is applied in the direction in which no current flows (reverse bias). Therefore, the effect of gate Gt2 (gate Gs2) being "H" (0V) does not affect gate Gt1 (gate Gs1). In other words, the transfer thyristor T with gate Gt connected by a reverse-biased coupling diode D will not turn on even when the threshold voltage becomes -6.5V and the first transfer signal φ1 or the second transfer signal φ2 becomes "L" (-5V). Immediately after time f, the transfer thyristor T2 and the lower diode UD2 are in the ON state.

[0088] (7) Others At time g, when the illumination signal φI changes from "H" (0V) to "L" (-5V), the setting thyristor S2 turns on, and VCSEL2 lights up (emits light), similar to VCSEL1 and setting thyristor S1 at time c. Then, at time h, when the illumination signal φI changes from "L" (-5V) to "H" (0V), the setting thyristor S2 turns off, and VCSEL2 turns off, just like VCSEL1 and setting thyristor S1 at time d. Furthermore, at time i, when the first transfer signal φ1 transitions from "H" (0V) to "L" (-5V), the transfer thyristor T3 with a threshold voltage of -3V turns on, similar to the transfer thyristor T1 at time b or the transfer thyristor T2 at time e. At time i, the period T(2) for controlling the illumination of VCSEL2 ends, and the period T(3) for controlling the illumination of VCSEL3 begins. From here on, it will be a repetition of what has been explained so far.

[0089] Furthermore, if you want to keep the VCSEL off (not lit) instead of turning it on (emitting light), you can keep the lighting signal φI at "H" (0V), as shown in the lighting signal φI from time j to time k during the period T(4) in Figure 5 where the VCSEL4 is controlled to light up. In this way, even if the threshold voltage of the setting thyristor S4 is -1.5V, the setting thyristor S4 will not turn on, and the VCSEL will remain off (not lit).

[0090] As explained above, the gate terminals Gt of the transfer thyristor T are interconnected by coupling diodes D. Therefore, when the potential of gate Gt changes, the potential of gate Gs, which is connected to the gate Gt with the changed potential via the forward-biased coupling diode D, also changes. Consequently, the threshold voltage of the transfer thyristor T with the gate whose potential has changed changes. The transfer thyristor T turns on when the threshold voltage is higher than -3.3V (a negative value with a small absolute value) at the timing when the first transfer signal φ1 or the second transfer signal φ2 transitions from "H" (0V) to "L" (-5V). Then, the setting thyristor S, whose gate Gs is connected to the gate Gt of the ON transfer thyristor T, has a threshold voltage of -1.5V. Therefore, when the lighting signal φI changes from "H" (0V) to "L" (-5V), it turns on, and the VCSEL connected in series with the setting thyristor S lights up (emits light).

[0091] In other words, when the transfer thyristor T turns on, it specifies the VCSEL to be controlled, and the "L" (-5V) lighting signal φI turns on the setting thyristor S connected in series with the VCSEL to be controlled, and lights up the VCSEL. In short, in the light-emitting chip 10, the ON state of the transfer thyristor T is transferred, causing the VCSELs to light up sequentially. The "H" (0V) illumination signal φI keeps the setting thyristor S in the off state and keeps the VCSEL off. In other words, the illumination signal φI sets whether the VCSEL is on or off.

[0092] As described above, the light source device 1 of this embodiment has multiple elements (transfer thyristors T1-T6, setting thyristors S1-S6, VCSEL1-VCSEL6, etc.), and the elements that turn on are successively switched to the ON state. As a result, in the light source device 1 of this embodiment, the multiple transfer thyristors T1-T6 in the transfer unit 12 of the light-emitting chip 10 are individually turned on by the lighting control by the control unit 110. When the transfer thyristors T1-T6 turn on, the VCSEL that is the target of the lighting control is specified, and the multiple setting thyristors S1-S6 in the light-emitting unit 11 are individually turned on. When each setting thyristor S turns on, the VCSEL corresponding to that setting thyristor S lights up individually. In addition, in the light source device 1 of this embodiment, the control unit 110 and the transfer unit 12 of the light-emitting chip 10 are examples of drive units that individually drive the multiple setting thyristors S and switch them to the ON state. Furthermore, in the light-emitting chip 10 of this embodiment, the portion of the light-emitting layer 82 that each VCSEL has that actually emits light when current is supplied is the light-emitting region of each VCSEL.

[0093] As described above, in the light-emitting chip 10 of this embodiment, when the setting thyristor S is turned on, it becomes possible to supply current to the corresponding VCSEL. Then, when a current of the magnitude necessary for the VCSEL to emit light is actually supplied to the VCSEL, the VCSEL emits light. Incidentally, depending on the configuration of the light-emitting chip 10 and the control by the control unit 110, after the setting thyristor S turns on and becomes capable of supplying current to the corresponding VCSEL, the ON signal to the setting thyristor S may be stopped while the VCSEL remains capable of emitting light by supplying current before the VCSEL actually emits light. Even in such a case, after the setting thyristor S turns off, the VCSEL can be made to emit light by supplying the VCSEL with a current of the magnitude necessary for the VCSEL to emit light. Furthermore, in this case, the setting thyristor S turns on in order to make the VCSEL emit light, but is in the OFF state at the time the VCSEL actually emits light. In this embodiment, "the thyristor (setting thyristor S) turns on, causing the light-emitting element (VCSEL) to emit light" means that when the setting thyristor S turns on, it puts the corresponding VCSEL into a state where it can emit light when current is supplied. In addition, after the setting thyristor S has put the VCSEL into a state where it can emit light when current is supplied, it may remain in the ON state or be in the OFF state when current is supplied to the VCSEL and the VCSEL is actually emitting light.

[0094] (Regarding the light emitted from the setting thyristor S) Incidentally, since the setting thyristor S is made of a compound semiconductor as described above, when it is turned on, it may emit light from between the n-gate layer 86 and the p-gate layer 87. Furthermore, when the current flowing between the p-anode layer 85 and the n-cathode layer 88 of the setting thyristor S becomes large, it may emit light from between the n-gate layer 86 and the p-gate layer 87.

[0095] Consider a case where a light source device 1 (light-emitting chip 10) has multiple VCSELs and setting thyristors S formed on the same substrate 80, and the lighting control of the VCSELs is performed so that one VCSEL (e.g., VCSEL1) selected from the multiple VCSELs is lit, and the other VCSELs (e.g., VCSEL2 to VCSEL6) are not lit. In this case, the control unit 110 turns on the setting thyristor S1 connected to the VCSEL1 to be lit, and as a result, VCSEL1 lights up. On the other hand, when the setting thyristor S1 is turned on, the other setting thyristors S2 to S6 connected to the other VCSEL2 to VCSEL6 that are not to be lit remain in the off state.

[0096] When the setting thyristor S1 is turned on, light may be emitted from the setting thyristor S1 due to the current supplied to it. Figure 6 illustrates an example of the behavior of light emitted from the setting thyristor S when the substrate 80 does not absorb the light emitted from the setting thyristor S. Similar to Figure 4 described above, Figure 6 shows island 301 in which VCSEL1 and setting thyristor S1 are stacked, and island (unsigned) in which VCSEL2 and setting thyristor S2 are stacked. Light emitted from the setting thyristor S1 propagates through the semiconductor layers that make up the setting thyristor S1 and VCSEL1. If the substrate 80 does not absorb the light emitted from the setting thyristor S, the light emitted from the setting thyristor S may reach other setting thyristors S adjacent to setting thyristor S1 (for example, setting thyristor S2) without changing its wavelength, as shown by arrow X in Figure 6. In particular, as mentioned above, if a part of the semiconductor layer that makes up the VCSEL is continuous between adjacent VCSELs, the light emitted from the setting thyristor S1 is likely to propagate to the adjacent setting thyristor S2 through this semiconductor layer.

[0097] As described above, in this example, the setting thyristor S2 is in the off state in order to keep the VCSEL2 corresponding to it from lighting up. However, when the light emitted from the setting thyristor S1 propagates directly to the setting thyristor S2 and is absorbed by the gate layer (n-gate layer 86, p-gate layer 87) of the setting thyristor S2, generating an electromotive force, the setting thyristor S2 turns on. As a result of the setting thyristor S2 turning on, the VCSEL2, which should normally be in the off state, begins to emit light. In this way, when light emitted from one setting thyristor S is absorbed by another setting thyristor S, a non-lit VCSEL among the multiple VCSELs that is not subject to lighting control may be mistakenly lit. In this case, it becomes difficult to accurately control the lighting of multiple VCSELs in the light source device 1.

[0098] (Details of the semiconductor layers constituting the substrate 80 and the setting thyristor S and VCSEL) The light-emitting chip 10 of this embodiment has a substrate 80 that absorbs light emitted from a set thyristor S and emits light that is not absorbed by the gate layers (n-gate layer 86, p-gate layer 87) of the set thyristor S. Generally, compound semiconductors absorb light with a shorter wavelength (i.e., a larger band gap energy) than the wavelength corresponding to their own band gap energy. When a compound semiconductor absorbs light, it emits light corresponding to its own band gap energy. Therefore, light emitted from the set thyristor S can be absorbed by a semiconductor with a band gap energy smaller than the band gap energy corresponding to the light emitted from the set thyristor S. The substrate 80 of this embodiment is made of a semiconductor with a band gap energy smaller than the band gap energy corresponding to the light emitted from the set thyristor S. The substrate 80 of the light-emitting chip 10 to which this embodiment is applied, and each layer of the semiconductor layer constituting the setting thyristor S and VCSEL will be described in more detail below with reference to Figure 4 and other figures.

[0099] <Layer configuration of thyristor S> As described above, the set thyristor S is composed of a p-anode layer 85, an n-gate layer 86, a p-gate layer 87, and an n-cathode layer 88 stacked on a tunnel junction layer 84. As described above, the p-anode layer 85, n-gate layer 86, p-gate layer 87, and n-cathode layer 88 are composed of III-V compound semiconductors.

[0100] In this embodiment, the n-gate layer 86 and the p-gate layer 87 are preferably composed of a III-V compound semiconductor containing Al. Examples of the Al-containing III-V compound semiconductor constituting the n-gate layer 86 and the p-gate layer 87 include AlGaAs, AlGaN, and AlAs, with AlGaAs being preferred. By using an Al-containing III-V compound semiconductor, such as AlGaAs, as the n-gate layer 86 and p-gate layer 87, the band gap energy corresponding to the light emitted from the n-gate layer 86 and p-gate layer 87 can be increased compared to the case where an Al-free III-V compound semiconductor, such as GaAs, is used as the n-gate layer 86 and p-gate layer 87. This makes it easier for the light emitted from the n-gate layer 86 and p-gate layer 87 to be absorbed by the substrate 80. Furthermore, because the light emitted from the n-gate layer 86 and p-gate layer 87 is absorbed by the substrate 80, the light emitted again from the substrate 80 (re-emission) is less likely to be absorbed by the n-gate layer 86 and p-gate layer 87 of the adjacent setting thyristor S. This suppresses the adjacent setting thyristor S from turning on. As a variation, when the n-gate layer 86 and p-gate layer 87 are made of a semiconductor that does not contain Al, it is preferable to use, for example, GaInAsP.

[0101] Furthermore, in the configured thyristor S of this embodiment, if the n-gate layer 86 and p-gate layer 87 are composed of a III-V compound semiconductor containing Al, it is preferable that the Al content of the n-gate layer 86 and p-gate layer 87 is lower than that of the Al-containing semiconductor layer in a VCSEL. It should be noted that the statement "the n-gate layer 86 and p-gate layer 87 have a lower Al content compared to the Al-containing semiconductor layers in the VCSEL" does not only refer to the case where the Al content is lower than that of all the semiconductor layers constituting the VCSEL. Here, it means that the n-gate layer 86 and p-gate layer 87 have a lower Al content compared to the semiconductor layers that account for more than half of the film thickness of the entire VCSEL. As will be described in detail later, the n-gate layer 86 and p-gate layer 87 in this embodiment have a lower Al content compared to the p-anode (DBR) layer 81 and n-cathode (DBR) layer 83 as Al-containing semiconductor layers in the VCSEL.

[0102] Furthermore, when the n-gate layer 86 and the p-gate layer 87 are composed of a III-V compound semiconductor containing Al, the Al content of the n-gate layer 86 and the p-gate layer 87 is preferably 1% or more, more preferably 7% or more, and even more preferably 10% or more. If the Al content in the n-gate layer 86 and the p-gate layer 87 is less than 1%, the light emitted from between the n-gate layer 86 and the p-gate layer 87 is less likely to be absorbed by the substrate 80, and the light may be more easily propagated to the adjacent setting thyristor S.

[0103] Furthermore, the n-gate layer 86 and the p-gate layer 87 preferably have an Al content of less than 30%, and more preferably less than 20%. The manufacturing process of the light-emitting chip 10 may include steps in which the n-gate layer 86 and p-gate layer 87 are exposed to air. In this case, if the Al content ratio in the n-gate layer 86 and p-gate layer 87 is 30% or more, the surfaces of the n-gate layer 86 and p-gate layer 87 are easily oxidized by the air. In this case, the connection between the n-gate layer 86 and p-gate layer 87 and the electrodes provided on these layers (for example, the connection between the p-gate layer 87 and the p-ohmic electrode 331) may become faulty. Furthermore, generally speaking, among the semiconductor layers constituting the setting thyristor S, the n-gate layer 86 and the p-gate layer 87 have a lower Al content compared to the p-anode layer 85 and the n-cathode layer 88. The driving voltage of the setting thyristor S is determined by the n-gate layer 86 and the p-gate layer 87, which are the semiconductor layers with a low Al content among the semiconductor layers constituting the setting thyristor S. In addition, the driving voltage of the setting thyristor S is lower the lower the Al content in the n-gate layer 86 and the p-gate layer 87, and higher the Al content in the n-gate layer 86 and the p-gate layer 87. Therefore, if the Al content in the n-gate layer 86 and the p-gate layer 87 is 30% or more, the driving voltage of the setting thyristor S becomes too high, which is undesirable.

[0104] The Al content ratio of the n-gate layer 86 and the p-gate layer 87 is preferably determined in relation to the substrate 80 and the p-anode (DBR) layer 81 and n-cathode (DBR) layer 83 of the VCSEL, as will be described later. In this embodiment, the Al content ratio in a III-V compound semiconductor containing Al refers to the ratio of the number of Al atoms to the sum of the number of Group III elements atoms contained in the III-V compound semiconductor. For example, the Al content ratio in AlGaAs refers to the ratio of the number of Al atoms to the sum of the number of Al and Ga atoms contained in AlGaAs.

[0105] For the p-anode layer 85 of the thyristor S configured as described above, for example, an impurity concentration of 1 × 10⁻¹⁶ 18 / cm 3 p-type AlGaAs can be used. The Al content ratio in the p-anode layer 85 may be changed between 0% and 100%. For example, the n-gate layer 86 has an impurity concentration of 1 × 10⁻⁶. 17 / cm 3n-type AlGaAs can be used. The Al content ratio in the n-gate layer 86 may be determined in relation to the substrate 80, the p-anode (DBR) layer 81 of the VCSEL, and the n-cathode (DBR) layer 83, as described later. In this embodiment, as the n-gate layer 86, AlGaAs having a lower Al content ratio than the high refractive index layer of the p-anode (DBR) layer 81 and the high refractive index layer of the n-cathode (DBR) layer 83, which will be described later, can be used. As the p-gate layer 87, for example, an impurity concentration of 1×10 17 / cm 3 p-type AlGaAs can be used. The Al content ratio in the n-gate layer 86 may be determined in relation to the substrate 80, the p-anode (DBR) layer 81 of the VCSEL, and the n-cathode (DBR) layer 83, as described later. In this embodiment, as the p-gate layer 87, AlGaAs having a lower Al content ratio than the high refractive index layer of the p-anode (DBR) layer 81 and the high refractive index layer of the n-cathode (DBR) layer 83, which will be described later, can be used. As the n-cathode layer 88, for example, an impurity concentration of 1×10 18 / cm 3 n-type AlGaAs can be used. The Al content ratio in the p-anode layer 85 may be varied between 0% and 100%.

[0106] <Layer Structure of VCSEL> A VCSEL is constituted by a p-anode (DBR) layer 81, a light-emitting layer 82, and an n-cathode (DBR) layer 83 stacked on a substrate 80. In the light-emitting layer 82 sandwiched between the p-anode (DBR) layer 81 and the n-cathode (DBR) layer 83, the VCSEL resonates light to cause laser oscillation. The VCSEL undergoes laser oscillation when the light reflectance of the p-anode (DBR) layer 81 and the n-cathode (DBR) layer 83 reaches, for example, 99% or higher.

[0107] The VCSEL of the present embodiment preferably transmits light emitted from the setting thyristor S. In this case, when a semiconductor layer absorbs light, it may generate heat. In this embodiment, the VCSEL transmits the light emitted from the set thyristor S, which suppresses the heat generated by the semiconductor layer constituting the VCSEL due to the absorption of light emitted from the set thyristor S, compared to the case where the VCSEL does not transmit the light emitted from the set thyristor S. This suppresses the deterioration of the VCSEL's characteristics due to the rise in the VCSEL's temperature.

[0108] Furthermore, the statement that "the VCSEL transmits light emitted from the setting thyristor S" does not mean that all of the light emitted from the setting thyristor S is transmitted; rather, it is sufficient for at least a portion of the light emitted from the setting thyristor S to be transmitted, and it is preferable that 70% or more of the light emitted from the setting thyristor S is transmitted. Furthermore, the semiconductor layers constituting the VCSEL may include a layer that readily transmits light emitted from the set thyristor S and a layer that does not readily transmit light emitted from the set thyristor S.

[0109] As described above, the VCSEL includes a p-anode (DBR) layer 81, an emissive layer 82, and an n-cathode (DBR) layer 83. In this embodiment, the VCSEL has bandgap energies greater than the bandgap energy of at least the p-anode (DBR) layer 81 and the n-cathode (DBR) layer 83, which corresponds to the bandgap energy of the light emitted from the set thyristor S. In this case, the p-anode (DBR) layer 81 and the n-cathode (DBR) layer 83 do not absorb the light emitted from the set thyristor S by band-edge absorption due to the difference in bandgap energies. The p-anode (DBR) layer 81 and the n-cathode (DBR) layer 83 contain impurities. In compound semiconductors, as the impurity concentration increases, the number of electrons and holes (free carriers) that can move freely within the semiconductor increases, making it easier to absorb light through free carrier absorption. Therefore, the p-anode (DBR) layer 81 and the n-cathode (DBR) layer 83 may absorb light emitted from the set thyristor S due to free carrier absorption by the impurities. However, generally, the amount of light absorbed by free carrier absorption is smaller than that absorbed by band-edge absorption. For this reason, even if light emitted from the set thyristor S is absorbed by free carrier absorption, the amount of light transmitted through the p-anode (DBR) layer 81 and the n-cathode (DBR) layer 83 does not decrease significantly.

[0110] The p-anode (DBR) layer 81 and the n-cathode (DBR) layer 83 are examples of multilayer reflective layers, and as described above, they are DBR layers in which multiple semiconductor layers having a refractive index difference are stacked. In addition, the p-anode (DBR) layer 81 has a structure in which high-refractive-index layers with relatively high refractive indices and low-refractive-index layers with relatively low refractive indices are alternately stacked. Note that "relatively high refractive index" in the high-refractive-index layers means that its refractive index is higher than that of the low-refractive-index layers. Similarly, "relatively low refractive index" in the low-refractive-index layers means that its refractive index is lower than that of the high-refractive-index layers. Furthermore, the n-cathode (DBR) layer 83, like the p-anode (DBR) layer 81, has a structure in which a high refractive index layer with a relatively high refractive index and a low refractive index layer with a relatively low refractive index are alternately stacked.

[0111] In this embodiment, it is preferable that the high refractive index layer and the low refractive index layer of the p-anode (DBR) layer 81 are composed of an Al-containing III-V compound semiconductor doped with p-type impurities. Examples of III-V compound semiconductors that constitute the high refractive index layer and low refractive index layer of the p-anode (DBR) layer 81 include AlGaAs, AlGaN, and AlAs, similar to the n-gate layer 86 and p-gate layer 87 of the setting thyristor S, with AlGaAs being preferred.

[0112] More specifically, the p-anode (DBR) layer 81 preferably includes a high refractive index layer, which is an example of a first semiconductor layer made of AlGaAs, and a low refractive index layer, which is an example of a second semiconductor layer made of AlGaAs with a higher Al content ratio compared to the high refractive index layer. Furthermore, it is preferable that the Al content ratio of the AlGaAs constituting the high refractive index layer in the p-anode (DBR) layer 81 is higher than that of the AlGaAs constituting the n-gate layer 86 and p-gate layer 87 of the set thyristor S.

[0113] In this context, for III-V compound semiconductors containing Al, the higher the Al content, the larger the band gap energy, and the lower the Al content, the smaller the band gap energy. As a result, the bandgap energies of the high-refractive-index and low-refractive-index layers of the p-anode (DBR) layer 81 become larger compared to the bandgap energy corresponding to the light emitted from the set thyristor S. Consequently, the light emitted from the set thyristor S is more easily transmitted through the high-refractive-index and low-refractive-index layers of the p-anode (DBR) layer 81 without being absorbed at the band edge.

[0114] Similarly, the high refractive index layer and the low refractive index layer of the n cathode (DBR) layer 83 are preferably composed of an Al-containing III-V compound semiconductor doped with n-type impurities. Examples of III-V compound semiconductors that constitute the high refractive index layer and low refractive index layer of the n cathode (DBR) layer 83 include AlGaAs, AlGaN, and AlAs, similar to the p anode (DBR) layer 81, with AlGaAs being preferred.

[0115] More specifically, the n-cathode (DBR) layer 83 preferably includes a high refractive index layer, which is another example of a first semiconductor layer made of AlGaAs, and a low refractive index layer, which is another example of a second semiconductor layer made of AlGaAs with a higher Al content ratio compared to the high refractive index layer. Furthermore, it is preferable that the Al content ratio of the AlGaAs constituting the high refractive index layer in the n-cathode (DBR) layer 83 is higher than that of the AlGaAs constituting the n-gate layer 86 and p-gate layer 87 of the set thyristor S. As a result, the band gap energies of the high-refractive-index and low-refractive-index layers of the n-cathode (DBR) layer 83 become larger compared to the band gap energy corresponding to the light emitted from the set thyristor S. Consequently, the light emitted from the set thyristor S is more easily transmitted through the high-refractive-index and low-refractive-index layers of the n-cathode (DBR) layer 83 without being absorbed at the band edge.

[0116] Furthermore, when the high-refractive-index layer and the low-refractive-index layer of the p-anode (DBR) layer 81 and the n-cathode (DBR) layer 83 are made of a III-V compound semiconductor containing Al, it is preferable that the Al content ratio be less than 30%. If the Al content ratio of the high refractive index layer and the low refractive index layer of the p-anode (DBR) layer 81 and the n-cathode (DBR) layer 83 is 30% or more, the reflectivity of the light emitted from the light-emitting layer 82 by the p-anode (DBR) layer 81 and the n-cathode (DBR) layer 83 may decrease.

[0117] The thickness of each high refractive index layer in the p-anode (DBR) layer 81 is (λ / 4n p1 )×0.4 or more (λ / 4n p1 ) is in the range of 1.2 or less, and λ / 4n p1 It is preferable to do so. Here, λ is the wavelength of light emitted from the luminescent layer 82 of the VCSEL, and n p1 This is the refractive index of the high refractive index layer of the p-anode (DBR) layer 81. Similarly, the film thickness of each high refractive index layer in the n cathode (DBR) layer 83 is (λ / 4n n1 )×0.4 or more (λ / 4n n1) is in the range of 1.2 or less, and λ / 4n n1 It is preferable to do so. Here, n n1 This is the refractive index of the high refractive index layer of the n-cathode (DBR) layer 83.

[0118] Furthermore, it is preferable that the thickness of each high refractive index layer of the p-anode (DBR) layer 81 be such that the combined thickness of each high refractive index layer and each low refractive index layer of the p-anode (DBR) layer 81 is λ / 2. Therefore, for example, the thickness of the high refractive index layer of the p-anode (DBR) layer 81 is λ / 4n p1 If it is thinner, the film thickness of the low refractive index layer of the p-anode (DBR) layer 81 is λ / 4n p2 (n p2 This can be made thicker than the refractive index of the low refractive index layer of the p-anode (DBR) layer 81. Similarly, the thickness of each high refractive index layer in the n-cathode (DBR) layer 83 is set such that the combined thickness of each high refractive index layer and each low refractive index layer of the n-cathode (DBR) layer 83 is λ / 2. Therefore, for example, the thickness of the high refractive index layer of the n-cathode (DBR) layer 83 is λ / 4n n1 If it is thinner, the film thickness of the low refractive index layer of the n cathode (DBR) layer 83 is λ / 4n n2 (n n2 The thickness should be greater than the refractive index of the low refractive index layer of the n-cathode (DBR) layer 83.

[0119] In this embodiment of the VCSEL, it is preferable that the n-cathode (DBR) layer 83 has a higher transmittance of light emitted from the set thyristor S compared with the p-anode (DBR) layer 81. In other words, it is preferable that the n-cathode (DBR) layer 83 absorbs less light emitted from the set thyristor S compared with the p-anode (DBR) layer 81. Here, the n-cathode (DBR) layer 83 is further away from the substrate 80 than the p-anode (DBR) layer 81. Therefore, when light emitted from the set thyristor S is absorbed by the n-cathode (DBR) layer 83 and generates heat, the heat generated in the n-cathode (DBR) layer 83 is less likely to be released to the outside through the substrate 80. In this embodiment, the n-cathode (DBR) layer 83 has a higher transmittance of light emitted from the set thyristor S, which suppresses heat generation in the n-cathode (DBR) layer 83 and suppresses the deterioration of the VCSEL's characteristics due to the temperature rise of the VCSEL.

[0120] Furthermore, in the VCSEL of this embodiment, it is preferable that the n-cathode (DBR) layer 83, which has a current-constricting layer 83a, has a higher transmittance of light emitted from the set thyristor S compared to the p-anode (DBR) layer 81, which does not have a current-constricting layer. As described above, the current-constricting layer 83a has a current-blocking section β where current is difficult to flow and a current-passing section α where current is easy to flow. In a VCSEL, the current concentrates in the current-passing section α, so the light-emitting layer 82 emits light near the current-passing section α. In this embodiment, the n-cathode (DBR) layer 83, which is provided with the current-constricting layer 83a, has a higher transmittance of light emitted from the set thyristor S. As a result, the light emitted from the set thyristor S is less likely to be absorbed near the current-passing section α, and the effect on the light-emitting layer 82 due to the heat generated by the absorption of light emitted from the set thyristor S can be reduced.

[0121] Furthermore, in the VCSEL of this embodiment, the transmittance of light emitted from the set thyristor S may differ among the multiple semiconductor layers constituting the p-anode (DBR) layer 81 and the n-cathode (DBR) layer. Specifically, it is preferable that the p-anode (DBR) layer 81 has a higher transmittance of light emitted from the set thyristor S as it is closer to the light-emitting layer 82 (i.e., as it is an upper semiconductor layer in Figure 4). Similarly, it is preferable that the n-cathode (DBR) layer 83 has a higher transmittance of light emitted from the set thyristor S as it is closer to the light-emitting layer 82 (i.e., as it is a lower semiconductor layer in Figure 4). By adopting this configuration, the light emitted from the set thyristor S is less likely to be absorbed by the semiconductor layer close to the light-emitting layer 82, and the effect on the light-emitting layer 82 due to the heat generated by the absorption of light emitted from the set thyristor S can be reduced.

[0122] The p-anode (DBR) layer 81 of the VCSEL described above can be a semiconductor layer in which a low refractive index layer made of AlGaAs doped with p-type impurities and a high refractive index layer made of AlGaAs doped with p-type impurities and having a lower Al content compared to the low refractive index layer are alternately stacked for 40 periods. The Al content in the AlGaAs constituting the low refractive index layer and the Al content in the AlGaAs constituting the high refractive index layer of the p-anode (DBR) layer 81 should be determined so as to satisfy the above conditions. Furthermore, the n-cathode (DBR) layer 83 can be a semiconductor layer in which, for example, a low refractive index layer made of AlGaAs doped with n-type impurities and a high refractive index layer made of AlGaAs doped with n-type impurities and having a lower Al content compared to the low refractive index layer are alternately stacked in 19 periods. Similarly, the Al content in the AlGaAs constituting the low refractive index layer and the Al content in the AlGaAs constituting the high refractive index layer of the n-cathode (DBR) layer 83 should be determined so as to satisfy the above-mentioned conditions.

[0123] Furthermore, the light-emitting layer 82 can be a semiconductor layer in which well layers made of GaN, InGaN, AlGaN, etc., and barrier layers made of AlGaN, GaN, etc., are alternately stacked. Here, the light-emitting layer 82 generally has a smaller bandgap energy compared to the p-anode (DBR) layer 81 and the n-cathode (DBR) layer 83, and light emitted from the set thyristor S may be absorbed by band-edge absorption. In addition, in the well layer and barrier layer of the light-emitting layer 82, light emitted from the set thyristor S may be absorbed by band-edge absorption. However, since the well layer and barrier layer of the light-emitting layer 82 are thinner than the p-anode (DBR) layer 81 and the n-cathode (DBR) layer 83, the amount of light absorbed from the set thyristor S is not large, and the effect of absorbing light emitted from the set thyristor S is unlikely to occur.

[0124] <Configuration of substrate 80> As described above, the substrate 80 in this embodiment is a p-type substrate 80. The substrate 80 can be, for example, a substrate made of a III-V compound semiconductor on which semiconductor layers such as the p-anode (DBR) layer 81, the light-emitting layer 82, and the n-cathode (DBR) layer 83 that constitute the VCSEL can be epitaxially grown. In this embodiment, the substrate 80 is made of a semiconductor having a bandgap energy smaller than the bandgap energy corresponding to the light emitted from the setting thyristor S. More specifically, it is preferable to use a substrate 80 made of a III-V compound semiconductor with a lower Al content ratio compared to the n-gate layer 86 and p-gate layer 87 that constitute the setting thyristor S, and it is even more preferable to use a GaAs substrate that does not contain Al (i.e., has an Al content ratio of 0%). In this embodiment, the configuration using a p-type substrate 80 containing p-type impurities is described, but a substrate 80 containing n-type impurities may also be used, or an intrinsic (i) type substrate 80 without added impurities may be used.

[0125] In a VCSEL, light emitted from the setting thyristor S, transmitted through the p-anode (DBR) layer 81 and the n-cathode (DBR) layer 83, reaches the substrate 80. If the substrate 80 is made of a semiconductor with a bandgap energy smaller than the bandgap energy corresponding to the light emitted from the setting thyristor S, the light emitted from the setting thyristor S is absorbed by the substrate 80, and light corresponding to the bandgap energy of the substrate 80 is emitted from the substrate 80. In addition, the bandgap energy of the light emitted from the substrate 80 (re-emission) is smaller than the bandgap energies of the n-gate layer 86 and p-gate layer 87 of the setting thyristor S. Therefore, in this embodiment, the re-emitting light emitted from the substrate 80 is not absorbed by the n-gate layer 86 and p-gate layer 87 of the thyristor S. This suppresses the activation of adjacent setting thyristors S by re-emitting light from the substrate 80.

[0126] (Behavior of light emitted from setting thyristor S) Next, we will explain the behavior of the light emitted from the configured thyristor S. Figure 7 illustrates an example of the behavior of light emitted from the setting thyristor S in the light-emitting chip 10 to which this embodiment is applied. Similar to Figure 4 described above, Figure 7 shows an island 301 in which VCSEL1 and setting thyristor S1 are stacked, and an island (unsigned) in which VCSEL2 and setting thyristor S2 are stacked. Here, we will explain using an example similar to the one shown in Figure 6, where the setting thyristor S1 is turned on and light is emitted from the setting thyristor S1.

[0127] As described above, in the light-emitting chip 10 of this embodiment, the VCSEL absorbs the light emitted from the setting thyristor S1. To explain in more detail, the light emitted from between the n-gate layer 86 and the p-gate layer 87 of the setting thyristor S1 propagates toward the VCSEL1 located below the setting thyristor S1, as shown by arrow A in Figure 7. The light emitted from the setting thyristor S1 then passes through the n-cathode (DBR) layer 83, p-anode (DBR) layer 81, etc., that make up the VCSEL. As described above, by the light emitted from the setting thyristor S1 passing through the VCSEL, the heat generated by the absorption of the light emitted from the setting thyristor S1 by the VCSEL is suppressed, and the deterioration of the VCSEL's characteristics is suppressed.

[0128] The light emitted from the setting thyristor S1 and transmitted through the VCSEL reaches the substrate 80. As described above, the substrate 80 has a bandgap energy smaller than the bandgap energy corresponding to the light emitted from the setting thyristor S1, such as GaAs. Therefore, the light emitted from the setting thyristor S1 and reaching the substrate 80 is absorbed by the substrate 80. Then, as shown by arrow B in Figure 7, long-wavelength light (re-emission) corresponding to the bandgap energy of the substrate 80 is emitted from the substrate 80. In addition, long-wavelength light (re-emission) corresponding to the bandgap energy of the substrate 80 is emitted from the substrate 80 toward the VCSEL and setting thyristor S stacked on the substrate 80. Since the re-emission emitted from the substrate 80 is smaller than the bandgap energy of the n-gate layer 86 and the p-gate layer 87, even if it reaches the set thyristor S2, it is not absorbed by the set thyristor S2. Therefore, the re-emission emitted from the substrate 80 does not turn on the set thyristor S2.

[0129] As described above, in the light-emitting chip 10 of this embodiment, the substrate 80 absorbs the light emitted from the setting thyristor S and emits light that is not absorbed by the n-gate layer 86 and p-gate layer 87 of the setting thyristor S. As a result, compared to the case where the substrate 80 does not absorb the light emitted from the setting thyristor S, it is possible to suppress the propagation of the light emitted from the setting thyristor S to other setting thyristors S and the transition of other setting thyristors S to the ON state, thereby suppressing the accidental illumination of VCSELs that are not intended to emit light.

[0130] In this embodiment, the example described is when the substrate 80 absorbs the light emitted from the setting thyristor S, which acts as a thyristor. As described above, in the light-emitting chip 10 of this embodiment, the transfer thyristor T also has the same layer configuration as the setting thyristor S, and when the transfer thyristor T is turned on, light may be emitted from between the n-gate layer 86 and the p-gate layer 87 of the transfer thyristor T. In the light-emitting chip 10 of this embodiment, similar to the example described above, the substrate 80 absorbs the light emitted from the transfer thyristor T and emits light that is not absorbed by the n-gate layer 86 and the p-gate layer 87 of the transfer thyristor T. As a result, in the light-emitting chip 10, the propagation of light emitted from the transfer thyristor T to other transfer thyristors T and setting thyristors S is suppressed, and the accidental illumination of VCSELs that are not intended to be lit is suppressed.

[0131] (Method for manufacturing the light-emitting chip 10) Next, an example of a method for manufacturing the light-emitting chip 10 to which this embodiment is applied will be described. The light-emitting chip 10 is formed by a semiconductor stack formation process, an n-ohmic electrode (n-ohmic electrodes 321, 323, 324, etc.) formation process, a semiconductor stack separation process, a current blocking section β formation process, an etching process, a protective layer 90 formation process, wiring, and an electrode formation process.

[0132] In the semiconductor stack formation process, a p-anode (DBR) layer 81, an emissive layer 82, an n-cathode (DBR) layer 83, a tunnel junction layer 84, a p-anode layer 85, an n-gate layer 86, a p-gate layer 87, and an n-cathode layer 88 are epitaxially grown in sequence on a substrate 80 to form a semiconductor stack. These semiconductor layers are stacked by methods such as metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) to form the semiconductor stack. Here, the p-anode (DBR) layer 81, the light-emitting layer 82, and the n-cathode (DBR) layer 83 are an example of a first semiconductor laminate that will be processed into a light-emitting element. The p-anode layer 85, n-gate layer 86, p-gate layer 87, and n-cathode layer 88 provided on the tunnel junction layer 84 are an example of a second semiconductor laminate that will be processed into multiple thyristors (setting thyristor S, transfer thyristor T). The substrate 80 and the semiconductor laminate epitaxially grown on the substrate 80 are an example of a semiconductor laminate substrate.

[0133] Next, in the n-ohmic electrode formation process, first, n-ohmic electrodes 321, 323, 324, etc., are formed on the n-cathode layer 88. n-ohmic electrodes (n-ohmic electrodes 321, 323, 324, etc.) are, for example, Au (AuGe) containing Ge, which facilitates ohmic contact with n-type semiconductor layers such as the n-cathode layer 88. Then, the n-ohmic electrodes (n-ohmic electrodes 321, 323, 324, etc.) are formed by, for example, the lift-off method.

[0134] Next, in the semiconductor stack separation process, the n-cathode layer 88, p-gate layer 87, n-gate layer 86, p-anode layer 85, tunnel junction layer 84, n-cathode (DBR) layer 83, light-emitting layer 82, and p-anode (DBR) layer 81 are etched in sequence to separate them into islands such as islands 301 and 302. This etching may be performed by wet etching using a sulfuric acid-based etching solution (sulfuric acid:hydrogen peroxide:water = 1:10:300 by weight ratio), or by anisotropic dry etching (RIE) using, for example, boron chloride. This etching in the semiconductor stack separation process is sometimes called mesa etching or post-etching.

[0135] Next, in the current blocking section formation process, the current-constricting layer 83b, whose sides are exposed by the semiconductor laminate separation process, is oxidized from the sides to form a current blocking section β that blocks the current. The portion that remains unoxidized becomes the current-passing section α. Oxidation of the current-constricting layer 83b is carried out, for example, by steam oxidation at 300-400°C to oxidize the Al in the current-constricting layer 83b, such as AlGaAs. At this time, oxidation proceeds from the exposed side surface, and a current-blocking portion β made of Al2O3, an oxide of Al, is formed around the islands 301, 302, etc. The unoxidized portion of the current-constricting layer 83b becomes the current-passing portion α.

[0136] In the p-gate layer etching process, the n-cathode layer 88 is etched to expose the p-gate layer 87. This etching may be performed by wet etching using a sulfuric acid-based etching solution (sulfuric acid:hydrogen peroxide:water = 1:10:300 by weight), or by anisotropic dry etching using, for example, boron chloride.

[0137] In the p-ohmic electrode formation process, p-ohmic electrodes 331, 332, etc., are formed on the p-gate layer 87. p-ohmic electrodes (such as p-ohmic electrodes 331 and 332) are, for example, Au (AuZn) containing Zn, which makes it easy to form ohmic contacts with p-type semiconductor layers such as the p-gate layer 87. Then, the p-ohmic electrodes (p-ohmic electrodes 331, 332, etc.) are formed by, for example, the lift-off method.

[0138] In the protective layer formation process, a protective layer 90 is formed using an insulating material such as SiO2, SiON, or SiN to cover the surfaces of islands 301, 302, etc. Then, through-holes (openings) are provided in the protective layer 90 above the n-ohmic electrodes (n-ohmic electrodes 321, 323, 324, etc.) and p-ohmic electrodes (p-ohmic electrodes 331, 332, etc.).

[0139] In the wiring formation process, wiring (power lines 71, first transfer signal lines 72, second transfer signal lines 73, lighting signal lines 75, etc.) connecting n-ohmic electrodes (n-ohmic electrodes 321, 323, 324, etc.) and p-ohmic electrodes (p-ohmic electrodes 331, 332, etc.), back surface electrodes 91, and a light-shielding layer 95 are formed through through holes provided in the protective layer 90. The wiring, back electrode 91, and light-shielding layer 95 are made of materials such as Au or Al.

[0140] By following the above steps, the light-emitting chip 10 of this embodiment is obtained. In this embodiment, the light-emitting chip 10 has a VCSEL and a setting thyristor S stacked on top of each other. As a result, the light-emitting chip 10 is a self-scanning type that individually lights up the VCSEL using a transfer thyristor T and a setting thyristor S. This reduces the number of terminals provided on the light-emitting chip 10, making the light-emitting chip 10 and the light source device 1 more compact.

[0141] Although various embodiments of the present invention have been described above, the technical scope of the present invention is not limited to the above embodiments. For example, in the light source device 1 of the embodiment described above, an example was described in which the control unit 110 and the transfer unit 12 of the light-emitting chip 10 are used as drive units that individually drive the setting thyristor S to switch it to the ON state. However, the control unit 110 may also directly send a signal to the setting thyristor S to drive the setting thyristor S2 individually.

[0142] Furthermore, various modifications and substitutions of configurations that do not deviate from the technical concept of the present invention are included in the present invention.

[0143] (Note) (((1))) circuit board and A plurality of light-emitting elements are provided on the substrate, each having a light-emitting region, Each of the aforementioned light-emitting elements is provided with a plurality of thyristors, each including a gate layer, which, when turned on, cause the light-emitting region of the light-emitting element to emit light or increase the amount of light emitted in the light-emitting region, The substrate absorbs light emitted from the thyristor and emits light that is not absorbed by the gate layer. Light-emitting component. (((2))) The light-emitting element is characterized in that it transmits light emitted from the thyristor, as described in (((1))). (((3))) The light-emitting element has a semiconductor layer containing Al, The light-emitting component according to (((2))), characterized in that the gate layer of the thyristor is made of a semiconductor that contains Al and has a lower Al content ratio compared to the semiconductor layer of the light-emitting element. (((4))) The semiconductor layer of the light-emitting element is a multilayer reflective layer in which a first semiconductor layer made of AlGaAs and a second semiconductor layer made of AlGaAs having a higher Al content ratio than the first semiconductor layer are alternately stacked. The light-emitting component according to (((3))), characterized in that the gate layer of the thyristor is made of AlGaAs with a lower Al content ratio compared to the first semiconductor layer of the multilayer reflector. (((5))) The light-emitting element has a lower semiconductor layer laminated on the substrate, a light-emitting layer laminated on the lower semiconductor layer, and an upper semiconductor layer laminated on the light-emitting layer, wherein the upper semiconductor layer has a higher transmittance of light emitted from the thyristor than the lower semiconductor layer, as described in (((2))). (((6))) The light-emitting component according to (((1))) to (((5))), characterized in that the substrate emits light with a longer wavelength than the light emitted from the thyristor towards the light-emitting element. (((7))) The gate layer of the thyristor is made of a semiconductor containing Al. The light-emitting component according to (((6))), characterized in that the substrate is made of GaAs. (((8))) circuit board and A first semiconductor laminate provided on the substrate and processed into a light-emitting element, The present invention comprises a second semiconductor laminate provided on the first semiconductor laminate, including a gate layer, and processed into a plurality of thyristors, The substrate is made of a semiconductor having a smaller bandgap energy than the gate layer of the second semiconductor stack. Semiconductor multilayer substrate. (((9))) circuit board and A plurality of light-emitting elements are provided on the substrate, each having a light-emitting region, A plurality of thyristors are provided on each of the light-emitting elements, each including a gate layer, and when turned on, they cause the light-emitting region of the light-emitting element to emit light or increase the amount of light emitted in the light-emitting region. A drive unit that drives multiple thyristors individually to switch them to the ON state. Equipped with, The substrate absorbs light emitted from the thyristor and emits light that is not absorbed by the gate layer. Light-emitting device. (((10))) circuit board and A plurality of light-emitting elements are provided on the substrate, each having a light-emitting region, A plurality of thyristors are provided on each of the light-emitting elements, each including a gate layer, and when turned on, they cause the light-emitting region of the light-emitting element to emit light or increase the amount of light emitted in the light-emitting region. A drive unit that individually drives multiple thyristors and causes each of the light-emitting regions to emit light at a predetermined timing, An acquisition unit acquires information about an object based on the reflected light from each of the aforementioned light-emitting regions that is reflected by the object. Equipped with, The substrate absorbs light emitted from the thyristor and emits light that is not absorbed by the gate layer. Measuring device. (((11))) The light-emitting component according to (((2))), characterized in that the gate layer of the thyristor is made of a semiconductor having a smaller bandgap energy than the semiconductor layer of the light-emitting element. (((12))) The semiconductor layer of the light-emitting element is a multilayer reflective layer in which a first semiconductor layer and a second semiconductor layer having a larger bandgap energy than the first semiconductor layer are alternately stacked. The light-emitting component according to (((11))), characterized in that the gate layer of the thyristor is made of a material with a smaller bandgap energy than the first semiconductor layer of the multilayer reflective layer. (((13))) The light-emitting element has a semiconductor layer containing Al, The light-emitting component according to (((2))), characterized in that the gate layer of the thyristor is made of a semiconductor that does not contain Al.

[0144] With the light-emitting component according to (((1))), compared to a case where the substrate on which the light-emitting element and multiple thyristors are provided does not absorb the light emitted from the thyristors, it is possible to suppress the turning on of other thyristors due to the light emitted from one thyristor. According to the light-emitting component in (((2))), the temperature rise of the light-emitting element can be suppressed compared to the case in which the light-emitting element does not transmit light emitted from the thyristor. According to the light-emitting component described in (((3))), compared to the case where the Al content ratio of the gate layer of the thyristor is higher than that of the semiconductor layer of the light-emitting element, the light emitted from the thyristor is less likely to be absorbed by the light-emitting element. In the case of the light-emitting component relating to (((4))), compared to the case where the gate layer of the thyristor is made of AlGaAs with a higher Al content ratio compared to the first semiconductor layer, the light emitted from the thyristor is less likely to be absorbed by the light-emitting element. In the case of the light-emitting component relating to (((5))), the deterioration of the characteristics of the light-emitting element due to temperature rise is suppressed compared to the case where the upper semiconductor layer has a lower transmittance of light emitted from the thyristor compared to the lower semiconductor layer. With the light-emitting component related to (((6))), the light emitted from the substrate is less likely to be absorbed by the thyristor compared to the case where the substrate emits light of the same wavelength as the light emitted from the thyristor. With the light-emitting component related to (((7))), the light emitted from the substrate is less likely to be absorbed by the thyristor compared to when the substrate contains Al. The semiconductor multilayer substrate according to (((8))) can suppress the turning on of other thyristors by light emitted from one thyristor, compared to a substrate on which a light-emitting element and multiple thyristors are provided that does not absorb light emitted from a thyristor. The light-emitting device according to (((9))) can suppress the turning on of other thyristors by the light emitted from one thyristor, compared to a case where the substrate on which the light-emitting element and multiple thyristors are provided does not absorb the light emitted from the thyristors. According to the measuring device of (((10))), compared to a case where the substrate on which the light-emitting element and multiple thyristors are provided does not absorb the light emitted from the thyristors, it is possible to suppress the turning on of other thyristors due to the light emitted from one thyristor. According to the light-emitting component related to (((11))), the light emitted from the thyristor is less likely to be absorbed by the light-emitting element. According to the light-emitting component related to (((12))), the light emitted from the thyristor is less likely to be absorbed by the light-emitting element. According to the light-emitting component related to (((13))), the light emitted from the thyristor is less likely to be absorbed by the light-emitting element. [Explanation of symbols]

[0145] 1…Light source device, 5…3D sensor, 10…Light-emitting chip, 11…Light-emitting unit, 12…Transfer unit, 110…Control unit, 81…p-anode (DBR) layer, 82…Light-emitting layer, 83…n-cathode (DBR) layer, 84…Tunnel junction layer, 85…p-anode layer, 86…n-gate layer, 87…p-gate layer, 88…n-cathode layer, 80…Substrate, 100…Measurement device, 200…Measurement control unit, S…Setting thyristor, T…Transfer thyristor, VCSEL…Vertical cavity surface-emitting laser

Claims

1. circuit board and A plurality of light-emitting elements are provided on the substrate, each having a light-emitting region, Each of the aforementioned light-emitting elements is provided with a plurality of thyristors, each including a gate layer, which, when turned on, cause the light-emitting region of the light-emitting element to emit light or increase the amount of light emitted in the light-emitting region, The substrate absorbs light emitted from the thyristor and emits light that is not absorbed by the gate layer. Light-emitting component.

2. The light-emitting element is characterized by transmitting light emitted from the thyristor, as described in claim 1.

3. The light-emitting element has a semiconductor layer containing Al, The light-emitting component according to claim 2, characterized in that the gate layer of the thyristor is made of a semiconductor that contains Al and has a lower Al content ratio compared to the semiconductor layer of the light-emitting element.

4. The semiconductor layer of the light-emitting element is a multilayer reflective layer in which a first semiconductor layer made of AlGaAs and a second semiconductor layer made of AlGaAs with a higher Al content ratio than the first semiconductor layer are alternately stacked. The light-emitting component according to claim 3, characterized in that the gate layer of the thyristor is made of AlGaAs with a lower Al content ratio compared to the first semiconductor layer of the multilayer reflective layer.

5. The light-emitting element comprises a lower semiconductor layer laminated on the substrate, a light-emitting layer laminated on the lower semiconductor layer, and an upper semiconductor layer laminated on the light-emitting layer, wherein the upper semiconductor layer has a higher transmittance of light emitted from the thyristor compared to the lower semiconductor layer, as described in claim 2.

6. The light-emitting component according to claim 1, characterized in that the substrate emits light with a longer wavelength than the light emitted from the thyristor to the light-emitting element side.

7. The gate layer of the thyristor is made of a semiconductor containing Al, The light-emitting component according to claim 6, characterized in that the substrate is made of GaAs.

8. circuit board and A plurality of light-emitting elements are provided on the substrate, each having a light-emitting region, A plurality of thyristors are provided on each of the light-emitting elements, each including a gate layer, and when turned on, they cause the light-emitting region of the light-emitting element to emit light or increase the amount of light emitted in the light-emitting region. A drive unit that drives multiple thyristors individually to switch them to the ON state. Equipped with, The substrate absorbs light emitted from the thyristor and emits light that is not absorbed by the gate layer. Light-emitting device.

9. circuit board and A plurality of light-emitting elements are provided on the substrate, each having a light-emitting region, A plurality of thyristors are provided on each of the light-emitting elements, each including a gate layer, and when turned on, they cause the light-emitting region of the light-emitting element to emit light or increase the amount of light emitted in the light-emitting region. A drive unit that individually drives multiple thyristors and causes each of the light-emitting regions to emit light at a predetermined timing, An acquisition unit acquires information about an object based on the reflected light from each of the aforementioned light-emitting regions that is reflected by the object. Equipped with, The substrate absorbs light emitted from the thyristor and emits light that is not absorbed by the gate layer. Measuring device.

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