Semiconductor device, semiconductor module, and method for manufacturing a semiconductor device.

Abstract

To prescribe a wire connection position on a top face electrode with accuracy.SOLUTION: A semiconductor device that comprises a transistor part and a diode part provided at different positions in a top view, comprises: a semiconductor substrate on which the transistor part and the diode part are provided; a top face electrode arranged above the semiconductor substrate; and a first mark part arranged above the top face electrode so as to be overlapped with both the transistor part and the diode part in the top view. The first mark part has a concave or convex shape in the top view or in a depth direction of the semiconductor substrate.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, a semiconductor module, and a method for manufacturing a semiconductor device. [Background Art]

[0002] Conventionally, semiconductor devices including a transistor portion such as an IGBT (Insulated Gate Bipolar Transistor) and a diode portion such as an FWD (Free Wheeling Diode) have been known (see, for example, Patent Documents 1 to 4). Patent Document 1: Japanese Unexamined Patent Publication No. 2020-202250 Patent Document 2: Japanese Re-Publication No. 2020 / 059285 Patent Document 3: Japanese Unexamined Patent Publication No. 2019-201160 Patent Document 4: Japanese Unexamined Patent Publication No. 2021-166247 [Summary of the Invention] [Problems to be Solved by the Invention]

[0003] A wire or the like is connected to an upper surface electrode of a semiconductor device. It is preferable that the wire or the like is accurately connected to a predetermined position on the upper surface electrode. [Means for Solving the Problems]

[0004] In order to solve the above problem, according to one aspect of the present invention, there is provided a semiconductor device including a transistor portion and a diode portion provided at different positions in a top view. The semiconductor device may include a semiconductor substrate on which the transistor portion and the diode portion are provided. Any of the above semiconductor devices may include an upper surface electrode disposed above the semiconductor substrate. Any of the above semiconductor devices may include a first mark portion disposed above the upper surface electrode, and overlapping both the transistor portion and the diode portion in a top view. In any of the above semiconductor devices, the first mark portion may have a concave shape or a convex shape in the top view or in a depth direction of the semiconductor substrate.

[0005] In any of the above semiconductor devices, the transistor portion and the diode portion may be arranged alternately along the first direction in the top view. In any of the above semiconductor devices, the length of the first mark portion in the first direction may be less than the sum of the lengths of one transistor portion and one diode portion in the first direction.

[0006] Any of the above semiconductor devices may include a protective film positioned above the upper electrode. In any of the above semiconductor devices, the first mark portion may be provided on the protective film.

[0007] In any of the above semiconductor devices, the transistor portion and the diode portion may be arranged alternately along the first direction in the top view. In any of the above semiconductor devices, the protective film may have a first extended portion that extends along the first direction. In any of the above semiconductor devices, the first mark portion may protrude from the first extended portion in a second direction different from the first direction in the top view.

[0008] In any of the semiconductor devices described above, the upper end position of the first mark portion may be lower than the upper end position of the first extension portion.

[0009] In any of the above semiconductor devices, the transistor portion and the diode portion may be arranged alternately along the first direction in the top view. In any of the above semiconductor devices, the protective film may have a first extended portion that extends along the first direction. In any of the above semiconductor devices, the first mark portion may protrude upward from the first extended portion.

[0010] In any of the above semiconductor devices, the transistor portion and the diode portion may be arranged alternately along the first direction in the top view. In any of the above semiconductor devices, the protective film may have a first extended portion that is stretched along the first direction and has the first mark portion. In any of the above semiconductor devices, the protective film may have a second extended portion that is stretched along a second direction different from the first direction in the top view. In any of the above semiconductor devices, the second extended portion may have a second mark portion that is provided on the second extended portion and has a concave or convex shape in the top view or in the depth direction of the semiconductor substrate.

[0011] In any of the above semiconductor devices, the length of the first mark portion in the first direction may be greater than the length of the second mark portion in the second direction.

[0012] Any of the above semiconductor devices may include a third mark portion positioned above the top electrode and overlapping both the transistor portion and the diode portion in the top view. In any of the above semiconductor devices, the third mark portion may have a concave or convex shape in the top view or in the depth direction of the semiconductor substrate. In any of the above semiconductor devices, the transistor portion and the diode portion may have an elongated length along the second direction in the top view. In any of the above semiconductor devices, the first mark portion and the third mark portion may be positioned opposite each other in the second direction.

[0013] In a second embodiment of the present invention, a semiconductor module is provided comprising a semiconductor device according to the first embodiment, an electrical circuit, and wires connecting the semiconductor device and the electrical circuit.

[0014] In the semiconductor module described above, the semiconductor device may include a second mark portion positioned above the top electrode and overlapping both the transistor portion and the diode portion in the top view. In any of the semiconductor modules described above, the second mark portion may have a concave or convex shape in the top view or in the depth direction of the semiconductor substrate. In any of the semiconductor modules described above, the transistor portion and the diode portion may be arranged alternately along the first direction in the top view. In any of the semiconductor modules described above, the transistor portion and the diode portion may have a longitudinal length along the second direction in the top view. In any of the semiconductor modules described above, the connection portion of the wire connected to the top electrode may be positioned facing the first mark portion in the second direction and facing the second mark portion in the first direction.

[0015] In any of the above semiconductor modules, the semiconductor device may include a third mark portion positioned above the top electrode and overlapping both the transistor portion and the diode portion in the top view. In any of the above semiconductor modules, the third mark portion may have a concave or convex shape in the top view or in the depth direction of the semiconductor substrate. In any of the above semiconductor modules, the connection portion of the wire connected to the top electrode may be sandwiched between the first mark portion and the third mark portion.

[0016] In a third aspect of the present invention, there is provided a method for manufacturing a semiconductor device including a transistor portion and a diode portion provided at different positions in a top view. In the manufacturing method, the transistor portion and the diode portion may be formed on the semiconductor substrate. In any of the above manufacturing methods, a top electrode may be formed above the semiconductor substrate. In any of the above manufacturing methods, a first mark portion that is disposed above the top electrode, overlaps both the transistor portion and the diode portion in a top view, and has a concave shape or a convex shape in the top view or in the depth direction of the semiconductor substrate may be formed.

[0017] The above summary of the invention does not list all of the necessary features of the present invention. Subcombinations of these feature groups may also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] [Figure 1] It is a top view showing an example of a semiconductor wafer 200. [Figure 2] It is a cross-sectional view showing an example of a semiconductor module 300 according to one embodiment of the present invention. [Figure 3] It is a diagram showing an example of a top structure of a semiconductor device 100-r according to a reference example. [Figure 4] It is a diagram showing an example of a top structure of a semiconductor device 100 according to one embodiment of the present invention. [Figure 5] It is a diagram showing an arrangement example of each mark portion and a connecting portion 172. [Figure 6] It is a diagram showing an example of an A-A cross section in FIG. 4. [Figure 7] It is a diagram showing an example of a B-B cross section in FIG. 4. [Figure 8] It is a diagram showing an example of a C-C cross section in FIG. 4. [Figure 9] It is a diagram showing another example of the C-C cross section. [Figure 10] It is a diagram showing another example of the top structure of the semiconductor device 100. [Figure 11]It is a diagram showing another example of the top structure of the semiconductor device 100. [Figure 12] It is a diagram showing an example of the D-D cross-section in FIG. 11. [Figure 13] It is a diagram showing another example of the D-D cross-section in FIG. 11. [Figure 14] It is a diagram showing an example of a method for manufacturing the semiconductor module 300. [Figure 15] It is a diagram showing the relationship between the position of the connecting portion 172 and the temperature of the connecting portion 172. [Figure 16] It is a diagram showing the relationship between the temperature of the connecting portion 172 and power cycle resistance. DESCRIPTION OF EMBODIMENTS

[0019] Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all combinations of features described in the embodiments are essential to the solution of the invention.

[0020] Unless otherwise specified, the unit system used in the present specification is the SI unit system. Although the unit of length may be expressed in centimeters, all calculations may be performed after conversion to meters (m). In the present specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". Of the two main surfaces of a substrate, a layer, or other members, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction when the semiconductor device is mounted.

[0021] In the present specification, technical matters may be described using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes only specify the relative positions of constituent elements, and do not limit any specific direction. For example, the Z-axis does not limitedly indicate the height direction relative to the ground. The +Z direction and the -Z direction are directions opposite to each other. When the term Z-axis direction is described without indicating positive or negative, it means directions parallel to both the +Z axis and the -Z axis.

[0022] In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X and Y axes, may be referred to as the horizontal direction. In this specification, when the term "top surface side" refers to the region from the center to the top surface in the depth direction of the semiconductor substrate, it means the region from the center to the bottom surface in the depth direction of the semiconductor substrate.

[0023] In this specification, when we refer to "identical" or "equal," we may include cases where there are errors due to manufacturing variations, etc. Such errors are, for example, within 10%. In this specification, when we describe directions as "perpendicular," "parallel," or "along," we may include cases where there are errors due to manufacturing variations, etc. Such errors are, for example, within 5 degrees.

[0024] Figure 1 is a top view showing an example of a semiconductor wafer 200. The semiconductor wafer 200 is a plate-shaped substrate formed of a semiconductor material such as silicon or a compound semiconductor. The semiconductor wafer 200 is, for example, disc-shaped. Multiple semiconductor devices 100 are formed on the semiconductor wafer 200. Each semiconductor device 100 can be cut out by cutting the semiconductor wafer 200 along the dicing line 202 on the semiconductor wafer 200. The semiconductor wafer 200 may be provided with a reference portion 204 that indicates a reference position on the semiconductor wafer 200. The reference portion 204 is, for example, a notch cut out at the edge of the semiconductor wafer 200.

[0025] Figure 2 is a cross-sectional view showing an example of a semiconductor module 300 according to one embodiment of the present invention. The semiconductor module 300 comprises a case portion 310, one or more semiconductor devices 100, external wiring 320, internal wiring 330, and wires 170. The case portion 310 is formed of an insulating material such as resin or ceramic and houses one or more semiconductor devices 100, internal wiring 330, and wires 170. Inside the case portion 310, a sealing portion 312 may be provided to cover the semiconductor devices 100, internal wiring 330, and wires 170. The sealing portion 312 is formed of an insulating material such as silicon gel. The case portion 310 may have a heat dissipation portion for dissipating heat from inside the case portion 310 to the outside. The heat dissipation portion is, for example, a metal plate exposed from the case portion 310.

[0026] The internal wiring 330 and the external wiring 320 are part of an electrical circuit. The internal wiring 330 and the external wiring 320 may be electrically connected to each other. The electrical circuit provided in the semiconductor module 300 may include other electrical elements. The internal wiring 330 is provided inside the case portion 310. The external wiring 320 electrically connects the inside and outside of the case portion 310.

[0027] The semiconductor device 100 is electrically connected to an electrical circuit located inside the semiconductor module 300. In this example, the semiconductor device 100 is electrically connected to at least one of the internal wiring 330 and the external wiring 320. In the example shown in Figure 2, electrodes located on the upper surface of the semiconductor device 100 are electrically connected to the external wiring 320 by a wire 170.

[0028] Figure 3 shows an example of the top surface structure of semiconductor device 100-r according to a reference example. In this specification, semiconductor device 100-r may sometimes be simply referred to as semiconductor device 100. In this example, semiconductor device 100 is cut from a semiconductor wafer 200 and mounted on a semiconductor module 300.

[0029] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material such as silicon or a compound semiconductor. As an example, the semiconductor substrate 10 is a silicon substrate. Figure 3 shows the projected positions of each component of the semiconductor device 100 onto the upper surface of the semiconductor substrate 10. Figure 3 shows only some of the components of the semiconductor device 100, and some components are omitted. In this specification, when simply referred to as a "top view," it means viewing from the upper side of the semiconductor substrate 10. In a top view, as described above, the positions of each component may be projected onto the upper surface of the semiconductor substrate 10.

[0030] The semiconductor substrate 10 has edges 102 when viewed from above. In this example, the semiconductor substrate 10 has two pairs of edges 102 that face each other when viewed from above (a pair of edges 102-1 and 102-3, and a pair of edges 102-2 and 102-4). In Figure 3, the X and Y axes are parallel to one of the edges 102. The Z axis is perpendicular to the top surface of the semiconductor substrate 10.

[0031] An active section 160 is provided on the semiconductor substrate 10. The active section 160 is the region through which the main current flows when the semiconductor device 100 is operating. The semiconductor device 100 may be a vertical device through which the main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10, or it may be a horizontal device through which the main current flows in a horizontal direction substantially parallel to the upper surface of the semiconductor substrate 10. In this example, the semiconductor device 100 is a vertical device. An upper electrode, such as an emitter electrode, is provided above the active section 160 in this example, but it is omitted in Figure 3.

[0032] The active section 160 is provided with a transistor section 70 including a transistor element such as an IGBT, and a diode section 80 including a diode element such as an FWD. The transistor section 70 and the diode section 80 are located at different positions when viewed from above. In the example shown in Figure 3, the transistor section 70 and the diode section 80 are alternately arranged along a predetermined first direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 in this example is a reverse-conducting IGBT (RC-IGBT).

[0033] In Figure 3, the region where the transistor section 70 is located is denoted by the symbol "I," and the region where the diode section 80 is located is denoted by the symbol "F." In this example, the transistor section 70 and the diode section 80 may each have their longitudinal length in the Y-axis direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction.

[0034] The diode portion 80 has an N+ type cathode region in the area in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode portion 80. In other words, the diode portion 80 is the region that overlaps with the cathode region when viewed from above. A P+ type collector region may be provided in the area other than the cathode region on the lower surface of the semiconductor substrate 10.

[0035] The transistor section 70 has a P+ type collector region in the area in contact with the lower surface of the semiconductor substrate 10. Furthermore, the transistor section 70 has a gate structure periodically arranged on the upper surface side of the semiconductor substrate 10, which includes an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film.

[0036] The semiconductor device 100 may have one or more pads on the semiconductor substrate 10. In this example, the semiconductor device 100 has a gate pad 120. Each pad is located near an edge 102. The vicinity of the edge 102 refers to the area between the edge 102 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad is connected to an electrical circuit different from the semiconductor device 100 via wiring such as wires.

[0037] A gate potential is applied to the gate pad 120. The gate pad 120 is electrically connected to the conductive portion of the gate trench, which will be described later. The semiconductor device 100 includes gate wiring that connects the gate pad 120 and the gate trench. The gate wiring is provided so as to surround the active portion 160. The gate wiring may also be arranged so as to cross the active portion 160.

[0038] In this example, the semiconductor device 100 includes a pressure-resistant structure 90 between the active portion 160 and the edge 102 when viewed from above. The pressure-resistant structure 90 mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The pressure-resistant structure 90 may include at least one of a guard ring, a field plate, and a resurf arranged in an annular shape surrounding the active portion 160.

[0039] A protective film 110 is provided above the semiconductor substrate 10, covering a portion of the semiconductor substrate 10. In Figure 3, the protective film 110 is hatched with diagonal lines. The protective film 110 is made of an insulating material such as polyimide. The protective film 110 may be positioned to cover the pressure-resistant structure 90. The protective film 110 may also be positioned to further cover the gate wiring described above. The protective film 110 shown in Figure 3 has a portion that covers the pressure-resistant structure 90 and the gate wiring, which are positioned between the active portion 160 and the edge 102. The protective film 110 in this example has a first extended portion 111, a second extended portion 112, a third extended portion 113, and a fourth extended portion 114. The protective film 110 may further have a portion that covers the gate wiring positioned across the active portion 160.

[0040] The first extended portion 111 extends in the first direction (X-axis direction). That is, the first extended portion 111 has its longitudinal side in the first direction. The first extended portion 111 is positioned between the end side 102-1, which is parallel to the X-axis direction, and the active portion 160. The first extended portion 111 may also be positioned above the active portion 160.

[0041] The second extension portion 112 extends in a second direction (in this example, the Y-axis direction) that is different from the first direction. In other words, the second extension portion 112 has its longitudinal side in the second direction. The second extension portion 112 is positioned between the end side 102-2, which is parallel to the Y-axis direction, and the active portion 160. The second extension portion 112 may also be positioned above the active portion 160.

[0042] The third extension portion 113 extends in the first direction (X-axis direction). That is, the third extension portion 113 has its longitudinal side in the first direction. The third extension portion 113 is positioned opposite the first extension portion 111 in the Y-axis direction. The third extension portion 113 is positioned between the end 102-3 opposite to end 102-1 and the active portion 160. The third extension portion 113 may also be positioned above the active portion 160.

[0043] The fourth extension portion 114 extends in the second direction (Y-axis direction). That is, the fourth extension portion 114 has its longitudinal side in the second direction. The fourth extension portion 114 is positioned opposite the second extension portion 112 in the X-axis direction. The fourth extension portion 114 is positioned between the end 102-4 opposite to the end 102-2 and the active portion 160. The fourth extension portion 114 may also be positioned above the active portion 160.

[0044] A wire 170 is connected to the upper surface of the emitter electrode (see Figure 4, etc.) of the semiconductor device 100. The area in contact with the upper surface of the emitter electrode is referred to as the connection portion 172. The wire 170 may be crimped to the emitter electrode or fixed with a fixing member such as solder. If the wire 170 is fixed with a fixing member, the area in contact with the emitter electrode by the fixing member and the wire 170 is referred to as the connection portion 172. It is preferable that the connection portion 172 be positioned in a location that does not reduce the reliability of the connection with the emitter electrode.

[0045] When the semiconductor device 100 is mounted on a circuit such as an inverter, the transistor section 70 and the diode section 80 operate alternately (i.e., the main current flows alternately). When the transistor section 70 is operating, the transistor section 70 generates most of the heat, and when the diode section 80 is operating, the diode section 80 generates most of the heat.

[0046] Depending on the operating conditions of the circuit, the operating time of either the transistor section 70 or the diode section 80 may be extended, leading to increased heat generation in that section. In such cases, if the connection section 172 is located only above that section, the reliability of the connection between the wire 170 and the emitter electrode may decrease when the on and off operations of the transistor section 70 and the diode section 80 are repeatedly performed. In other words, the power cycle withstand capability may decrease.

[0047] To suppress the aforementioned decrease in connection reliability, it is conceivable to position the connection portion 172 so as to span both the transistor portion 70 and the diode portion 80, as shown in Figure 3. By positioning the connection portion 172 in this way, the heat generated near the connection portion 172 can be made uniform regardless of the operating state of the semiconductor device 100. However, the transistor portion 70 and the diode portion 80 are covered by emitter electrodes made of metal such as aluminum, and it is difficult to detect the positions of the transistor portion 70 and the diode portion 80 from above the emitter electrodes. For this reason, it is difficult to check the position of the connection portion 172 relative to the transistor portion 70 and the diode portion 80 after connecting the wire 170 to the semiconductor device 100.

[0048] Figure 4 shows an example of the top surface structure of a semiconductor device 100 according to one embodiment of the present invention. The semiconductor device 100 in this example includes a first mark portion 141 in addition to the structure of the semiconductor device 100-r described in Figure 3. The semiconductor device 100 in this example may further include at least one of the second mark portion 142, the third mark portion 143, and the fourth mark portion 144. The other structure is the same as that of the semiconductor device 100-r. Each of the mark portions, the first mark portion 141, the second mark portion 142, the third mark portion 143, and the fourth mark portion 144, may be provided one at a time or multiple at a time. Each mark portion defines the position where the connecting portion 172 should be placed. Each mark portion has a concave or convex shape when viewed from above or in the depth direction of the semiconductor substrate 10.

[0049] The first mark portion 141 is positioned above the upper electrodes such as the emitter electrode, and overlaps with both the transistor portion 70 and the diode portion 80 in a top view. In this example, the first mark portion 141 has a convex shape in a top view. That is, the first mark portion 141 in this example is in contact with a member positioned above the upper electrodes and protrudes from that member in one direction in a top view.

[0050] In this example, the first mark portion 141 is provided on the protective film 110. The first mark portion 141 may be made of the same material as the protective film 110. In this example, the first mark portion 141 protrudes from the first extended portion 111, which extends in the first direction, in the opposite direction to the second direction (in this example, the negative direction of the Y axis). In this example, the first direction is the X-axis direction, and the second direction is the Y-axis direction. In other words, the first mark portion 141 protrudes from the first extended portion 111 in a direction perpendicular to the extension direction of the first extended portion 111. The first mark portion 141 may protrude from the first extended portion 111 toward the interior of the active portion 160.

[0051] The first mark portion 141 defines the position where the connecting portion 172 should be provided in the X-axis direction. The first mark portion 141 and the connecting portion 172 may be positioned opposite each other in the Y-axis direction. In this example, the first mark portion 141 protrudes from the first extension portion 111 toward the connecting portion 172. The first mark portion 141 and the connecting portion 172 are positioned apart in a top view. If the connecting portion 172 is provided at multiple positions in the X-axis direction, the first mark portion 141 may be provided for each of the connecting portions 172. In the example in Figure 4, the connecting portion 172 is provided at two positions in the X-axis direction. The first mark portion 141 is provided for each of the connecting portions 172.

[0052] The length L1 of the first mark portion 141 in the X-axis direction is less than the sum of the lengths L2 of one transistor portion 70 and one diode portion 80 in the X-axis direction. This length L2 is the sum of the lengths of the transistor portion 70 and diode portion 80 that overlap with the first mark portion 141. The first mark portion 141 does not overlap with the two transistor portions 70, nor does it overlap with the two diode portions 80. In other words, the first mark portion 141 straddles only one boundary line in the X-axis direction of the transistor portion 70 and diode portion 80. The length L1 may be greater than or less than the length in the X-axis direction of the transistor portion 70 that overlaps with the first mark portion 141. The length L1 may be greater than or less than the length in the X-axis direction of the diode portion 80 that overlaps with the first mark portion 141. By providing the first mark portion 141, the position where the connection portion 172 should be provided in the X-axis direction can be defined.

[0053] The second mark portion 142 is positioned above the upper electrodes such as the emitter electrode, and in a top view, it overlaps with either the transistor portion 70 or the diode portion 80. In this example, the second mark portion 142 has a convex shape in a top view. That is, the second mark portion 142 in this example is in contact with a member positioned above the upper electrodes and protrudes from that member in either direction in a top view.

[0054] In this example, the second mark portion 142 is provided on the protective film 110. The second mark portion 142 may be formed from the same material as the protective film 110. In this example, the second mark portion 142 protrudes toward the first direction from the second extended portion 112 which extends in the second direction. The second mark portion 142 protrudes from the second extended portion 112 in a direction perpendicular to the extension direction of the second extended portion 112. The second mark portion 142 may protrude toward the interior of the active portion 160 from the second extended portion 112.

[0055] The second mark portion 142 defines the position in the Y-axis direction where the connecting portion 172 should be provided. The second mark portion 142 and the connecting portion 172 may be positioned opposite each other in the X-axis direction. In this example, the second mark portion 142 protrudes from the second extension portion 112 toward the connecting portion 172. The second mark portion 142 and the connecting portion 172 are positioned apart in a top view. If the connecting portion 172 is provided at multiple positions in the Y-axis direction, the second mark portion 142 may be provided for each of the connecting portions 172. In the example in Figure 4, the connecting portions 172 are provided at four positions in the Y-axis direction. The second mark portion 142 is provided for each of the connecting portions 172.

[0056] In this example, the second mark portion 142 is positioned to overlap with the transistor portion 70. If the diode portion 80 is located at the X-axis end of the active portion 160, the second mark portion 142 is positioned to overlap with the diode portion 80. The length of the second mark portion 142 in the X-axis direction may be shorter than the length of the transistor portion 70 in the X-axis direction that overlaps with the second mark portion 142, or shorter than the length of the diode portion 80 in the X-axis direction that overlaps with the second mark portion 142. In other words, the second mark portion 142 does not have to overlap with the X-axis boundary between the transistor portion 70 and the diode portion 80. By providing the second mark portion 142, the position where the connection portion 172 should be provided in the Y-axis direction can be defined.

[0057] The third mark portion 143 has the same arrangement and structure as the first mark portion 141, except that it is provided on the third extension portion 113. The first mark portion 141 and the third mark portion 143 may be arranged facing each other in the Y-axis direction. The connecting portion 172 may be positioned between the first mark portion 141 and the third mark portion 143 which face each other in the Y-axis direction. By further providing the third mark portion 143, the position where the connecting portion 172 should be provided in the X-axis direction can be defined with even greater precision.

[0058] The fourth mark portion 144 has the same arrangement and structure as the second mark portion 142, except that it is provided on the fourth extension portion 114. The second mark portion 142 and the fourth mark portion 144 may be arranged facing each other in the X-axis direction. The connecting portion 172 may be positioned between the second mark portion 142 and the fourth mark portion 144, which face each other in the X-axis direction. By further providing the fourth mark portion 144, the position where the connecting portion 172 should be provided in the Y-axis direction can be defined with even greater precision.

[0059] Figure 5 shows an example of the arrangement of each mark and the connecting part 172. In Figure 5, some of the components shown in Figure 4 are omitted. The arrangement of the protective film 110, each mark, and the connecting part 172 is the same as in the example in Figure 4.

[0060] As described above, at least one connecting portion 172 is sandwiched between the first mark portion 141 and the third mark portion 143, and also sandwiched between the second mark portion 142 and the fourth mark portion 144. All connecting portions 172 may be sandwiched between the first mark portion 141 and the third mark portion 143, and also sandwiched between the second mark portion 142 and the fourth mark portion 144.

[0061] The area between the first mark portion 141 and the third mark portion 143 is designated as region 145, and the area between the second mark portion 142 and the fourth mark portion 144 is designated as region 146. A connecting portion 172 may be placed in the area where regions 145 and 146 overlap. At least a portion of the connecting portion 172 may be placed in this region, at least the center (or centroid) of the connecting portion 172 may be placed, more than half of the area of ​​the connecting portion 172 may be placed, or the entire connecting portion 172 may be placed.

[0062] The length L1 in the X-axis direction of the first mark portion 141 and the third mark portion 143, and the length L3 in the Y-axis direction of the second mark portion 142 and the fourth mark portion 144 may be determined according to the shape of the connecting portion 172. In this example, the connecting portion 172 has a perpendicular axis in the X-axis direction and a minor axis in the Y-axis direction. Length L1 may be greater than length L3. Length L1 may also be the same as the length of the connecting portion 172 in the X-axis direction. Length L3 may also be the same as the length of the connecting portion 172 in the Y-axis direction.

[0063] As explained in Figures 4 and 5, by providing each mark on the semiconductor device 100, the position where the connection portion 172 should be placed can be precisely defined. Each mark may be formed on the semiconductor wafer 200 as shown in Figure 1. Markers are formed on the semiconductor wafer 200 to define the position within the plane of the semiconductor wafer 200. For example, the dicing line 202 is provided with a marker that is not covered by the top electrode such as the emitter electrode. By forming each mark based on the position of the marker, each mark can be precisely placed at a predetermined position on the semiconductor substrate 10. Therefore, when the wire 170 is connected to the semiconductor device 100 cut from the semiconductor wafer 200, it is possible to accurately confirm whether the connection portion 172 is positioned in the predetermined location using each mark. Furthermore, by controlling the position where the wire 170 is connected to the semiconductor device 100 using the position of each mark, the position of the connection portion 172 can be precisely controlled.

[0064] Figure 6 shows an example of the AA cross-section in Figure 4. The AA cross-section is the XZ plane that passes through a part of the transistor section 70 and a part of the diode section 80. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross-section. The emitter electrode 52 is an example of a top electrode. The emitter electrode 52 and the collector electrode 24 are made of a metallic material such as aluminum.

[0065] The interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is a film that includes at least one layer of insulating film such as silicate glass with impurities such as boron or phosphorus added, a thermal oxide film, and other insulating films. Contact holes 54 are provided in the interlayer insulating film 38.

[0066] The emitter electrode 52 is located above the interlayer insulating film 38. The emitter electrode 52 is in contact with the upper surface 21 of the semiconductor substrate 10 through a contact hole 54 in the interlayer insulating film 38. The collector electrode 24 is located on the lower surface 23 of the semiconductor substrate 10. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (Z-axis direction) is referred to as the depth direction.

[0067] The semiconductor substrate 10 has an N-type drift region 18. The drift region 18 is provided in both the transistor section 70 and the diode section 80. The upper surface 21 of the semiconductor substrate 10 is provided with a plurality of trench sections. The plurality of trench sections include a gate trench section 40 connected to the gate wiring and a dummy trench section 30 connected to the emitter electrode 52. The plurality of trench sections are arranged in a line along the X-axis. Each trench section extends in the Y-axis direction. As an example, the transistor section 70 has a gate trench section 40 and a dummy trench section 30. As an example, the diode section 80 has a dummy trench section 30 and no gate trench section 40.

[0068] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided covering the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench, on the inside of the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0069] The gate conductive portion 44 may be longer than the base region 14 in the depth direction. The gate trench portion 40 in this cross-section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface of the base region 14 that is in contact with the gate trench portion 40.

[0070] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in its cross-section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided covering the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is located inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed from the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 may be formed from a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0071] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. However, the gate conductive portion 44 of the gate trench portion 40 is connected to the gate wiring via a contact hole provided in the interlayer insulating film 38. Also, the dummy conductive portion 34 of the dummy trench portion 30 is connected to the emitter electrode 52 via a contact hole provided in the interlayer insulating film 38.

[0072] The portion between the two trenches, which are aligned in the X-axis direction, is called a mesa. A mesa portion 60 is provided in the transistor portion 70, and a mesa portion 61 is provided in the diode portion 80.

[0073] In the mesa portion 60 of the transistor portion 70, an N+ type emitter region 12 and a P- type base region 14 are provided in order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+ type storage region may also be provided in the mesa portion 60. The storage region is located between the base region 14 and the drift region 18. By providing a storage region, the carrier injection promotion effect (IE effect) can be enhanced and the on-voltage can be reduced. The storage region may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.

[0074] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The doping concentration of the emitter region 12 is higher than that of the drift region 18.

[0075] The base region 14 is located below the emitter region 12. In this example, the base region 14 is located in contact with the emitter region 12. The base region 14 may be in contact with the trenches on both sides of the mesa region 60.

[0076] The mesa portion 61 of the diode portion 80 is provided with a P-type base region 14 in contact with the upper surface 21 of the semiconductor substrate 10. Below the base region 14, a drift region 18 is provided. In the mesa portion 61, an accumulation region may be provided below the base region 14.

[0077] In both the transistor section 70 and the diode section 80, an N+ type buffer section 20 may be provided below the drift section 18. The doping concentration of the buffer section 20 is higher than that of the drift section 18. The buffer section 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base section 14 from reaching the P+ type collector section 22 and the N+ type cathode section 82.

[0078] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than that of the base region 14.

[0079] In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration of the cathode region 82 is higher than that of the drift region 18. The collector region 22 and the cathode region 82 are exposed to the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10.

[0080] The boundary position between the collector region 22 and the cathode region 82 in the X-axis direction is defined as the boundary position between the transistor section 70 and the diode section 80. As explained in Figure 4, the first mark section 141 and the third mark section 143 are positioned to overlap with the boundary position between the collector region 22 and the cathode region 82.

[0081] Figure 7 shows an example of a BB cross-section in Figure 4. The BB cross-section is the XZ plane passing through the protective film 110 and the withstand voltage structure 90. Figure 7 shows a cross-section passing through the second stretched portion 112 of the protective film 110, but the semiconductor device 100 has a similar structure in cross-sections passing through other stretched portions of the protective film 110. In Figure 7, a portion of the transistor portion 70 near the withstand voltage structure 90 is also shown.

[0082] In this example, the region including the edge 102 of the semiconductor substrate 10 to the gate wiring 130 is defined as the withstand voltage structure 90. The gate wiring 130 is wiring connected to the gate pad 120. The gate wiring 130 is located above the upper surface 21 of the semiconductor substrate 10. The gate wiring 130 is provided so as to surround the active portion 160 when viewed from above.

[0083] In this example, gate wiring 130-1 and gate wiring 130-2 are stacked in the Z-axis direction. Gate wiring 130-1 is made of a metallic material such as aluminum, and gate wiring 130-2 is made of polysilicon with impurities added.

[0084] The gate wiring 130-2 and the semiconductor substrate 10 are insulated by an insulating film such as a thermal oxide film. The gate wiring 130-2 is connected to the gate conductive part 44 at a position different from the cross-section shown in Figure 7.

[0085] Gate wiring 130-1 is positioned above gate wiring 130-2. An interlayer insulating film 38 is positioned between gate wiring 130-1 and gate wiring 130-2. The interlayer insulating film 38 is provided with contact holes for connecting gate wiring 130-1 and gate wiring 130-2.

[0086] A well region 11 is provided in the semiconductor substrate 10 below the gate wiring 130. The well region 11 may be provided so as to surround the active portion 160 when viewed from above. The well region 11 extends from the upper surface 21 of the semiconductor substrate 10 to a depth greater than the base region 14. The well region 11 is exposed on the upper surface 21. The well region 11 may be electrically connected to the emitter electrode 52. The region including the edge 102 of the semiconductor substrate 10 to the well region 11 may be defined as the withstand voltage structure 90.

[0087] The pressure-resistant structure 90 has one or more guard rings 92. The pressure-resistant structure 90 may further have field plates positioned above each guard ring 92. The pressure-resistant structure 90 in this example further has channel stoppers 98.

[0088] The guard ring 92 is a P+ type region provided in contact with the upper surface 21 of the semiconductor substrate 10. One or more guard rings 92 are provided between the well region 11 and the edge 102 of the semiconductor substrate 10, and are exposed to the upper surface 21 of the semiconductor substrate 10. Each guard ring 92 surrounds the active portion 160.

[0089] The channel stopper 98 is provided in contact with the edge 102 and the top surface 21 of the semiconductor substrate 10. The channel stopper 98 is a P-type with the same or higher concentration as the base region 14, or an N-type with a higher concentration than the drift region 18. A collector potential may be applied to the channel stopper 98. By setting the potential of the channel stopper 98 to the potential of the collector electrode 24, the depletion layer extending from the active portion 160 is prevented from reaching the side surface of the semiconductor substrate 10. This improves the breakdown voltage of the semiconductor device 100.

[0090] The protective film 110 may cover the entire pressure-resistant structure 90. The protective film 110 may be provided from the edge 102 to the end of the active part 160. The protective film 110 may cover the gate wiring 130. The protective film 110 may cover the well region 11. The protective film 110 may cover a part of the emitter electrode 52.

[0091] Figure 8 shows an example of a CC cross-section in Figure 4. The CC cross-section is the YZ plane passing through the first extension portion 111 and the first mark portion 141. Other extension portions and other mark portions may also have the structure described in Figure 8.

[0092] In this example, the first extension portion 111 covers the end of the emitter electrode 52. The first mark portion 141 is provided above the emitter electrode 52, protruding from the first extension portion 111 in the opposite direction to the Y-axis (i.e., the negative direction of the Y-axis). Above the emitter electrode 52, the upper end position of the first extension portion 111 and the upper end position of the first mark portion 141 may be the same. The upper end position is the position of the uppermost part in the Z-axis direction.

[0093] Let T1 be the thickness of the first marked portion 141 in the Z-axis direction, and T2 be the thickness of the first stretched portion 111 in the Z-axis direction. Thickness T1 is the distance in the Z-axis direction from the upper end of the emitter electrode 52 to the upper end of the first marked portion 141. Thickness T2 is the thickness of the first stretched portion 111 at a position that does not overlap with the emitter electrode 52. Thickness T2 may be the distance in the Z-axis direction from the upper end of the interlayer insulating film 38 to the upper end of the first stretched portion 111.

[0094] The thickness T1 may be less than the thickness T2. Making the first extended portion 111 thicker makes it easier to protect the pressure-resistant structure 90 and the gate wiring 130, etc. The first marked portion 141 does not need to have a protective function, so it may be formed relatively thinly. Making the first marked portion 141 thin reduces the stress generated in the first marked portion 141. The protective film 110, including the first extended portion 111 and the first marked portion 141, is formed of an insulating material such as resin or polyimide. The adhesive strength between the protective film 110 and the emitter electrode 52 is lower than the adhesive strength between the protective film 110 and the interlayer insulating film 38 (or semiconductor substrate 10). For this reason, making the first marked portion 141 thin reduces the stress in the first marked portion 141 and suppresses peeling of the first marked portion 141 from the emitter electrode 52.

[0095] Figure 9 shows another example of a CC cross section. The CC cross section is a YZ plane passing through the first extension portion 111 and the first mark portion 141, but other extension portions and other mark portions may also have the structure described in Figure 9.

[0096] In this example, the upper end position of the first mark portion 141 is lower than the upper end position of the first extension portion 111. The other structural features are the same as in the example in Figure 8. In this example, the thickness T1 of the first mark portion 141 is smaller than the thickness T3 of the first extension portion 111 above the emitter electrode 52. This configuration further reduces the stress in the first mark portion 141 and suppresses peeling of the first mark portion 141 from the emitter electrode 52. The thickness T1 may be 90% or less of the thickness T3, 80% or less, 70% or less, or 50% or less. The thickness T1 may be 10% or more of the thickness T3.

[0097] Figure 10 shows another example of the top surface structure of the semiconductor device 100. The structure of each marked portion of the semiconductor device 100 in this example differs from that of the semiconductor device 100 described in Figures 4 to 9. The structure of other parts may be the same as in any of the embodiments described in Figures 4 to 9.

[0098] Each marked portion in this example has a concave shape when viewed from above. That is, each marked portion in this example is a recessed portion in a member positioned above the top electrode, extending inward from the edge of the member. Each marked portion may be a recess provided in each extended portion of the protective film 110. Each marked portion is a recess formed in each extended portion of the protective film 110, extending inward from the edge closest to the active portion 160, away from the active portion 160. The position and size of each marked portion may be the same as in the example described in Figures 4 to 9. Each marked portion in this example may be positioned in a range that does not overlap with the gate wiring 130 or the guard ring 92. This allows the gate wiring 130 and the guard ring 92 to be covered and protected by the protective film 110. Each marked portion may be positioned above the emitter electrode 52. Each marked portion may be positioned in a range that does not extend beyond the emitter electrode 52.

[0099] Figure 11 shows another example of the top surface structure of the semiconductor device 100. The structure of each marked portion of the semiconductor device 100 in this example differs from that of the semiconductor device 100 described in Figures 4 to 10. The structure of other parts may be the same as in any of the embodiments described in Figures 4 to 10.

[0100] Each marked portion in this example has a concave or convex shape in the Z-axis direction. In other words, each marked portion in this example is a recess or convex portion provided on the upper surface of a member that is positioned above the upper electrode. Each marked portion may be provided on the upper surface of each stretched portion of the protective film 110. The position and size of each marked portion may be the same as in the example described in Figures 4 to 11.

[0101] Figure 12 shows an example of a DD cross-section in Figure 11. The DD cross-section is the YZ plane passing through the first extension portion 111 and the first mark portion 141, but other extension portions and other mark portions may also have the structure described in Figure 12.

[0102] In this example, the first mark portion 141 is a recess that is recessed downward from the upper surface 101 of the first extension portion 111. However, the first extension portion 111 remains even when the first mark portion 141 is present. In other words, the thickness T4 of the first mark portion 141 (i.e., the depth of the recess) is smaller than the thickness T3 of the first extension portion 111. The thickness T4 may be 10% or more of the thickness T3, 20% or more, 30% or more, or 50% or more. The thickness T4 may be 90% or less of the thickness T3. The first mark portion 141 may be positioned in a range that does not overlap with the gate wiring 130 or the guard ring 92. This allows the gate wiring 130 and the guard ring 92 to be covered and protected by the protective film 110. The first mark portion 141 may be positioned above the emitter electrode 52. The first mark portion 141 may be positioned in a range that does not extend beyond the emitter electrode 52.

[0103] Figure 13 shows another example of the DD section in Figure 11. The DD section is the YZ plane passing through the first extension 111 and the first mark 141, but other extensions and other mark sections may have the structure described in Figure 12.

[0104] In this example, the first mark portion 141 is a protrusion that projects upward from the upper surface 101 of the first extension portion 111. The thickness T4 of the first mark portion 141 may be 10% or less of the thickness T3, 20% or less, 30% or less, or 50% or less. The thickness T4 may be 90% or more of the thickness T3. The first mark portion 141 may or may not overlap with the gate wiring 130 or the guard ring 92.

[0105] Figure 14 shows an example of a method for manufacturing a semiconductor module 300. The method for manufacturing a semiconductor module 300 includes a semiconductor device manufacturing process S500, a mounting process S514, and an inspection process S516.

[0106] In the manufacturing process S500 of the semiconductor device 100, a voltage-resistant structure portion 90 is formed on each semiconductor device 100 of the semiconductor wafer 200 (S502). In addition, semiconductor elements such as transistor portions 70 and diode portions 80 are formed on the upper surface of the semiconductor wafer 200 (S504). In S504, each trench portion, emitter region 12 and base region 14 may be formed.

[0107] Next, an emitter electrode 52, a gate pad 120, and metal top electrodes such as gate wiring 130-1 are formed on the semiconductor wafer 200 (S506). In S506, gate wiring 130-2, an interlayer insulating film 38, and contact holes may be formed before forming the top electrodes. In steps S502 to S506, a predetermined marker may be formed on the dicing line 202. This marker may be formed from the interlayer insulating film 38 or the like.

[0108] Next, a protective film 110 and each mark portion (first mark portion 141, second mark portion 142, third mark portion 143, fourth mark portion 144) are formed above the upper electrode (S508). As shown in Figure 8, the protective film 110 may include a portion positioned below the upper electrode. The position of each mark portion may be controlled based on the position of a marker or the like provided on the semiconductor wafer 200. This allows for precise control of the position of each mark portion.

[0109] Next, the structure on the lower surface of the semiconductor wafer 200 is formed (S510). In S510, the buffer region 20, collector region 22, cathode region 82, and collector electrode 24, as described in Figure 5, etc., may be formed.

[0110] Next, the semiconductor wafer 200 is cut along the dicing line 202 to cut out each semiconductor device 100 (S512). This allows the semiconductor device 100 to be manufactured.

[0111] Next, the semiconductor device 100 is mounted onto the semiconductor module 300 (S514). In S514, the wire 170 is connected to the upper electrode of the semiconductor device 100.

[0112] Next, it is checked whether the connection portion 172 of the wire 170 is located in the predetermined position (S516). In S516, the connection portion 172 may be automatically checked by an optical inspection device to determine whether it is located in the position specified by each mark. In this example, since each mark is located above the emitter electrode 52, the position of the connection portion 172 can be checked easily and accurately.

[0113] Figure 15 shows the relationship between the position of the connection point 172 and the temperature of the connection point 172. The horizontal axis of Figure 15 indicates whether the connection point 172 is located above the transistor section 70, above the boundary between the transistor section 70 and the diode section 80, or above the diode section 80. The vertical axis of Figure 15 shows the temperature of the connection point 172. The vertical axis of Figure 15 is a linear axis. The circular plots in Figure 15 show the temperature measurement results when the main current is flowing through the transistor section 70, and the square plots show the temperature measurement results when the main current is flowing through the diode section 80.

[0114] As shown in Figure 15, if the connection portion 172 is positioned above the transistor portion 70 or the diode portion 80, the temperature of the connection portion 172 changes depending on the operating state of the semiconductor device 100. In contrast, if the connection portion 172 is positioned above the boundary between the transistor portion 70 and the diode portion 80, the temperature of the connection portion 172 hardly changes even if the operating state of the semiconductor device 100 changes. Therefore, by positioning the connection portion 172 above the boundary between the transistor portion 70 and the diode portion 80, temperature changes at the connection portion 172 can be suppressed even if the operating state of the semiconductor device 100 changes repeatedly, thereby suppressing the generation of thermal stress at the connection portion 172. This improves the connection reliability of the connection portion 172.

[0115] Figure 16 shows the relationship between the temperature of the connection portion 172 and its power cycle tolerance. In the example in Figure 16, the temperature of the connection portion 172 is repeatedly changed between the temperature shown on the horizontal axis and a predetermined temperature. The power cycle tolerance on the vertical axis of Figure 16 indicates the number of repeated temperature changes of the connection portion 172 until the connection portion 172 separates from the upper electrode. The vertical axis of Figure 16 is a logarithmic axis, and the horizontal axis is a linear axis. As shown in Figure 16, there is a correlation between the temperature of the connection portion 172 and its power cycle tolerance. Therefore, the smaller the variation in the temperature of the connection portion 172, the smaller the variation in the power cycle tolerance of the connection portion 172. By precisely defining the position of the connection portion 172 using each mark, the variation in the temperature of the connection portion 172 can be reduced, and thus the variation in the power cycle tolerance of the connection portion 172 can be reduced.

[0116] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0117] It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of Symbols]

[0118] 10...Semiconductor substrate, 11...Well region, 12...Emitter region, 14...Base region, 18...Drift region, 20...Buffer region, 21...Top surface, 22...Collector region, 23...Bottom surface, 24...Collector electrode, 30...Dummy trench section, 32...Dummy insulating film, 34...Dummy conductive section, 38...Interlayer insulating film, 40...Gate trench section, 42...Gate insulating film, 44...Gate conductive section, 52...Emitter electrode, 54...Contact hole, 60, 61...Mesa section, 70...Transistor section, 80...Diode section, 82...Cathode region, 90...Withstand voltage structure section, 92...Guard ring, 98...Channel stop P, 100... Semiconductor device, 101... Top surface, 102... Edge, 110... Protective film, 111... First extended portion, 112... Second extended portion, 113... Third extended portion, 114... Fourth extended portion, 120... Gate pad, 130... Gate wiring, 141... First mark portion, 142... Second mark portion, 143... Third mark portion 144...4th mark section, 145...area, 146...area, 160...active section, 170...wire, 172...connection section, 200...semiconductor wafer, 202...dicing line, 204...reference section, 300...semiconductor module, 310...case section, 312...sealing section, 320...wiring, 330...wiring

Claims

1. A semiconductor device comprising a transistor section and a diode section located at different positions in a top view, A semiconductor substrate on which the transistor section and the diode section are provided, An upper electrode positioned above the semiconductor substrate, A first mark portion is positioned above the upper electrode and overlaps with both the transistor portion and the diode portion when viewed from above. Equipped with, The first mark portion is a semiconductor device having a concave or convex shape when viewed from above or in the depth direction of the semiconductor substrate.

2. The transistor section and the diode section are arranged alternately along the first direction in the top view, The length of the first mark portion in the first direction is smaller than the sum of the lengths of one transistor portion and one diode portion in the first direction. The semiconductor device according to claim 1.

3. The protective film is further positioned above the upper electrode, The first mark portion is provided on the protective film. The semiconductor device according to claim 1.

4. The transistor section and the diode section are arranged alternately along the first direction in the top view, The protective film has a first stretched portion that extends along the first direction, The first mark portion protrudes from the first extension portion in a second direction different from the first direction when viewed from above. The semiconductor device according to claim 3.

5. The upper end position of the first mark portion is lower than the upper end position of the first extension portion. The semiconductor device according to claim 4.

6. The transistor section and the diode section are arranged alternately along the first direction in the top view, The protective film has a first stretched portion that extends along the first direction, The first mark portion protrudes upward from the first extension portion. The semiconductor device according to claim 3.

7. The transistor section and the diode section are arranged alternately along the first direction in the top view, The aforementioned protective film is A first extended portion extending along the first direction and having the first marked portion provided, A second extended portion extending in a second direction different from the first direction in a top view, It has, The second extended portion further comprises a second mark portion having a concave or convex shape when viewed from above or in the depth direction of the semiconductor substrate. The semiconductor device according to claim 3.

8. The length of the first mark portion in the first direction is greater than the length of the second mark portion in the second direction. The semiconductor device according to claim 7.

9. The system further comprises a third mark portion, which is positioned above the upper electrode and overlaps with both the transistor portion and the diode portion in the top view, The third mark portion has a concave or convex shape when viewed from above or in the depth direction of the semiconductor substrate. The transistor section and the diode section have an elongated length along the second direction in the top view, The first mark portion and the third mark portion are arranged facing each other in the second direction. The semiconductor device according to claim 1.

10. A semiconductor module comprising a semiconductor device having a transistor section and a diode section located at different positions in a top view, an electrical circuit, and wires connecting the semiconductor device and the electrical circuit, The aforementioned semiconductor device is A semiconductor substrate on which the transistor section and the diode section are provided, An upper electrode is positioned above the semiconductor substrate and to which the wire is connected, A first mark portion is positioned above the upper electrode and overlaps with both the transistor portion and the diode portion in the top view. Equipped with, The first mark portion has a concave or convex shape when viewed from above or in the depth direction of the semiconductor substrate. Semiconductor module.

11. The semiconductor device further comprises a second marked portion, which is positioned above the upper electrode and overlaps with one of the transistor portion and the diode portion in the top view. The second mark portion has a concave or convex shape when viewed from above or in the depth direction of the semiconductor substrate. The transistor section and the diode section are arranged alternately along the first direction in the top view, The transistor section and the diode section have an elongated length along the second direction in the top view, The connection portion of the wire connected to the upper electrode is positioned facing the first mark portion in the second direction, and also facing the second mark portion in the first direction. The semiconductor module according to claim 10.

12. The semiconductor device further comprises a third marked portion, which is positioned above the upper electrode and overlaps with both the transistor portion and the diode portion in the top view. The third mark portion has a concave or convex shape when viewed from above or in the depth direction of the semiconductor substrate. In the wire, the connection portion connected to the upper electrode is sandwiched between the first mark portion and the third mark portion. The semiconductor module according to claim 10.

13. A method for manufacturing a semiconductor device comprising a transistor section and a diode section located at different positions in a top view, The transistor portion and the diode portion are formed on a semiconductor substrate. An upper electrode is formed on top of the semiconductor substrate. The first mark portion is positioned above the upper electrode, overlapping both the transistor portion and the diode portion in a top view, and having a concave or convex shape in the top view or in the depth direction of the semiconductor substrate. A method for manufacturing a semiconductor device.

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